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drm/radeon: dpm updates for KV/KB
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
4589433c
CC		 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
4589433c
CC		 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
c93bb85b 63 } else if (a2 > a1) {
942b0e95
AD		 64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
c93bb85b 66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
4589433c
CC		 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
5df3196b
AD		 86 struct radeon_encoder *radeon_encoder =
87 to_radeon_encoder(radeon_crtc->encoder);
c93bb85b
JG		 88 /* fixme - fill in enc_priv for atom dac */
89 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab 90 bool is_tv = false, is_cv = false;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
5df3196b
AD		 95 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
96 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
97 tv_std = tv_dac->tv_std;
98 is_tv = true;
4ce001ab
DA		 99 }
100
c93bb85b
JG		 101 memset(&args, 0, sizeof(args));
102
103 args.ucScaler = radeon_crtc->crtc_id;
104
4ce001ab 105 if (is_tv) {
c93bb85b
JG		 106 switch (tv_std) {
107 case TV_STD_NTSC:
108 default:
109 args.ucTVStandard = ATOM_TV_NTSC;
110 break;
111 case TV_STD_PAL:
112 args.ucTVStandard = ATOM_TV_PAL;
113 break;
114 case TV_STD_PAL_M:
115 args.ucTVStandard = ATOM_TV_PALM;
116 break;
117 case TV_STD_PAL_60:
118 args.ucTVStandard = ATOM_TV_PAL60;
119 break;
120 case TV_STD_NTSC_J:
121 args.ucTVStandard = ATOM_TV_NTSCJ;
122 break;
123 case TV_STD_SCART_PAL:
124 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
125 break;
126 case TV_STD_SECAM:
127 args.ucTVStandard = ATOM_TV_SECAM;
128 break;
129 case TV_STD_PAL_CN:
130 args.ucTVStandard = ATOM_TV_PALCN;
131 break;
132 }
133 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 134 } else if (is_cv) {
c93bb85b
JG		 135 args.ucTVStandard = ATOM_TV_CV;
136 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
137 } else {
138 switch (radeon_crtc->rmx_type) {
139 case RMX_FULL:
140 args.ucEnable = ATOM_SCALER_EXPANSION;
141 break;
142 case RMX_CENTER:
143 args.ucEnable = ATOM_SCALER_CENTER;
144 break;
145 case RMX_ASPECT:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 default:
149 if (ASIC_IS_AVIVO(rdev))
150 args.ucEnable = ATOM_SCALER_DISABLE;
151 else
152 args.ucEnable = ATOM_SCALER_CENTER;
153 break;
154 }
155 }
156 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 157 if ((is_tv || is_cv)
158 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
159 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 160 }
161}
162
771fe6b9
JG		 163static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
164{
165 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
166 struct drm_device *dev = crtc->dev;
167 struct radeon_device *rdev = dev->dev_private;
168 int index =
169 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
170 ENABLE_CRTC_PS_ALLOCATION args;
171
172 memset(&args, 0, sizeof(args));
173
174 args.ucCRTC = radeon_crtc->crtc_id;
175 args.ucEnable = lock;
176
177 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
178}
179
180static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
181{
182 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
183 struct drm_device *dev = crtc->dev;
184 struct radeon_device *rdev = dev->dev_private;
185 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
186 ENABLE_CRTC_PS_ALLOCATION args;
187
188 memset(&args, 0, sizeof(args));
189
190 args.ucCRTC = radeon_crtc->crtc_id;
191 args.ucEnable = state;
192
193 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
194}
195
196static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
197{
198 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
199 struct drm_device *dev = crtc->dev;
200 struct radeon_device *rdev = dev->dev_private;
201 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
202 ENABLE_CRTC_PS_ALLOCATION args;
203
204 memset(&args, 0, sizeof(args));
205
206 args.ucCRTC = radeon_crtc->crtc_id;
207 args.ucEnable = state;
208
209 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
210}
211
78fe9e54
AD		 212static const u32 vga_control_regs[6] =
213{
214 AVIVO_D1VGA_CONTROL,
215 AVIVO_D2VGA_CONTROL,
216 EVERGREEN_D3VGA_CONTROL,
217 EVERGREEN_D4VGA_CONTROL,
218 EVERGREEN_D5VGA_CONTROL,
219 EVERGREEN_D6VGA_CONTROL,
220};
221
771fe6b9
JG		 222static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
223{
224 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
225 struct drm_device *dev = crtc->dev;
226 struct radeon_device *rdev = dev->dev_private;
227 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
228 BLANK_CRTC_PS_ALLOCATION args;
78fe9e54 229 u32 vga_control = 0;
771fe6b9
JG		 230
231 memset(&args, 0, sizeof(args));
232
78fe9e54
AD		 233 if (ASIC_IS_DCE8(rdev)) {
234 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
235 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
236 }
237
771fe6b9
JG		 238 args.ucCRTC = radeon_crtc->crtc_id;
239 args.ucBlanking = state;
240
241 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
78fe9e54
AD		 242
243 if (ASIC_IS_DCE8(rdev)) {
244 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
245 }
771fe6b9
JG		 246}
247
fef9f91f
AD		 248static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
249{
250 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
251 struct drm_device *dev = crtc->dev;
252 struct radeon_device *rdev = dev->dev_private;
253 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
254 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
255
256 memset(&args, 0, sizeof(args));
257
258 args.ucDispPipeId = radeon_crtc->crtc_id;
259 args.ucEnable = state;
260
261 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
262}
263
771fe6b9
JG		 264void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
265{
266 struct drm_device *dev = crtc->dev;
267 struct radeon_device *rdev = dev->dev_private;
500b7587 268 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 269
270 switch (mode) {
271 case DRM_MODE_DPMS_ON:
d7311171
AD		 272 radeon_crtc->enabled = true;
273 /* adjust pm to dpms changes BEFORE enabling crtcs */
274 radeon_pm_compute_clocks(rdev);
37b4390e 275 atombios_enable_crtc(crtc, ATOM_ENABLE);
79f17c64 276 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
37b4390e
AD		 277 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
278 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 279 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 280 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 281 break;
282 case DRM_MODE_DPMS_STANDBY:
283 case DRM_MODE_DPMS_SUSPEND:
284 case DRM_MODE_DPMS_OFF:
45f9a39b 285 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 286 if (radeon_crtc->enabled)
287 atombios_blank_crtc(crtc, ATOM_ENABLE);
79f17c64 288 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
37b4390e
AD		 289 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
290 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 291 radeon_crtc->enabled = false;
d7311171
AD		 292 /* adjust pm to dpms changes AFTER disabling crtcs */
293 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 294 break;
295 }
771fe6b9
JG		 296}
297
298static void
299atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 300 struct drm_display_mode *mode)
771fe6b9 301{
5a9bcacc 302 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 303 struct drm_device *dev = crtc->dev;
304 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 305 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 306 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 307 u16 misc = 0;
771fe6b9 308
5a9bcacc 309 memset(&args, 0, sizeof(args));
5b1714d3 310 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 311 args.usH_Blanking_Time =
5b1714d3
AD		 312 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
313 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 314 args.usV_Blanking_Time =
5b1714d3 315 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 316 args.usH_SyncOffset =
5b1714d3 317 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 318 args.usH_SyncWidth =
319 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
320 args.usV_SyncOffset =
5b1714d3 321 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 322 args.usV_SyncWidth =
323 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 324 args.ucH_Border = radeon_crtc->h_border;
325 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 326
327 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
328 misc |= ATOM_VSYNC_POLARITY;
329 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
330 misc |= ATOM_HSYNC_POLARITY;
331 if (mode->flags & DRM_MODE_FLAG_CSYNC)
332 misc |= ATOM_COMPOSITESYNC;
333 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
334 misc |= ATOM_INTERLACE;
335 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
336 misc |= ATOM_DOUBLE_CLOCK_MODE;
337
338 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
339 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 340
5a9bcacc 341 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 342}
343
5a9bcacc
AD		 344static void atombios_crtc_set_timing(struct drm_crtc *crtc,
345 struct drm_display_mode *mode)
771fe6b9 346{
5a9bcacc 347 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 348 struct drm_device *dev = crtc->dev;
349 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 350 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 351 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 352 u16 misc = 0;
771fe6b9 353
5a9bcacc
AD		 354 memset(&args, 0, sizeof(args));
355 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
356 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
357 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
358 args.usH_SyncWidth =
359 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
360 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
361 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
362 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
363 args.usV_SyncWidth =
364 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
365
54bfe496
AD		 366 args.ucOverscanRight = radeon_crtc->h_border;
367 args.ucOverscanLeft = radeon_crtc->h_border;
368 args.ucOverscanBottom = radeon_crtc->v_border;
369 args.ucOverscanTop = radeon_crtc->v_border;
370
5a9bcacc
AD		 371 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
372 misc |= ATOM_VSYNC_POLARITY;
373 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
374 misc |= ATOM_HSYNC_POLARITY;
375 if (mode->flags & DRM_MODE_FLAG_CSYNC)
376 misc |= ATOM_COMPOSITESYNC;
377 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
378 misc |= ATOM_INTERLACE;
379 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
380 misc |= ATOM_DOUBLE_CLOCK_MODE;
381
382 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
383 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 384
5a9bcacc 385 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 386}
387
3fa47d9e 388static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
b792210e 389{
b792210e
AD		 390 u32 ss_cntl;
391
392 if (ASIC_IS_DCE4(rdev)) {
3fa47d9e 393 switch (pll_id) {
b792210e
AD		 394 case ATOM_PPLL1:
395 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
396 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
397 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
398 break;
399 case ATOM_PPLL2:
400 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
401 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
402 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
403 break;
404 case ATOM_DCPLL:
405 case ATOM_PPLL_INVALID:
406 return;
407 }
408 } else if (ASIC_IS_AVIVO(rdev)) {
3fa47d9e 409 switch (pll_id) {
b792210e
AD		 410 case ATOM_PPLL1:
411 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
412 ss_cntl &= ~1;
413 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
414 break;
415 case ATOM_PPLL2:
416 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
417 ss_cntl &= ~1;
418 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
419 break;
420 case ATOM_DCPLL:
421 case ATOM_PPLL_INVALID:
422 return;
423 }
424 }
425}
426
427
26b9fc3a 428union atom_enable_ss {
ba032a58
AD		 429 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
430 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 431 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 432 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 433 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 434};
435
3fa47d9e 436static void atombios_crtc_program_ss(struct radeon_device *rdev,
ba032a58
AD		 437 int enable,
438 int pll_id,
5efcc76c 439 int crtc_id,
ba032a58 440 struct radeon_atom_ss *ss)
ebbe1cb9 441{
5efcc76c 442 unsigned i;
ebbe1cb9 443 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 444 union atom_enable_ss args;
ebbe1cb9 445
c4756baa
AD		 446 if (enable) {
447 /* Don't mess with SS if percentage is 0 or external ss.
448 * SS is already disabled previously, and disabling it
449 * again can cause display problems if the pll is already
450 * programmed.
451 */
452 if (ss->percentage == 0)
453 return;
454 if (ss->type & ATOM_EXTERNAL_SS_MASK)
455 return;
456 } else {
53176706 457 for (i = 0; i < rdev->num_crtc; i++) {
5efcc76c
JG		 458 if (rdev->mode_info.crtcs[i] &&
459 rdev->mode_info.crtcs[i]->enabled &&
460 i != crtc_id &&
461 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
462 /* one other crtc is using this pll don't turn
463 * off spread spectrum as it might turn off
464 * display on active crtc
465 */
466 return;
467 }
468 }
469 }
470
ba032a58 471 memset(&args, 0, sizeof(args));
bcc1c2a1 472
a572eaa3 473 if (ASIC_IS_DCE5(rdev)) {
4589433c 474 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
8e8e523d 475 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
a572eaa3
AD		 476 switch (pll_id) {
477 case ATOM_PPLL1:
478 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
a572eaa3
AD		 479 break;
480 case ATOM_PPLL2:
481 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
a572eaa3
AD		 482 break;
483 case ATOM_DCPLL:
484 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
a572eaa3
AD		 485 break;
486 case ATOM_PPLL_INVALID:
487 return;
488 }
f312f093
AD		 489 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
490 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
d0ae3e89 491 args.v3.ucEnable = enable;
a572eaa3 492 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58 493 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 494 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 495 switch (pll_id) {
496 case ATOM_PPLL1:
497 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
ba032a58
AD		 498 break;
499 case ATOM_PPLL2:
500 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
ebbe1cb9 501 break;
ba032a58
AD		 502 case ATOM_DCPLL:
503 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
ba032a58
AD		 504 break;
505 case ATOM_PPLL_INVALID:
506 return;
ebbe1cb9 507 }
f312f093
AD		 508 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
509 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ba032a58
AD		 510 args.v2.ucEnable = enable;
511 } else if (ASIC_IS_DCE3(rdev)) {
512 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 513 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 514 args.v1.ucSpreadSpectrumStep = ss->step;
515 args.v1.ucSpreadSpectrumDelay = ss->delay;
516 args.v1.ucSpreadSpectrumRange = ss->range;
517 args.v1.ucPpll = pll_id;
518 args.v1.ucEnable = enable;
519 } else if (ASIC_IS_AVIVO(rdev)) {
8e8e523d
AD		 520 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
521 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
3fa47d9e 522 atombios_disable_ss(rdev, pll_id);
ba032a58
AD		 523 return;
524 }
525 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 526 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 527 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
528 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
529 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
530 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 531 } else {
c4756baa 532 if (enable == ATOM_DISABLE) {
3fa47d9e 533 atombios_disable_ss(rdev, pll_id);
ba032a58
AD		 534 return;
535 }
536 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 537 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 538 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
539 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
540 args.lvds_ss.ucEnable = enable;
ebbe1cb9 541 }
26b9fc3a 542 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 543}
544
4eaeca33
AD		 545union adjust_pixel_clock {
546 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 547 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 548};
549
550static u32 atombios_adjust_pll(struct drm_crtc *crtc,
19eca43e 551 struct drm_display_mode *mode)
771fe6b9 552{
19eca43e 553 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 554 struct drm_device *dev = crtc->dev;
555 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 556 struct drm_encoder *encoder = radeon_crtc->encoder;
557 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
558 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
4eaeca33 559 u32 adjusted_clock = mode->clock;
5df3196b 560 int encoder_mode = atombios_get_encoder_mode(encoder);
fbee67a6 561 u32 dp_clock = mode->clock;
7d5a33b0 562 int bpc = radeon_crtc->bpc;
5df3196b 563 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
fc10332b 564
4eaeca33 565 /* reset the pll flags */
19eca43e 566 radeon_crtc->pll_flags = 0;
771fe6b9
JG		 567
568 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 569 if ((rdev->family == CHIP_RS600) ||
570 (rdev->family == CHIP_RS690) ||
571 (rdev->family == CHIP_RS740))
19eca43e
AD		 572 radeon_crtc->pll_flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
573 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 574
575 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
19eca43e 576 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
5480f727 577 else
19eca43e 578 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
9bb09fa1 579
5785e53f 580 if (rdev->family < CHIP_RV770)
19eca43e 581 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
37d4174d 582 /* use frac fb div on APUs */
c7d2f227 583 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
19eca43e 584 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
41167828
AD		 585 /* use frac fb div on RS780/RS880 */
586 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
587 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
a02dc74b
AD		 588 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
589 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
5480f727 590 } else {
19eca43e 591 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
771fe6b9 592
5480f727 593 if (mode->clock > 200000) /* range limits??? */
19eca43e 594 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
5480f727 595 else
19eca43e 596 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
5480f727
DA		 597 }
598
5df3196b
AD		 599 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
600 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
601 if (connector) {
602 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
603 struct radeon_connector_atom_dig *dig_connector =
604 radeon_connector->con_priv;
5b40ddf8 605
5df3196b
AD		 606 dp_clock = dig_connector->dp_clock;
607 }
608 }
5b40ddf8 609
5df3196b
AD		 610 /* use recommended ref_div for ss */
611 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
612 if (radeon_crtc->ss_enabled) {
613 if (radeon_crtc->ss.refdiv) {
614 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
615 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
616 if (ASIC_IS_AVIVO(rdev))
617 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
771fe6b9 618 }
771fe6b9
JG		 619 }
620 }
621
5df3196b
AD		 622 if (ASIC_IS_AVIVO(rdev)) {
623 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
624 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
625 adjusted_clock = mode->clock * 2;
626 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
627 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
628 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
629 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
630 } else {
631 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
632 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
633 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
634 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
635 }
636
2606c886
AD		 637 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
638 * accordingly based on the encoder/transmitter to work around
639 * special hw requirements.
640 */
641 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 642 union adjust_pixel_clock args;
4eaeca33
AD		 643 u8 frev, crev;
644 int index;
2606c886 645
2606c886 646 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 647 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
648 &crev))
649 return adjusted_clock;
4eaeca33
AD		 650
651 memset(&args, 0, sizeof(args));
652
653 switch (frev) {
654 case 1:
655 switch (crev) {
656 case 1:
657 case 2:
658 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
659 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 660 args.v1.ucEncodeMode = encoder_mode;
19eca43e 661 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
fbee67a6
AD		 662 args.v1.ucConfig |=
663 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
4eaeca33
AD		 664
665 atom_execute_table(rdev->mode_info.atom_context,
666 index, (uint32_t *)&args);
667 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
668 break;
bcc1c2a1
AD		 669 case 3:
670 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
671 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
672 args.v3.sInput.ucEncodeMode = encoder_mode;
673 args.v3.sInput.ucDispPllConfig = 0;
19eca43e 674 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
b526ce22
AD		 675 args.v3.sInput.ucDispPllConfig |=
676 DISPPLL_CONFIG_SS_ENABLE;
996d5c59 677 if (ENCODER_MODE_IS_DP(encoder_mode)) {
b4f15f80
AD		 678 args.v3.sInput.ucDispPllConfig |=
679 DISPPLL_CONFIG_COHERENT_MODE;
680 /* 16200 or 27000 */
681 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
682 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
bcc1c2a1 683 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b4f15f80
AD		 684 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
685 /* deep color support */
686 args.v3.sInput.usPixelClock =
687 cpu_to_le16((mode->clock * bpc / 8) / 10);
688 if (dig->coherent_mode)
bcc1c2a1
AD		 689 args.v3.sInput.ucDispPllConfig |=
690 DISPPLL_CONFIG_COHERENT_MODE;
9aa59993 691 if (is_duallink)
bcc1c2a1 692 args.v3.sInput.ucDispPllConfig |=
b4f15f80 693 DISPPLL_CONFIG_DUAL_LINK;
bcc1c2a1 694 }
1d33e1fc
AD		 695 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
696 ENCODER_OBJECT_ID_NONE)
697 args.v3.sInput.ucExtTransmitterID =
698 radeon_encoder_get_dp_bridge_encoder_id(encoder);
699 else
cc9f67a0
AD		 700 args.v3.sInput.ucExtTransmitterID = 0;
701
bcc1c2a1
AD		 702 atom_execute_table(rdev->mode_info.atom_context,
703 index, (uint32_t *)&args);
704 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
705 if (args.v3.sOutput.ucRefDiv) {
19eca43e
AD		 706 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
707 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
708 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
bcc1c2a1
AD		 709 }
710 if (args.v3.sOutput.ucPostDiv) {
19eca43e
AD		 711 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
712 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
713 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
bcc1c2a1
AD		 714 }
715 break;
4eaeca33
AD		 716 default:
717 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
718 return adjusted_clock;
719 }
720 break;
721 default:
722 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
723 return adjusted_clock;
724 }
d56ef9c8 725 }
4eaeca33
AD		 726 return adjusted_clock;
727}
728
729union set_pixel_clock {
730 SET_PIXEL_CLOCK_PS_ALLOCATION base;
731 PIXEL_CLOCK_PARAMETERS v1;
732 PIXEL_CLOCK_PARAMETERS_V2 v2;
733 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 734 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 735 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 736};
737
f82b3ddc
AD		 738/* on DCE5, make sure the voltage is high enough to support the
739 * required disp clk.
740 */
f3f1f03e 741static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
f82b3ddc 742 u32 dispclk)
bcc1c2a1 743{
bcc1c2a1
AD		 744 u8 frev, crev;
745 int index;
746 union set_pixel_clock args;
747
748 memset(&args, 0, sizeof(args));
749
750 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 751 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
752 &crev))
753 return;
bcc1c2a1
AD		 754
755 switch (frev) {
756 case 1:
757 switch (crev) {
758 case 5:
759 /* if the default dcpll clock is specified,
760 * SetPixelClock provides the dividers
761 */
762 args.v5.ucCRTC = ATOM_CRTC_INVALID;
4589433c 763 args.v5.usPixelClock = cpu_to_le16(dispclk);
bcc1c2a1
AD		 764 args.v5.ucPpll = ATOM_DCPLL;
765 break;
f82b3ddc
AD		 766 case 6:
767 /* if the default dcpll clock is specified,
768 * SetPixelClock provides the dividers
769 */
265aa6c8 770 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
8542c12b 771 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
729b95ef
AD		 772 args.v6.ucPpll = ATOM_EXT_PLL1;
773 else if (ASIC_IS_DCE6(rdev))
f3f1f03e
AD		 774 args.v6.ucPpll = ATOM_PPLL0;
775 else
776 args.v6.ucPpll = ATOM_DCPLL;
f82b3ddc 777 break;
bcc1c2a1
AD		 778 default:
779 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
780 return;
781 }
782 break;
783 default:
784 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
785 return;
786 }
787 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
788}
789
37f9003b 790static void atombios_crtc_program_pll(struct drm_crtc *crtc,
f1bece7f 791 u32 crtc_id,
37f9003b
AD		 792 int pll_id,
793 u32 encoder_mode,
794 u32 encoder_id,
795 u32 clock,
796 u32 ref_div,
797 u32 fb_div,
798 u32 frac_fb_div,
df271bec 799 u32 post_div,
8e8e523d
AD		 800 int bpc,
801 bool ss_enabled,
802 struct radeon_atom_ss *ss)
4eaeca33 803{
4eaeca33
AD		 804 struct drm_device *dev = crtc->dev;
805 struct radeon_device *rdev = dev->dev_private;
4eaeca33 806 u8 frev, crev;
37f9003b 807 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 808 union set_pixel_clock args;
4eaeca33
AD		 809
810 memset(&args, 0, sizeof(args));
811
a084e6ee
AD		 812 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
813 &crev))
814 return;
771fe6b9
JG		 815
816 switch (frev) {
817 case 1:
818 switch (crev) {
819 case 1:
37f9003b
AD		 820 if (clock == ATOM_DISABLE)
821 return;
822 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 823 args.v1.usRefDiv = cpu_to_le16(ref_div);
824 args.v1.usFbDiv = cpu_to_le16(fb_div);
825 args.v1.ucFracFbDiv = frac_fb_div;
826 args.v1.ucPostDiv = post_div;
37f9003b
AD		 827 args.v1.ucPpll = pll_id;
828 args.v1.ucCRTC = crtc_id;
4eaeca33 829 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 830 break;
831 case 2:
37f9003b 832 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 833 args.v2.usRefDiv = cpu_to_le16(ref_div);
834 args.v2.usFbDiv = cpu_to_le16(fb_div);
835 args.v2.ucFracFbDiv = frac_fb_div;
836 args.v2.ucPostDiv = post_div;
37f9003b
AD		 837 args.v2.ucPpll = pll_id;
838 args.v2.ucCRTC = crtc_id;
4eaeca33 839 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 840 break;
841 case 3:
37f9003b 842 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 843 args.v3.usRefDiv = cpu_to_le16(ref_div);
844 args.v3.usFbDiv = cpu_to_le16(fb_div);
845 args.v3.ucFracFbDiv = frac_fb_div;
846 args.v3.ucPostDiv = post_div;
37f9003b 847 args.v3.ucPpll = pll_id;
e729586e
AD		 848 if (crtc_id == ATOM_CRTC2)
849 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
850 else
851 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
6f15c506
AD		 852 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
853 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
37f9003b 854 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 855 args.v3.ucEncoderMode = encoder_mode;
856 break;
857 case 5:
37f9003b
AD		 858 args.v5.ucCRTC = crtc_id;
859 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 860 args.v5.ucRefDiv = ref_div;
861 args.v5.usFbDiv = cpu_to_le16(fb_div);
862 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
863 args.v5.ucPostDiv = post_div;
864 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 865 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
866 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
df271bec
AD		 867 switch (bpc) {
868 case 8:
869 default:
870 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
871 break;
872 case 10:
873 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
874 break;
875 }
37f9003b 876 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 877 args.v5.ucEncoderMode = encoder_mode;
37f9003b 878 args.v5.ucPpll = pll_id;
771fe6b9 879 break;
f82b3ddc 880 case 6:
f1bece7f 881 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
f82b3ddc
AD		 882 args.v6.ucRefDiv = ref_div;
883 args.v6.usFbDiv = cpu_to_le16(fb_div);
884 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
885 args.v6.ucPostDiv = post_div;
886 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 887 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
888 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
df271bec
AD		 889 switch (bpc) {
890 case 8:
891 default:
892 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
893 break;
894 case 10:
895 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
896 break;
897 case 12:
898 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
899 break;
900 case 16:
901 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
902 break;
903 }
f82b3ddc
AD		 904 args.v6.ucTransmitterID = encoder_id;
905 args.v6.ucEncoderMode = encoder_mode;
906 args.v6.ucPpll = pll_id;
907 break;
771fe6b9
JG		 908 default:
909 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
910 return;
911 }
912 break;
913 default:
914 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
915 return;
916 }
917
771fe6b9
JG		 918 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
919}
920
19eca43e 921static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
37f9003b
AD		 922{
923 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
924 struct drm_device *dev = crtc->dev;
925 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 926 struct radeon_encoder *radeon_encoder =
927 to_radeon_encoder(radeon_crtc->encoder);
928 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
19eca43e
AD		 929
930 radeon_crtc->bpc = 8;
931 radeon_crtc->ss_enabled = false;
37f9003b 932
700698e7 933 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
5df3196b 934 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
ba032a58
AD		 935 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
936 struct drm_connector *connector =
5df3196b 937 radeon_get_connector_for_encoder(radeon_crtc->encoder);
ba032a58
AD		 938 struct radeon_connector *radeon_connector =
939 to_radeon_connector(connector);
940 struct radeon_connector_atom_dig *dig_connector =
941 radeon_connector->con_priv;
942 int dp_clock;
19eca43e 943 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
ba032a58
AD		 944
945 switch (encoder_mode) {
996d5c59 946 case ATOM_ENCODER_MODE_DP_MST:
ba032a58
AD		 947 case ATOM_ENCODER_MODE_DP:
948 /* DP/eDP */
949 dp_clock = dig_connector->dp_clock / 10;
2307790f 950 if (ASIC_IS_DCE4(rdev))
19eca43e
AD		 951 radeon_crtc->ss_enabled =
952 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
2307790f
AD		 953 ASIC_INTERNAL_SS_ON_DP,
954 dp_clock);
955 else {
956 if (dp_clock == 16200) {
19eca43e
AD		 957 radeon_crtc->ss_enabled =
958 radeon_atombios_get_ppll_ss_info(rdev,
959 &radeon_crtc->ss,
2307790f 960 ATOM_DP_SS_ID2);
19eca43e
AD		 961 if (!radeon_crtc->ss_enabled)
962 radeon_crtc->ss_enabled =
963 radeon_atombios_get_ppll_ss_info(rdev,
964 &radeon_crtc->ss,
2307790f 965 ATOM_DP_SS_ID1);
d8e24525 966 } else {
19eca43e
AD		 967 radeon_crtc->ss_enabled =
968 radeon_atombios_get_ppll_ss_info(rdev,
969 &radeon_crtc->ss,
2307790f 970 ATOM_DP_SS_ID1);
d8e24525
AD		 971 }
972 /* disable spread spectrum on DCE3 DP */
973 radeon_crtc->ss_enabled = false;
ba032a58
AD		 974 }
975 break;
976 case ATOM_ENCODER_MODE_LVDS:
977 if (ASIC_IS_DCE4(rdev))
19eca43e
AD		 978 radeon_crtc->ss_enabled =
979 radeon_atombios_get_asic_ss_info(rdev,
980 &radeon_crtc->ss,
981 dig->lcd_ss_id,
982 mode->clock / 10);
ba032a58 983 else
19eca43e
AD		 984 radeon_crtc->ss_enabled =
985 radeon_atombios_get_ppll_ss_info(rdev,
986 &radeon_crtc->ss,
987 dig->lcd_ss_id);
ba032a58
AD		 988 break;
989 case ATOM_ENCODER_MODE_DVI:
990 if (ASIC_IS_DCE4(rdev))
19eca43e
AD		 991 radeon_crtc->ss_enabled =
992 radeon_atombios_get_asic_ss_info(rdev,
993 &radeon_crtc->ss,
ba032a58
AD		 994 ASIC_INTERNAL_SS_ON_TMDS,
995 mode->clock / 10);
996 break;
997 case ATOM_ENCODER_MODE_HDMI:
998 if (ASIC_IS_DCE4(rdev))
19eca43e
AD		 999 radeon_crtc->ss_enabled =
1000 radeon_atombios_get_asic_ss_info(rdev,
1001 &radeon_crtc->ss,
ba032a58
AD		 1002 ASIC_INTERNAL_SS_ON_HDMI,
1003 mode->clock / 10);
1004 break;
1005 default:
1006 break;
1007 }
1008 }
1009
37f9003b 1010 /* adjust pixel clock as needed */
19eca43e
AD		 1011 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1012
1013 return true;
1014}
1015
1016static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1017{
1018 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1019 struct drm_device *dev = crtc->dev;
1020 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 1021 struct radeon_encoder *radeon_encoder =
1022 to_radeon_encoder(radeon_crtc->encoder);
19eca43e
AD		 1023 u32 pll_clock = mode->clock;
1024 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1025 struct radeon_pll *pll;
5df3196b 1026 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
19eca43e
AD		 1027
1028 switch (radeon_crtc->pll_id) {
1029 case ATOM_PPLL1:
1030 pll = &rdev->clock.p1pll;
1031 break;
1032 case ATOM_PPLL2:
1033 pll = &rdev->clock.p2pll;
1034 break;
1035 case ATOM_DCPLL:
1036 case ATOM_PPLL_INVALID:
1037 default:
1038 pll = &rdev->clock.dcpll;
1039 break;
1040 }
1041
1042 /* update pll params */
1043 pll->flags = radeon_crtc->pll_flags;
1044 pll->reference_div = radeon_crtc->pll_reference_div;
1045 pll->post_div = radeon_crtc->pll_post_div;
37f9003b 1046
64146f8b
AD		 1047 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1048 /* TV seems to prefer the legacy algo on some boards */
19eca43e
AD		 1049 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1050 &fb_div, &frac_fb_div, &ref_div, &post_div);
64146f8b 1051 else if (ASIC_IS_AVIVO(rdev))
19eca43e
AD		 1052 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1053 &fb_div, &frac_fb_div, &ref_div, &post_div);
619efb10 1054 else
19eca43e
AD		 1055 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1056 &fb_div, &frac_fb_div, &ref_div, &post_div);
37f9003b 1057
19eca43e
AD		 1058 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1059 radeon_crtc->crtc_id, &radeon_crtc->ss);
ba032a58 1060
37f9003b
AD		 1061 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1062 encoder_mode, radeon_encoder->encoder_id, mode->clock,
19eca43e
AD		 1063 ref_div, fb_div, frac_fb_div, post_div,
1064 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
37f9003b 1065
19eca43e 1066 if (radeon_crtc->ss_enabled) {
ba032a58
AD		 1067 /* calculate ss amount and step size */
1068 if (ASIC_IS_DCE4(rdev)) {
1069 u32 step_size;
18f8f52b
AD		 1070 u32 amount = (((fb_div * 10) + frac_fb_div) *
1071 (u32)radeon_crtc->ss.percentage) /
1072 (100 * (u32)radeon_crtc->ss.percentage_divider);
19eca43e
AD		 1073 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1074 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
ba032a58 1075 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
19eca43e 1076 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
18f8f52b 1077 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
ba032a58
AD		 1078 (125 * 25 * pll->reference_freq / 100);
1079 else
18f8f52b 1080 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
ba032a58 1081 (125 * 25 * pll->reference_freq / 100);
19eca43e 1082 radeon_crtc->ss.step = step_size;
ba032a58
AD		 1083 }
1084
19eca43e
AD		 1085 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1086 radeon_crtc->crtc_id, &radeon_crtc->ss);
ba032a58 1087 }
37f9003b
AD		 1088}
1089
c9417bdd
AD		 1090static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1091 struct drm_framebuffer *fb,
1092 int x, int y, int atomic)
bcc1c2a1
AD		 1093{
1094 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1095 struct drm_device *dev = crtc->dev;
1096 struct radeon_device *rdev = dev->dev_private;
1097 struct radeon_framebuffer *radeon_fb;
4dd19b0d 1098 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 1099 struct drm_gem_object *obj;
1100 struct radeon_bo *rbo;
1101 uint64_t fb_location;
1102 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
285484e2 1103 unsigned bankw, bankh, mtaspect, tile_split;
fa6bee46 1104 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
adcfde51 1105 u32 tmp, viewport_w, viewport_h;
bcc1c2a1
AD		 1106 int r;
1107
1108 /* no fb bound */
f4510a27 1109 if (!atomic && !crtc->primary->fb) {
d9fdaafb 1110 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1111 return 0;
1112 }
1113
4dd19b0d
CB		 1114 if (atomic) {
1115 radeon_fb = to_radeon_framebuffer(fb);
1116 target_fb = fb;
1117 }
1118 else {
f4510a27
MR		 1119 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1120 target_fb = crtc->primary->fb;
4dd19b0d 1121 }
bcc1c2a1 1122
4dd19b0d
CB		 1123 /* If atomic, assume fb object is pinned & idle & fenced and
1124 * just update base pointers
1125 */
bcc1c2a1 1126 obj = radeon_fb->obj;
7e4d15d9 1127 rbo = gem_to_radeon_bo(obj);
bcc1c2a1
AD		 1128 r = radeon_bo_reserve(rbo, false);
1129 if (unlikely(r != 0))
1130 return r;
4dd19b0d
CB		 1131
1132 if (atomic)
1133 fb_location = radeon_bo_gpu_offset(rbo);
1134 else {
1135 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1136 if (unlikely(r != 0)) {
1137 radeon_bo_unreserve(rbo);
1138 return -EINVAL;
1139 }
bcc1c2a1 1140 }
4dd19b0d 1141
bcc1c2a1
AD		 1142 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1143 radeon_bo_unreserve(rbo);
1144
4dd19b0d 1145 switch (target_fb->bits_per_pixel) {
bcc1c2a1
AD		 1146 case 8:
1147 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1148 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1149 break;
1150 case 15:
1151 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1152 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1153 break;
1154 case 16:
1155 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1156 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
fa6bee46
AD		 1157#ifdef __BIG_ENDIAN
1158 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1159#endif
bcc1c2a1
AD		 1160 break;
1161 case 24:
1162 case 32:
1163 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1164 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fa6bee46
AD		 1165#ifdef __BIG_ENDIAN
1166 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1167#endif
bcc1c2a1
AD		 1168 break;
1169 default:
1170 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1171 target_fb->bits_per_pixel);
bcc1c2a1
AD		 1172 return -EINVAL;
1173 }
1174
392e3722 1175 if (tiling_flags & RADEON_TILING_MACRO) {
e3ea94a6 1176 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
392e3722 1177
e3ea94a6 1178 /* Set NUM_BANKS. */
6d8ea7de 1179 if (rdev->family >= CHIP_TAHITI) {
e9d14aeb 1180 unsigned index, num_banks;
e3ea94a6 1181
e9d14aeb
MD		 1182 if (rdev->family >= CHIP_BONAIRE) {
1183 unsigned tileb, tile_split_bytes;
e3ea94a6 1184
e9d14aeb
MD		 1185 /* Calculate the macrotile mode index. */
1186 tile_split_bytes = 64 << tile_split;
1187 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1188 tileb = min(tile_split_bytes, tileb);
e3ea94a6 1189
e9d14aeb
MD		 1190 for (index = 0; tileb > 64; index++)
1191 tileb >>= 1;
1192
1193 if (index >= 16) {
1194 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1195 target_fb->bits_per_pixel, tile_split);
1196 return -EINVAL;
1197 }
e3ea94a6 1198
6d8ea7de 1199 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
e9d14aeb
MD		 1200 } else {
1201 switch (target_fb->bits_per_pixel) {
1202 case 8:
1203 index = 10;
1204 break;
1205 case 16:
1206 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1207 break;
1208 default:
1209 case 32:
1210 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1211 break;
1212 }
1213
6d8ea7de 1214 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
e9d14aeb
MD		 1215 }
1216
e3ea94a6
MO		 1217 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1218 } else {
6d8ea7de
AD		 1219 /* NI and older. */
1220 if (rdev->family >= CHIP_CAYMAN)
e3ea94a6
MO		 1221 tmp = rdev->config.cayman.tile_config;
1222 else
1223 tmp = rdev->config.evergreen.tile_config;
1224
1225 switch ((tmp & 0xf0) >> 4) {
1226 case 0: /* 4 banks */
1227 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1228 break;
1229 case 1: /* 8 banks */
1230 default:
1231 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1232 break;
1233 case 2: /* 16 banks */
1234 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1235 break;
1236 }
392e3722
AD		 1237 }
1238
97d66328 1239 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
285484e2
JG		 1240 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1241 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1242 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1243 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
8da0e500
AD		 1244 if (rdev->family >= CHIP_BONAIRE) {
1245 /* XXX need to know more about the surface tiling mode */
1246 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1247 }
392e3722 1248 } else if (tiling_flags & RADEON_TILING_MICRO)
97d66328
AD		 1249 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1250
8da0e500 1251 if (rdev->family >= CHIP_BONAIRE) {
35a90528
MO		 1252 /* Read the pipe config from the 2D TILED SCANOUT mode.
1253 * It should be the same for the other modes too, but not all
1254 * modes set the pipe config field. */
1255 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1256
1257 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
8da0e500
AD		 1258 } else if ((rdev->family == CHIP_TAHITI) ||
1259 (rdev->family == CHIP_PITCAIRN))
b7019b2f 1260 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
227ae10f
AD		 1261 else if ((rdev->family == CHIP_VERDE) ||
1262 (rdev->family == CHIP_OLAND) ||
1263 (rdev->family == CHIP_HAINAN)) /* for completeness. HAINAN has no display hw */
b7019b2f
AD		 1264 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1265
bcc1c2a1
AD		 1266 switch (radeon_crtc->crtc_id) {
1267 case 0:
1268 WREG32(AVIVO_D1VGA_CONTROL, 0);
1269 break;
1270 case 1:
1271 WREG32(AVIVO_D2VGA_CONTROL, 0);
1272 break;
1273 case 2:
1274 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1275 break;
1276 case 3:
1277 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1278 break;
1279 case 4:
1280 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1281 break;
1282 case 5:
1283 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1284 break;
1285 default:
1286 break;
1287 }
1288
1289 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1290 upper_32_bits(fb_location));
1291 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1292 upper_32_bits(fb_location));
1293 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1294 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1295 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1296 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1297 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46 1298 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
bcc1c2a1
AD		 1299
1300 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1301 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1302 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1303 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1304 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1305 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1306
01f2c773 1307 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1308 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1309 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1310
8da0e500
AD		 1311 if (rdev->family >= CHIP_BONAIRE)
1312 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1313 target_fb->height);
1314 else
1315 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1316 target_fb->height);
bcc1c2a1
AD		 1317 x &= ~3;
1318 y &= ~1;
1319 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1320 (x << 16) | y);
adcfde51
AD		 1321 viewport_w = crtc->mode.hdisplay;
1322 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
bcc1c2a1 1323 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1324 (viewport_w << 16) | viewport_h);
bcc1c2a1 1325
fb9674bd
AD		 1326 /* pageflip setup */
1327 /* make sure flip is at vb rather than hb */
1328 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1329 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1330 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1331
1332 /* set pageflip to happen anywhere in vblank interval */
1333 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1334
f4510a27 1335 if (!atomic && fb && fb != crtc->primary->fb) {
4dd19b0d 1336 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1337 rbo = gem_to_radeon_bo(radeon_fb->obj);
bcc1c2a1
AD		 1338 r = radeon_bo_reserve(rbo, false);
1339 if (unlikely(r != 0))
1340 return r;
1341 radeon_bo_unpin(rbo);
1342 radeon_bo_unreserve(rbo);
1343 }
1344
1345 /* Bytes per pixel may have changed */
1346 radeon_bandwidth_update(rdev);
1347
1348 return 0;
1349}
1350
4dd19b0d
CB		 1351static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1352 struct drm_framebuffer *fb,
1353 int x, int y, int atomic)
771fe6b9
JG		 1354{
1355 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1356 struct drm_device *dev = crtc->dev;
1357 struct radeon_device *rdev = dev->dev_private;
1358 struct radeon_framebuffer *radeon_fb;
1359 struct drm_gem_object *obj;
4c788679 1360 struct radeon_bo *rbo;
4dd19b0d 1361 struct drm_framebuffer *target_fb;
771fe6b9 1362 uint64_t fb_location;
e024e110 1363 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1364 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
adcfde51 1365 u32 tmp, viewport_w, viewport_h;
4c788679 1366 int r;
771fe6b9 1367
2de3b484 1368 /* no fb bound */
f4510a27 1369 if (!atomic && !crtc->primary->fb) {
d9fdaafb 1370 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1371 return 0;
1372 }
771fe6b9 1373
4dd19b0d
CB		 1374 if (atomic) {
1375 radeon_fb = to_radeon_framebuffer(fb);
1376 target_fb = fb;
1377 }
1378 else {
f4510a27
MR		 1379 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1380 target_fb = crtc->primary->fb;
4dd19b0d 1381 }
771fe6b9
JG		 1382
1383 obj = radeon_fb->obj;
7e4d15d9 1384 rbo = gem_to_radeon_bo(obj);
4c788679
JG		 1385 r = radeon_bo_reserve(rbo, false);
1386 if (unlikely(r != 0))
1387 return r;
4dd19b0d
CB		 1388
1389 /* If atomic, assume fb object is pinned & idle & fenced and
1390 * just update base pointers
1391 */
1392 if (atomic)
1393 fb_location = radeon_bo_gpu_offset(rbo);
1394 else {
1395 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1396 if (unlikely(r != 0)) {
1397 radeon_bo_unreserve(rbo);
1398 return -EINVAL;
1399 }
771fe6b9 1400 }
4c788679
JG		 1401 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1402 radeon_bo_unreserve(rbo);
771fe6b9 1403
4dd19b0d 1404 switch (target_fb->bits_per_pixel) {
41456df2
DA		 1405 case 8:
1406 fb_format =
1407 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1408 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1409 break;
771fe6b9
JG		 1410 case 15:
1411 fb_format =
1412 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1413 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1414 break;
1415 case 16:
1416 fb_format =
1417 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1418 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
fa6bee46
AD		 1419#ifdef __BIG_ENDIAN
1420 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1421#endif
771fe6b9
JG		 1422 break;
1423 case 24:
1424 case 32:
1425 fb_format =
1426 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1427 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
fa6bee46
AD		 1428#ifdef __BIG_ENDIAN
1429 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1430#endif
771fe6b9
JG		 1431 break;
1432 default:
1433 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1434 target_fb->bits_per_pixel);
771fe6b9
JG		 1435 return -EINVAL;
1436 }
1437
40c4ac1c
AD		 1438 if (rdev->family >= CHIP_R600) {
1439 if (tiling_flags & RADEON_TILING_MACRO)
1440 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1441 else if (tiling_flags & RADEON_TILING_MICRO)
1442 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1443 } else {
1444 if (tiling_flags & RADEON_TILING_MACRO)
1445 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1446
40c4ac1c
AD		 1447 if (tiling_flags & RADEON_TILING_MICRO)
1448 fb_format |= AVIVO_D1GRPH_TILED;
1449 }
e024e110 1450
771fe6b9
JG		 1451 if (radeon_crtc->crtc_id == 0)
1452 WREG32(AVIVO_D1VGA_CONTROL, 0);
1453 else
1454 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1455
1456 if (rdev->family >= CHIP_RV770) {
1457 if (radeon_crtc->crtc_id) {
95347871
AD		 1458 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1459 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1460 } else {
95347871
AD		 1461 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1462 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1463 }
1464 }
771fe6b9
JG		 1465 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1466 (u32) fb_location);
1467 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1468 radeon_crtc->crtc_offset, (u32) fb_location);
1469 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46
AD		 1470 if (rdev->family >= CHIP_R600)
1471 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
771fe6b9
JG		 1472
1473 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1474 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1475 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1476 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1477 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1478 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1479
01f2c773 1480 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1481 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1482 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1483
1484 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1b619250 1485 target_fb->height);
771fe6b9
JG		 1486 x &= ~3;
1487 y &= ~1;
1488 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1489 (x << 16) | y);
adcfde51
AD		 1490 viewport_w = crtc->mode.hdisplay;
1491 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
771fe6b9 1492 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1493 (viewport_w << 16) | viewport_h);
771fe6b9 1494
fb9674bd
AD		 1495 /* pageflip setup */
1496 /* make sure flip is at vb rather than hb */
1497 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1498 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1499 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1500
1501 /* set pageflip to happen anywhere in vblank interval */
1502 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1503
f4510a27 1504 if (!atomic && fb && fb != crtc->primary->fb) {
4dd19b0d 1505 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1506 rbo = gem_to_radeon_bo(radeon_fb->obj);
4c788679
JG		 1507 r = radeon_bo_reserve(rbo, false);
1508 if (unlikely(r != 0))
1509 return r;
1510 radeon_bo_unpin(rbo);
1511 radeon_bo_unreserve(rbo);
771fe6b9 1512 }
f30f37de
MD		 1513
1514 /* Bytes per pixel may have changed */
1515 radeon_bandwidth_update(rdev);
1516
771fe6b9
JG		 1517 return 0;
1518}
1519
54f088a9
AD		 1520int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1521 struct drm_framebuffer *old_fb)
1522{
1523 struct drm_device *dev = crtc->dev;
1524 struct radeon_device *rdev = dev->dev_private;
1525
bcc1c2a1 1526 if (ASIC_IS_DCE4(rdev))
c9417bdd 1527 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
4dd19b0d
CB		 1528 else if (ASIC_IS_AVIVO(rdev))
1529 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1530 else
1531 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1532}
1533
1534int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1535 struct drm_framebuffer *fb,
21c74a8e 1536 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1537{
1538 struct drm_device *dev = crtc->dev;
1539 struct radeon_device *rdev = dev->dev_private;
1540
1541 if (ASIC_IS_DCE4(rdev))
c9417bdd 1542 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1543 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1544 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1545 else
4dd19b0d 1546 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1547}
1548
615e0cb6
AD		 1549/* properly set additional regs when using atombios */
1550static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1551{
1552 struct drm_device *dev = crtc->dev;
1553 struct radeon_device *rdev = dev->dev_private;
1554 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1555 u32 disp_merge_cntl;
1556
1557 switch (radeon_crtc->crtc_id) {
1558 case 0:
1559 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1560 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1561 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1562 break;
1563 case 1:
1564 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1565 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1566 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1567 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1568 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1569 break;
1570 }
1571}
1572
f3dd8508
AD		 1573/**
1574 * radeon_get_pll_use_mask - look up a mask of which pplls are in use
1575 *
1576 * @crtc: drm crtc
1577 *
1578 * Returns the mask of which PPLLs (Pixel PLLs) are in use.
1579 */
1580static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1581{
1582 struct drm_device *dev = crtc->dev;
1583 struct drm_crtc *test_crtc;
57b35e29 1584 struct radeon_crtc *test_radeon_crtc;
f3dd8508
AD		 1585 u32 pll_in_use = 0;
1586
1587 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1588 if (crtc == test_crtc)
1589 continue;
1590
57b35e29
AD		 1591 test_radeon_crtc = to_radeon_crtc(test_crtc);
1592 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1593 pll_in_use |= (1 << test_radeon_crtc->pll_id);
f3dd8508
AD		 1594 }
1595 return pll_in_use;
1596}
1597
1598/**
1599 * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
1600 *
1601 * @crtc: drm crtc
1602 *
1603 * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
1604 * also in DP mode. For DP, a single PPLL can be used for all DP
1605 * crtcs/encoders.
1606 */
1607static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1608{
1609 struct drm_device *dev = crtc->dev;
57b35e29 1610 struct drm_crtc *test_crtc;
5df3196b 1611 struct radeon_crtc *test_radeon_crtc;
f3dd8508 1612
57b35e29
AD		 1613 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1614 if (crtc == test_crtc)
1615 continue;
1616 test_radeon_crtc = to_radeon_crtc(test_crtc);
1617 if (test_radeon_crtc->encoder &&
1618 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1619 /* for DP use the same PLL for all */
1620 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1621 return test_radeon_crtc->pll_id;
f3dd8508
AD		 1622 }
1623 }
1624 return ATOM_PPLL_INVALID;
1625}
1626
2f454cf1
AD		 1627/**
1628 * radeon_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
1629 *
1630 * @crtc: drm crtc
1631 * @encoder: drm encoder
1632 *
1633 * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
1634 * be shared (i.e., same clock).
1635 */
5df3196b 1636static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
2f454cf1 1637{
5df3196b 1638 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2f454cf1 1639 struct drm_device *dev = crtc->dev;
9642ac0e 1640 struct drm_crtc *test_crtc;
5df3196b 1641 struct radeon_crtc *test_radeon_crtc;
9642ac0e 1642 u32 adjusted_clock, test_adjusted_clock;
2f454cf1 1643
9642ac0e
AD		 1644 adjusted_clock = radeon_crtc->adjusted_clock;
1645
1646 if (adjusted_clock == 0)
1647 return ATOM_PPLL_INVALID;
2f454cf1 1648
57b35e29
AD		 1649 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1650 if (crtc == test_crtc)
1651 continue;
1652 test_radeon_crtc = to_radeon_crtc(test_crtc);
1653 if (test_radeon_crtc->encoder &&
1654 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1655 /* check if we are already driving this connector with another crtc */
1656 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1657 /* if we are, return that pll */
1658 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
5df3196b 1659 return test_radeon_crtc->pll_id;
2f454cf1 1660 }
57b35e29
AD		 1661 /* for non-DP check the clock */
1662 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1663 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1664 (adjusted_clock == test_adjusted_clock) &&
1665 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1666 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1667 return test_radeon_crtc->pll_id;
2f454cf1
AD		 1668 }
1669 }
1670 return ATOM_PPLL_INVALID;
1671}
1672
f3dd8508
AD		 1673/**
1674 * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
1675 *
1676 * @crtc: drm crtc
1677 *
1678 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1679 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1680 * monitors a dedicated PPLL must be used. If a particular board has
1681 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1682 * as there is no need to program the PLL itself. If we are not able to
1683 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1684 * avoid messing up an existing monitor.
1685 *
1686 * Asic specific PLL information
1687 *
0331f674
AD		 1688 * DCE 8.x
1689 * KB/KV
1690 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
1691 * CI
1692 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1693 *
f3dd8508
AD		 1694 * DCE 6.1
1695 * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
1696 * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
1697 *
1698 * DCE 6.0
1699 * - PPLL0 is available to all UNIPHY (DP only)
1700 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1701 *
1702 * DCE 5.0
1703 * - DCPLL is available to all UNIPHY (DP only)
1704 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1705 *
1706 * DCE 3.0/4.0/4.1
1707 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
1708 *
1709 */
bcc1c2a1
AD		 1710static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1711{
5df3196b 1712 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
bcc1c2a1
AD		 1713 struct drm_device *dev = crtc->dev;
1714 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 1715 struct radeon_encoder *radeon_encoder =
1716 to_radeon_encoder(radeon_crtc->encoder);
f3dd8508
AD		 1717 u32 pll_in_use;
1718 int pll;
bcc1c2a1 1719
0331f674
AD		 1720 if (ASIC_IS_DCE8(rdev)) {
1721 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1722 if (rdev->clock.dp_extclk)
1723 /* skip PPLL programming if using ext clock */
1724 return ATOM_PPLL_INVALID;
1725 else {
1726 /* use the same PPLL for all DP monitors */
1727 pll = radeon_get_shared_dp_ppll(crtc);
1728 if (pll != ATOM_PPLL_INVALID)
1729 return pll;
1730 }
1731 } else {
1732 /* use the same PPLL for all monitors with the same clock */
1733 pll = radeon_get_shared_nondp_ppll(crtc);
1734 if (pll != ATOM_PPLL_INVALID)
1735 return pll;
1736 }
1737 /* otherwise, pick one of the plls */
1738 if ((rdev->family == CHIP_KAVERI) ||
1739 (rdev->family == CHIP_KABINI)) {
1740 /* KB/KV has PPLL1 and PPLL2 */
1741 pll_in_use = radeon_get_pll_use_mask(crtc);
1742 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1743 return ATOM_PPLL2;
1744 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1745 return ATOM_PPLL1;
1746 DRM_ERROR("unable to allocate a PPLL\n");
1747 return ATOM_PPLL_INVALID;
1748 } else {
1749 /* CI has PPLL0, PPLL1, and PPLL2 */
1750 pll_in_use = radeon_get_pll_use_mask(crtc);
1751 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1752 return ATOM_PPLL2;
1753 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1754 return ATOM_PPLL1;
1755 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1756 return ATOM_PPLL0;
1757 DRM_ERROR("unable to allocate a PPLL\n");
1758 return ATOM_PPLL_INVALID;
1759 }
1760 } else if (ASIC_IS_DCE61(rdev)) {
5df3196b
AD		 1761 struct radeon_encoder_atom_dig *dig =
1762 radeon_encoder->enc_priv;
1763
1764 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1765 (dig->linkb == false))
1766 /* UNIPHY A uses PPLL2 */
1767 return ATOM_PPLL2;
1768 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1769 /* UNIPHY B/C/D/E/F */
1770 if (rdev->clock.dp_extclk)
1771 /* skip PPLL programming if using ext clock */
1772 return ATOM_PPLL_INVALID;
1773 else {
1774 /* use the same PPLL for all DP monitors */
1775 pll = radeon_get_shared_dp_ppll(crtc);
1776 if (pll != ATOM_PPLL_INVALID)
1777 return pll;
24e1f794 1778 }
5df3196b
AD		 1779 } else {
1780 /* use the same PPLL for all monitors with the same clock */
1781 pll = radeon_get_shared_nondp_ppll(crtc);
1782 if (pll != ATOM_PPLL_INVALID)
1783 return pll;
24e1f794
AD		 1784 }
1785 /* UNIPHY B/C/D/E/F */
f3dd8508
AD		 1786 pll_in_use = radeon_get_pll_use_mask(crtc);
1787 if (!(pll_in_use & (1 << ATOM_PPLL0)))
24e1f794 1788 return ATOM_PPLL0;
f3dd8508
AD		 1789 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1790 return ATOM_PPLL1;
1791 DRM_ERROR("unable to allocate a PPLL\n");
1792 return ATOM_PPLL_INVALID;
9ef4e1d0
AD		 1793 } else if (ASIC_IS_DCE41(rdev)) {
1794 /* Don't share PLLs on DCE4.1 chips */
1795 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1796 if (rdev->clock.dp_extclk)
1797 /* skip PPLL programming if using ext clock */
1798 return ATOM_PPLL_INVALID;
1799 }
1800 pll_in_use = radeon_get_pll_use_mask(crtc);
1801 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1802 return ATOM_PPLL1;
1803 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1804 return ATOM_PPLL2;
1805 DRM_ERROR("unable to allocate a PPLL\n");
1806 return ATOM_PPLL_INVALID;
24e1f794 1807 } else if (ASIC_IS_DCE4(rdev)) {
5df3196b
AD		 1808 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1809 * depending on the asic:
1810 * DCE4: PPLL or ext clock
1811 * DCE5: PPLL, DCPLL, or ext clock
1812 * DCE6: PPLL, PPLL0, or ext clock
1813 *
1814 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1815 * PPLL/DCPLL programming and only program the DP DTO for the
1816 * crtc virtual pixel clock.
1817 */
1818 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1819 if (rdev->clock.dp_extclk)
1820 /* skip PPLL programming if using ext clock */
1821 return ATOM_PPLL_INVALID;
1822 else if (ASIC_IS_DCE6(rdev))
1823 /* use PPLL0 for all DP */
1824 return ATOM_PPLL0;
1825 else if (ASIC_IS_DCE5(rdev))
1826 /* use DCPLL for all DP */
1827 return ATOM_DCPLL;
1828 else {
1829 /* use the same PPLL for all DP monitors */
1830 pll = radeon_get_shared_dp_ppll(crtc);
1831 if (pll != ATOM_PPLL_INVALID)
1832 return pll;
bcc1c2a1 1833 }
9ef4e1d0 1834 } else {
5df3196b
AD		 1835 /* use the same PPLL for all monitors with the same clock */
1836 pll = radeon_get_shared_nondp_ppll(crtc);
1837 if (pll != ATOM_PPLL_INVALID)
1838 return pll;
bcc1c2a1 1839 }
f3dd8508
AD		 1840 /* all other cases */
1841 pll_in_use = radeon_get_pll_use_mask(crtc);
f3dd8508 1842 if (!(pll_in_use & (1 << ATOM_PPLL1)))
bcc1c2a1 1843 return ATOM_PPLL1;
29dbe3bc
AD		 1844 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1845 return ATOM_PPLL2;
f3dd8508
AD		 1846 DRM_ERROR("unable to allocate a PPLL\n");
1847 return ATOM_PPLL_INVALID;
1e4db5f2
AD		 1848 } else {
1849 /* on pre-R5xx asics, the crtc to pll mapping is hardcoded */
fc58acdb
JG		 1850 /* some atombios (observed in some DCE2/DCE3) code have a bug,
1851 * the matching btw pll and crtc is done through
1852 * PCLK_CRTC[1|2]_CNTL (0x480/0x484) but atombios code use the
1853 * pll (1 or 2) to select which register to write. ie if using
1854 * pll1 it will use PCLK_CRTC1_CNTL (0x480) and if using pll2
1855 * it will use PCLK_CRTC2_CNTL (0x484), it then use crtc id to
1856 * choose which value to write. Which is reverse order from
1857 * register logic. So only case that works is when pllid is
1858 * same as crtcid or when both pll and crtc are enabled and
1859 * both use same clock.
1860 *
1861 * So just return crtc id as if crtc and pll were hard linked
1862 * together even if they aren't
1863 */
1e4db5f2 1864 return radeon_crtc->crtc_id;
2f454cf1 1865 }
bcc1c2a1
AD		 1866}
1867
f3f1f03e 1868void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
3fa47d9e
AD		 1869{
1870 /* always set DCPLL */
f3f1f03e
AD		 1871 if (ASIC_IS_DCE6(rdev))
1872 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1873 else if (ASIC_IS_DCE4(rdev)) {
3fa47d9e
AD		 1874 struct radeon_atom_ss ss;
1875 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1876 ASIC_INTERNAL_SS_ON_DCPLL,
1877 rdev->clock.default_dispclk);
1878 if (ss_enabled)
5efcc76c 1879 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
3fa47d9e 1880 /* XXX: DCE5, make sure voltage, dispclk is high enough */
f3f1f03e 1881 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
3fa47d9e 1882 if (ss_enabled)
5efcc76c 1883 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
3fa47d9e
AD		 1884 }
1885
1886}
1887
771fe6b9
JG		 1888int atombios_crtc_mode_set(struct drm_crtc *crtc,
1889 struct drm_display_mode *mode,
1890 struct drm_display_mode *adjusted_mode,
1891 int x, int y, struct drm_framebuffer *old_fb)
1892{
1893 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1894 struct drm_device *dev = crtc->dev;
1895 struct radeon_device *rdev = dev->dev_private;
5df3196b
AD		 1896 struct radeon_encoder *radeon_encoder =
1897 to_radeon_encoder(radeon_crtc->encoder);
54bfe496 1898 bool is_tvcv = false;
771fe6b9 1899
5df3196b
AD		 1900 if (radeon_encoder->active_device &
1901 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1902 is_tvcv = true;
771fe6b9 1903
cde10122
CK		 1904 if (!radeon_crtc->adjusted_clock)
1905 return -EINVAL;
1906
771fe6b9 1907 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 1908
54bfe496 1909 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1910 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1911 else if (ASIC_IS_AVIVO(rdev)) {
1912 if (is_tvcv)
1913 atombios_crtc_set_timing(crtc, adjusted_mode);
1914 else
1915 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1916 } else {
bcc1c2a1 1917 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1918 if (radeon_crtc->crtc_id == 0)
1919 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1920 radeon_legacy_atom_fixup(crtc);
771fe6b9 1921 }
bcc1c2a1 1922 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1923 atombios_overscan_setup(crtc, mode, adjusted_mode);
1924 atombios_scaler_setup(crtc);
66edc1c9
AD		 1925 /* update the hw version fpr dpm */
1926 radeon_crtc->hw_mode = *adjusted_mode;
1927
771fe6b9
JG		 1928 return 0;
1929}
1930
1931static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
e811f5ae 1932 const struct drm_display_mode *mode,
771fe6b9
JG		 1933 struct drm_display_mode *adjusted_mode)
1934{
5df3196b
AD		 1935 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1936 struct drm_device *dev = crtc->dev;
1937 struct drm_encoder *encoder;
1938
1939 /* assign the encoder to the radeon crtc to avoid repeated lookups later */
1940 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1941 if (encoder->crtc == crtc) {
1942 radeon_crtc->encoder = encoder;
57b35e29 1943 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
5df3196b
AD		 1944 break;
1945 }
1946 }
57b35e29
AD		 1947 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
1948 radeon_crtc->encoder = NULL;
1949 radeon_crtc->connector = NULL;
5df3196b 1950 return false;
57b35e29 1951 }
c93bb85b
JG		 1952 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1953 return false;
19eca43e
AD		 1954 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
1955 return false;
c0fd0834
AD		 1956 /* pick pll */
1957 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1958 /* if we can't get a PPLL for a non-DP encoder, fail */
1959 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
1960 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
1961 return false;
1962
771fe6b9
JG		 1963 return true;
1964}
1965
1966static void atombios_crtc_prepare(struct drm_crtc *crtc)
1967{
6c0ae2ab
AD		 1968 struct drm_device *dev = crtc->dev;
1969 struct radeon_device *rdev = dev->dev_private;
267364ac 1970
6c0ae2ab
AD		 1971 /* disable crtc pair power gating before programming */
1972 if (ASIC_IS_DCE6(rdev))
1973 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1974
37b4390e 1975 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1976 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1977}
1978
1979static void atombios_crtc_commit(struct drm_crtc *crtc)
1980{
1981 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1982 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1983}
1984
37f9003b
AD		 1985static void atombios_crtc_disable(struct drm_crtc *crtc)
1986{
1987 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
64199870
AD		 1988 struct drm_device *dev = crtc->dev;
1989 struct radeon_device *rdev = dev->dev_private;
8e8e523d 1990 struct radeon_atom_ss ss;
4e58591c 1991 int i;
8e8e523d 1992
37f9003b 1993 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
f4510a27 1994 if (crtc->primary->fb) {
75b871e2
IH		 1995 int r;
1996 struct radeon_framebuffer *radeon_fb;
1997 struct radeon_bo *rbo;
1998
f4510a27 1999 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
75b871e2
IH		 2000 rbo = gem_to_radeon_bo(radeon_fb->obj);
2001 r = radeon_bo_reserve(rbo, false);
2002 if (unlikely(r))
2003 DRM_ERROR("failed to reserve rbo before unpin\n");
2004 else {
2005 radeon_bo_unpin(rbo);
2006 radeon_bo_unreserve(rbo);
2007 }
2008 }
ac4d04d4
AD		 2009 /* disable the GRPH */
2010 if (ASIC_IS_DCE4(rdev))
2011 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2012 else if (ASIC_IS_AVIVO(rdev))
2013 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2014
0e3d50bf
AD		 2015 if (ASIC_IS_DCE6(rdev))
2016 atombios_powergate_crtc(crtc, ATOM_ENABLE);
37f9003b 2017
4e58591c
AD		 2018 for (i = 0; i < rdev->num_crtc; i++) {
2019 if (rdev->mode_info.crtcs[i] &&
2020 rdev->mode_info.crtcs[i]->enabled &&
2021 i != radeon_crtc->crtc_id &&
2022 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2023 /* one other crtc is using this pll don't turn
2024 * off the pll
2025 */
2026 goto done;
2027 }
2028 }
2029
37f9003b
AD		 2030 switch (radeon_crtc->pll_id) {
2031 case ATOM_PPLL1:
2032 case ATOM_PPLL2:
2033 /* disable the ppll */
2034 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
8e8e523d 2035 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
37f9003b 2036 break;
64199870
AD		 2037 case ATOM_PPLL0:
2038 /* disable the ppll */
7eeeabfc
AD		 2039 if ((rdev->family == CHIP_ARUBA) ||
2040 (rdev->family == CHIP_BONAIRE) ||
2041 (rdev->family == CHIP_HAWAII))
64199870
AD		 2042 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2043 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2044 break;
37f9003b
AD		 2045 default:
2046 break;
2047 }
4e58591c 2048done:
f3dd8508 2049 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
9642ac0e 2050 radeon_crtc->adjusted_clock = 0;
5df3196b 2051 radeon_crtc->encoder = NULL;
57b35e29 2052 radeon_crtc->connector = NULL;
37f9003b
AD		 2053}
2054
771fe6b9
JG		 2055static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2056 .dpms = atombios_crtc_dpms,
2057 .mode_fixup = atombios_crtc_mode_fixup,
2058 .mode_set = atombios_crtc_mode_set,
2059 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 2060 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 2061 .prepare = atombios_crtc_prepare,
2062 .commit = atombios_crtc_commit,
068143d3 2063 .load_lut = radeon_crtc_load_lut,
37f9003b 2064 .disable = atombios_crtc_disable,
771fe6b9
JG		 2065};
2066
2067void radeon_atombios_init_crtc(struct drm_device *dev,
2068 struct radeon_crtc *radeon_crtc)
2069{
bcc1c2a1
AD		 2070 struct radeon_device *rdev = dev->dev_private;
2071
2072 if (ASIC_IS_DCE4(rdev)) {
2073 switch (radeon_crtc->crtc_id) {
2074 case 0:
2075 default:
12d7798f 2076 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 2077 break;
2078 case 1:
12d7798f 2079 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 2080 break;
2081 case 2:
12d7798f 2082 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 2083 break;
2084 case 3:
12d7798f 2085 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 2086 break;
2087 case 4:
12d7798f 2088 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 2089 break;
2090 case 5:
12d7798f 2091 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 2092 break;
2093 }
2094 } else {
2095 if (radeon_crtc->crtc_id == 1)
2096 radeon_crtc->crtc_offset =
2097 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2098 else
2099 radeon_crtc->crtc_offset = 0;
2100 }
f3dd8508 2101 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
9642ac0e 2102 radeon_crtc->adjusted_clock = 0;
5df3196b 2103 radeon_crtc->encoder = NULL;
57b35e29 2104 radeon_crtc->connector = NULL;
771fe6b9
JG		 2105 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2106}
Linux 6.x block layer and io_uring tree(s)