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drm/radeon: finish getting bios earlier
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
68adac5e 29#include <drm/drm_fixed.h>
771fe6b9
JG		 30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
c93bb85b
JG		 47 args.ucCRTC = radeon_crtc->crtc_id;
48
49 switch (radeon_crtc->rmx_type) {
50 case RMX_CENTER:
4589433c
CC		 51 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
c93bb85b
JG		 55 break;
56 case RMX_ASPECT:
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60 if (a1 > a2) {
4589433c
CC		 61 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
c93bb85b 63 } else if (a2 > a1) {
942b0e95
AD		 64 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
c93bb85b 66 }
c93bb85b
JG		 67 break;
68 case RMX_FULL:
69 default:
4589433c
CC		 70 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
c93bb85b
JG		 74 break;
75 }
5b1714d3 76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
c93bb85b
JG		 77}
78
79static void atombios_scaler_setup(struct drm_crtc *crtc)
80{
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 86
c93bb85b
JG		 87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
c93bb85b
JG		 91
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93 return;
94
4ce001ab
DA		 95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96 /* find tv std */
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
102 is_tv = true;
103 }
104 }
105 }
106
c93bb85b
JG		 107 memset(&args, 0, sizeof(args));
108
109 args.ucScaler = radeon_crtc->crtc_id;
110
4ce001ab 111 if (is_tv) {
c93bb85b
JG		 112 switch (tv_std) {
113 case TV_STD_NTSC:
114 default:
115 args.ucTVStandard = ATOM_TV_NTSC;
116 break;
117 case TV_STD_PAL:
118 args.ucTVStandard = ATOM_TV_PAL;
119 break;
120 case TV_STD_PAL_M:
121 args.ucTVStandard = ATOM_TV_PALM;
122 break;
123 case TV_STD_PAL_60:
124 args.ucTVStandard = ATOM_TV_PAL60;
125 break;
126 case TV_STD_NTSC_J:
127 args.ucTVStandard = ATOM_TV_NTSCJ;
128 break;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131 break;
132 case TV_STD_SECAM:
133 args.ucTVStandard = ATOM_TV_SECAM;
134 break;
135 case TV_STD_PAL_CN:
136 args.ucTVStandard = ATOM_TV_PALCN;
137 break;
138 }
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 140 } else if (is_cv) {
c93bb85b
JG		 141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143 } else {
144 switch (radeon_crtc->rmx_type) {
145 case RMX_FULL:
146 args.ucEnable = ATOM_SCALER_EXPANSION;
147 break;
148 case RMX_CENTER:
149 args.ucEnable = ATOM_SCALER_CENTER;
150 break;
151 case RMX_ASPECT:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 default:
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
157 else
158 args.ucEnable = ATOM_SCALER_CENTER;
159 break;
160 }
161 }
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 163 if ((is_tv || is_cv)
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 166 }
167}
168
771fe6b9
JG		 169static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170{
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
174 int index =
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
177
178 memset(&args, 0, sizeof(args));
179
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
182
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184}
185
186static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187{
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
193
194 memset(&args, 0, sizeof(args));
195
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
198
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200}
201
202static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203{
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
209
210 memset(&args, 0, sizeof(args));
211
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
214
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216}
217
218static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219{
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
225
226 memset(&args, 0, sizeof(args));
227
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
230
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
235{
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
500b7587 238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 239
240 switch (mode) {
241 case DRM_MODE_DPMS_ON:
d7311171
AD		 242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
37b4390e 245 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 246 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
45f9a39b 249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 250 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 251 break;
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
45f9a39b 255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
a93f344d
AD		 256 if (radeon_crtc->enabled)
257 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 258 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 259 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
260 atombios_enable_crtc(crtc, ATOM_DISABLE);
a48b9b4e 261 radeon_crtc->enabled = false;
d7311171
AD		 262 /* adjust pm to dpms changes AFTER disabling crtcs */
263 radeon_pm_compute_clocks(rdev);
771fe6b9
JG		 264 break;
265 }
771fe6b9
JG		 266}
267
268static void
269atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 270 struct drm_display_mode *mode)
771fe6b9 271{
5a9bcacc 272 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 273 struct drm_device *dev = crtc->dev;
274 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 275 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 276 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 277 u16 misc = 0;
771fe6b9 278
5a9bcacc 279 memset(&args, 0, sizeof(args));
5b1714d3 280 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
5a9bcacc 281 args.usH_Blanking_Time =
5b1714d3
AD		 282 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
283 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
5a9bcacc 284 args.usV_Blanking_Time =
5b1714d3 285 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
5a9bcacc 286 args.usH_SyncOffset =
5b1714d3 287 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
5a9bcacc
AD		 288 args.usH_SyncWidth =
289 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
290 args.usV_SyncOffset =
5b1714d3 291 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
5a9bcacc
AD		 292 args.usV_SyncWidth =
293 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
5b1714d3
AD		 294 args.ucH_Border = radeon_crtc->h_border;
295 args.ucV_Border = radeon_crtc->v_border;
5a9bcacc
AD		 296
297 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
298 misc |= ATOM_VSYNC_POLARITY;
299 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
300 misc |= ATOM_HSYNC_POLARITY;
301 if (mode->flags & DRM_MODE_FLAG_CSYNC)
302 misc |= ATOM_COMPOSITESYNC;
303 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
304 misc |= ATOM_INTERLACE;
305 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
306 misc |= ATOM_DOUBLE_CLOCK_MODE;
307
308 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
309 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 310
5a9bcacc 311 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 312}
313
5a9bcacc
AD		 314static void atombios_crtc_set_timing(struct drm_crtc *crtc,
315 struct drm_display_mode *mode)
771fe6b9 316{
5a9bcacc 317 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 318 struct drm_device *dev = crtc->dev;
319 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 320 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 321 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 322 u16 misc = 0;
771fe6b9 323
5a9bcacc
AD		 324 memset(&args, 0, sizeof(args));
325 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
326 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
327 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 args.usH_SyncWidth =
329 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
330 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
331 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
332 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 args.usV_SyncWidth =
334 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335
54bfe496
AD		 336 args.ucOverscanRight = radeon_crtc->h_border;
337 args.ucOverscanLeft = radeon_crtc->h_border;
338 args.ucOverscanBottom = radeon_crtc->v_border;
339 args.ucOverscanTop = radeon_crtc->v_border;
340
5a9bcacc
AD		 341 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
342 misc |= ATOM_VSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
344 misc |= ATOM_HSYNC_POLARITY;
345 if (mode->flags & DRM_MODE_FLAG_CSYNC)
346 misc |= ATOM_COMPOSITESYNC;
347 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
348 misc |= ATOM_INTERLACE;
349 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
350 misc |= ATOM_DOUBLE_CLOCK_MODE;
351
352 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
353 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 354
5a9bcacc 355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 356}
357
b792210e
AD		 358static void atombios_disable_ss(struct drm_crtc *crtc)
359{
360 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
361 struct drm_device *dev = crtc->dev;
362 struct radeon_device *rdev = dev->dev_private;
363 u32 ss_cntl;
364
365 if (ASIC_IS_DCE4(rdev)) {
366 switch (radeon_crtc->pll_id) {
367 case ATOM_PPLL1:
368 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
369 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
370 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
371 break;
372 case ATOM_PPLL2:
373 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
374 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
375 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
376 break;
377 case ATOM_DCPLL:
378 case ATOM_PPLL_INVALID:
379 return;
380 }
381 } else if (ASIC_IS_AVIVO(rdev)) {
382 switch (radeon_crtc->pll_id) {
383 case ATOM_PPLL1:
384 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 ss_cntl &= ~1;
386 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
387 break;
388 case ATOM_PPLL2:
389 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 ss_cntl &= ~1;
391 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
392 break;
393 case ATOM_DCPLL:
394 case ATOM_PPLL_INVALID:
395 return;
396 }
397 }
398}
399
400
26b9fc3a 401union atom_enable_ss {
ba032a58
AD		 402 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
403 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
26b9fc3a 404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
ba032a58 405 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
a572eaa3 406 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
26b9fc3a
AD		 407};
408
ba032a58
AD		 409static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 int enable,
411 int pll_id,
412 struct radeon_atom_ss *ss)
ebbe1cb9 413{
ebbe1cb9
AD		 414 struct drm_device *dev = crtc->dev;
415 struct radeon_device *rdev = dev->dev_private;
ebbe1cb9 416 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 417 union atom_enable_ss args;
ebbe1cb9 418
ba032a58 419 memset(&args, 0, sizeof(args));
bcc1c2a1 420
a572eaa3 421 if (ASIC_IS_DCE5(rdev)) {
4589433c 422 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
8e8e523d 423 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
a572eaa3
AD		 424 switch (pll_id) {
425 case ATOM_PPLL1:
426 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
4589433c
CC		 427 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
428 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 429 break;
430 case ATOM_PPLL2:
431 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
4589433c
CC		 432 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
433 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
a572eaa3
AD		 434 break;
435 case ATOM_DCPLL:
436 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
4589433c
CC		 437 args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
438 args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
a572eaa3
AD		 439 break;
440 case ATOM_PPLL_INVALID:
441 return;
442 }
d0ae3e89 443 args.v3.ucEnable = enable;
8e8e523d
AD		 444 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
445 args.v3.ucEnable = ATOM_DISABLE;
a572eaa3 446 } else if (ASIC_IS_DCE4(rdev)) {
ba032a58 447 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 448 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 449 switch (pll_id) {
450 case ATOM_PPLL1:
451 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
4589433c
CC		 452 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
453 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ba032a58
AD		 454 break;
455 case ATOM_PPLL2:
456 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
4589433c
CC		 457 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
458 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
ebbe1cb9 459 break;
ba032a58
AD		 460 case ATOM_DCPLL:
461 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
4589433c
CC		 462 args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
463 args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
ba032a58
AD		 464 break;
465 case ATOM_PPLL_INVALID:
466 return;
ebbe1cb9 467 }
ba032a58 468 args.v2.ucEnable = enable;
09cc6506 469 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
8e8e523d 470 args.v2.ucEnable = ATOM_DISABLE;
ba032a58
AD		 471 } else if (ASIC_IS_DCE3(rdev)) {
472 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 473 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 474 args.v1.ucSpreadSpectrumStep = ss->step;
475 args.v1.ucSpreadSpectrumDelay = ss->delay;
476 args.v1.ucSpreadSpectrumRange = ss->range;
477 args.v1.ucPpll = pll_id;
478 args.v1.ucEnable = enable;
479 } else if (ASIC_IS_AVIVO(rdev)) {
8e8e523d
AD		 480 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
481 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
ba032a58
AD		 482 atombios_disable_ss(crtc);
483 return;
484 }
485 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 486 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 487 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
488 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
489 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
490 args.lvds_ss_2.ucEnable = enable;
ebbe1cb9 491 } else {
8e8e523d
AD		 492 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
493 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
ba032a58
AD		 494 atombios_disable_ss(crtc);
495 return;
496 }
497 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
8e8e523d 498 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
ba032a58
AD		 499 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
500 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
501 args.lvds_ss.ucEnable = enable;
ebbe1cb9 502 }
26b9fc3a 503 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 504}
505
4eaeca33
AD		 506union adjust_pixel_clock {
507 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 508 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 509};
510
511static u32 atombios_adjust_pll(struct drm_crtc *crtc,
512 struct drm_display_mode *mode,
ba032a58
AD		 513 struct radeon_pll *pll,
514 bool ss_enabled,
515 struct radeon_atom_ss *ss)
771fe6b9 516{
771fe6b9
JG		 517 struct drm_device *dev = crtc->dev;
518 struct radeon_device *rdev = dev->dev_private;
519 struct drm_encoder *encoder = NULL;
520 struct radeon_encoder *radeon_encoder = NULL;
df271bec 521 struct drm_connector *connector = NULL;
4eaeca33 522 u32 adjusted_clock = mode->clock;
bcc1c2a1 523 int encoder_mode = 0;
fbee67a6
AD		 524 u32 dp_clock = mode->clock;
525 int bpc = 8;
fc10332b 526
4eaeca33
AD		 527 /* reset the pll flags */
528 pll->flags = 0;
771fe6b9
JG		 529
530 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 531 if ((rdev->family == CHIP_RS600) ||
532 (rdev->family == CHIP_RS690) ||
533 (rdev->family == CHIP_RS740))
2ff776cf 534 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
fc10332b 535 RADEON_PLL_PREFER_CLOSEST_LOWER);
5480f727
DA		 536
537 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
538 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
539 else
540 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
9bb09fa1 541
5785e53f 542 if (rdev->family < CHIP_RV770)
9bb09fa1 543 pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
5480f727 544 } else {
fc10332b 545 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9 546
5480f727
DA		 547 if (mode->clock > 200000) /* range limits??? */
548 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
549 else
550 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
5480f727
DA		 551 }
552
771fe6b9
JG		 553 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
554 if (encoder->crtc == crtc) {
4eaeca33 555 radeon_encoder = to_radeon_encoder(encoder);
df271bec 556 connector = radeon_get_connector_for_encoder(encoder);
06e4cd64 557 if (connector && connector->display_info.bpc)
df271bec 558 bpc = connector->display_info.bpc;
bcc1c2a1 559 encoder_mode = atombios_get_encoder_mode(encoder);
eac4dff6 560 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
1d33e1fc 561 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
fbee67a6
AD		 562 if (connector) {
563 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
564 struct radeon_connector_atom_dig *dig_connector =
565 radeon_connector->con_priv;
566
567 dp_clock = dig_connector->dp_clock;
568 }
569 }
5b40ddf8 570
ba032a58
AD		 571 /* use recommended ref_div for ss */
572 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
573 if (ss_enabled) {
574 if (ss->refdiv) {
575 pll->flags |= RADEON_PLL_USE_REF_DIV;
576 pll->reference_div = ss->refdiv;
5b40ddf8
AD		 577 if (ASIC_IS_AVIVO(rdev))
578 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
ba032a58
AD		 579 }
580 }
581 }
5b40ddf8 582
4eaeca33
AD		 583 if (ASIC_IS_AVIVO(rdev)) {
584 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
585 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
586 adjusted_clock = mode->clock * 2;
48dfaaeb 587 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
a1a4b23b 588 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
5b40ddf8
AD		 589 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
590 pll->flags |= RADEON_PLL_IS_LCD;
4eaeca33
AD		 591 } else {
592 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 593 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 594 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 595 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 596 }
3ce0a23d 597 break;
771fe6b9
JG		 598 }
599 }
600
2606c886
AD		 601 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
602 * accordingly based on the encoder/transmitter to work around
603 * special hw requirements.
604 */
605 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 606 union adjust_pixel_clock args;
4eaeca33
AD		 607 u8 frev, crev;
608 int index;
2606c886 609
2606c886 610 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 611 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
612 &crev))
613 return adjusted_clock;
4eaeca33
AD		 614
615 memset(&args, 0, sizeof(args));
616
617 switch (frev) {
618 case 1:
619 switch (crev) {
620 case 1:
621 case 2:
622 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
623 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 624 args.v1.ucEncodeMode = encoder_mode;
8e8e523d 625 if (ss_enabled && ss->percentage)
fbee67a6
AD		 626 args.v1.ucConfig |=
627 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
4eaeca33
AD		 628
629 atom_execute_table(rdev->mode_info.atom_context,
630 index, (uint32_t *)&args);
631 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
632 break;
bcc1c2a1
AD		 633 case 3:
634 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
635 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
636 args.v3.sInput.ucEncodeMode = encoder_mode;
637 args.v3.sInput.ucDispPllConfig = 0;
8e8e523d 638 if (ss_enabled && ss->percentage)
b526ce22
AD		 639 args.v3.sInput.ucDispPllConfig |=
640 DISPPLL_CONFIG_SS_ENABLE;
996d5c59 641 if (ENCODER_MODE_IS_DP(encoder_mode)) {
b4f15f80
AD		 642 args.v3.sInput.ucDispPllConfig |=
643 DISPPLL_CONFIG_COHERENT_MODE;
644 /* 16200 or 27000 */
645 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
646 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
bcc1c2a1 647 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
b4f15f80
AD		 648 if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
649 /* deep color support */
650 args.v3.sInput.usPixelClock =
651 cpu_to_le16((mode->clock * bpc / 8) / 10);
652 if (dig->coherent_mode)
bcc1c2a1
AD		 653 args.v3.sInput.ucDispPllConfig |=
654 DISPPLL_CONFIG_COHERENT_MODE;
b4f15f80 655 if (mode->clock > 165000)
bcc1c2a1 656 args.v3.sInput.ucDispPllConfig |=
b4f15f80 657 DISPPLL_CONFIG_DUAL_LINK;
bcc1c2a1 658 }
1d33e1fc
AD		 659 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
660 ENCODER_OBJECT_ID_NONE)
661 args.v3.sInput.ucExtTransmitterID =
662 radeon_encoder_get_dp_bridge_encoder_id(encoder);
663 else
cc9f67a0
AD		 664 args.v3.sInput.ucExtTransmitterID = 0;
665
bcc1c2a1
AD		 666 atom_execute_table(rdev->mode_info.atom_context,
667 index, (uint32_t *)&args);
668 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
669 if (args.v3.sOutput.ucRefDiv) {
9f4283f4 670 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 671 pll->flags |= RADEON_PLL_USE_REF_DIV;
672 pll->reference_div = args.v3.sOutput.ucRefDiv;
673 }
674 if (args.v3.sOutput.ucPostDiv) {
9f4283f4 675 pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
bcc1c2a1
AD		 676 pll->flags |= RADEON_PLL_USE_POST_DIV;
677 pll->post_div = args.v3.sOutput.ucPostDiv;
678 }
679 break;
4eaeca33
AD		 680 default:
681 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
682 return adjusted_clock;
683 }
684 break;
685 default:
686 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
687 return adjusted_clock;
688 }
d56ef9c8 689 }
4eaeca33
AD		 690 return adjusted_clock;
691}
692
693union set_pixel_clock {
694 SET_PIXEL_CLOCK_PS_ALLOCATION base;
695 PIXEL_CLOCK_PARAMETERS v1;
696 PIXEL_CLOCK_PARAMETERS_V2 v2;
697 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 698 PIXEL_CLOCK_PARAMETERS_V5 v5;
f82b3ddc 699 PIXEL_CLOCK_PARAMETERS_V6 v6;
4eaeca33
AD		 700};
701
f82b3ddc
AD		 702/* on DCE5, make sure the voltage is high enough to support the
703 * required disp clk.
704 */
705static void atombios_crtc_set_dcpll(struct drm_crtc *crtc,
706 u32 dispclk)
bcc1c2a1
AD		 707{
708 struct drm_device *dev = crtc->dev;
709 struct radeon_device *rdev = dev->dev_private;
710 u8 frev, crev;
711 int index;
712 union set_pixel_clock args;
713
714 memset(&args, 0, sizeof(args));
715
716 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 717 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
718 &crev))
719 return;
bcc1c2a1
AD		 720
721 switch (frev) {
722 case 1:
723 switch (crev) {
724 case 5:
725 /* if the default dcpll clock is specified,
726 * SetPixelClock provides the dividers
727 */
728 args.v5.ucCRTC = ATOM_CRTC_INVALID;
4589433c 729 args.v5.usPixelClock = cpu_to_le16(dispclk);
bcc1c2a1
AD		 730 args.v5.ucPpll = ATOM_DCPLL;
731 break;
f82b3ddc
AD		 732 case 6:
733 /* if the default dcpll clock is specified,
734 * SetPixelClock provides the dividers
735 */
265aa6c8 736 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
f82b3ddc
AD		 737 args.v6.ucPpll = ATOM_DCPLL;
738 break;
bcc1c2a1
AD		 739 default:
740 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
741 return;
742 }
743 break;
744 default:
745 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
746 return;
747 }
748 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
749}
750
37f9003b 751static void atombios_crtc_program_pll(struct drm_crtc *crtc,
f1bece7f 752 u32 crtc_id,
37f9003b
AD		 753 int pll_id,
754 u32 encoder_mode,
755 u32 encoder_id,
756 u32 clock,
757 u32 ref_div,
758 u32 fb_div,
759 u32 frac_fb_div,
df271bec 760 u32 post_div,
8e8e523d
AD		 761 int bpc,
762 bool ss_enabled,
763 struct radeon_atom_ss *ss)
4eaeca33 764{
4eaeca33
AD		 765 struct drm_device *dev = crtc->dev;
766 struct radeon_device *rdev = dev->dev_private;
4eaeca33 767 u8 frev, crev;
37f9003b 768 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
4eaeca33 769 union set_pixel_clock args;
4eaeca33
AD		 770
771 memset(&args, 0, sizeof(args));
772
a084e6ee
AD		 773 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
774 &crev))
775 return;
771fe6b9
JG		 776
777 switch (frev) {
778 case 1:
779 switch (crev) {
780 case 1:
37f9003b
AD		 781 if (clock == ATOM_DISABLE)
782 return;
783 args.v1.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 784 args.v1.usRefDiv = cpu_to_le16(ref_div);
785 args.v1.usFbDiv = cpu_to_le16(fb_div);
786 args.v1.ucFracFbDiv = frac_fb_div;
787 args.v1.ucPostDiv = post_div;
37f9003b
AD		 788 args.v1.ucPpll = pll_id;
789 args.v1.ucCRTC = crtc_id;
4eaeca33 790 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 791 break;
792 case 2:
37f9003b 793 args.v2.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 794 args.v2.usRefDiv = cpu_to_le16(ref_div);
795 args.v2.usFbDiv = cpu_to_le16(fb_div);
796 args.v2.ucFracFbDiv = frac_fb_div;
797 args.v2.ucPostDiv = post_div;
37f9003b
AD		 798 args.v2.ucPpll = pll_id;
799 args.v2.ucCRTC = crtc_id;
4eaeca33 800 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 801 break;
802 case 3:
37f9003b 803 args.v3.usPixelClock = cpu_to_le16(clock / 10);
4eaeca33
AD		 804 args.v3.usRefDiv = cpu_to_le16(ref_div);
805 args.v3.usFbDiv = cpu_to_le16(fb_div);
806 args.v3.ucFracFbDiv = frac_fb_div;
807 args.v3.ucPostDiv = post_div;
37f9003b
AD		 808 args.v3.ucPpll = pll_id;
809 args.v3.ucMiscInfo = (pll_id << 2);
6f15c506
AD		 810 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
811 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
37f9003b 812 args.v3.ucTransmitterId = encoder_id;
bcc1c2a1
AD		 813 args.v3.ucEncoderMode = encoder_mode;
814 break;
815 case 5:
37f9003b
AD		 816 args.v5.ucCRTC = crtc_id;
817 args.v5.usPixelClock = cpu_to_le16(clock / 10);
bcc1c2a1
AD		 818 args.v5.ucRefDiv = ref_div;
819 args.v5.usFbDiv = cpu_to_le16(fb_div);
820 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
821 args.v5.ucPostDiv = post_div;
822 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 823 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
824 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
df271bec
AD		 825 switch (bpc) {
826 case 8:
827 default:
828 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
829 break;
830 case 10:
831 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
832 break;
833 }
37f9003b 834 args.v5.ucTransmitterID = encoder_id;
bcc1c2a1 835 args.v5.ucEncoderMode = encoder_mode;
37f9003b 836 args.v5.ucPpll = pll_id;
771fe6b9 837 break;
f82b3ddc 838 case 6:
f1bece7f 839 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
f82b3ddc
AD		 840 args.v6.ucRefDiv = ref_div;
841 args.v6.usFbDiv = cpu_to_le16(fb_div);
842 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
843 args.v6.ucPostDiv = post_div;
844 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
8e8e523d
AD		 845 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
846 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
df271bec
AD		 847 switch (bpc) {
848 case 8:
849 default:
850 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
851 break;
852 case 10:
853 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
854 break;
855 case 12:
856 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
857 break;
858 case 16:
859 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
860 break;
861 }
f82b3ddc
AD		 862 args.v6.ucTransmitterID = encoder_id;
863 args.v6.ucEncoderMode = encoder_mode;
864 args.v6.ucPpll = pll_id;
865 break;
771fe6b9
JG		 866 default:
867 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
868 return;
869 }
870 break;
871 default:
872 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
873 return;
874 }
875
771fe6b9
JG		 876 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
877}
878
37f9003b
AD		 879static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
880{
881 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
882 struct drm_device *dev = crtc->dev;
883 struct radeon_device *rdev = dev->dev_private;
884 struct drm_encoder *encoder = NULL;
885 struct radeon_encoder *radeon_encoder = NULL;
886 u32 pll_clock = mode->clock;
887 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
888 struct radeon_pll *pll;
889 u32 adjusted_clock;
890 int encoder_mode = 0;
ba032a58
AD		 891 struct radeon_atom_ss ss;
892 bool ss_enabled = false;
df271bec 893 int bpc = 8;
37f9003b
AD		 894
895 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
896 if (encoder->crtc == crtc) {
897 radeon_encoder = to_radeon_encoder(encoder);
898 encoder_mode = atombios_get_encoder_mode(encoder);
899 break;
900 }
901 }
902
903 if (!radeon_encoder)
904 return;
905
906 switch (radeon_crtc->pll_id) {
907 case ATOM_PPLL1:
908 pll = &rdev->clock.p1pll;
909 break;
910 case ATOM_PPLL2:
911 pll = &rdev->clock.p2pll;
912 break;
913 case ATOM_DCPLL:
914 case ATOM_PPLL_INVALID:
915 default:
916 pll = &rdev->clock.dcpll;
917 break;
918 }
919
ba032a58
AD		 920 if (radeon_encoder->active_device &
921 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
922 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
923 struct drm_connector *connector =
924 radeon_get_connector_for_encoder(encoder);
925 struct radeon_connector *radeon_connector =
926 to_radeon_connector(connector);
927 struct radeon_connector_atom_dig *dig_connector =
928 radeon_connector->con_priv;
929 int dp_clock;
df271bec 930 bpc = connector->display_info.bpc;
ba032a58
AD		 931
932 switch (encoder_mode) {
996d5c59 933 case ATOM_ENCODER_MODE_DP_MST:
ba032a58
AD		 934 case ATOM_ENCODER_MODE_DP:
935 /* DP/eDP */
936 dp_clock = dig_connector->dp_clock / 10;
2307790f
AD		 937 if (ASIC_IS_DCE4(rdev))
938 ss_enabled =
939 radeon_atombios_get_asic_ss_info(rdev, &ss,
940 ASIC_INTERNAL_SS_ON_DP,
941 dp_clock);
942 else {
943 if (dp_clock == 16200) {
ba032a58 944 ss_enabled =
2307790f
AD		 945 radeon_atombios_get_ppll_ss_info(rdev, &ss,
946 ATOM_DP_SS_ID2);
8e8e523d
AD		 947 if (!ss_enabled)
948 ss_enabled =
2307790f
AD		 949 radeon_atombios_get_ppll_ss_info(rdev, &ss,
950 ATOM_DP_SS_ID1);
8e8e523d 951 } else
ba032a58
AD		 952 ss_enabled =
953 radeon_atombios_get_ppll_ss_info(rdev, &ss,
2307790f 954 ATOM_DP_SS_ID1);
ba032a58
AD		 955 }
956 break;
957 case ATOM_ENCODER_MODE_LVDS:
958 if (ASIC_IS_DCE4(rdev))
959 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
960 dig->lcd_ss_id,
961 mode->clock / 10);
962 else
963 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
964 dig->lcd_ss_id);
965 break;
966 case ATOM_ENCODER_MODE_DVI:
967 if (ASIC_IS_DCE4(rdev))
968 ss_enabled =
969 radeon_atombios_get_asic_ss_info(rdev, &ss,
970 ASIC_INTERNAL_SS_ON_TMDS,
971 mode->clock / 10);
972 break;
973 case ATOM_ENCODER_MODE_HDMI:
974 if (ASIC_IS_DCE4(rdev))
975 ss_enabled =
976 radeon_atombios_get_asic_ss_info(rdev, &ss,
977 ASIC_INTERNAL_SS_ON_HDMI,
978 mode->clock / 10);
979 break;
980 default:
981 break;
982 }
983 }
984
37f9003b 985 /* adjust pixel clock as needed */
ba032a58 986 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
37f9003b 987
64146f8b
AD		 988 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
989 /* TV seems to prefer the legacy algo on some boards */
990 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
991 &ref_div, &post_div);
992 else if (ASIC_IS_AVIVO(rdev))
619efb10
AD		 993 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
994 &ref_div, &post_div);
995 else
996 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
997 &ref_div, &post_div);
37f9003b 998
ba032a58
AD		 999 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
1000
37f9003b
AD		 1001 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1002 encoder_mode, radeon_encoder->encoder_id, mode->clock,
8e8e523d 1003 ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
37f9003b 1004
ba032a58
AD		 1005 if (ss_enabled) {
1006 /* calculate ss amount and step size */
1007 if (ASIC_IS_DCE4(rdev)) {
1008 u32 step_size;
1009 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1010 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
8e8e523d 1011 ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
ba032a58
AD		 1012 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1013 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1014 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1015 (125 * 25 * pll->reference_freq / 100);
1016 else
1017 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1018 (125 * 25 * pll->reference_freq / 100);
1019 ss.step = step_size;
1020 }
1021
1022 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
1023 }
37f9003b
AD		 1024}
1025
c9417bdd
AD		 1026static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1027 struct drm_framebuffer *fb,
1028 int x, int y, int atomic)
bcc1c2a1
AD		 1029{
1030 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1031 struct drm_device *dev = crtc->dev;
1032 struct radeon_device *rdev = dev->dev_private;
1033 struct radeon_framebuffer *radeon_fb;
4dd19b0d 1034 struct drm_framebuffer *target_fb;
bcc1c2a1
AD		 1035 struct drm_gem_object *obj;
1036 struct radeon_bo *rbo;
1037 uint64_t fb_location;
1038 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1039 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
adcfde51 1040 u32 tmp, viewport_w, viewport_h;
bcc1c2a1
AD		 1041 int r;
1042
1043 /* no fb bound */
4dd19b0d 1044 if (!atomic && !crtc->fb) {
d9fdaafb 1045 DRM_DEBUG_KMS("No FB bound\n");
bcc1c2a1
AD		 1046 return 0;
1047 }
1048
4dd19b0d
CB		 1049 if (atomic) {
1050 radeon_fb = to_radeon_framebuffer(fb);
1051 target_fb = fb;
1052 }
1053 else {
1054 radeon_fb = to_radeon_framebuffer(crtc->fb);
1055 target_fb = crtc->fb;
1056 }
bcc1c2a1 1057
4dd19b0d
CB		 1058 /* If atomic, assume fb object is pinned & idle & fenced and
1059 * just update base pointers
1060 */
bcc1c2a1 1061 obj = radeon_fb->obj;
7e4d15d9 1062 rbo = gem_to_radeon_bo(obj);
bcc1c2a1
AD		 1063 r = radeon_bo_reserve(rbo, false);
1064 if (unlikely(r != 0))
1065 return r;
4dd19b0d
CB		 1066
1067 if (atomic)
1068 fb_location = radeon_bo_gpu_offset(rbo);
1069 else {
1070 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1071 if (unlikely(r != 0)) {
1072 radeon_bo_unreserve(rbo);
1073 return -EINVAL;
1074 }
bcc1c2a1 1075 }
4dd19b0d 1076
bcc1c2a1
AD		 1077 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1078 radeon_bo_unreserve(rbo);
1079
4dd19b0d 1080 switch (target_fb->bits_per_pixel) {
bcc1c2a1
AD		 1081 case 8:
1082 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1083 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1084 break;
1085 case 15:
1086 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1087 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1088 break;
1089 case 16:
1090 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1091 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
fa6bee46
AD		 1092#ifdef __BIG_ENDIAN
1093 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1094#endif
bcc1c2a1
AD		 1095 break;
1096 case 24:
1097 case 32:
1098 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1099 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fa6bee46
AD		 1100#ifdef __BIG_ENDIAN
1101 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1102#endif
bcc1c2a1
AD		 1103 break;
1104 default:
1105 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1106 target_fb->bits_per_pixel);
bcc1c2a1
AD		 1107 return -EINVAL;
1108 }
1109
392e3722
AD		 1110 if (tiling_flags & RADEON_TILING_MACRO) {
1111 if (rdev->family >= CHIP_CAYMAN)
1112 tmp = rdev->config.cayman.tile_config;
1113 else
1114 tmp = rdev->config.evergreen.tile_config;
1115
1116 switch ((tmp & 0xf0) >> 4) {
1117 case 0: /* 4 banks */
1118 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1119 break;
1120 case 1: /* 8 banks */
1121 default:
1122 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1123 break;
1124 case 2: /* 16 banks */
1125 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1126 break;
1127 }
1128
1129 switch ((tmp & 0xf000) >> 12) {
1130 case 0: /* 1KB rows */
1131 default:
1132 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_1KB);
1133 break;
1134 case 1: /* 2KB rows */
1135 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_2KB);
1136 break;
1137 case 2: /* 4KB rows */
1138 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(EVERGREEN_ADDR_SURF_TILE_SPLIT_4KB);
1139 break;
1140 }
1141
97d66328 1142 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
392e3722 1143 } else if (tiling_flags & RADEON_TILING_MICRO)
97d66328
AD		 1144 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1145
bcc1c2a1
AD		 1146 switch (radeon_crtc->crtc_id) {
1147 case 0:
1148 WREG32(AVIVO_D1VGA_CONTROL, 0);
1149 break;
1150 case 1:
1151 WREG32(AVIVO_D2VGA_CONTROL, 0);
1152 break;
1153 case 2:
1154 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1155 break;
1156 case 3:
1157 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1158 break;
1159 case 4:
1160 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1161 break;
1162 case 5:
1163 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1164 break;
1165 default:
1166 break;
1167 }
1168
1169 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1170 upper_32_bits(fb_location));
1171 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1172 upper_32_bits(fb_location));
1173 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1174 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1175 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1176 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1177 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46 1178 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
bcc1c2a1
AD		 1179
1180 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1181 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1182 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1183 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1184 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1185 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
bcc1c2a1 1186
01f2c773 1187 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
bcc1c2a1
AD		 1188 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1189 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1190
1191 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1192 crtc->mode.vdisplay);
1193 x &= ~3;
1194 y &= ~1;
1195 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1196 (x << 16) | y);
adcfde51
AD		 1197 viewport_w = crtc->mode.hdisplay;
1198 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
bcc1c2a1 1199 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1200 (viewport_w << 16) | viewport_h);
bcc1c2a1 1201
fb9674bd
AD		 1202 /* pageflip setup */
1203 /* make sure flip is at vb rather than hb */
1204 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1205 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1206 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1207
1208 /* set pageflip to happen anywhere in vblank interval */
1209 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1210
4dd19b0d
CB		 1211 if (!atomic && fb && fb != crtc->fb) {
1212 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1213 rbo = gem_to_radeon_bo(radeon_fb->obj);
bcc1c2a1
AD		 1214 r = radeon_bo_reserve(rbo, false);
1215 if (unlikely(r != 0))
1216 return r;
1217 radeon_bo_unpin(rbo);
1218 radeon_bo_unreserve(rbo);
1219 }
1220
1221 /* Bytes per pixel may have changed */
1222 radeon_bandwidth_update(rdev);
1223
1224 return 0;
1225}
1226
4dd19b0d
CB		 1227static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1228 struct drm_framebuffer *fb,
1229 int x, int y, int atomic)
771fe6b9
JG		 1230{
1231 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1232 struct drm_device *dev = crtc->dev;
1233 struct radeon_device *rdev = dev->dev_private;
1234 struct radeon_framebuffer *radeon_fb;
1235 struct drm_gem_object *obj;
4c788679 1236 struct radeon_bo *rbo;
4dd19b0d 1237 struct drm_framebuffer *target_fb;
771fe6b9 1238 uint64_t fb_location;
e024e110 1239 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
fa6bee46 1240 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
adcfde51 1241 u32 tmp, viewport_w, viewport_h;
4c788679 1242 int r;
771fe6b9 1243
2de3b484 1244 /* no fb bound */
4dd19b0d 1245 if (!atomic && !crtc->fb) {
d9fdaafb 1246 DRM_DEBUG_KMS("No FB bound\n");
2de3b484
JG		 1247 return 0;
1248 }
771fe6b9 1249
4dd19b0d
CB		 1250 if (atomic) {
1251 radeon_fb = to_radeon_framebuffer(fb);
1252 target_fb = fb;
1253 }
1254 else {
1255 radeon_fb = to_radeon_framebuffer(crtc->fb);
1256 target_fb = crtc->fb;
1257 }
771fe6b9
JG		 1258
1259 obj = radeon_fb->obj;
7e4d15d9 1260 rbo = gem_to_radeon_bo(obj);
4c788679
JG		 1261 r = radeon_bo_reserve(rbo, false);
1262 if (unlikely(r != 0))
1263 return r;
4dd19b0d
CB		 1264
1265 /* If atomic, assume fb object is pinned & idle & fenced and
1266 * just update base pointers
1267 */
1268 if (atomic)
1269 fb_location = radeon_bo_gpu_offset(rbo);
1270 else {
1271 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1272 if (unlikely(r != 0)) {
1273 radeon_bo_unreserve(rbo);
1274 return -EINVAL;
1275 }
771fe6b9 1276 }
4c788679
JG		 1277 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1278 radeon_bo_unreserve(rbo);
771fe6b9 1279
4dd19b0d 1280 switch (target_fb->bits_per_pixel) {
41456df2
DA		 1281 case 8:
1282 fb_format =
1283 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1284 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1285 break;
771fe6b9
JG		 1286 case 15:
1287 fb_format =
1288 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1289 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1290 break;
1291 case 16:
1292 fb_format =
1293 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1294 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
fa6bee46
AD		 1295#ifdef __BIG_ENDIAN
1296 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1297#endif
771fe6b9
JG		 1298 break;
1299 case 24:
1300 case 32:
1301 fb_format =
1302 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1303 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
fa6bee46
AD		 1304#ifdef __BIG_ENDIAN
1305 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1306#endif
771fe6b9
JG		 1307 break;
1308 default:
1309 DRM_ERROR("Unsupported screen depth %d\n",
4dd19b0d 1310 target_fb->bits_per_pixel);
771fe6b9
JG		 1311 return -EINVAL;
1312 }
1313
40c4ac1c
AD		 1314 if (rdev->family >= CHIP_R600) {
1315 if (tiling_flags & RADEON_TILING_MACRO)
1316 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1317 else if (tiling_flags & RADEON_TILING_MICRO)
1318 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1319 } else {
1320 if (tiling_flags & RADEON_TILING_MACRO)
1321 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
cf2f05d3 1322
40c4ac1c
AD		 1323 if (tiling_flags & RADEON_TILING_MICRO)
1324 fb_format |= AVIVO_D1GRPH_TILED;
1325 }
e024e110 1326
771fe6b9
JG		 1327 if (radeon_crtc->crtc_id == 0)
1328 WREG32(AVIVO_D1VGA_CONTROL, 0);
1329 else
1330 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 1331
1332 if (rdev->family >= CHIP_RV770) {
1333 if (radeon_crtc->crtc_id) {
95347871
AD		 1334 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1335 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf 1336 } else {
95347871
AD		 1337 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1338 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
c290dadf
AD		 1339 }
1340 }
771fe6b9
JG		 1341 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1342 (u32) fb_location);
1343 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1344 radeon_crtc->crtc_offset, (u32) fb_location);
1345 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
fa6bee46
AD		 1346 if (rdev->family >= CHIP_R600)
1347 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
771fe6b9
JG		 1348
1349 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1350 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1351 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1352 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
4dd19b0d
CB		 1353 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1354 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
771fe6b9 1355
01f2c773 1356 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
771fe6b9
JG		 1357 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1358 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1359
1360 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1361 crtc->mode.vdisplay);
1362 x &= ~3;
1363 y &= ~1;
1364 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1365 (x << 16) | y);
adcfde51
AD		 1366 viewport_w = crtc->mode.hdisplay;
1367 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
771fe6b9 1368 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
adcfde51 1369 (viewport_w << 16) | viewport_h);
771fe6b9 1370
fb9674bd
AD		 1371 /* pageflip setup */
1372 /* make sure flip is at vb rather than hb */
1373 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1374 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1375 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1376
1377 /* set pageflip to happen anywhere in vblank interval */
1378 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1379
4dd19b0d
CB		 1380 if (!atomic && fb && fb != crtc->fb) {
1381 radeon_fb = to_radeon_framebuffer(fb);
7e4d15d9 1382 rbo = gem_to_radeon_bo(radeon_fb->obj);
4c788679
JG		 1383 r = radeon_bo_reserve(rbo, false);
1384 if (unlikely(r != 0))
1385 return r;
1386 radeon_bo_unpin(rbo);
1387 radeon_bo_unreserve(rbo);
771fe6b9 1388 }
f30f37de
MD		 1389
1390 /* Bytes per pixel may have changed */
1391 radeon_bandwidth_update(rdev);
1392
771fe6b9
JG		 1393 return 0;
1394}
1395
54f088a9
AD		 1396int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1397 struct drm_framebuffer *old_fb)
1398{
1399 struct drm_device *dev = crtc->dev;
1400 struct radeon_device *rdev = dev->dev_private;
1401
bcc1c2a1 1402 if (ASIC_IS_DCE4(rdev))
c9417bdd 1403 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
4dd19b0d
CB		 1404 else if (ASIC_IS_AVIVO(rdev))
1405 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1406 else
1407 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1408}
1409
1410int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1411 struct drm_framebuffer *fb,
21c74a8e 1412 int x, int y, enum mode_set_atomic state)
4dd19b0d
CB		 1413{
1414 struct drm_device *dev = crtc->dev;
1415 struct radeon_device *rdev = dev->dev_private;
1416
1417 if (ASIC_IS_DCE4(rdev))
c9417bdd 1418 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
bcc1c2a1 1419 else if (ASIC_IS_AVIVO(rdev))
4dd19b0d 1420 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9 1421 else
4dd19b0d 1422 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
54f088a9
AD		 1423}
1424
615e0cb6
AD		 1425/* properly set additional regs when using atombios */
1426static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1427{
1428 struct drm_device *dev = crtc->dev;
1429 struct radeon_device *rdev = dev->dev_private;
1430 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1431 u32 disp_merge_cntl;
1432
1433 switch (radeon_crtc->crtc_id) {
1434 case 0:
1435 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1436 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1437 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1438 break;
1439 case 1:
1440 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1441 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1442 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1443 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1444 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1445 break;
1446 }
1447}
1448
bcc1c2a1
AD		 1449static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1450{
1451 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1452 struct drm_device *dev = crtc->dev;
1453 struct radeon_device *rdev = dev->dev_private;
1454 struct drm_encoder *test_encoder;
1455 struct drm_crtc *test_crtc;
1456 uint32_t pll_in_use = 0;
1457
1458 if (ASIC_IS_DCE4(rdev)) {
bcc1c2a1
AD		 1459 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1460 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
86a94def
AD		 1461 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1462 * depending on the asic:
1463 * DCE4: PPLL or ext clock
1464 * DCE5: DCPLL or ext clock
1465 *
1466 * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1467 * PPLL/DCPLL programming and only program the DP DTO for the
1468 * crtc virtual pixel clock.
1469 */
996d5c59 1470 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
86a94def 1471 if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
bcc1c2a1
AD		 1472 return ATOM_PPLL_INVALID;
1473 }
1474 }
1475 }
1476
1477 /* otherwise, pick one of the plls */
1478 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1479 struct radeon_crtc *radeon_test_crtc;
1480
1481 if (crtc == test_crtc)
1482 continue;
1483
1484 radeon_test_crtc = to_radeon_crtc(test_crtc);
1485 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1486 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1487 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1488 }
1489 if (!(pll_in_use & 1))
1490 return ATOM_PPLL1;
1491 return ATOM_PPLL2;
1492 } else
1493 return radeon_crtc->crtc_id;
1494
1495}
1496
771fe6b9
JG		 1497int atombios_crtc_mode_set(struct drm_crtc *crtc,
1498 struct drm_display_mode *mode,
1499 struct drm_display_mode *adjusted_mode,
1500 int x, int y, struct drm_framebuffer *old_fb)
1501{
1502 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1503 struct drm_device *dev = crtc->dev;
1504 struct radeon_device *rdev = dev->dev_private;
54bfe496
AD		 1505 struct drm_encoder *encoder;
1506 bool is_tvcv = false;
771fe6b9 1507
54bfe496
AD		 1508 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1509 /* find tv std */
1510 if (encoder->crtc == crtc) {
1511 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1512 if (radeon_encoder->active_device &
1513 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1514 is_tvcv = true;
1515 }
1516 }
771fe6b9 1517
bcc1c2a1 1518 /* always set DCPLL */
ba032a58
AD		 1519 if (ASIC_IS_DCE4(rdev)) {
1520 struct radeon_atom_ss ss;
1521 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1522 ASIC_INTERNAL_SS_ON_DCPLL,
1523 rdev->clock.default_dispclk);
1524 if (ss_enabled)
1525 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
f82b3ddc
AD		 1526 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1527 atombios_crtc_set_dcpll(crtc, rdev->clock.default_dispclk);
ba032a58
AD		 1528 if (ss_enabled)
1529 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1530 }
771fe6b9 1531 atombios_crtc_set_pll(crtc, adjusted_mode);
771fe6b9 1532
54bfe496 1533 if (ASIC_IS_DCE4(rdev))
bcc1c2a1 1534 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
54bfe496
AD		 1535 else if (ASIC_IS_AVIVO(rdev)) {
1536 if (is_tvcv)
1537 atombios_crtc_set_timing(crtc, adjusted_mode);
1538 else
1539 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1540 } else {
bcc1c2a1 1541 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1542 if (radeon_crtc->crtc_id == 0)
1543 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1544 radeon_legacy_atom_fixup(crtc);
771fe6b9 1545 }
bcc1c2a1 1546 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1547 atombios_overscan_setup(crtc, mode, adjusted_mode);
1548 atombios_scaler_setup(crtc);
771fe6b9
JG		 1549 return 0;
1550}
1551
1552static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1553 struct drm_display_mode *mode,
1554 struct drm_display_mode *adjusted_mode)
1555{
c93bb85b
JG		 1556 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1557 return false;
771fe6b9
JG		 1558 return true;
1559}
1560
1561static void atombios_crtc_prepare(struct drm_crtc *crtc)
1562{
267364ac
AD		 1563 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1564
1565 /* pick pll */
1566 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1567
37b4390e 1568 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1569 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1570}
1571
1572static void atombios_crtc_commit(struct drm_crtc *crtc)
1573{
1574 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1575 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1576}
1577
37f9003b
AD		 1578static void atombios_crtc_disable(struct drm_crtc *crtc)
1579{
1580 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
8e8e523d
AD		 1581 struct radeon_atom_ss ss;
1582
37f9003b
AD		 1583 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1584
1585 switch (radeon_crtc->pll_id) {
1586 case ATOM_PPLL1:
1587 case ATOM_PPLL2:
1588 /* disable the ppll */
1589 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
8e8e523d 1590 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
37f9003b
AD		 1591 break;
1592 default:
1593 break;
1594 }
1595 radeon_crtc->pll_id = -1;
1596}
1597
771fe6b9
JG		 1598static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1599 .dpms = atombios_crtc_dpms,
1600 .mode_fixup = atombios_crtc_mode_fixup,
1601 .mode_set = atombios_crtc_mode_set,
1602 .mode_set_base = atombios_crtc_set_base,
4dd19b0d 1603 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
771fe6b9
JG		 1604 .prepare = atombios_crtc_prepare,
1605 .commit = atombios_crtc_commit,
068143d3 1606 .load_lut = radeon_crtc_load_lut,
37f9003b 1607 .disable = atombios_crtc_disable,
771fe6b9
JG		 1608};
1609
1610void radeon_atombios_init_crtc(struct drm_device *dev,
1611 struct radeon_crtc *radeon_crtc)
1612{
bcc1c2a1
AD		 1613 struct radeon_device *rdev = dev->dev_private;
1614
1615 if (ASIC_IS_DCE4(rdev)) {
1616 switch (radeon_crtc->crtc_id) {
1617 case 0:
1618 default:
12d7798f 1619 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1620 break;
1621 case 1:
12d7798f 1622 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1623 break;
1624 case 2:
12d7798f 1625 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1626 break;
1627 case 3:
12d7798f 1628 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1629 break;
1630 case 4:
12d7798f 1631 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1632 break;
1633 case 5:
12d7798f 1634 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1635 break;
1636 }
1637 } else {
1638 if (radeon_crtc->crtc_id == 1)
1639 radeon_crtc->crtc_offset =
1640 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1641 else
1642 radeon_crtc->crtc_offset = 0;
1643 }
1644 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1645 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1646}
Linux 6.x block layer and io_uring tree(s)