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Merge branch 'bkl/procfs' of git://git.kernel.org/pub/scm/linux/kernel/git/frederic...
[linux-2.6-block.git] / drivers / gpu / drm / radeon / atombios_crtc.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/radeon_drm.h>
29#include "radeon_fixed.h"
30#include "radeon.h"
31#include "atom.h"
32#include "atom-bits.h"
33
c93bb85b
JG		 34static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
37{
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43 int a1, a2;
44
45 memset(&args, 0, sizeof(args));
46
47 args.usOverscanRight = 0;
48 args.usOverscanLeft = 0;
49 args.usOverscanBottom = 0;
50 args.usOverscanTop = 0;
51 args.ucCRTC = radeon_crtc->crtc_id;
52
53 switch (radeon_crtc->rmx_type) {
54 case RMX_CENTER:
55 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
56 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
57 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
58 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
59 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
60 break;
61 case RMX_ASPECT:
62 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
63 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
64
65 if (a1 > a2) {
66 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
67 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
68 } else if (a2 > a1) {
69 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
71 }
72 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
73 break;
74 case RMX_FULL:
75 default:
76 args.usOverscanRight = 0;
77 args.usOverscanLeft = 0;
78 args.usOverscanBottom = 0;
79 args.usOverscanTop = 0;
80 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 break;
82 }
83}
84
85static void atombios_scaler_setup(struct drm_crtc *crtc)
86{
87 struct drm_device *dev = crtc->dev;
88 struct radeon_device *rdev = dev->dev_private;
89 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
90 ENABLE_SCALER_PS_ALLOCATION args;
91 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
4ce001ab 92
c93bb85b
JG		 93 /* fixme - fill in enc_priv for atom dac */
94 enum radeon_tv_std tv_std = TV_STD_NTSC;
4ce001ab
DA		 95 bool is_tv = false, is_cv = false;
96 struct drm_encoder *encoder;
c93bb85b
JG		 97
98 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
99 return;
100
4ce001ab
DA		 101 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
102 /* find tv std */
103 if (encoder->crtc == crtc) {
104 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
105 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
106 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
107 tv_std = tv_dac->tv_std;
108 is_tv = true;
109 }
110 }
111 }
112
c93bb85b
JG		 113 memset(&args, 0, sizeof(args));
114
115 args.ucScaler = radeon_crtc->crtc_id;
116
4ce001ab 117 if (is_tv) {
c93bb85b
JG		 118 switch (tv_std) {
119 case TV_STD_NTSC:
120 default:
121 args.ucTVStandard = ATOM_TV_NTSC;
122 break;
123 case TV_STD_PAL:
124 args.ucTVStandard = ATOM_TV_PAL;
125 break;
126 case TV_STD_PAL_M:
127 args.ucTVStandard = ATOM_TV_PALM;
128 break;
129 case TV_STD_PAL_60:
130 args.ucTVStandard = ATOM_TV_PAL60;
131 break;
132 case TV_STD_NTSC_J:
133 args.ucTVStandard = ATOM_TV_NTSCJ;
134 break;
135 case TV_STD_SCART_PAL:
136 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
137 break;
138 case TV_STD_SECAM:
139 args.ucTVStandard = ATOM_TV_SECAM;
140 break;
141 case TV_STD_PAL_CN:
142 args.ucTVStandard = ATOM_TV_PALCN;
143 break;
144 }
145 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
4ce001ab 146 } else if (is_cv) {
c93bb85b
JG		 147 args.ucTVStandard = ATOM_TV_CV;
148 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
149 } else {
150 switch (radeon_crtc->rmx_type) {
151 case RMX_FULL:
152 args.ucEnable = ATOM_SCALER_EXPANSION;
153 break;
154 case RMX_CENTER:
155 args.ucEnable = ATOM_SCALER_CENTER;
156 break;
157 case RMX_ASPECT:
158 args.ucEnable = ATOM_SCALER_EXPANSION;
159 break;
160 default:
161 if (ASIC_IS_AVIVO(rdev))
162 args.ucEnable = ATOM_SCALER_DISABLE;
163 else
164 args.ucEnable = ATOM_SCALER_CENTER;
165 break;
166 }
167 }
168 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
4ce001ab
DA		 169 if ((is_tv || is_cv)
170 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
171 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
c93bb85b
JG		 172 }
173}
174
771fe6b9
JG		 175static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
176{
177 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
178 struct drm_device *dev = crtc->dev;
179 struct radeon_device *rdev = dev->dev_private;
180 int index =
181 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
182 ENABLE_CRTC_PS_ALLOCATION args;
183
184 memset(&args, 0, sizeof(args));
185
186 args.ucCRTC = radeon_crtc->crtc_id;
187 args.ucEnable = lock;
188
189 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
190}
191
192static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
193{
194 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
195 struct drm_device *dev = crtc->dev;
196 struct radeon_device *rdev = dev->dev_private;
197 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
198 ENABLE_CRTC_PS_ALLOCATION args;
199
200 memset(&args, 0, sizeof(args));
201
202 args.ucCRTC = radeon_crtc->crtc_id;
203 args.ucEnable = state;
204
205 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
206}
207
208static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
209{
210 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
211 struct drm_device *dev = crtc->dev;
212 struct radeon_device *rdev = dev->dev_private;
213 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
214 ENABLE_CRTC_PS_ALLOCATION args;
215
216 memset(&args, 0, sizeof(args));
217
218 args.ucCRTC = radeon_crtc->crtc_id;
219 args.ucEnable = state;
220
221 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
222}
223
224static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
225{
226 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
227 struct drm_device *dev = crtc->dev;
228 struct radeon_device *rdev = dev->dev_private;
229 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
230 BLANK_CRTC_PS_ALLOCATION args;
231
232 memset(&args, 0, sizeof(args));
233
234 args.ucCRTC = radeon_crtc->crtc_id;
235 args.ucBlanking = state;
236
237 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
238}
239
240void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
241{
242 struct drm_device *dev = crtc->dev;
243 struct radeon_device *rdev = dev->dev_private;
500b7587 244 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 245
246 switch (mode) {
247 case DRM_MODE_DPMS_ON:
37b4390e 248 atombios_enable_crtc(crtc, ATOM_ENABLE);
771fe6b9 249 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 250 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
251 atombios_blank_crtc(crtc, ATOM_DISABLE);
bcc1c2a1
AD		 252 /* XXX re-enable when interrupt support is added */
253 if (!ASIC_IS_DCE4(rdev))
254 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
500b7587 255 radeon_crtc_load_lut(crtc);
771fe6b9
JG		 256 break;
257 case DRM_MODE_DPMS_STANDBY:
258 case DRM_MODE_DPMS_SUSPEND:
259 case DRM_MODE_DPMS_OFF:
bcc1c2a1
AD		 260 /* XXX re-enable when interrupt support is added */
261 if (!ASIC_IS_DCE4(rdev))
262 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
37b4390e 263 atombios_blank_crtc(crtc, ATOM_ENABLE);
771fe6b9 264 if (ASIC_IS_DCE3(rdev))
37b4390e
AD		 265 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
266 atombios_enable_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 267 break;
268 }
771fe6b9
JG		 269}
270
271static void
272atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
5a9bcacc 273 struct drm_display_mode *mode)
771fe6b9 274{
5a9bcacc 275 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 276 struct drm_device *dev = crtc->dev;
277 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 278 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
771fe6b9 279 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
5a9bcacc 280 u16 misc = 0;
771fe6b9 281
5a9bcacc
AD		 282 memset(&args, 0, sizeof(args));
283 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay);
284 args.usH_Blanking_Time =
285 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay);
286 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay);
287 args.usV_Blanking_Time =
288 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay);
289 args.usH_SyncOffset =
290 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay);
291 args.usH_SyncWidth =
292 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
293 args.usV_SyncOffset =
294 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay);
295 args.usV_SyncWidth =
296 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
297 /*args.ucH_Border = mode->hborder;*/
298 /*args.ucV_Border = mode->vborder;*/
299
300 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
301 misc |= ATOM_VSYNC_POLARITY;
302 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
303 misc |= ATOM_HSYNC_POLARITY;
304 if (mode->flags & DRM_MODE_FLAG_CSYNC)
305 misc |= ATOM_COMPOSITESYNC;
306 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
307 misc |= ATOM_INTERLACE;
308 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
309 misc |= ATOM_DOUBLE_CLOCK_MODE;
310
311 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
312 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 313
5a9bcacc 314 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 315}
316
5a9bcacc
AD		 317static void atombios_crtc_set_timing(struct drm_crtc *crtc,
318 struct drm_display_mode *mode)
771fe6b9 319{
5a9bcacc 320 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
771fe6b9
JG		 321 struct drm_device *dev = crtc->dev;
322 struct radeon_device *rdev = dev->dev_private;
5a9bcacc 323 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
771fe6b9 324 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
5a9bcacc 325 u16 misc = 0;
771fe6b9 326
5a9bcacc
AD		 327 memset(&args, 0, sizeof(args));
328 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
329 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
330 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
331 args.usH_SyncWidth =
332 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
333 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
334 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
335 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
336 args.usV_SyncWidth =
337 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
338
339 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
340 misc |= ATOM_VSYNC_POLARITY;
341 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
342 misc |= ATOM_HSYNC_POLARITY;
343 if (mode->flags & DRM_MODE_FLAG_CSYNC)
344 misc |= ATOM_COMPOSITESYNC;
345 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
346 misc |= ATOM_INTERLACE;
347 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
348 misc |= ATOM_DOUBLE_CLOCK_MODE;
349
350 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
351 args.ucCRTC = radeon_crtc->crtc_id;
771fe6b9 352
5a9bcacc 353 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
771fe6b9
JG		 354}
355
b792210e
AD		 356static void atombios_disable_ss(struct drm_crtc *crtc)
357{
358 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
359 struct drm_device *dev = crtc->dev;
360 struct radeon_device *rdev = dev->dev_private;
361 u32 ss_cntl;
362
363 if (ASIC_IS_DCE4(rdev)) {
364 switch (radeon_crtc->pll_id) {
365 case ATOM_PPLL1:
366 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
367 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
368 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
369 break;
370 case ATOM_PPLL2:
371 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
372 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
373 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
374 break;
375 case ATOM_DCPLL:
376 case ATOM_PPLL_INVALID:
377 return;
378 }
379 } else if (ASIC_IS_AVIVO(rdev)) {
380 switch (radeon_crtc->pll_id) {
381 case ATOM_PPLL1:
382 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
383 ss_cntl &= ~1;
384 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
385 break;
386 case ATOM_PPLL2:
387 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
388 ss_cntl &= ~1;
389 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
390 break;
391 case ATOM_DCPLL:
392 case ATOM_PPLL_INVALID:
393 return;
394 }
395 }
396}
397
398
26b9fc3a
AD		 399union atom_enable_ss {
400 ENABLE_LVDS_SS_PARAMETERS legacy;
401 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
402};
403
b792210e 404static void atombios_enable_ss(struct drm_crtc *crtc)
ebbe1cb9
AD		 405{
406 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
407 struct drm_device *dev = crtc->dev;
408 struct radeon_device *rdev = dev->dev_private;
409 struct drm_encoder *encoder = NULL;
410 struct radeon_encoder *radeon_encoder = NULL;
411 struct radeon_encoder_atom_dig *dig = NULL;
412 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
26b9fc3a 413 union atom_enable_ss args;
ebbe1cb9
AD		 414 uint16_t percentage = 0;
415 uint8_t type = 0, step = 0, delay = 0, range = 0;
416
bcc1c2a1
AD		 417 /* XXX add ss support for DCE4 */
418 if (ASIC_IS_DCE4(rdev))
419 return;
420
ebbe1cb9
AD		 421 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
422 if (encoder->crtc == crtc) {
423 radeon_encoder = to_radeon_encoder(encoder);
ebbe1cb9 424 /* only enable spread spectrum on LVDS */
d11aa88b
AD		 425 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
426 dig = radeon_encoder->enc_priv;
427 if (dig && dig->ss) {
428 percentage = dig->ss->percentage;
429 type = dig->ss->type;
430 step = dig->ss->step;
431 delay = dig->ss->delay;
432 range = dig->ss->range;
b792210e 433 } else
d11aa88b 434 return;
b792210e 435 } else
ebbe1cb9
AD		 436 return;
437 break;
438 }
439 }
440
441 if (!radeon_encoder)
442 return;
443
26b9fc3a 444 memset(&args, 0, sizeof(args));
ebbe1cb9 445 if (ASIC_IS_AVIVO(rdev)) {
26b9fc3a
AD		 446 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
447 args.v1.ucSpreadSpectrumType = type;
448 args.v1.ucSpreadSpectrumStep = step;
449 args.v1.ucSpreadSpectrumDelay = delay;
450 args.v1.ucSpreadSpectrumRange = range;
451 args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
b792210e 452 args.v1.ucEnable = ATOM_ENABLE;
ebbe1cb9 453 } else {
26b9fc3a
AD		 454 args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
455 args.legacy.ucSpreadSpectrumType = type;
456 args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
457 args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
b792210e 458 args.legacy.ucEnable = ATOM_ENABLE;
ebbe1cb9 459 }
26b9fc3a 460 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
ebbe1cb9
AD		 461}
462
4eaeca33
AD		 463union adjust_pixel_clock {
464 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
bcc1c2a1 465 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
4eaeca33
AD		 466};
467
468static u32 atombios_adjust_pll(struct drm_crtc *crtc,
469 struct drm_display_mode *mode,
470 struct radeon_pll *pll)
771fe6b9 471{
771fe6b9
JG		 472 struct drm_device *dev = crtc->dev;
473 struct radeon_device *rdev = dev->dev_private;
474 struct drm_encoder *encoder = NULL;
475 struct radeon_encoder *radeon_encoder = NULL;
4eaeca33 476 u32 adjusted_clock = mode->clock;
bcc1c2a1 477 int encoder_mode = 0;
fc10332b 478
4eaeca33
AD		 479 /* reset the pll flags */
480 pll->flags = 0;
771fe6b9 481
7c27f87d
AD		 482 /* select the PLL algo */
483 if (ASIC_IS_AVIVO(rdev)) {
383be5d1
AD		 484 if (radeon_new_pll == 0)
485 pll->algo = PLL_ALGO_LEGACY;
486 else
487 pll->algo = PLL_ALGO_NEW;
488 } else {
489 if (radeon_new_pll == 1)
490 pll->algo = PLL_ALGO_NEW;
7c27f87d
AD		 491 else
492 pll->algo = PLL_ALGO_LEGACY;
383be5d1 493 }
7c27f87d 494
771fe6b9 495 if (ASIC_IS_AVIVO(rdev)) {
eb1300bc
AD		 496 if ((rdev->family == CHIP_RS600) ||
497 (rdev->family == CHIP_RS690) ||
498 (rdev->family == CHIP_RS740))
fc10332b
AD		 499 pll->flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
500 RADEON_PLL_PREFER_CLOSEST_LOWER);
eb1300bc 501
771fe6b9 502 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
fc10332b 503 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 504 else
fc10332b 505 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9 506 } else {
fc10332b 507 pll->flags |= RADEON_PLL_LEGACY;
771fe6b9
JG		 508
509 if (mode->clock > 200000) /* range limits??? */
fc10332b 510 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
771fe6b9 511 else
fc10332b 512 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
771fe6b9
JG		 513
514 }
515
516 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
517 if (encoder->crtc == crtc) {
4eaeca33 518 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 519 encoder_mode = atombios_get_encoder_mode(encoder);
4eaeca33
AD		 520 if (ASIC_IS_AVIVO(rdev)) {
521 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
522 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
523 adjusted_clock = mode->clock * 2;
a1a4b23b
AD		 524 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
525 pll->algo = PLL_ALGO_LEGACY;
526 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
527 }
4eaeca33
AD		 528 } else {
529 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
fc10332b 530 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
4eaeca33 531 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
fc10332b 532 pll->flags |= RADEON_PLL_USE_REF_DIV;
771fe6b9 533 }
3ce0a23d 534 break;
771fe6b9
JG		 535 }
536 }
537
2606c886
AD		 538 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
539 * accordingly based on the encoder/transmitter to work around
540 * special hw requirements.
541 */
542 if (ASIC_IS_DCE3(rdev)) {
4eaeca33 543 union adjust_pixel_clock args;
4eaeca33
AD		 544 u8 frev, crev;
545 int index;
2606c886 546
2606c886 547 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
a084e6ee
AD		 548 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
549 &crev))
550 return adjusted_clock;
4eaeca33
AD		 551
552 memset(&args, 0, sizeof(args));
553
554 switch (frev) {
555 case 1:
556 switch (crev) {
557 case 1:
558 case 2:
559 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
560 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
bcc1c2a1 561 args.v1.ucEncodeMode = encoder_mode;
4eaeca33
AD		 562
563 atom_execute_table(rdev->mode_info.atom_context,
564 index, (uint32_t *)&args);
565 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
566 break;
bcc1c2a1
AD		 567 case 3:
568 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
569 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
570 args.v3.sInput.ucEncodeMode = encoder_mode;
571 args.v3.sInput.ucDispPllConfig = 0;
572 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
573 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
574
575 if (encoder_mode == ATOM_ENCODER_MODE_DP)
576 args.v3.sInput.ucDispPllConfig |=
577 DISPPLL_CONFIG_COHERENT_MODE;
578 else {
579 if (dig->coherent_mode)
580 args.v3.sInput.ucDispPllConfig |=
581 DISPPLL_CONFIG_COHERENT_MODE;
582 if (mode->clock > 165000)
583 args.v3.sInput.ucDispPllConfig |=
584 DISPPLL_CONFIG_DUAL_LINK;
585 }
586 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
587 /* may want to enable SS on DP/eDP eventually */
9f998ad7
AD		 588 /*args.v3.sInput.ucDispPllConfig |=
589 DISPPLL_CONFIG_SS_ENABLE;*/
590 if (encoder_mode == ATOM_ENCODER_MODE_DP)
bcc1c2a1 591 args.v3.sInput.ucDispPllConfig |=
9f998ad7
AD		 592 DISPPLL_CONFIG_COHERENT_MODE;
593 else {
594 if (mode->clock > 165000)
595 args.v3.sInput.ucDispPllConfig |=
596 DISPPLL_CONFIG_DUAL_LINK;
597 }
bcc1c2a1
AD		 598 }
599 atom_execute_table(rdev->mode_info.atom_context,
600 index, (uint32_t *)&args);
601 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
602 if (args.v3.sOutput.ucRefDiv) {
603 pll->flags |= RADEON_PLL_USE_REF_DIV;
604 pll->reference_div = args.v3.sOutput.ucRefDiv;
605 }
606 if (args.v3.sOutput.ucPostDiv) {
607 pll->flags |= RADEON_PLL_USE_POST_DIV;
608 pll->post_div = args.v3.sOutput.ucPostDiv;
609 }
610 break;
4eaeca33
AD		 611 default:
612 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
613 return adjusted_clock;
614 }
615 break;
616 default:
617 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
618 return adjusted_clock;
619 }
d56ef9c8 620 }
4eaeca33
AD		 621 return adjusted_clock;
622}
623
624union set_pixel_clock {
625 SET_PIXEL_CLOCK_PS_ALLOCATION base;
626 PIXEL_CLOCK_PARAMETERS v1;
627 PIXEL_CLOCK_PARAMETERS_V2 v2;
628 PIXEL_CLOCK_PARAMETERS_V3 v3;
bcc1c2a1 629 PIXEL_CLOCK_PARAMETERS_V5 v5;
4eaeca33
AD		 630};
631
bcc1c2a1
AD		 632static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
633{
634 struct drm_device *dev = crtc->dev;
635 struct radeon_device *rdev = dev->dev_private;
636 u8 frev, crev;
637 int index;
638 union set_pixel_clock args;
639
640 memset(&args, 0, sizeof(args));
641
642 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 643 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
644 &crev))
645 return;
bcc1c2a1
AD		 646
647 switch (frev) {
648 case 1:
649 switch (crev) {
650 case 5:
651 /* if the default dcpll clock is specified,
652 * SetPixelClock provides the dividers
653 */
654 args.v5.ucCRTC = ATOM_CRTC_INVALID;
655 args.v5.usPixelClock = rdev->clock.default_dispclk;
656 args.v5.ucPpll = ATOM_DCPLL;
657 break;
658 default:
659 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
660 return;
661 }
662 break;
663 default:
664 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
665 return;
666 }
667 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
668}
669
670static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
4eaeca33
AD		 671{
672 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
673 struct drm_device *dev = crtc->dev;
674 struct radeon_device *rdev = dev->dev_private;
675 struct drm_encoder *encoder = NULL;
676 struct radeon_encoder *radeon_encoder = NULL;
677 u8 frev, crev;
678 int index;
679 union set_pixel_clock args;
680 u32 pll_clock = mode->clock;
681 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
682 struct radeon_pll *pll;
683 u32 adjusted_clock;
bcc1c2a1 684 int encoder_mode = 0;
4eaeca33
AD		 685
686 memset(&args, 0, sizeof(args));
687
688 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
689 if (encoder->crtc == crtc) {
690 radeon_encoder = to_radeon_encoder(encoder);
bcc1c2a1 691 encoder_mode = atombios_get_encoder_mode(encoder);
4eaeca33
AD		 692 break;
693 }
694 }
695
696 if (!radeon_encoder)
697 return;
698
bcc1c2a1
AD		 699 switch (radeon_crtc->pll_id) {
700 case ATOM_PPLL1:
4eaeca33 701 pll = &rdev->clock.p1pll;
bcc1c2a1
AD		 702 break;
703 case ATOM_PPLL2:
4eaeca33 704 pll = &rdev->clock.p2pll;
bcc1c2a1
AD		 705 break;
706 case ATOM_DCPLL:
707 case ATOM_PPLL_INVALID:
708 pll = &rdev->clock.dcpll;
709 break;
710 }
4eaeca33
AD		 711
712 /* adjust pixel clock as needed */
713 adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
2606c886 714
7c27f87d
AD		 715 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
716 &ref_div, &post_div);
771fe6b9 717
39deb2d6 718 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
a084e6ee
AD		 719 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
720 &crev))
721 return;
771fe6b9
JG		 722
723 switch (frev) {
724 case 1:
725 switch (crev) {
726 case 1:
4eaeca33
AD		 727 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
728 args.v1.usRefDiv = cpu_to_le16(ref_div);
729 args.v1.usFbDiv = cpu_to_le16(fb_div);
730 args.v1.ucFracFbDiv = frac_fb_div;
731 args.v1.ucPostDiv = post_div;
bcc1c2a1 732 args.v1.ucPpll = radeon_crtc->pll_id;
4eaeca33
AD		 733 args.v1.ucCRTC = radeon_crtc->crtc_id;
734 args.v1.ucRefDivSrc = 1;
771fe6b9
JG		 735 break;
736 case 2:
4eaeca33
AD		 737 args.v2.usPixelClock = cpu_to_le16(mode->clock / 10);
738 args.v2.usRefDiv = cpu_to_le16(ref_div);
739 args.v2.usFbDiv = cpu_to_le16(fb_div);
740 args.v2.ucFracFbDiv = frac_fb_div;
741 args.v2.ucPostDiv = post_div;
bcc1c2a1 742 args.v2.ucPpll = radeon_crtc->pll_id;
4eaeca33
AD		 743 args.v2.ucCRTC = radeon_crtc->crtc_id;
744 args.v2.ucRefDivSrc = 1;
771fe6b9
JG		 745 break;
746 case 3:
4eaeca33
AD		 747 args.v3.usPixelClock = cpu_to_le16(mode->clock / 10);
748 args.v3.usRefDiv = cpu_to_le16(ref_div);
749 args.v3.usFbDiv = cpu_to_le16(fb_div);
750 args.v3.ucFracFbDiv = frac_fb_div;
751 args.v3.ucPostDiv = post_div;
bcc1c2a1
AD		 752 args.v3.ucPpll = radeon_crtc->pll_id;
753 args.v3.ucMiscInfo = (radeon_crtc->pll_id << 2);
4eaeca33 754 args.v3.ucTransmitterId = radeon_encoder->encoder_id;
bcc1c2a1
AD		 755 args.v3.ucEncoderMode = encoder_mode;
756 break;
757 case 5:
758 args.v5.ucCRTC = radeon_crtc->crtc_id;
759 args.v5.usPixelClock = cpu_to_le16(mode->clock / 10);
760 args.v5.ucRefDiv = ref_div;
761 args.v5.usFbDiv = cpu_to_le16(fb_div);
762 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
763 args.v5.ucPostDiv = post_div;
764 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
765 args.v5.ucTransmitterID = radeon_encoder->encoder_id;
766 args.v5.ucEncoderMode = encoder_mode;
767 args.v5.ucPpll = radeon_crtc->pll_id;
771fe6b9
JG		 768 break;
769 default:
770 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
771 return;
772 }
773 break;
774 default:
775 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
776 return;
777 }
778
771fe6b9
JG		 779 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
780}
781
bcc1c2a1
AD		 782static int evergreen_crtc_set_base(struct drm_crtc *crtc, int x, int y,
783 struct drm_framebuffer *old_fb)
784{
785 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
786 struct drm_device *dev = crtc->dev;
787 struct radeon_device *rdev = dev->dev_private;
788 struct radeon_framebuffer *radeon_fb;
789 struct drm_gem_object *obj;
790 struct radeon_bo *rbo;
791 uint64_t fb_location;
792 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
793 int r;
794
795 /* no fb bound */
796 if (!crtc->fb) {
797 DRM_DEBUG("No FB bound\n");
798 return 0;
799 }
800
801 radeon_fb = to_radeon_framebuffer(crtc->fb);
802
803 /* Pin framebuffer & get tilling informations */
804 obj = radeon_fb->obj;
805 rbo = obj->driver_private;
806 r = radeon_bo_reserve(rbo, false);
807 if (unlikely(r != 0))
808 return r;
809 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
810 if (unlikely(r != 0)) {
811 radeon_bo_unreserve(rbo);
812 return -EINVAL;
813 }
814 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
815 radeon_bo_unreserve(rbo);
816
817 switch (crtc->fb->bits_per_pixel) {
818 case 8:
819 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
820 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
821 break;
822 case 15:
823 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
824 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
825 break;
826 case 16:
827 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
828 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
829 break;
830 case 24:
831 case 32:
832 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
833 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
834 break;
835 default:
836 DRM_ERROR("Unsupported screen depth %d\n",
837 crtc->fb->bits_per_pixel);
838 return -EINVAL;
839 }
840
841 switch (radeon_crtc->crtc_id) {
842 case 0:
843 WREG32(AVIVO_D1VGA_CONTROL, 0);
844 break;
845 case 1:
846 WREG32(AVIVO_D2VGA_CONTROL, 0);
847 break;
848 case 2:
849 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
850 break;
851 case 3:
852 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
853 break;
854 case 4:
855 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
856 break;
857 case 5:
858 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
859 break;
860 default:
861 break;
862 }
863
864 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
865 upper_32_bits(fb_location));
866 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
867 upper_32_bits(fb_location));
868 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
869 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
870 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
871 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
872 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
873
874 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
875 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
876 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
877 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
878 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
879 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
880
881 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
882 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
883 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
884
885 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
886 crtc->mode.vdisplay);
887 x &= ~3;
888 y &= ~1;
889 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
890 (x << 16) | y);
891 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
892 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
893
894 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
895 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
896 EVERGREEN_INTERLEAVE_EN);
897 else
898 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
899
900 if (old_fb && old_fb != crtc->fb) {
901 radeon_fb = to_radeon_framebuffer(old_fb);
902 rbo = radeon_fb->obj->driver_private;
903 r = radeon_bo_reserve(rbo, false);
904 if (unlikely(r != 0))
905 return r;
906 radeon_bo_unpin(rbo);
907 radeon_bo_unreserve(rbo);
908 }
909
910 /* Bytes per pixel may have changed */
911 radeon_bandwidth_update(rdev);
912
913 return 0;
914}
915
54f088a9
AD		 916static int avivo_crtc_set_base(struct drm_crtc *crtc, int x, int y,
917 struct drm_framebuffer *old_fb)
771fe6b9
JG		 918{
919 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
920 struct drm_device *dev = crtc->dev;
921 struct radeon_device *rdev = dev->dev_private;
922 struct radeon_framebuffer *radeon_fb;
923 struct drm_gem_object *obj;
4c788679 924 struct radeon_bo *rbo;
771fe6b9 925 uint64_t fb_location;
e024e110 926 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
4c788679 927 int r;
771fe6b9 928
2de3b484
JG		 929 /* no fb bound */
930 if (!crtc->fb) {
931 DRM_DEBUG("No FB bound\n");
932 return 0;
933 }
771fe6b9
JG		 934
935 radeon_fb = to_radeon_framebuffer(crtc->fb);
936
4c788679 937 /* Pin framebuffer & get tilling informations */
771fe6b9 938 obj = radeon_fb->obj;
4c788679
JG		 939 rbo = obj->driver_private;
940 r = radeon_bo_reserve(rbo, false);
941 if (unlikely(r != 0))
942 return r;
943 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
944 if (unlikely(r != 0)) {
945 radeon_bo_unreserve(rbo);
771fe6b9
JG		 946 return -EINVAL;
947 }
4c788679
JG		 948 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
949 radeon_bo_unreserve(rbo);
771fe6b9
JG		 950
951 switch (crtc->fb->bits_per_pixel) {
41456df2
DA		 952 case 8:
953 fb_format =
954 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
955 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
956 break;
771fe6b9
JG		 957 case 15:
958 fb_format =
959 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
960 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
961 break;
962 case 16:
963 fb_format =
964 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
965 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
966 break;
967 case 24:
968 case 32:
969 fb_format =
970 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
971 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
972 break;
973 default:
974 DRM_ERROR("Unsupported screen depth %d\n",
975 crtc->fb->bits_per_pixel);
976 return -EINVAL;
977 }
978
cf2f05d3
DA		 979 if (tiling_flags & RADEON_TILING_MACRO)
980 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
981
e024e110
DA		 982 if (tiling_flags & RADEON_TILING_MICRO)
983 fb_format |= AVIVO_D1GRPH_TILED;
984
771fe6b9
JG		 985 if (radeon_crtc->crtc_id == 0)
986 WREG32(AVIVO_D1VGA_CONTROL, 0);
987 else
988 WREG32(AVIVO_D2VGA_CONTROL, 0);
c290dadf
AD		 989
990 if (rdev->family >= CHIP_RV770) {
991 if (radeon_crtc->crtc_id) {
992 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
993 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
994 } else {
995 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, 0);
996 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, 0);
997 }
998 }
771fe6b9
JG		 999 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1000 (u32) fb_location);
1001 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1002 radeon_crtc->crtc_offset, (u32) fb_location);
1003 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1004
1005 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1006 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1007 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1008 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1009 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
1010 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
1011
1012 fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
1013 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1014 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1015
1016 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1017 crtc->mode.vdisplay);
1018 x &= ~3;
1019 y &= ~1;
1020 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1021 (x << 16) | y);
1022 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1023 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1024
1025 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1026 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1027 AVIVO_D1MODE_INTERLEAVE_EN);
1028 else
1029 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1030
1031 if (old_fb && old_fb != crtc->fb) {
1032 radeon_fb = to_radeon_framebuffer(old_fb);
4c788679
JG		 1033 rbo = radeon_fb->obj->driver_private;
1034 r = radeon_bo_reserve(rbo, false);
1035 if (unlikely(r != 0))
1036 return r;
1037 radeon_bo_unpin(rbo);
1038 radeon_bo_unreserve(rbo);
771fe6b9 1039 }
f30f37de
MD		 1040
1041 /* Bytes per pixel may have changed */
1042 radeon_bandwidth_update(rdev);
1043
771fe6b9
JG		 1044 return 0;
1045}
1046
54f088a9
AD		 1047int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1048 struct drm_framebuffer *old_fb)
1049{
1050 struct drm_device *dev = crtc->dev;
1051 struct radeon_device *rdev = dev->dev_private;
1052
bcc1c2a1
AD		 1053 if (ASIC_IS_DCE4(rdev))
1054 return evergreen_crtc_set_base(crtc, x, y, old_fb);
1055 else if (ASIC_IS_AVIVO(rdev))
54f088a9
AD		 1056 return avivo_crtc_set_base(crtc, x, y, old_fb);
1057 else
1058 return radeon_crtc_set_base(crtc, x, y, old_fb);
1059}
1060
615e0cb6
AD		 1061/* properly set additional regs when using atombios */
1062static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1063{
1064 struct drm_device *dev = crtc->dev;
1065 struct radeon_device *rdev = dev->dev_private;
1066 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1067 u32 disp_merge_cntl;
1068
1069 switch (radeon_crtc->crtc_id) {
1070 case 0:
1071 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1072 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1073 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1074 break;
1075 case 1:
1076 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1077 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1078 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1079 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1080 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1081 break;
1082 }
1083}
1084
bcc1c2a1
AD		 1085static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1086{
1087 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1088 struct drm_device *dev = crtc->dev;
1089 struct radeon_device *rdev = dev->dev_private;
1090 struct drm_encoder *test_encoder;
1091 struct drm_crtc *test_crtc;
1092 uint32_t pll_in_use = 0;
1093
1094 if (ASIC_IS_DCE4(rdev)) {
1095 /* if crtc is driving DP and we have an ext clock, use that */
1096 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1097 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1098 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1099 if (rdev->clock.dp_extclk)
1100 return ATOM_PPLL_INVALID;
1101 }
1102 }
1103 }
1104
1105 /* otherwise, pick one of the plls */
1106 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1107 struct radeon_crtc *radeon_test_crtc;
1108
1109 if (crtc == test_crtc)
1110 continue;
1111
1112 radeon_test_crtc = to_radeon_crtc(test_crtc);
1113 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1114 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1115 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1116 }
1117 if (!(pll_in_use & 1))
1118 return ATOM_PPLL1;
1119 return ATOM_PPLL2;
1120 } else
1121 return radeon_crtc->crtc_id;
1122
1123}
1124
771fe6b9
JG		 1125int atombios_crtc_mode_set(struct drm_crtc *crtc,
1126 struct drm_display_mode *mode,
1127 struct drm_display_mode *adjusted_mode,
1128 int x, int y, struct drm_framebuffer *old_fb)
1129{
1130 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1131 struct drm_device *dev = crtc->dev;
1132 struct radeon_device *rdev = dev->dev_private;
771fe6b9
JG		 1133
1134 /* TODO color tiling */
771fe6b9 1135
b792210e 1136 atombios_disable_ss(crtc);
bcc1c2a1
AD		 1137 /* always set DCPLL */
1138 if (ASIC_IS_DCE4(rdev))
1139 atombios_crtc_set_dcpll(crtc);
771fe6b9 1140 atombios_crtc_set_pll(crtc, adjusted_mode);
b792210e 1141 atombios_enable_ss(crtc);
771fe6b9 1142
bcc1c2a1
AD		 1143 if (ASIC_IS_DCE4(rdev))
1144 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1145 else if (ASIC_IS_AVIVO(rdev))
1146 atombios_crtc_set_timing(crtc, adjusted_mode);
771fe6b9 1147 else {
bcc1c2a1 1148 atombios_crtc_set_timing(crtc, adjusted_mode);
5a9bcacc
AD		 1149 if (radeon_crtc->crtc_id == 0)
1150 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
615e0cb6 1151 radeon_legacy_atom_fixup(crtc);
771fe6b9 1152 }
bcc1c2a1 1153 atombios_crtc_set_base(crtc, x, y, old_fb);
c93bb85b
JG		 1154 atombios_overscan_setup(crtc, mode, adjusted_mode);
1155 atombios_scaler_setup(crtc);
771fe6b9
JG		 1156 return 0;
1157}
1158
1159static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1160 struct drm_display_mode *mode,
1161 struct drm_display_mode *adjusted_mode)
1162{
c93bb85b
JG		 1163 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1164 return false;
771fe6b9
JG		 1165 return true;
1166}
1167
1168static void atombios_crtc_prepare(struct drm_crtc *crtc)
1169{
267364ac
AD		 1170 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1171
1172 /* pick pll */
1173 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1174
37b4390e 1175 atombios_lock_crtc(crtc, ATOM_ENABLE);
a348c84d 1176 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
771fe6b9
JG		 1177}
1178
1179static void atombios_crtc_commit(struct drm_crtc *crtc)
1180{
1181 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
37b4390e 1182 atombios_lock_crtc(crtc, ATOM_DISABLE);
771fe6b9
JG		 1183}
1184
1185static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1186 .dpms = atombios_crtc_dpms,
1187 .mode_fixup = atombios_crtc_mode_fixup,
1188 .mode_set = atombios_crtc_mode_set,
1189 .mode_set_base = atombios_crtc_set_base,
1190 .prepare = atombios_crtc_prepare,
1191 .commit = atombios_crtc_commit,
068143d3 1192 .load_lut = radeon_crtc_load_lut,
771fe6b9
JG		 1193};
1194
1195void radeon_atombios_init_crtc(struct drm_device *dev,
1196 struct radeon_crtc *radeon_crtc)
1197{
bcc1c2a1
AD		 1198 struct radeon_device *rdev = dev->dev_private;
1199
1200 if (ASIC_IS_DCE4(rdev)) {
1201 switch (radeon_crtc->crtc_id) {
1202 case 0:
1203 default:
12d7798f 1204 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
bcc1c2a1
AD		 1205 break;
1206 case 1:
12d7798f 1207 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
bcc1c2a1
AD		 1208 break;
1209 case 2:
12d7798f 1210 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
bcc1c2a1
AD		 1211 break;
1212 case 3:
12d7798f 1213 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
bcc1c2a1
AD		 1214 break;
1215 case 4:
12d7798f 1216 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
bcc1c2a1
AD		 1217 break;
1218 case 5:
12d7798f 1219 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
bcc1c2a1
AD		 1220 break;
1221 }
1222 } else {
1223 if (radeon_crtc->crtc_id == 1)
1224 radeon_crtc->crtc_offset =
1225 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1226 else
1227 radeon_crtc->crtc_offset = 0;
1228 }
1229 radeon_crtc->pll_id = -1;
771fe6b9
JG		 1230 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1231}
Linux 6.x block layer and io_uring tree(s)