[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nvkm / engine / fifo / gk104.h

#ifndef __GK104_FIFO_H__
#define __GK104_FIFO_H__
#define gk104_fifo(p) container_of((p), struct gk104_fifo, base)
#include "priv.h"

#include <subdev/mmu.h>

struct gk104_fifo_chan;
struct gk104_fifo {
	struct nvkm_fifo base;

	struct {
		struct work_struct work;
		u32 engm;
		u32 runm;
	} recover;

	int pbdma_nr;

	struct {
		struct nvkm_engine *engine;
		int runl;
		int pbid;
	} engine[16];
	int engine_nr;

	struct {
		struct nvkm_memory *mem[2];
		int next;
		wait_queue_head_t wait;
		struct list_head chan;
		u32 engm;
	} runlist[16];
	int runlist_nr;

	struct {
		struct nvkm_memory *mem;
		struct nvkm_vma bar;
	} user;
};

int gk104_fifo_new_(const struct nvkm_fifo_func *, struct nvkm_device *,
		    int index, int nr, struct nvkm_fifo **);
void *gk104_fifo_dtor(struct nvkm_fifo *);
int gk104_fifo_oneinit(struct nvkm_fifo *);
void gk104_fifo_init(struct nvkm_fifo *);
void gk104_fifo_fini(struct nvkm_fifo *);
void gk104_fifo_intr(struct nvkm_fifo *);
void gk104_fifo_uevent_init(struct nvkm_fifo *);
void gk104_fifo_uevent_fini(struct nvkm_fifo *);
void gk104_fifo_runlist_insert(struct gk104_fifo *, struct gk104_fifo_chan *);
void gk104_fifo_runlist_remove(struct gk104_fifo *, struct gk104_fifo_chan *);
void gk104_fifo_runlist_commit(struct gk104_fifo *, int runl);

static inline u64
gk104_fifo_engine_subdev(int engine)
{
	switch (engine) {
	case 0: return (1ULL << NVKM_ENGINE_GR) |
		       (1ULL << NVKM_ENGINE_SW) |
		       (1ULL << NVKM_ENGINE_CE2);
	case 1: return (1ULL << NVKM_ENGINE_MSPDEC);
	case 2: return (1ULL << NVKM_ENGINE_MSPPP);
	case 3: return (1ULL << NVKM_ENGINE_MSVLD);
	case 4: return (1ULL << NVKM_ENGINE_CE0);
	case 5: return (1ULL << NVKM_ENGINE_CE1);
	case 6: return (1ULL << NVKM_ENGINE_MSENC);
	default:
		WARN_ON(1);
		return 0;
	}
}
#endif
Commit	Line	Data
9a65a38c BS	1	#ifndef __GK104_FIFO_H__
9a65a38c BS	2	#define __GK104_FIFO_H__
8f0649b5	3	#define gk104_fifo(p) container_of((p), struct gk104_fifo, base)
9a65a38c	4	#include "priv.h"
05c7145d	5
8f0649b5 BS	6	#include <subdev/mmu.h>
8f0649b5 BS	7
386ffd5e	8	struct gk104_fifo_chan;
9a65a38c BS	9	struct gk104_fifo {
	10	struct nvkm_fifo base;
	11
55252da1 BS	12	struct {
55252da1 BS	13	struct work_struct work;
19f89279 BS	14	u32 engm;
19f89279 BS	15	u32 runm;
55252da1	16	} recover;
9a65a38c	17
6d39b83f BS	18	int pbdma_nr;
6d39b83f BS	19
41e5171b BS	20	struct {
	21	struct nvkm_engine *engine;
	22	int runl;
	23	int pbid;
	24	} engine[16];
	25	int engine_nr;
	26
69aa40e2 BS	27	struct {
	28	struct nvkm_memory *mem[2];
	29	int next;
	30	wait_queue_head_t wait;
	31	struct list_head chan;
41e5171b BS	32	u32 engm;
	33	} runlist[16];
	34	int runlist_nr;
69aa40e2	35
9a65a38c BS	36	struct {
	37	struct nvkm_memory *mem;
	38	struct nvkm_vma bar;
	39	} user;
9a65a38c	40	};
05c7145d	41
13de7f46 BS	42	int gk104_fifo_new_(const struct nvkm_fifo_func , struct nvkm_device ,
	43	int index, int nr, struct nvkm_fifo **);
	44	void gk104_fifo_dtor(struct nvkm_fifo );
	45	int gk104_fifo_oneinit(struct nvkm_fifo *);
	46	void gk104_fifo_init(struct nvkm_fifo *);
	47	void gk104_fifo_fini(struct nvkm_fifo *);
	48	void gk104_fifo_intr(struct nvkm_fifo *);
	49	void gk104_fifo_uevent_init(struct nvkm_fifo *);
	50	void gk104_fifo_uevent_fini(struct nvkm_fifo *);
386ffd5e BS	51	void gk104_fifo_runlist_insert(struct gk104_fifo , struct gk104_fifo_chan );
386ffd5e BS	52	void gk104_fifo_runlist_remove(struct gk104_fifo , struct gk104_fifo_chan );
69aa40e2	53	void gk104_fifo_runlist_commit(struct gk104_fifo *, int runl);
3326060a	54
8f0649b5 BS	55	static inline u64
	56	gk104_fifo_engine_subdev(int engine)
	57	{
	58	switch (engine) {
68f3f702 BS	59	case 0: return (1ULL << NVKM_ENGINE_GR) \|
	60	(1ULL << NVKM_ENGINE_SW) \|
	61	(1ULL << NVKM_ENGINE_CE2);
	62	case 1: return (1ULL << NVKM_ENGINE_MSPDEC);
	63	case 2: return (1ULL << NVKM_ENGINE_MSPPP);
	64	case 3: return (1ULL << NVKM_ENGINE_MSVLD);
	65	case 4: return (1ULL << NVKM_ENGINE_CE0);
	66	case 5: return (1ULL << NVKM_ENGINE_CE1);
	67	case 6: return (1ULL << NVKM_ENGINE_MSENC);
8f0649b5 BS	68	default:
	69	WARN_ON(1);
	70	return 0;
	71	}
	72	}
05c7145d	73	#endif