drm/nouveau/device: audit and version NVIF_CONTROL class and methods
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / nouveau_drm.c
CommitLineData
94580299
BS
1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
77145f1c 25#include <linux/console.h>
94580299
BS
26#include <linux/module.h>
27#include <linux/pci.h>
5addcf0a
DA
28#include <linux/pm_runtime.h>
29#include <linux/vga_switcheroo.h>
fdb751ef 30
5addcf0a
DA
31#include "drmP.h"
32#include "drm_crtc_helper.h"
fdb751ef 33
94580299 34#include <core/device.h>
ebb945a9 35#include <core/gpuobj.h>
94580299 36#include <core/class.h>
c33e05a1 37#include <core/option.h>
94580299 38
94580299 39#include "nouveau_drm.h"
ebb945a9 40#include "nouveau_dma.h"
77145f1c
BS
41#include "nouveau_ttm.h"
42#include "nouveau_gem.h"
cb75d97e 43#include "nouveau_agp.h"
77145f1c 44#include "nouveau_vga.h"
26fdd78c 45#include "nouveau_sysfs.h"
b9ed919f 46#include "nouveau_hwmon.h"
77145f1c
BS
47#include "nouveau_acpi.h"
48#include "nouveau_bios.h"
49#include "nouveau_ioctl.h"
ebb945a9
BS
50#include "nouveau_abi16.h"
51#include "nouveau_fbcon.h"
52#include "nouveau_fence.h"
33b903e8 53#include "nouveau_debugfs.h"
ebb945a9 54
94580299
BS
55MODULE_PARM_DESC(config, "option string to pass to driver core");
56static char *nouveau_config;
57module_param_named(config, nouveau_config, charp, 0400);
58
59MODULE_PARM_DESC(debug, "debug string to pass to driver core");
60static char *nouveau_debug;
61module_param_named(debug, nouveau_debug, charp, 0400);
62
ebb945a9
BS
63MODULE_PARM_DESC(noaccel, "disable kernel/abi16 acceleration");
64static int nouveau_noaccel = 0;
65module_param_named(noaccel, nouveau_noaccel, int, 0400);
66
9430738d
BS
67MODULE_PARM_DESC(modeset, "enable driver (default: auto, "
68 "0 = disabled, 1 = enabled, 2 = headless)");
69int nouveau_modeset = -1;
77145f1c
BS
70module_param_named(modeset, nouveau_modeset, int, 0400);
71
5addcf0a
DA
72MODULE_PARM_DESC(runpm, "disable (0), force enable (1), optimus only default (-1)");
73int nouveau_runtime_pm = -1;
74module_param_named(runpm, nouveau_runtime_pm, int, 0400);
75
77145f1c
BS
76static struct drm_driver driver;
77
94580299 78static u64
420b9469 79nouveau_pci_name(struct pci_dev *pdev)
94580299
BS
80{
81 u64 name = (u64)pci_domain_nr(pdev->bus) << 32;
82 name |= pdev->bus->number << 16;
83 name |= PCI_SLOT(pdev->devfn) << 8;
84 return name | PCI_FUNC(pdev->devfn);
85}
86
420b9469
AC
87static u64
88nouveau_platform_name(struct platform_device *platformdev)
89{
90 return platformdev->id;
91}
92
93static u64
94nouveau_name(struct drm_device *dev)
95{
96 if (dev->pdev)
97 return nouveau_pci_name(dev->pdev);
98 else
99 return nouveau_platform_name(dev->platformdev);
100}
101
94580299 102static int
420b9469 103nouveau_cli_create(u64 name, const char *sname,
fa6df8c1 104 int size, void **pcli)
94580299 105{
0ad72863
BS
106 struct nouveau_cli *cli = *pcli = kzalloc(size, GFP_KERNEL);
107 if (cli) {
108 int ret = nvif_client_init(NULL, NULL, sname, name,
109 nouveau_config, nouveau_debug,
110 &cli->base);
111 if (ret == 0)
112 mutex_init(&cli->mutex);
94580299 113 return ret;
dd5700ea 114 }
0ad72863 115 return -ENOMEM;
94580299
BS
116}
117
118static void
119nouveau_cli_destroy(struct nouveau_cli *cli)
120{
0ad72863
BS
121 nouveau_vm_ref(NULL, &nvkm_client(&cli->base)->vm, NULL);
122 nvif_client_fini(&cli->base);
94580299
BS
123}
124
ebb945a9
BS
125static void
126nouveau_accel_fini(struct nouveau_drm *drm)
127{
ebb945a9 128 nouveau_channel_del(&drm->channel);
0ad72863
BS
129 nvif_object_fini(&drm->ntfy);
130 nouveau_gpuobj_ref(NULL, &drm->notify);
131 nvif_object_fini(&drm->nvsw);
49981046 132 nouveau_channel_del(&drm->cechan);
0ad72863 133 nvif_object_fini(&drm->ttm.copy);
ebb945a9
BS
134 if (drm->fence)
135 nouveau_fence(drm)->dtor(drm);
136}
137
138static void
139nouveau_accel_init(struct nouveau_drm *drm)
140{
967e7bde 141 struct nvif_device *device = &drm->device;
49981046 142 u32 arg0, arg1;
967e7bde
BS
143 u32 sclass[16];
144 int ret, i;
ebb945a9 145
967e7bde 146 if (nouveau_noaccel)
ebb945a9
BS
147 return;
148
149 /* initialise synchronisation routines */
967e7bde
BS
150 /*XXX: this is crap, but the fence/channel stuff is a little
151 * backwards in some places. this will be fixed.
152 */
0ad72863 153 ret = nvif_object_sclass(&device->base, sclass, ARRAY_SIZE(sclass));
967e7bde
BS
154 if (ret < 0)
155 return;
156
157 for (ret = -ENOSYS, i = 0; ret && i < ARRAY_SIZE(sclass); i++) {
158 switch (sclass[i]) {
159 case NV03_CHANNEL_DMA_CLASS:
160 ret = nv04_fence_create(drm);
161 break;
162 case NV10_CHANNEL_DMA_CLASS:
163 ret = nv10_fence_create(drm);
164 break;
165 case NV17_CHANNEL_DMA_CLASS:
166 case NV40_CHANNEL_DMA_CLASS:
167 ret = nv17_fence_create(drm);
168 break;
169 case NV50_CHANNEL_IND_CLASS:
170 ret = nv50_fence_create(drm);
171 break;
172 case NV84_CHANNEL_IND_CLASS:
173 ret = nv84_fence_create(drm);
174 break;
175 case NVC0_CHANNEL_IND_CLASS:
176 case NVE0_CHANNEL_IND_CLASS:
177 ret = nvc0_fence_create(drm);
178 break;
179 default:
180 break;
181 }
182 }
183
ebb945a9
BS
184 if (ret) {
185 NV_ERROR(drm, "failed to initialise sync subsystem, %d\n", ret);
186 nouveau_accel_fini(drm);
187 return;
188 }
189
967e7bde 190 if (device->info.family >= NV_DEVICE_INFO_V0_KEPLER) {
0ad72863 191 ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1,
49981046
BS
192 NVE0_CHANNEL_IND_ENGINE_CE0 |
193 NVE0_CHANNEL_IND_ENGINE_CE1, 0,
194 &drm->cechan);
195 if (ret)
196 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
197
198 arg0 = NVE0_CHANNEL_IND_ENGINE_GR;
49469800 199 arg1 = 1;
00fc6f6f 200 } else
967e7bde
BS
201 if (device->info.chipset >= 0xa3 &&
202 device->info.chipset != 0xaa &&
203 device->info.chipset != 0xac) {
0ad72863
BS
204 ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN + 1,
205 NvDmaFB, NvDmaTT, &drm->cechan);
00fc6f6f
BS
206 if (ret)
207 NV_ERROR(drm, "failed to create ce channel, %d\n", ret);
208
209 arg0 = NvDmaFB;
210 arg1 = NvDmaTT;
49981046
BS
211 } else {
212 arg0 = NvDmaFB;
213 arg1 = NvDmaTT;
214 }
215
0ad72863
BS
216 ret = nouveau_channel_new(drm, &drm->device, NVDRM_CHAN, arg0, arg1,
217 &drm->channel);
ebb945a9
BS
218 if (ret) {
219 NV_ERROR(drm, "failed to create kernel channel, %d\n", ret);
220 nouveau_accel_fini(drm);
221 return;
222 }
223
0ad72863
BS
224 ret = nvif_object_init(drm->channel->object, NULL, NVDRM_NVSW,
225 nouveau_abi16_swclass(drm), NULL, 0, &drm->nvsw);
69a6146d 226 if (ret == 0) {
0ad72863 227 struct nouveau_software_chan *swch;
69a6146d
BS
228 ret = RING_SPACE(drm->channel, 2);
229 if (ret == 0) {
967e7bde 230 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
69a6146d
BS
231 BEGIN_NV04(drm->channel, NvSubSw, 0, 1);
232 OUT_RING (drm->channel, NVDRM_NVSW);
233 } else
967e7bde 234 if (device->info.family < NV_DEVICE_INFO_V0_KEPLER) {
69a6146d
BS
235 BEGIN_NVC0(drm->channel, FermiSw, 0, 1);
236 OUT_RING (drm->channel, 0x001f0000);
237 }
238 }
0ad72863 239 swch = (void *)nvkm_object(&drm->nvsw)->parent;
69a6146d
BS
240 swch->flip = nouveau_flip_complete;
241 swch->flip_data = drm->channel;
242 }
243
244 if (ret) {
245 NV_ERROR(drm, "failed to allocate software object, %d\n", ret);
246 nouveau_accel_fini(drm);
247 return;
248 }
249
967e7bde
BS
250 if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
251 ret = nouveau_gpuobj_new(nvkm_object(&drm->device), NULL, 32,
252 0, 0, &drm->notify);
ebb945a9
BS
253 if (ret) {
254 NV_ERROR(drm, "failed to allocate notifier, %d\n", ret);
255 nouveau_accel_fini(drm);
256 return;
257 }
258
0ad72863 259 ret = nvif_object_init(drm->channel->object, NULL, NvNotify0,
4acfd707
BS
260 NV_DMA_IN_MEMORY,
261 &(struct nv_dma_v0) {
262 .target = NV_DMA_V0_TARGET_VRAM,
263 .access = NV_DMA_V0_ACCESS_RDWR,
ebb945a9
BS
264 .start = drm->notify->addr,
265 .limit = drm->notify->addr + 31
4acfd707 266 }, sizeof(struct nv_dma_v0),
0ad72863 267 &drm->ntfy);
ebb945a9
BS
268 if (ret) {
269 nouveau_accel_fini(drm);
270 return;
271 }
272 }
273
274
49981046 275 nouveau_bo_move_init(drm);
ebb945a9
BS
276}
277
56550d94
GKH
278static int nouveau_drm_probe(struct pci_dev *pdev,
279 const struct pci_device_id *pent)
94580299
BS
280{
281 struct nouveau_device *device;
ebb945a9
BS
282 struct apertures_struct *aper;
283 bool boot = false;
94580299
BS
284 int ret;
285
ebb945a9
BS
286 /* remove conflicting drivers (vesafb, efifb etc) */
287 aper = alloc_apertures(3);
288 if (!aper)
289 return -ENOMEM;
290
291 aper->ranges[0].base = pci_resource_start(pdev, 1);
292 aper->ranges[0].size = pci_resource_len(pdev, 1);
293 aper->count = 1;
294
295 if (pci_resource_len(pdev, 2)) {
296 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
297 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
298 aper->count++;
299 }
300
301 if (pci_resource_len(pdev, 3)) {
302 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
303 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
304 aper->count++;
305 }
306
307#ifdef CONFIG_X86
308 boot = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
309#endif
310 remove_conflicting_framebuffers(aper, "nouveaufb", boot);
83ef7777 311 kfree(aper);
ebb945a9 312
420b9469
AC
313 ret = nouveau_device_create(pdev, NOUVEAU_BUS_PCI,
314 nouveau_pci_name(pdev), pci_name(pdev),
94580299
BS
315 nouveau_config, nouveau_debug, &device);
316 if (ret)
317 return ret;
318
319 pci_set_master(pdev);
320
77145f1c 321 ret = drm_get_pci_dev(pdev, pent, &driver);
94580299 322 if (ret) {
ebb945a9 323 nouveau_object_ref(NULL, (struct nouveau_object **)&device);
94580299
BS
324 return ret;
325 }
326
327 return 0;
328}
329
5addcf0a
DA
330#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
331
332static void
46941b0f 333nouveau_get_hdmi_dev(struct nouveau_drm *drm)
5addcf0a 334{
46941b0f 335 struct pci_dev *pdev = drm->dev->pdev;
5addcf0a 336
420b9469 337 if (!pdev) {
40189b0c 338 DRM_INFO("not a PCI device; no HDMI\n");
420b9469
AC
339 drm->hdmi_device = NULL;
340 return;
341 }
342
5addcf0a
DA
343 /* subfunction one is a hdmi audio device? */
344 drm->hdmi_device = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
345 PCI_DEVFN(PCI_SLOT(pdev->devfn), 1));
346
347 if (!drm->hdmi_device) {
46941b0f 348 NV_DEBUG(drm, "hdmi device not found %d %d %d\n", pdev->bus->number, PCI_SLOT(pdev->devfn), 1);
5addcf0a
DA
349 return;
350 }
351
352 if ((drm->hdmi_device->class >> 8) != PCI_CLASS_MULTIMEDIA_HD_AUDIO) {
46941b0f 353 NV_DEBUG(drm, "possible hdmi device not audio %d\n", drm->hdmi_device->class);
5addcf0a
DA
354 pci_dev_put(drm->hdmi_device);
355 drm->hdmi_device = NULL;
356 return;
357 }
358}
359
5b8a43ae 360static int
94580299
BS
361nouveau_drm_load(struct drm_device *dev, unsigned long flags)
362{
363 struct pci_dev *pdev = dev->pdev;
364 struct nouveau_drm *drm;
365 int ret;
366
420b9469
AC
367 ret = nouveau_cli_create(nouveau_name(dev), "DRM", sizeof(*drm),
368 (void **)&drm);
94580299
BS
369 if (ret)
370 return ret;
371
77145f1c
BS
372 dev->dev_private = drm;
373 drm->dev = dev;
0ad72863
BS
374 nvkm_client(&drm->client.base)->debug =
375 nouveau_dbgopt(nouveau_debug, "DRM");
77145f1c 376
94580299 377 INIT_LIST_HEAD(&drm->clients);
ebb945a9 378 spin_lock_init(&drm->tile.lock);
94580299 379
46941b0f 380 nouveau_get_hdmi_dev(drm);
5addcf0a 381
cb75d97e
BS
382 /* make sure AGP controller is in a consistent state before we
383 * (possibly) execute vbios init tables (see nouveau_agp.h)
384 */
420b9469 385 if (pdev && drm_pci_device_is_agp(dev) && dev->agp) {
586491e6
BS
386 const u64 enables = NV_DEVICE_V0_DISABLE_IDENTIFY |
387 NV_DEVICE_V0_DISABLE_MMIO;
cb75d97e
BS
388 /* dummy device object, doesn't init anything, but allows
389 * agp code access to registers
390 */
0ad72863 391 ret = nvif_device_init(&drm->client.base.base, NULL,
586491e6
BS
392 NVDRM_DEVICE, NV_DEVICE,
393 &(struct nv_device_v0) {
cb75d97e 394 .device = ~0,
586491e6 395 .disable = ~enables,
cb75d97e 396 .debug0 = ~0,
586491e6 397 }, sizeof(struct nv_device_v0),
0ad72863 398 &drm->device);
cb75d97e 399 if (ret)
ebb945a9 400 goto fail_device;
cb75d97e
BS
401
402 nouveau_agp_reset(drm);
0ad72863 403 nvif_device_fini(&drm->device);
cb75d97e
BS
404 }
405
0ad72863 406 ret = nvif_device_init(&drm->client.base.base, NULL, NVDRM_DEVICE,
586491e6
BS
407 NV_DEVICE,
408 &(struct nv_device_v0) {
94580299
BS
409 .device = ~0,
410 .disable = 0,
411 .debug0 = 0,
586491e6 412 }, sizeof(struct nv_device_v0),
0ad72863 413 &drm->device);
94580299
BS
414 if (ret)
415 goto fail_device;
416
7d3428cd
IM
417 dev->irq_enabled = true;
418
77145f1c
BS
419 /* workaround an odd issue on nvc1 by disabling the device's
420 * nosnoop capability. hopefully won't cause issues until a
421 * better fix is found - assuming there is one...
422 */
967e7bde
BS
423 if (drm->device.info.chipset == 0xc1)
424 nvif_mask(&drm->device, 0x00088080, 0x00000800, 0x00000000);
ebb945a9 425
77145f1c 426 nouveau_vga_init(drm);
cb75d97e
BS
427 nouveau_agp_init(drm);
428
967e7bde
BS
429 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
430 ret = nouveau_vm_new(nvkm_device(&drm->device), 0, (1ULL << 40),
3ee6f5b5 431 0x1000, &drm->client.vm);
ebb945a9
BS
432 if (ret)
433 goto fail_device;
3ee6f5b5 434
0ad72863 435 nvkm_client(&drm->client.base)->vm = drm->client.vm;
ebb945a9
BS
436 }
437
438 ret = nouveau_ttm_init(drm);
94580299 439 if (ret)
77145f1c
BS
440 goto fail_ttm;
441
442 ret = nouveau_bios_init(dev);
443 if (ret)
444 goto fail_bios;
445
77145f1c 446 ret = nouveau_display_create(dev);
ebb945a9 447 if (ret)
77145f1c
BS
448 goto fail_dispctor;
449
450 if (dev->mode_config.num_crtc) {
451 ret = nouveau_display_init(dev);
452 if (ret)
453 goto fail_dispinit;
454 }
455
26fdd78c 456 nouveau_sysfs_init(dev);
b9ed919f 457 nouveau_hwmon_init(dev);
ebb945a9
BS
458 nouveau_accel_init(drm);
459 nouveau_fbcon_init(dev);
5addcf0a
DA
460
461 if (nouveau_runtime_pm != 0) {
462 pm_runtime_use_autosuspend(dev->dev);
463 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
464 pm_runtime_set_active(dev->dev);
465 pm_runtime_allow(dev->dev);
466 pm_runtime_mark_last_busy(dev->dev);
467 pm_runtime_put(dev->dev);
468 }
94580299
BS
469 return 0;
470
77145f1c
BS
471fail_dispinit:
472 nouveau_display_destroy(dev);
473fail_dispctor:
77145f1c
BS
474 nouveau_bios_takedown(dev);
475fail_bios:
ebb945a9 476 nouveau_ttm_fini(drm);
77145f1c
BS
477fail_ttm:
478 nouveau_agp_fini(drm);
479 nouveau_vga_fini(drm);
94580299 480fail_device:
0ad72863 481 nvif_device_fini(&drm->device);
94580299
BS
482 nouveau_cli_destroy(&drm->client);
483 return ret;
484}
485
5b8a43ae 486static int
94580299
BS
487nouveau_drm_unload(struct drm_device *dev)
488{
77145f1c 489 struct nouveau_drm *drm = nouveau_drm(dev);
94580299 490
5addcf0a 491 pm_runtime_get_sync(dev->dev);
ebb945a9
BS
492 nouveau_fbcon_fini(dev);
493 nouveau_accel_fini(drm);
b9ed919f 494 nouveau_hwmon_fini(dev);
26fdd78c 495 nouveau_sysfs_fini(dev);
77145f1c 496
9430738d
BS
497 if (dev->mode_config.num_crtc)
498 nouveau_display_fini(dev);
77145f1c
BS
499 nouveau_display_destroy(dev);
500
77145f1c 501 nouveau_bios_takedown(dev);
94580299 502
ebb945a9 503 nouveau_ttm_fini(drm);
cb75d97e 504 nouveau_agp_fini(drm);
77145f1c 505 nouveau_vga_fini(drm);
cb75d97e 506
0ad72863 507 nvif_device_fini(&drm->device);
5addcf0a
DA
508 if (drm->hdmi_device)
509 pci_dev_put(drm->hdmi_device);
94580299
BS
510 nouveau_cli_destroy(&drm->client);
511 return 0;
512}
513
8ba9ff11
AC
514void
515nouveau_drm_device_remove(struct drm_device *dev)
94580299 516{
77145f1c 517 struct nouveau_drm *drm = nouveau_drm(dev);
0ad72863 518 struct nouveau_client *client;
ebb945a9 519 struct nouveau_object *device;
77145f1c 520
7d3428cd 521 dev->irq_enabled = false;
0ad72863
BS
522 client = nvkm_client(&drm->client.base);
523 device = client->device;
77145f1c
BS
524 drm_put_dev(dev);
525
ebb945a9
BS
526 nouveau_object_ref(NULL, &device);
527 nouveau_object_debug();
94580299 528}
8ba9ff11
AC
529EXPORT_SYMBOL(nouveau_drm_device_remove);
530
531static void
532nouveau_drm_remove(struct pci_dev *pdev)
533{
534 struct drm_device *dev = pci_get_drvdata(pdev);
535
536 nouveau_drm_device_remove(dev);
537}
94580299 538
cd897837 539static int
05c63c2f 540nouveau_do_suspend(struct drm_device *dev, bool runtime)
94580299 541{
77145f1c 542 struct nouveau_drm *drm = nouveau_drm(dev);
94580299
BS
543 struct nouveau_cli *cli;
544 int ret;
545
05c63c2f 546 if (dev->mode_config.num_crtc && !runtime) {
c52f4fa6 547 NV_INFO(drm, "suspending display...\n");
9430738d
BS
548 ret = nouveau_display_suspend(dev);
549 if (ret)
550 return ret;
551 }
94580299 552
c52f4fa6 553 NV_INFO(drm, "evicting buffers...\n");
ebb945a9
BS
554 ttm_bo_evict_mm(&drm->ttm.bdev, TTM_PL_VRAM);
555
c52f4fa6 556 NV_INFO(drm, "waiting for kernel channels to go idle...\n");
81dff21b
BS
557 if (drm->cechan) {
558 ret = nouveau_channel_idle(drm->cechan);
559 if (ret)
f3980dc5 560 goto fail_display;
81dff21b
BS
561 }
562
563 if (drm->channel) {
564 ret = nouveau_channel_idle(drm->channel);
565 if (ret)
f3980dc5 566 goto fail_display;
81dff21b
BS
567 }
568
c52f4fa6 569 NV_INFO(drm, "suspending client object trees...\n");
ebb945a9 570 if (drm->fence && nouveau_fence(drm)->suspend) {
f3980dc5
IM
571 if (!nouveau_fence(drm)->suspend(drm)) {
572 ret = -ENOMEM;
573 goto fail_display;
574 }
ebb945a9
BS
575 }
576
94580299 577 list_for_each_entry(cli, &drm->clients, head) {
0ad72863 578 ret = nvif_client_suspend(&cli->base);
94580299
BS
579 if (ret)
580 goto fail_client;
581 }
582
c52f4fa6 583 NV_INFO(drm, "suspending kernel object tree...\n");
0ad72863 584 ret = nvif_client_suspend(&drm->client.base);
94580299
BS
585 if (ret)
586 goto fail_client;
587
cb75d97e 588 nouveau_agp_fini(drm);
94580299
BS
589 return 0;
590
591fail_client:
592 list_for_each_entry_continue_reverse(cli, &drm->clients, head) {
0ad72863 593 nvif_client_resume(&cli->base);
94580299
BS
594 }
595
f3980dc5
IM
596 if (drm->fence && nouveau_fence(drm)->resume)
597 nouveau_fence(drm)->resume(drm);
598
599fail_display:
9430738d 600 if (dev->mode_config.num_crtc) {
c52f4fa6 601 NV_INFO(drm, "resuming display...\n");
9430738d
BS
602 nouveau_display_resume(dev);
603 }
94580299
BS
604 return ret;
605}
606
2d8b9ccb 607int nouveau_pmops_suspend(struct device *dev)
94580299 608{
2d8b9ccb
DA
609 struct pci_dev *pdev = to_pci_dev(dev);
610 struct drm_device *drm_dev = pci_get_drvdata(pdev);
94580299
BS
611 int ret;
612
5addcf0a
DA
613 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
614 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
94580299
BS
615 return 0;
616
5addcf0a
DA
617 if (drm_dev->mode_config.num_crtc)
618 nouveau_fbcon_set_suspend(drm_dev, 1);
619
05c63c2f 620 ret = nouveau_do_suspend(drm_dev, false);
94580299
BS
621 if (ret)
622 return ret;
2d8b9ccb
DA
623
624 pci_save_state(pdev);
625 pci_disable_device(pdev);
626 pci_set_power_state(pdev, PCI_D3hot);
2d8b9ccb
DA
627 return 0;
628}
629
cd897837 630static int
2d8b9ccb
DA
631nouveau_do_resume(struct drm_device *dev)
632{
633 struct nouveau_drm *drm = nouveau_drm(dev);
634 struct nouveau_cli *cli;
635
c52f4fa6 636 NV_INFO(drm, "re-enabling device...\n");
94580299 637
cb75d97e
BS
638 nouveau_agp_reset(drm);
639
c52f4fa6 640 NV_INFO(drm, "resuming kernel object tree...\n");
0ad72863 641 nvif_client_resume(&drm->client.base);
ebb945a9 642 nouveau_agp_init(drm);
94580299 643
c52f4fa6 644 NV_INFO(drm, "resuming client object trees...\n");
81dff21b
BS
645 if (drm->fence && nouveau_fence(drm)->resume)
646 nouveau_fence(drm)->resume(drm);
647
94580299 648 list_for_each_entry(cli, &drm->clients, head) {
0ad72863 649 nvif_client_resume(&cli->base);
94580299 650 }
cb75d97e 651
77145f1c 652 nouveau_run_vbios_init(dev);
77145f1c 653
9430738d 654 if (dev->mode_config.num_crtc) {
c52f4fa6 655 NV_INFO(drm, "resuming display...\n");
5addcf0a 656 nouveau_display_repin(dev);
9430738d 657 }
5addcf0a 658
77145f1c 659 return 0;
94580299
BS
660}
661
2d8b9ccb
DA
662int nouveau_pmops_resume(struct device *dev)
663{
664 struct pci_dev *pdev = to_pci_dev(dev);
665 struct drm_device *drm_dev = pci_get_drvdata(pdev);
666 int ret;
667
5addcf0a
DA
668 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF ||
669 drm_dev->switch_power_state == DRM_SWITCH_POWER_DYNAMIC_OFF)
2d8b9ccb
DA
670 return 0;
671
672 pci_set_power_state(pdev, PCI_D0);
673 pci_restore_state(pdev);
674 ret = pci_enable_device(pdev);
675 if (ret)
676 return ret;
677 pci_set_master(pdev);
678
5addcf0a 679 ret = nouveau_do_resume(drm_dev);
c52f4fa6 680 if (ret)
5addcf0a 681 return ret;
5addcf0a 682
028791bb 683 if (drm_dev->mode_config.num_crtc) {
01172772 684 nouveau_display_resume(drm_dev);
028791bb
BS
685 nouveau_fbcon_set_suspend(drm_dev, 0);
686 }
687
5addcf0a 688 return 0;
2d8b9ccb
DA
689}
690
691static int nouveau_pmops_freeze(struct device *dev)
692{
693 struct pci_dev *pdev = to_pci_dev(dev);
694 struct drm_device *drm_dev = pci_get_drvdata(pdev);
5addcf0a
DA
695 int ret;
696
5addcf0a
DA
697 if (drm_dev->mode_config.num_crtc)
698 nouveau_fbcon_set_suspend(drm_dev, 1);
2d8b9ccb 699
05c63c2f 700 ret = nouveau_do_suspend(drm_dev, false);
5addcf0a 701 return ret;
2d8b9ccb
DA
702}
703
704static int nouveau_pmops_thaw(struct device *dev)
705{
706 struct pci_dev *pdev = to_pci_dev(dev);
707 struct drm_device *drm_dev = pci_get_drvdata(pdev);
5addcf0a 708 int ret;
2d8b9ccb 709
5addcf0a 710 ret = nouveau_do_resume(drm_dev);
c52f4fa6 711 if (ret)
5addcf0a 712 return ret;
028791bb
BS
713
714 if (drm_dev->mode_config.num_crtc) {
01172772 715 nouveau_display_resume(drm_dev);
028791bb
BS
716 nouveau_fbcon_set_suspend(drm_dev, 0);
717 }
718
5addcf0a 719 return 0;
2d8b9ccb
DA
720}
721
722
5b8a43ae 723static int
ebb945a9
BS
724nouveau_drm_open(struct drm_device *dev, struct drm_file *fpriv)
725{
ebb945a9
BS
726 struct nouveau_drm *drm = nouveau_drm(dev);
727 struct nouveau_cli *cli;
a2896ced 728 char name[32], tmpname[TASK_COMM_LEN];
ebb945a9
BS
729 int ret;
730
5addcf0a
DA
731 /* need to bring up power immediately if opening device */
732 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 733 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
734 return ret;
735
a2896ced
MS
736 get_task_comm(tmpname, current);
737 snprintf(name, sizeof(name), "%s[%d]", tmpname, pid_nr(fpriv->pid));
fa6df8c1 738
420b9469
AC
739 ret = nouveau_cli_create(nouveau_name(dev), name, sizeof(*cli),
740 (void **)&cli);
741
ebb945a9 742 if (ret)
5addcf0a 743 goto out_suspend;
ebb945a9 744
0ad72863
BS
745 cli->base.super = false;
746
967e7bde
BS
747 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
748 ret = nouveau_vm_new(nvkm_device(&drm->device), 0, (1ULL << 40),
3ee6f5b5 749 0x1000, &cli->vm);
ebb945a9
BS
750 if (ret) {
751 nouveau_cli_destroy(cli);
5addcf0a 752 goto out_suspend;
ebb945a9 753 }
3ee6f5b5 754
0ad72863 755 nvkm_client(&cli->base)->vm = cli->vm;
ebb945a9
BS
756 }
757
758 fpriv->driver_priv = cli;
759
760 mutex_lock(&drm->client.mutex);
761 list_add(&cli->head, &drm->clients);
762 mutex_unlock(&drm->client.mutex);
5addcf0a
DA
763
764out_suspend:
765 pm_runtime_mark_last_busy(dev->dev);
766 pm_runtime_put_autosuspend(dev->dev);
767
768 return ret;
ebb945a9
BS
769}
770
5b8a43ae 771static void
ebb945a9
BS
772nouveau_drm_preclose(struct drm_device *dev, struct drm_file *fpriv)
773{
774 struct nouveau_cli *cli = nouveau_cli(fpriv);
775 struct nouveau_drm *drm = nouveau_drm(dev);
776
5addcf0a
DA
777 pm_runtime_get_sync(dev->dev);
778
ebb945a9
BS
779 if (cli->abi16)
780 nouveau_abi16_fini(cli->abi16);
781
782 mutex_lock(&drm->client.mutex);
783 list_del(&cli->head);
784 mutex_unlock(&drm->client.mutex);
5addcf0a 785
ebb945a9
BS
786}
787
5b8a43ae 788static void
ebb945a9
BS
789nouveau_drm_postclose(struct drm_device *dev, struct drm_file *fpriv)
790{
791 struct nouveau_cli *cli = nouveau_cli(fpriv);
792 nouveau_cli_destroy(cli);
5addcf0a
DA
793 pm_runtime_mark_last_busy(dev->dev);
794 pm_runtime_put_autosuspend(dev->dev);
ebb945a9
BS
795}
796
baa70943 797static const struct drm_ioctl_desc
77145f1c 798nouveau_ioctls[] = {
7d761258 799 DRM_IOCTL_DEF_DRV(NOUVEAU_GETPARAM, nouveau_abi16_ioctl_getparam, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
77145f1c 800 DRM_IOCTL_DEF_DRV(NOUVEAU_SETPARAM, nouveau_abi16_ioctl_setparam, DRM_UNLOCKED|DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
7d761258
MP
801 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_ALLOC, nouveau_abi16_ioctl_channel_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
802 DRM_IOCTL_DEF_DRV(NOUVEAU_CHANNEL_FREE, nouveau_abi16_ioctl_channel_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
803 DRM_IOCTL_DEF_DRV(NOUVEAU_GROBJ_ALLOC, nouveau_abi16_ioctl_grobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
804 DRM_IOCTL_DEF_DRV(NOUVEAU_NOTIFIEROBJ_ALLOC, nouveau_abi16_ioctl_notifierobj_alloc, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
805 DRM_IOCTL_DEF_DRV(NOUVEAU_GPUOBJ_FREE, nouveau_abi16_ioctl_gpuobj_free, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
806 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_NEW, nouveau_gem_ioctl_new, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
807 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_PUSHBUF, nouveau_gem_ioctl_pushbuf, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
808 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_PREP, nouveau_gem_ioctl_cpu_prep, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
809 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_CPU_FINI, nouveau_gem_ioctl_cpu_fini, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
810 DRM_IOCTL_DEF_DRV(NOUVEAU_GEM_INFO, nouveau_gem_ioctl_info, DRM_UNLOCKED|DRM_AUTH|DRM_RENDER_ALLOW),
77145f1c
BS
811};
812
5addcf0a
DA
813long nouveau_drm_ioctl(struct file *filp,
814 unsigned int cmd, unsigned long arg)
815{
816 struct drm_file *file_priv = filp->private_data;
817 struct drm_device *dev;
818 long ret;
819 dev = file_priv->minor->dev;
820
821 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 822 if (ret < 0 && ret != -EACCES)
5addcf0a
DA
823 return ret;
824
825 ret = drm_ioctl(filp, cmd, arg);
826
827 pm_runtime_mark_last_busy(dev->dev);
828 pm_runtime_put_autosuspend(dev->dev);
829 return ret;
830}
77145f1c
BS
831static const struct file_operations
832nouveau_driver_fops = {
833 .owner = THIS_MODULE,
834 .open = drm_open,
835 .release = drm_release,
5addcf0a 836 .unlocked_ioctl = nouveau_drm_ioctl,
77145f1c
BS
837 .mmap = nouveau_ttm_mmap,
838 .poll = drm_poll,
77145f1c
BS
839 .read = drm_read,
840#if defined(CONFIG_COMPAT)
841 .compat_ioctl = nouveau_compat_ioctl,
842#endif
843 .llseek = noop_llseek,
844};
845
846static struct drm_driver
847driver = {
848 .driver_features =
4cb4ea39 849 DRIVER_USE_AGP |
7d761258 850 DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
77145f1c
BS
851
852 .load = nouveau_drm_load,
853 .unload = nouveau_drm_unload,
854 .open = nouveau_drm_open,
855 .preclose = nouveau_drm_preclose,
856 .postclose = nouveau_drm_postclose,
857 .lastclose = nouveau_vga_lastclose,
858
33b903e8
MS
859#if defined(CONFIG_DEBUG_FS)
860 .debugfs_init = nouveau_debugfs_init,
861 .debugfs_cleanup = nouveau_debugfs_takedown,
862#endif
863
77145f1c 864 .get_vblank_counter = drm_vblank_count,
51cb4b39
BS
865 .enable_vblank = nouveau_display_vblank_enable,
866 .disable_vblank = nouveau_display_vblank_disable,
d83ef853
BS
867 .get_scanout_position = nouveau_display_scanoutpos,
868 .get_vblank_timestamp = nouveau_display_vblstamp,
77145f1c
BS
869
870 .ioctls = nouveau_ioctls,
baa70943 871 .num_ioctls = ARRAY_SIZE(nouveau_ioctls),
77145f1c
BS
872 .fops = &nouveau_driver_fops,
873
874 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
875 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
ab9ccb96
AP
876 .gem_prime_export = drm_gem_prime_export,
877 .gem_prime_import = drm_gem_prime_import,
878 .gem_prime_pin = nouveau_gem_prime_pin,
1af7c7dd 879 .gem_prime_unpin = nouveau_gem_prime_unpin,
ab9ccb96
AP
880 .gem_prime_get_sg_table = nouveau_gem_prime_get_sg_table,
881 .gem_prime_import_sg_table = nouveau_gem_prime_import_sg_table,
882 .gem_prime_vmap = nouveau_gem_prime_vmap,
883 .gem_prime_vunmap = nouveau_gem_prime_vunmap,
77145f1c 884
77145f1c
BS
885 .gem_free_object = nouveau_gem_object_del,
886 .gem_open_object = nouveau_gem_object_open,
887 .gem_close_object = nouveau_gem_object_close,
888
889 .dumb_create = nouveau_display_dumb_create,
890 .dumb_map_offset = nouveau_display_dumb_map_offset,
43387b37 891 .dumb_destroy = drm_gem_dumb_destroy,
77145f1c
BS
892
893 .name = DRIVER_NAME,
894 .desc = DRIVER_DESC,
895#ifdef GIT_REVISION
896 .date = GIT_REVISION,
897#else
898 .date = DRIVER_DATE,
899#endif
900 .major = DRIVER_MAJOR,
901 .minor = DRIVER_MINOR,
902 .patchlevel = DRIVER_PATCHLEVEL,
903};
904
94580299
BS
905static struct pci_device_id
906nouveau_drm_pci_table[] = {
907 {
908 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
909 .class = PCI_BASE_CLASS_DISPLAY << 16,
910 .class_mask = 0xff << 16,
911 },
912 {
913 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID),
914 .class = PCI_BASE_CLASS_DISPLAY << 16,
915 .class_mask = 0xff << 16,
916 },
917 {}
918};
919
5addcf0a
DA
920static int nouveau_pmops_runtime_suspend(struct device *dev)
921{
922 struct pci_dev *pdev = to_pci_dev(dev);
923 struct drm_device *drm_dev = pci_get_drvdata(pdev);
924 int ret;
925
adbbdbac
DA
926 if (nouveau_runtime_pm == 0) {
927 pm_runtime_forbid(dev);
928 return -EBUSY;
929 }
5addcf0a 930
b25b4427
IM
931 /* are we optimus enabled? */
932 if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
933 DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
adbbdbac
DA
934 pm_runtime_forbid(dev);
935 return -EBUSY;
b25b4427
IM
936 }
937
c52f4fa6 938 nv_debug_level(SILENT);
5addcf0a
DA
939 drm_kms_helper_poll_disable(drm_dev);
940 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
941 nouveau_switcheroo_optimus_dsm();
05c63c2f 942 ret = nouveau_do_suspend(drm_dev, true);
5addcf0a
DA
943 pci_save_state(pdev);
944 pci_disable_device(pdev);
945 pci_set_power_state(pdev, PCI_D3cold);
946 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
947 return ret;
948}
949
950static int nouveau_pmops_runtime_resume(struct device *dev)
951{
952 struct pci_dev *pdev = to_pci_dev(dev);
953 struct drm_device *drm_dev = pci_get_drvdata(pdev);
967e7bde 954 struct nvif_device *device = &nouveau_drm(drm_dev)->device;
5addcf0a
DA
955 int ret;
956
957 if (nouveau_runtime_pm == 0)
958 return -EINVAL;
959
960 pci_set_power_state(pdev, PCI_D0);
961 pci_restore_state(pdev);
962 ret = pci_enable_device(pdev);
963 if (ret)
964 return ret;
965 pci_set_master(pdev);
966
967 ret = nouveau_do_resume(drm_dev);
5addcf0a
DA
968 drm_kms_helper_poll_enable(drm_dev);
969 /* do magic */
db2bec18 970 nvif_mask(device, 0x88488, (1 << 25), (1 << 25));
5addcf0a
DA
971 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
972 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
c52f4fa6 973 nv_debug_level(NORMAL);
5addcf0a
DA
974 return ret;
975}
976
977static int nouveau_pmops_runtime_idle(struct device *dev)
978{
979 struct pci_dev *pdev = to_pci_dev(dev);
980 struct drm_device *drm_dev = pci_get_drvdata(pdev);
981 struct nouveau_drm *drm = nouveau_drm(drm_dev);
982 struct drm_crtc *crtc;
983
adbbdbac
DA
984 if (nouveau_runtime_pm == 0) {
985 pm_runtime_forbid(dev);
5addcf0a 986 return -EBUSY;
adbbdbac 987 }
5addcf0a
DA
988
989 /* are we optimus enabled? */
990 if (nouveau_runtime_pm == -1 && !nouveau_is_optimus() && !nouveau_is_v1_dsm()) {
991 DRM_DEBUG_DRIVER("failing to power off - not optimus\n");
adbbdbac 992 pm_runtime_forbid(dev);
5addcf0a
DA
993 return -EBUSY;
994 }
995
996 /* if we have a hdmi audio device - make sure it has a driver loaded */
997 if (drm->hdmi_device) {
998 if (!drm->hdmi_device->driver) {
999 DRM_DEBUG_DRIVER("failing to power off - no HDMI audio driver loaded\n");
1000 pm_runtime_mark_last_busy(dev);
1001 return -EBUSY;
1002 }
1003 }
1004
1005 list_for_each_entry(crtc, &drm->dev->mode_config.crtc_list, head) {
1006 if (crtc->enabled) {
1007 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1008 return -EBUSY;
1009 }
1010 }
1011 pm_runtime_mark_last_busy(dev);
1012 pm_runtime_autosuspend(dev);
1013 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
1014 return 1;
1015}
1016
2d8b9ccb
DA
1017static const struct dev_pm_ops nouveau_pm_ops = {
1018 .suspend = nouveau_pmops_suspend,
1019 .resume = nouveau_pmops_resume,
1020 .freeze = nouveau_pmops_freeze,
1021 .thaw = nouveau_pmops_thaw,
1022 .poweroff = nouveau_pmops_freeze,
1023 .restore = nouveau_pmops_resume,
5addcf0a
DA
1024 .runtime_suspend = nouveau_pmops_runtime_suspend,
1025 .runtime_resume = nouveau_pmops_runtime_resume,
1026 .runtime_idle = nouveau_pmops_runtime_idle,
2d8b9ccb
DA
1027};
1028
94580299
BS
1029static struct pci_driver
1030nouveau_drm_pci_driver = {
1031 .name = "nouveau",
1032 .id_table = nouveau_drm_pci_table,
1033 .probe = nouveau_drm_probe,
1034 .remove = nouveau_drm_remove,
2d8b9ccb 1035 .driver.pm = &nouveau_pm_ops,
94580299
BS
1036};
1037
8ba9ff11
AC
1038struct drm_device *
1039nouveau_platform_device_create_(struct platform_device *pdev, int size,
1040 void **pobject)
420b9469 1041{
8ba9ff11
AC
1042 struct drm_device *drm;
1043 int err;
420b9469 1044
8ba9ff11 1045 err = nouveau_device_create_(pdev, NOUVEAU_BUS_PLATFORM,
420b9469
AC
1046 nouveau_platform_name(pdev),
1047 dev_name(&pdev->dev), nouveau_config,
8ba9ff11
AC
1048 nouveau_debug, size, pobject);
1049 if (err)
1050 return ERR_PTR(err);
1051
1052 drm = drm_dev_alloc(&driver, &pdev->dev);
1053 if (!drm) {
1054 err = -ENOMEM;
1055 goto err_free;
420b9469
AC
1056 }
1057
8ba9ff11
AC
1058 err = drm_dev_set_unique(drm, "%s", dev_name(&pdev->dev));
1059 if (err < 0)
1060 goto err_free;
1061
1062 drm->platformdev = pdev;
1063 platform_set_drvdata(pdev, drm);
1064
1065 return drm;
1066
1067err_free:
1068 nouveau_object_ref(NULL, (struct nouveau_object **)pobject);
1069
1070 return ERR_PTR(err);
420b9469 1071}
8ba9ff11 1072EXPORT_SYMBOL(nouveau_platform_device_create_);
420b9469 1073
94580299
BS
1074static int __init
1075nouveau_drm_init(void)
1076{
77145f1c
BS
1077 if (nouveau_modeset == -1) {
1078#ifdef CONFIG_VGA_CONSOLE
1079 if (vgacon_text_force())
1080 nouveau_modeset = 0;
77145f1c 1081#endif
77145f1c
BS
1082 }
1083
1084 if (!nouveau_modeset)
1085 return 0;
1086
1087 nouveau_register_dsm_handler();
1088 return drm_pci_init(&driver, &nouveau_drm_pci_driver);
94580299
BS
1089}
1090
1091static void __exit
1092nouveau_drm_exit(void)
1093{
77145f1c
BS
1094 if (!nouveau_modeset)
1095 return;
1096
1097 drm_pci_exit(&driver, &nouveau_drm_pci_driver);
1098 nouveau_unregister_dsm_handler();
94580299
BS
1099}
1100
1101module_init(nouveau_drm_init);
1102module_exit(nouveau_drm_exit);
1103
1104MODULE_DEVICE_TABLE(pci, nouveau_drm_pci_table);
77145f1c
BS
1105MODULE_AUTHOR(DRIVER_AUTHOR);
1106MODULE_DESCRIPTION(DRIVER_DESC);
94580299 1107MODULE_LICENSE("GPL and additional rights");