[linux-2.6-block.git] / drivers / gpu / drm / nouveau / dispnv50 / atom.h

#ifndef __NV50_KMS_ATOM_H__
#define __NV50_KMS_ATOM_H__
#define nv50_atom(p) container_of((p), struct nv50_atom, state)
#include <drm/drm_atomic.h>

struct nv50_atom {
	struct drm_atomic_state state;

	struct list_head outp;
	bool lock_core;
	bool flush_disable;
};

#define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)

struct nv50_head_atom {
	struct drm_crtc_state state;

	struct {
		u32 mask;
		u32 olut;
	} wndw;

	struct {
		u16 iW;
		u16 iH;
		u16 oW;
		u16 oH;
	} view;

	struct nv50_head_mode {
		bool interlace;
		u32 clock;
		struct {
			u16 active;
			u16 synce;
			u16 blanke;
			u16 blanks;
		} h;
		struct {
			u32 active;
			u16 synce;
			u16 blanke;
			u16 blanks;
			u16 blank2s;
			u16 blank2e;
			u16 blankus;
		} v;
	} mode;

	struct {
		bool visible;
		u32 handle;
		u64 offset:40;
		u8 buffer:1;
		u8 mode:4;
	} olut;

	struct {
		bool visible;
		u32 handle;
		u64 offset:40;
		u8  format;
		u8  kind:7;
		u8  layout:1;
		u8  blockh:4;
		u16 blocks:12;
		u32 pitch:20;
		u16 x;
		u16 y;
		u16 w;
		u16 h;
	} core;

	struct {
		bool visible;
		u32 handle;
		u64 offset:40;
		u8  layout:2;
		u8  format:1;
	} curs;

	struct {
		u8  depth;
		u8  cpp;
		u16 x;
		u16 y;
		u16 w;
		u16 h;
	} base;

	struct {
		u8 cpp;
	} ovly;

	struct {
		bool enable:1;
		u8 bits:2;
		u8 mode:4;
	} dither;

	struct {
		struct {
			u16 cos:12;
			u16 sin:12;
		} sat;
	} procamp;

	struct {
		u8 nhsync:1;
		u8 nvsync:1;
		u8 depth:4;
	} or;

	union nv50_head_atom_mask {
		struct {
			bool olut:1;
			bool core:1;
			bool curs:1;
			bool view:1;
			bool mode:1;
			bool base:1;
			bool ovly:1;
			bool dither:1;
			bool procamp:1;
			bool or:1;
		};
		u16 mask;
	} set, clr;
};

static inline struct nv50_head_atom *
nv50_head_atom_get(struct drm_atomic_state *state, struct drm_crtc *crtc)
{
	struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
	if (IS_ERR(statec))
		return (void *)statec;
	return nv50_head_atom(statec);
}

#define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)

struct nv50_wndw_atom {
	struct drm_plane_state state;

	struct drm_property_blob *ilut;
	bool visible;

	struct {
		u32  handle;
		u16  offset:12;
		bool awaken:1;
	} ntfy;

	struct {
		u32 handle;
		u16 offset:12;
		u32 acquire;
		u32 release;
	} sema;

	struct {
		u32 handle;
		struct {
			u64 offset:40;
			u8  buffer:1;
			u8  enable:2;
			u8  mode:4;
		} i;
	} xlut;

	struct {
		u8  mode:2;
		u8  interval:4;

		u8  format;
		u8  kind:7;
		u8  layout:1;
		u8  blockh:4;
		u16 blocks[3];
		u32 pitch[3];
		u16 w;
		u16 h;

		u32 handle[6];
		u64 offset[6];
	} image;

	struct {
		u16 x;
		u16 y;
	} point;

	union nv50_wndw_atom_mask {
		struct {
			bool ntfy:1;
			bool sema:1;
			bool xlut:1;
			bool image:1;
			bool point:1;
		};
		u8 mask;
	} set, clr;
};
#endif
Commit	Line	Data
1590700d BS	1	#ifndef __NV50_KMS_ATOM_H__
	2	#define __NV50_KMS_ATOM_H__
	3	#define nv50_atom(p) container_of((p), struct nv50_atom, state)
	4	#include <drm/drm_atomic.h>
	5
	6	struct nv50_atom {
	7	struct drm_atomic_state state;
	8
	9	struct list_head outp;
	10	bool lock_core;
	11	bool flush_disable;
	12	};
	13
	14	#define nv50_head_atom(p) container_of((p), struct nv50_head_atom, state)
	15
	16	struct nv50_head_atom {
	17	struct drm_crtc_state state;
	18
119608a7 BS	19	struct {
	20	u32 mask;
	21	u32 olut;
	22	} wndw;
	23
1590700d BS	24	struct {
	25	u16 iW;
	26	u16 iH;
	27	u16 oW;
	28	u16 oH;
	29	} view;
	30
	31	struct nv50_head_mode {
	32	bool interlace;
	33	u32 clock;
	34	struct {
	35	u16 active;
	36	u16 synce;
	37	u16 blanke;
	38	u16 blanks;
	39	} h;
	40	struct {
	41	u32 active;
	42	u16 synce;
	43	u16 blanke;
	44	u16 blanks;
	45	u16 blank2s;
	46	u16 blank2e;
	47	u16 blankus;
	48	} v;
	49	} mode;
	50
	51	struct {
	52	bool visible;
	53	u32 handle;
	54	u64 offset:40;
119608a7 BS	55	u8 buffer:1;
	56	u8 mode:4;
	57	} olut;
1590700d BS	58
	59	struct {
	60	bool visible;
	61	u32 handle;
	62	u64 offset:40;
	63	u8 format;
	64	u8 kind:7;
	65	u8 layout:1;
b05d8738 BS	66	u8 blockh:4;
b05d8738 BS	67	u16 blocks:12;
1590700d BS	68	u32 pitch:20;
	69	u16 x;
	70	u16 y;
	71	u16 w;
	72	u16 h;
	73	} core;
	74
	75	struct {
	76	bool visible;
	77	u32 handle;
	78	u64 offset:40;
01d380ab	79	u8 layout:2;
1590700d BS	80	u8 format:1;
	81	} curs;
	82
	83	struct {
	84	u8 depth;
	85	u8 cpp;
	86	u16 x;
	87	u16 y;
	88	u16 w;
	89	u16 h;
	90	} base;
	91
	92	struct {
	93	u8 cpp;
	94	} ovly;
	95
	96	struct {
	97	bool enable:1;
	98	u8 bits:2;
	99	u8 mode:4;
	100	} dither;
	101
	102	struct {
	103	struct {
	104	u16 cos:12;
	105	u16 sin:12;
	106	} sat;
	107	} procamp;
	108
	109	struct {
	110	u8 nhsync:1;
	111	u8 nvsync:1;
	112	u8 depth:4;
	113	} or;
	114
f88bc9d3	115	union nv50_head_atom_mask {
1590700d	116	struct {
119608a7	117	bool olut:1;
1590700d BS	118	bool core:1;
	119	bool curs:1;
	120	bool view:1;
	121	bool mode:1;
	122	bool base:1;
	123	bool ovly:1;
	124	bool dither:1;
	125	bool procamp:1;
	126	bool or:1;
	127	};
	128	u16 mask;
f88bc9d3	129	} set, clr;
1590700d BS	130	};
	131
	132	static inline struct nv50_head_atom *
	133	nv50_head_atom_get(struct drm_atomic_state state, struct drm_crtc crtc)
	134	{
	135	struct drm_crtc_state *statec = drm_atomic_get_crtc_state(state, crtc);
	136	if (IS_ERR(statec))
	137	return (void *)statec;
	138	return nv50_head_atom(statec);
	139	}
	140
	141	#define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
	142
	143	struct nv50_wndw_atom {
	144	struct drm_plane_state state;
1590700d	145
119608a7	146	struct drm_property_blob *ilut;
859b456b BS	147	bool visible;
859b456b BS	148
1590700d BS	149	struct {
	150	u32 handle;
	151	u16 offset:12;
	152	bool awaken:1;
	153	} ntfy;
	154
	155	struct {
	156	u32 handle;
	157	u16 offset:12;
	158	u32 acquire;
	159	u32 release;
	160	} sema;
	161
	162	struct {
119608a7 BS	163	u32 handle;
	164	struct {
	165	u64 offset:40;
	166	u8 buffer:1;
	167	u8 enable:2;
	168	u8 mode:4;
	169	} i;
	170	} xlut;
1590700d BS	171
	172	struct {
	173	u8 mode:2;
	174	u8 interval:4;
	175
	176	u8 format;
	177	u8 kind:7;
	178	u8 layout:1;
b05d8738 BS	179	u8 blockh:4;
b05d8738 BS	180	u16 blocks[3];
261fcfa9	181	u32 pitch[3];
1590700d BS	182	u16 w;
	183	u16 h;
	184
261fcfa9 BS	185	u32 handle[6];
261fcfa9 BS	186	u64 offset[6];
1590700d BS	187	} image;
	188
	189	struct {
	190	u16 x;
	191	u16 y;
	192	} point;
	193
f88bc9d3	194	union nv50_wndw_atom_mask {
1590700d BS	195	struct {
	196	bool ntfy:1;
	197	bool sema:1;
119608a7	198	bool xlut:1;
1590700d	199	bool image:1;
1590700d BS	200	bool point:1;
	201	};
	202	u8 mask;
f88bc9d3	203	} set, clr;
1590700d BS	204	};
1590700d BS	205	#endif