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drm/nouveau: implement devinit subdev, and new init table parser
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / core / subdev / bios / init.c
CommitLineData
cb75d97e
BS		 1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
5#include <subdev/bios/conn.h>
6#include <subdev/bios/bmp.h>
7#include <subdev/bios/bit.h>
8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
10#include <subdev/bios/init.h>
11#include <subdev/devinit.h>
12#include <subdev/clock.h>
13#include <subdev/i2c.h>
14#include <subdev/vga.h>
15#include <subdev/gpio.h>
16
17#define bioslog(lvl, fmt, args...) do { \
18 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
19 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
20} while(0)
21#define cont(fmt, args...) do { \
22 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
23 printk(fmt, ##args); \
24} while(0)
25#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
26#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
27#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
28
29/******************************************************************************
30 * init parser control flow helpers
31 *****************************************************************************/
32
33static inline bool
34init_exec(struct nvbios_init *init)
35{
36 return (init->execute == 1) || ((init->execute & 5) == 5);
37}
38
39static inline void
40init_exec_set(struct nvbios_init *init, bool exec)
41{
42 if (exec) init->execute &= 0xfd;
43 else init->execute |= 0x02;
44}
45
46static inline void
47init_exec_inv(struct nvbios_init *init)
48{
49 init->execute ^= 0x02;
50}
51
52static inline void
53init_exec_force(struct nvbios_init *init, bool exec)
54{
55 if (exec) init->execute |= 0x04;
56 else init->execute &= 0xfb;
57}
58
59/******************************************************************************
60 * init parser wrappers for normal register/i2c/whatever accessors
61 *****************************************************************************/
62
63static inline int
64init_or(struct nvbios_init *init)
65{
66 if (init->outp)
67 return ffs(init->outp->or) - 1;
68 error("script needs OR!!\n");
69 return 0;
70}
71
72static inline int
73init_link(struct nvbios_init *init)
74{
75 if (init->outp)
76 return !(init->outp->sorconf.link & 1);
77 error("script needs OR link\n");
78 return 0;
79}
80
81static inline int
82init_crtc(struct nvbios_init *init)
83{
84 if (init->crtc >= 0)
85 return init->crtc;
86 error("script needs crtc\n");
87 return 0;
88}
89
90static u8
91init_conn(struct nvbios_init *init)
92{
93 struct nouveau_bios *bios = init->bios;
94
95 if (init->outp) {
96 u8 ver, len;
97 u16 conn = dcb_conn(bios, init->outp->connector, &ver, &len);
98 if (conn)
99 return nv_ro08(bios, conn);
100 }
101
102 error("script needs connector type\n");
103 return 0x00;
104}
105
106static inline u32
107init_nvreg(struct nvbios_init *init, u32 reg)
108{
109 /* C51 (at least) sometimes has the lower bits set which the VBIOS
110 * interprets to mean that access needs to go through certain IO
111 * ports instead. The NVIDIA binary driver has been seen to access
112 * these through the NV register address, so lets assume we can
113 * do the same
114 */
115 reg &= ~0x00000003;
116
117 /* GF8+ display scripts need register addresses mangled a bit to
118 * select a specific CRTC/OR
119 */
120 if (nv_device(init->bios)->card_type >= NV_50) {
121 if (reg & 0x80000000) {
122 reg += init_crtc(init) * 0x800;
123 reg &= ~0x80000000;
124 }
125
126 if (reg & 0x40000000) {
127 reg += init_or(init) * 0x800;
128 reg &= ~0x40000000;
129 if (reg & 0x20000000) {
130 reg += init_link(init) * 0x80;
131 reg &= ~0x20000000;
132 }
133 }
134 }
135
136 if (reg & ~0x00fffffc)
137 warn("unknown bits in register 0x%08x\n", reg);
138 return reg;
139}
140
141static u32
142init_rd32(struct nvbios_init *init, u32 reg)
143{
144 reg = init_nvreg(init, reg);
145 if (init_exec(init))
146 return nv_rd32(init->subdev, reg);
147 return 0x00000000;
148}
149
150static void
151init_wr32(struct nvbios_init *init, u32 reg, u32 val)
152{
153 reg = init_nvreg(init, reg);
154 if (init_exec(init))
155 nv_wr32(init->subdev, reg, val);
156}
157
158static u32
159init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
160{
161 reg = init_nvreg(init, reg);
162 if (init_exec(init)) {
163 u32 tmp = nv_rd32(init->subdev, reg);
164 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
165 return tmp;
166 }
167 return 0x00000000;
168}
169
170static u8
171init_rdport(struct nvbios_init *init, u16 port)
172{
173 if (init_exec(init))
174 return nv_rdport(init->subdev, init->crtc, port);
175 return 0x00;
176}
177
178static void
179init_wrport(struct nvbios_init *init, u16 port, u8 value)
180{
181 if (init_exec(init))
182 nv_wrport(init->subdev, init->crtc, port, value);
183}
184
185static u8
186init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
187{
188 struct nouveau_subdev *subdev = init->subdev;
189 if (init_exec(init)) {
190 int head = init->crtc < 0 ? 0 : init->crtc;
191 return nv_rdvgai(subdev, head, port, index);
192 }
193 return 0x00;
194}
195
196static void
197init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
198{
199 /* force head 0 for updates to cr44, it only exists on first head */
200 if (nv_device(init->subdev)->card_type < NV_50) {
201 if (port == 0x03d4 && index == 0x44)
202 init->crtc = 0;
203 }
204
205 if (init_exec(init)) {
206 int head = init->crtc < 0 ? 0 : init->crtc;
207 nv_wrvgai(init->subdev, head, port, index, value);
208 }
209
210 /* select head 1 if cr44 write selected it */
211 if (nv_device(init->subdev)->card_type < NV_50) {
212 if (port == 0x03d4 && index == 0x44 && value == 3)
213 init->crtc = 1;
214 }
215}
216
217static struct nouveau_i2c_port *
218init_i2c(struct nvbios_init *init, int index)
219{
220 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
221
222 if (index == 0xff) {
223 index = NV_I2C_DEFAULT(0);
224 if (init->outp && init->outp->i2c_upper_default)
225 index = NV_I2C_DEFAULT(1);
226 } else
227 if (index < 0) {
228 if (!init->outp) {
229 error("script needs output for i2c\n");
230 return NULL;
231 }
232
233 index = init->outp->i2c_index;
234 }
235
236 return i2c->find(i2c, index);
237}
238
239static int
240init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
241{
242 struct nouveau_i2c_port *port = init_i2c(init, index);
243 if (port && init_exec(init))
244 return nv_rdi2cr(port, addr, reg);
245 return -ENODEV;
246}
247
248static int
249init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
250{
251 struct nouveau_i2c_port *port = init_i2c(init, index);
252 if (port && init_exec(init))
253 return nv_wri2cr(port, addr, reg, val);
254 return -ENODEV;
255}
256
257static int
258init_rdauxr(struct nvbios_init *init, u32 addr)
259{
260 struct nouveau_i2c_port *port = init_i2c(init, -1);
261 u8 data;
262
263 if (port && init_exec(init)) {
264 int ret = nv_rdaux(port, addr, &data, 1);
265 if (ret)
266 return ret;
267 return data;
268 }
269
270 return -ENODEV;
271}
272
273static int
274init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
275{
276 struct nouveau_i2c_port *port = init_i2c(init, -1);
277 if (port && init_exec(init))
278 return nv_wraux(port, addr, &data, 1);
279 return -ENODEV;
280}
281
282static void
283init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
284{
285 struct nouveau_clock *clk = nouveau_clock(init->bios);
286 if (clk && clk->pll_set && init_exec(init)) {
287 int ret = clk->pll_set(clk, id, freq);
288 if (ret)
289 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
290 }
291}
292
293/******************************************************************************
294 * parsing of bios structures that are required to execute init tables
295 *****************************************************************************/
296
297static u16
298init_table(struct nouveau_bios *bios, u16 *len)
299{
300 struct bit_entry bit_I;
301
302 if (!bit_entry(bios, 'I', &bit_I)) {
303 *len = bit_I.length;
304 return bit_I.offset;
305 }
306
307 if (bmp_version(bios) >= 0x0510) {
308 *len = 14;
309 return bios->bmp_offset + 75;
310 }
311
312 return 0x0000;
313}
314
315static u16
316init_table_(struct nvbios_init *init, u16 offset, const char *name)
317{
318 struct nouveau_bios *bios = init->bios;
319 u16 len, data = init_table(bios, &len);
320 if (data) {
321 if (len >= offset + 2) {
322 data = nv_ro16(bios, data + offset);
323 if (data)
324 return data;
325
326 warn("%s pointer invalid\n", name);
327 return 0x0000;
328 }
329
330 warn("init data too short for %s pointer", name);
331 return 0x0000;
332 }
333
334 warn("init data not found\n");
335 return 0x0000;
336}
337
338#define init_script_table(b) init_table_((b), 0x00, "script table")
339#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
340#define init_macro_table(b) init_table_((b), 0x04, "macro table")
341#define init_condition_table(b) init_table_((b), 0x06, "condition table")
342#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
343#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
344#define init_function_table(b) init_table_((b), 0x0c, "function table")
345#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
346
347static u16
348init_script(struct nouveau_bios *bios, int index)
349{
350 struct nvbios_init init = { .bios = bios };
351 u16 data;
352
353 if (bmp_version(bios) && bmp_version(bios) < 0x0510) {
354 if (index > 1)
355 return 0x0000;
356
357 data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18);
358 return nv_ro16(bios, data + (index * 2));
359 }
360
361 data = init_script_table(&init);
362 if (data)
363 return nv_ro16(bios, data + (index * 2));
364
365 return 0x0000;
366}
367
368static u16
369init_unknown_script(struct nouveau_bios *bios)
370{
371 u16 len, data = init_table(bios, &len);
372 if (data && len >= 16)
373 return nv_ro16(bios, data + 14);
374 return 0x0000;
375}
376
377static u16
378init_ram_restrict_table(struct nvbios_init *init)
379{
380 struct nouveau_bios *bios = init->bios;
381 struct bit_entry bit_M;
382 u16 data = 0x0000;
383
384 if (!bit_entry(bios, 'M', &bit_M)) {
385 if (bit_M.version == 1 && bit_M.length >= 5)
386 data = nv_ro16(bios, bit_M.offset + 3);
387 if (bit_M.version == 2 && bit_M.length >= 3)
388 data = nv_ro16(bios, bit_M.offset + 1);
389 }
390
391 if (data == 0x0000)
392 warn("ram restrict table not found\n");
393 return data;
394}
395
396static u8
397init_ram_restrict_group_count(struct nvbios_init *init)
398{
399 struct nouveau_bios *bios = init->bios;
400 struct bit_entry bit_M;
401
402 if (!bit_entry(bios, 'M', &bit_M)) {
403 if (bit_M.version == 1 && bit_M.length >= 5)
404 return nv_ro08(bios, bit_M.offset + 2);
405 if (bit_M.version == 2 && bit_M.length >= 3)
406 return nv_ro08(bios, bit_M.offset + 0);
407 }
408
409 return 0x00;
410}
411
412static u8
413init_ram_restrict(struct nvbios_init *init)
414{
415 u32 strap = (init_rd32(init, 0x101000) & 0x0000003c) >> 2;
416 u16 table = init_ram_restrict_table(init);
417 if (table)
418 return nv_ro08(init->bios, table + strap);
419 return 0x00;
420}
421
422static u8
423init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
424{
425 struct nouveau_bios *bios = init->bios;
426 u16 table = init_xlat_table(init);
427 if (table) {
428 u16 data = nv_ro16(bios, table + (index * 2));
429 if (data)
430 return nv_ro08(bios, data + offset);
431 warn("xlat table pointer %d invalid\n", index);
432 }
433 return 0x00;
434}
435
436/******************************************************************************
437 * utility functions used by various init opcode handlers
438 *****************************************************************************/
439
440static bool
441init_condition_met(struct nvbios_init *init, u8 cond)
442{
443 struct nouveau_bios *bios = init->bios;
444 u16 table = init_condition_table(init);
445 if (table) {
446 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
447 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
448 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
449 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
450 cond, reg, msk, val);
451 return (init_rd32(init, reg) & msk) == val;
452 }
453 return false;
454}
455
456static bool
457init_io_condition_met(struct nvbios_init *init, u8 cond)
458{
459 struct nouveau_bios *bios = init->bios;
460 u16 table = init_io_condition_table(init);
461 if (table) {
462 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
463 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
464 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
465 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
466 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
467 cond, port, index, mask, value);
468 return (init_rdvgai(init, port, index) & mask) == value;
469 }
470 return false;
471}
472
473static bool
474init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
475{
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_io_flag_condition_table(init);
478 if (table) {
479 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
480 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
481 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
482 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
483 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
484 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
485 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
486 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
487 return (nv_ro08(bios, data + ioval) & dmask) == value;
488 }
489 return false;
490}
491
492static inline u32
493init_shift(u32 data, u8 shift)
494{
495 if (shift < 0x80)
496 return data >> shift;
497 return data << (0x100 - shift);
498}
499
500static u32
501init_tmds_reg(struct nvbios_init *init, u8 tmds)
502{
503 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
504 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
505 * CR58 for CR57 = 0 to index a table of offsets to the basic
506 * 0x6808b0 address.
507 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
508 * CR58 for CR57 = 0 to index a table of offsets to the basic
509 * 0x6808b0 address, and then flip the offset by 8.
510 */
511
512 const int pramdac_offset[13] = {
513 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
514 const u32 pramdac_table[4] = {
515 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
516
517 if (tmds >= 0x80) {
518 if (init->outp) {
519 u32 dacoffset = pramdac_offset[init->outp->or];
520 if (tmds == 0x81)
521 dacoffset ^= 8;
522 return 0x6808b0 + dacoffset;
523 }
524
525 error("tmds opcodes need dcb\n");
526 } else {
527 if (tmds < ARRAY_SIZE(pramdac_table))
528 return pramdac_table[tmds];
529
530 error("tmds selector 0x%02x unknown\n", tmds);
531 }
532
533 return 0;
534}
535
536/******************************************************************************
537 * init opcode handlers
538 *****************************************************************************/
539
540/**
541 * init_reserved - stub for various unknown/unused single-byte opcodes
542 *
543 */
544static void
545init_reserved(struct nvbios_init *init)
546{
547 u8 opcode = nv_ro08(init->bios, init->offset);
548 trace("RESERVED\t0x%02x\n", opcode);
549 init->offset += 1;
550}
551
552/**
553 * INIT_DONE - opcode 0x71
554 *
555 */
556static void
557init_done(struct nvbios_init *init)
558{
559 trace("DONE\n");
560 init->offset = 0x0000;
561}
562
563/**
564 * INIT_IO_RESTRICT_PROG - opcode 0x32
565 *
566 */
567static void
568init_io_restrict_prog(struct nvbios_init *init)
569{
570 struct nouveau_bios *bios = init->bios;
571 u16 port = nv_ro16(bios, init->offset + 1);
572 u8 index = nv_ro08(bios, init->offset + 3);
573 u8 mask = nv_ro08(bios, init->offset + 4);
574 u8 shift = nv_ro08(bios, init->offset + 5);
575 u8 count = nv_ro08(bios, init->offset + 6);
576 u32 reg = nv_ro32(bios, init->offset + 7);
577 u8 conf, i;
578
579 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
580 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
581 reg, port, index, mask, shift);
582 init->offset += 11;
583
584 conf = (init_rdvgai(init, port, index) & mask) >> shift;
585 for (i = 0; i < count; i++) {
586 u32 data = nv_ro32(bios, init->offset);
587
588 if (i == conf) {
589 trace("\t0x%08x *\n", data);
590 init_wr32(init, reg, data);
591 } else {
592 trace("\t0x%08x\n", data);
593 }
594
595 init->offset += 4;
596 }
597 trace("}]\n");
598}
599
600/**
601 * INIT_REPEAT - opcode 0x33
602 *
603 */
604static void
605init_repeat(struct nvbios_init *init)
606{
607 struct nouveau_bios *bios = init->bios;
608 u8 count = nv_ro08(bios, init->offset + 1);
609 u16 repeat = init->repeat;
610
611 trace("REPEAT\t0x%02x\n", count);
612 init->offset += 2;
613
614 init->repeat = init->offset;
615 init->repend = init->offset;
616 while (count--) {
617 init->offset = init->repeat;
618 nvbios_exec(init);
619 if (count)
620 trace("REPEAT\t0x%02x\n", count);
621 }
622 init->offset = init->repend;
623 init->repeat = repeat;
624}
625
626/**
627 * INIT_IO_RESTRICT_PLL - opcode 0x34
628 *
629 */
630static void
631init_io_restrict_pll(struct nvbios_init *init)
632{
633 struct nouveau_bios *bios = init->bios;
634 u16 port = nv_ro16(bios, init->offset + 1);
635 u8 index = nv_ro08(bios, init->offset + 3);
636 u8 mask = nv_ro08(bios, init->offset + 4);
637 u8 shift = nv_ro08(bios, init->offset + 5);
638 s8 iofc = nv_ro08(bios, init->offset + 6);
639 u8 count = nv_ro08(bios, init->offset + 7);
640 u32 reg = nv_ro32(bios, init->offset + 8);
641 u8 conf, i;
642
643 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
644 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
645 reg, port, index, mask, shift, iofc);
646 init->offset += 12;
647
648 conf = (init_rdvgai(init, port, index) & mask) >> shift;
649 for (i = 0; i < count; i++) {
650 u32 freq = nv_ro16(bios, init->offset) * 10;
651
652 if (i == conf) {
653 trace("\t%dkHz *\n", freq);
654 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
655 freq *= 2;
656 init_prog_pll(init, reg, freq);
657 } else {
658 trace("\t%dkHz\n", freq);
659 }
660
661 init->offset += 2;
662 }
663 trace("}]\n");
664}
665
666/**
667 * INIT_END_REPEAT - opcode 0x36
668 *
669 */
670static void
671init_end_repeat(struct nvbios_init *init)
672{
673 trace("END_REPEAT\n");
674 init->offset += 1;
675
676 if (init->repeat) {
677 init->repend = init->offset;
678 init->offset = 0;
679 }
680}
681
682/**
683 * INIT_COPY - opcode 0x37
684 *
685 */
686static void
687init_copy(struct nvbios_init *init)
688{
689 struct nouveau_bios *bios = init->bios;
690 u32 reg = nv_ro32(bios, init->offset + 1);
691 u8 shift = nv_ro08(bios, init->offset + 5);
692 u8 smask = nv_ro08(bios, init->offset + 6);
693 u16 port = nv_ro16(bios, init->offset + 7);
694 u8 index = nv_ro08(bios, init->offset + 9);
695 u8 mask = nv_ro08(bios, init->offset + 10);
696 u8 data;
697
698 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
699 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
700 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
701 (shift & 0x80) ? (0x100 - shift) : shift, smask);
702 init->offset += 11;
703
704 data = init_rdvgai(init, port, index) & mask;
705 data |= init_shift(init_rd32(init, reg), shift) & smask;
706 init_wrvgai(init, port, index, data);
707}
708
709/**
710 * INIT_NOT - opcode 0x38
711 *
712 */
713static void
714init_not(struct nvbios_init *init)
715{
716 trace("NOT\n");
717 init->offset += 1;
718 init_exec_inv(init);
719}
720
721/**
722 * INIT_IO_FLAG_CONDITION - opcode 0x39
723 *
724 */
725static void
726init_io_flag_condition(struct nvbios_init *init)
727{
728 struct nouveau_bios *bios = init->bios;
729 u8 cond = nv_ro08(bios, init->offset + 1);
730
731 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
732 init->offset += 2;
733
734 if (!init_io_flag_condition_met(init, cond))
735 init_exec_set(init, false);
736}
737
738/**
739 * INIT_DP_CONDITION - opcode 0x3a
740 *
741 */
742static void
743init_dp_condition(struct nvbios_init *init)
744{
745 struct nouveau_bios *bios = init->bios;
746 u8 cond = nv_ro08(bios, init->offset + 1);
747 u8 unkn = nv_ro08(bios, init->offset + 2);
748 u8 ver, len;
749 u16 data;
750
751 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
752 init->offset += 3;
753
754 switch (cond) {
755 case 0:
756 if (init_conn(init) != DCB_CONNECTOR_eDP)
757 init_exec_set(init, false);
758 break;
759 case 1:
760 case 2:
761 if ( init->outp &&
762 (data = dp_outp_match(bios, init->outp, &ver, &len))) {
763 if (ver <= 0x40 && !(nv_ro08(bios, data + 5) & cond))
764 init_exec_set(init, false);
765 if (ver == 0x40 && !(nv_ro08(bios, data + 4) & cond))
766 init_exec_set(init, false);
767 break;
768 }
769
770 warn("script needs dp output table data\n");
771 break;
772 case 5:
773 if (!(init_rdauxr(init, 0x0d) & 1))
774 init_exec_set(init, false);
775 break;
776 default:
777 warn("unknown dp condition 0x%02x\n", cond);
778 break;
779 }
780}
781
782/**
783 * INIT_IO_MASK_OR - opcode 0x3b
784 *
785 */
786static void
787init_io_mask_or(struct nvbios_init *init)
788{
789 struct nouveau_bios *bios = init->bios;
790 u8 index = nv_ro08(bios, init->offset + 1);
791 u8 or = init_or(init);
792 u8 data;
793
794 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)", index, or);
795 init->offset += 2;
796
797 data = init_rdvgai(init, 0x03d4, index);
798 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
799}
800
801/**
802 * INIT_IO_OR - opcode 0x3c
803 *
804 */
805static void
806init_io_or(struct nvbios_init *init)
807{
808 struct nouveau_bios *bios = init->bios;
809 u8 index = nv_ro08(bios, init->offset + 1);
810 u8 or = init_or(init);
811 u8 data;
812
813 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)", index, or);
814 init->offset += 2;
815
816 data = init_rdvgai(init, 0x03d4, index);
817 init_wrvgai(init, 0x03d4, index, data | (1 << or));
818}
819
820/**
821 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
822 *
823 */
824static void
825init_idx_addr_latched(struct nvbios_init *init)
826{
827 struct nouveau_bios *bios = init->bios;
828 u32 creg = nv_ro32(bios, init->offset + 1);
829 u32 dreg = nv_ro32(bios, init->offset + 5);
830 u32 mask = nv_ro32(bios, init->offset + 9);
831 u32 data = nv_ro32(bios, init->offset + 13);
832 u8 count = nv_ro08(bios, init->offset + 17);
833
834 trace("INDEX_ADDRESS_LATCHED\t"
835 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
836 creg, dreg, mask, data);
837 init->offset += 18;
838
839 while (count--) {
840 u8 iaddr = nv_ro08(bios, init->offset + 0);
841 u8 idata = nv_ro08(bios, init->offset + 1);
842
843 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
844 init->offset += 2;
845
846 init_wr32(init, dreg, idata);
847 init_mask(init, creg, ~mask, data | idata);
848 }
849}
850
851/**
852 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
853 *
854 */
855static void
856init_io_restrict_pll2(struct nvbios_init *init)
857{
858 struct nouveau_bios *bios = init->bios;
859 u16 port = nv_ro16(bios, init->offset + 1);
860 u8 index = nv_ro08(bios, init->offset + 3);
861 u8 mask = nv_ro08(bios, init->offset + 4);
862 u8 shift = nv_ro08(bios, init->offset + 5);
863 u8 count = nv_ro08(bios, init->offset + 6);
864 u32 reg = nv_ro32(bios, init->offset + 7);
865 u8 conf, i;
866
867 trace("IO_RESTRICT_PLL2\t"
868 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
869 reg, port, index, mask, shift);
870 init->offset += 11;
871
872 conf = (init_rdvgai(init, port, index) & mask) >> shift;
873 for (i = 0; i < count; i++) {
874 u32 freq = nv_ro32(bios, init->offset);
875 if (i == conf) {
876 trace("\t%dkHz *\n", freq);
877 init_prog_pll(init, reg, freq);
878 } else {
879 trace("\t%dkHz\n", freq);
880 }
881 init->offset += 4;
882 }
883 trace("}]\n");
884}
885
886/**
887 * INIT_PLL2 - opcode 0x4b
888 *
889 */
890static void
891init_pll2(struct nvbios_init *init)
892{
893 struct nouveau_bios *bios = init->bios;
894 u32 reg = nv_ro32(bios, init->offset + 1);
895 u32 freq = nv_ro32(bios, init->offset + 5);
896
897 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
898 init->offset += 9;
899
900 init_prog_pll(init, reg, freq);
901}
902
903/**
904 * INIT_I2C_BYTE - opcode 0x4c
905 *
906 */
907static void
908init_i2c_byte(struct nvbios_init *init)
909{
910 struct nouveau_bios *bios = init->bios;
911 u8 index = nv_ro08(bios, init->offset + 1);
912 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
913 u8 count = nv_ro08(bios, init->offset + 3);
914
915 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
916 init->offset += 4;
917
918 while (count--) {
919 u8 reg = nv_ro08(bios, init->offset + 0);
920 u8 mask = nv_ro08(bios, init->offset + 1);
921 u8 data = nv_ro08(bios, init->offset + 2);
922 int val;
923
924 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
925 init->offset += 3;
926
927 val = init_rdi2cr(init, index, addr, reg);
928 if (val < 0)
929 continue;
930 init_wri2cr(init, index, addr, reg, (val & mask) | data);
931 }
932}
933
934/**
935 * INIT_ZM_I2C_BYTE - opcode 0x4d
936 *
937 */
938static void
939init_zm_i2c_byte(struct nvbios_init *init)
940{
941 struct nouveau_bios *bios = init->bios;
942 u8 index = nv_ro08(bios, init->offset + 1);
943 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
944 u8 count = nv_ro08(bios, init->offset + 3);
945
946 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
947 init->offset += 4;
948
949 while (count--) {
950 u8 reg = nv_ro08(bios, init->offset + 0);
951 u8 data = nv_ro08(bios, init->offset + 1);
952
953 trace("\t[0x%02x] = 0x%02x\n", reg, data);
954 init->offset += 2;
955
956 init_wri2cr(init, index, addr, reg, data);
957 }
958
959}
960
961/**
962 * INIT_ZM_I2C - opcode 0x4e
963 *
964 */
965static void
966init_zm_i2c(struct nvbios_init *init)
967{
968 struct nouveau_bios *bios = init->bios;
969 u8 index = nv_ro08(bios, init->offset + 1);
970 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
971 u8 count = nv_ro08(bios, init->offset + 3);
972 u8 data[256], i;
973
974 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
975 init->offset += 4;
976
977 for (i = 0; i < count; i++) {
978 data[i] = nv_ro08(bios, init->offset);
979 trace("\t0x%02x\n", data[i]);
980 init->offset++;
981 }
982
983 if (init_exec(init)) {
984 struct nouveau_i2c_port *port = init_i2c(init, index);
985 struct i2c_msg msg = {
986 .addr = addr, .flags = 0, .len = count, .buf = data,
987 };
988 int ret;
989
990 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
991 warn("i2c wr failed, %d\n", ret);
992 }
993}
994
995/**
996 * INIT_TMDS - opcode 0x4f
997 *
998 */
999static void
1000init_tmds(struct nvbios_init *init)
1001{
1002 struct nouveau_bios *bios = init->bios;
1003 u8 tmds = nv_ro08(bios, init->offset + 1);
1004 u8 addr = nv_ro08(bios, init->offset + 2);
1005 u8 mask = nv_ro08(bios, init->offset + 3);
1006 u8 data = nv_ro08(bios, init->offset + 4);
1007 u32 reg = init_tmds_reg(init, tmds);
1008
1009 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1010 tmds, addr, mask, data);
1011 init->offset += 5;
1012
1013 if (reg == 0)
1014 return;
1015
1016 init_wr32(init, reg + 0, addr | 0x00010000);
1017 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1018 init_wr32(init, reg + 0, addr);
1019}
1020
1021/**
1022 * INIT_ZM_TMDS_GROUP - opcode 0x50
1023 *
1024 */
1025static void
1026init_zm_tmds_group(struct nvbios_init *init)
1027{
1028 struct nouveau_bios *bios = init->bios;
1029 u8 tmds = nv_ro08(bios, init->offset + 1);
1030 u8 count = nv_ro08(bios, init->offset + 2);
1031 u32 reg = init_tmds_reg(init, tmds);
1032
1033 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1034 init->offset += 3;
1035
1036 while (count--) {
1037 u8 addr = nv_ro08(bios, init->offset + 0);
1038 u8 data = nv_ro08(bios, init->offset + 1);
1039
1040 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1041 init->offset += 2;
1042
1043 init_wr32(init, reg + 4, data);
1044 init_wr32(init, reg + 0, addr);
1045 }
1046}
1047
1048/**
1049 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1050 *
1051 */
1052static void
1053init_cr_idx_adr_latch(struct nvbios_init *init)
1054{
1055 struct nouveau_bios *bios = init->bios;
1056 u8 addr0 = nv_ro08(bios, init->offset + 1);
1057 u8 addr1 = nv_ro08(bios, init->offset + 2);
1058 u8 base = nv_ro08(bios, init->offset + 3);
1059 u8 count = nv_ro08(bios, init->offset + 4);
1060 u8 save0;
1061
1062 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1063 init->offset += 5;
1064
1065 save0 = init_rdvgai(init, 0x03d4, addr0);
1066 while (count--) {
1067 u8 data = nv_ro08(bios, init->offset);
1068
1069 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1070 init->offset += 1;
1071
1072 init_wrvgai(init, 0x03d4, addr0, base++);
1073 init_wrvgai(init, 0x03d4, addr1, data);
1074 }
1075 init_wrvgai(init, 0x03d4, addr0, save0);
1076}
1077
1078/**
1079 * INIT_CR - opcode 0x52
1080 *
1081 */
1082static void
1083init_cr(struct nvbios_init *init)
1084{
1085 struct nouveau_bios *bios = init->bios;
1086 u8 addr = nv_ro08(bios, init->offset + 1);
1087 u8 mask = nv_ro08(bios, init->offset + 2);
1088 u8 data = nv_ro08(bios, init->offset + 3);
1089 u8 val;
1090
1091 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1092 init->offset += 4;
1093
1094 val = init_rdvgai(init, 0x03d4, addr) & mask;
1095 init_wrvgai(init, 0x03d4, addr, val | data);
1096}
1097
1098/**
1099 * INIT_ZM_CR - opcode 0x53
1100 *
1101 */
1102static void
1103init_zm_cr(struct nvbios_init *init)
1104{
1105 struct nouveau_bios *bios = init->bios;
1106 u8 addr = nv_ro08(bios, init->offset + 1);
1107 u8 data = nv_ro08(bios, init->offset + 2);
1108
1109 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1110 init->offset += 3;
1111
1112 init_wrvgai(init, 0x03d4, addr, data);
1113}
1114
1115/**
1116 * INIT_ZM_CR_GROUP - opcode 0x54
1117 *
1118 */
1119static void
1120init_zm_cr_group(struct nvbios_init *init)
1121{
1122 struct nouveau_bios *bios = init->bios;
1123 u8 count = nv_ro08(bios, init->offset + 1);
1124
1125 trace("ZM_CR_GROUP\n");
1126 init->offset += 2;
1127
1128 while (count--) {
1129 u8 addr = nv_ro08(bios, init->offset + 0);
1130 u8 data = nv_ro08(bios, init->offset + 1);
1131
1132 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1133 init->offset += 2;
1134
1135 init_wrvgai(init, 0x03d4, addr, data);
1136 }
1137}
1138
1139/**
1140 * INIT_CONDITION_TIME - opcode 0x56
1141 *
1142 */
1143static void
1144init_condition_time(struct nvbios_init *init)
1145{
1146 struct nouveau_bios *bios = init->bios;
1147 u8 cond = nv_ro08(bios, init->offset + 1);
1148 u8 retry = nv_ro08(bios, init->offset + 2);
1149 u8 wait = min((u16)retry * 50, 100);
1150
1151 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1152 init->offset += 3;
1153
1154 if (!init_exec(init))
1155 return;
1156
1157 while (wait--) {
1158 if (init_condition_met(init, cond))
1159 return;
1160 mdelay(20);
1161 }
1162
1163 init_exec_set(init, false);
1164}
1165
1166/**
1167 * INIT_LTIME - opcode 0x57
1168 *
1169 */
1170static void
1171init_ltime(struct nvbios_init *init)
1172{
1173 struct nouveau_bios *bios = init->bios;
1174 u16 msec = nv_ro16(bios, init->offset + 1);
1175
1176 trace("LTIME\t0x%04x\n", msec);
1177 init->offset += 3;
1178
1179 if (init_exec(init))
1180 mdelay(msec);
1181}
1182
1183/**
1184 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1185 *
1186 */
1187static void
1188init_zm_reg_sequence(struct nvbios_init *init)
1189{
1190 struct nouveau_bios *bios = init->bios;
1191 u32 base = nv_ro32(bios, init->offset + 1);
1192 u8 count = nv_ro08(bios, init->offset + 5);
1193
1194 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1195 init->offset += 6;
1196
1197 while (count--) {
1198 u32 data = nv_ro32(bios, init->offset);
1199
1200 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1201 init->offset += 4;
1202
1203 init_wr32(init, base, data);
1204 base += 4;
1205 }
1206}
1207
1208/**
1209 * INIT_SUB_DIRECT - opcode 0x5b
1210 *
1211 */
1212static void
1213init_sub_direct(struct nvbios_init *init)
1214{
1215 struct nouveau_bios *bios = init->bios;
1216 u16 addr = nv_ro16(bios, init->offset + 1);
1217 u16 save;
1218
1219 trace("SUB_DIRECT\t0x%04x\n", addr);
1220
1221 if (init_exec(init)) {
1222 save = init->offset;
1223 init->offset = addr;
1224 if (nvbios_exec(init)) {
1225 error("error parsing sub-table\n");
1226 return;
1227 }
1228 init->offset = save;
1229 }
1230
1231 init->offset += 3;
1232}
1233
1234/**
1235 * INIT_JUMP - opcode 0x5c
1236 *
1237 */
1238static void
1239init_jump(struct nvbios_init *init)
1240{
1241 struct nouveau_bios *bios = init->bios;
1242 u16 offset = nv_ro16(bios, init->offset + 1);
1243
1244 trace("JUMP\t0x%04x\n", offset);
1245 init->offset = offset;
1246}
1247
1248/**
1249 * INIT_I2C_IF - opcode 0x5e
1250 *
1251 */
1252static void
1253init_i2c_if(struct nvbios_init *init)
1254{
1255 struct nouveau_bios *bios = init->bios;
1256 u8 index = nv_ro08(bios, init->offset + 1);
1257 u8 addr = nv_ro08(bios, init->offset + 2);
1258 u8 reg = nv_ro08(bios, init->offset + 3);
1259 u8 mask = nv_ro08(bios, init->offset + 4);
1260 u8 data = nv_ro08(bios, init->offset + 5);
1261 u8 value;
1262
1263 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1264 index, addr, reg, mask, data);
1265 init->offset += 6;
1266 init_exec_force(init, true);
1267
1268 value = init_rdi2cr(init, index, addr, reg);
1269 if ((value & mask) != data)
1270 init_exec_set(init, false);
1271
1272 init_exec_force(init, false);
1273}
1274
1275/**
1276 * INIT_COPY_NV_REG - opcode 0x5f
1277 *
1278 */
1279static void
1280init_copy_nv_reg(struct nvbios_init *init)
1281{
1282 struct nouveau_bios *bios = init->bios;
1283 u32 sreg = nv_ro32(bios, init->offset + 1);
1284 u8 shift = nv_ro08(bios, init->offset + 5);
1285 u32 smask = nv_ro32(bios, init->offset + 6);
1286 u32 sxor = nv_ro32(bios, init->offset + 10);
1287 u32 dreg = nv_ro32(bios, init->offset + 14);
1288 u32 dmask = nv_ro32(bios, init->offset + 18);
1289 u32 data;
1290
1291 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1292 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1293 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1294 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1295 init->offset += 22;
1296
1297 data = init_shift(init_rd32(init, sreg), shift);
1298 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1299}
1300
1301/**
1302 * INIT_ZM_INDEX_IO - opcode 0x62
1303 *
1304 */
1305static void
1306init_zm_index_io(struct nvbios_init *init)
1307{
1308 struct nouveau_bios *bios = init->bios;
1309 u16 port = nv_ro16(bios, init->offset + 1);
1310 u8 index = nv_ro08(bios, init->offset + 3);
1311 u8 data = nv_ro08(bios, init->offset + 4);
1312
1313 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1314 init->offset += 5;
1315
1316 init_wrvgai(init, port, index, data);
1317}
1318
1319/**
1320 * INIT_COMPUTE_MEM - opcode 0x63
1321 *
1322 */
1323static void
1324init_compute_mem(struct nvbios_init *init)
1325{
1326 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1327
1328 trace("COMPUTE_MEM\n");
1329 init->offset += 1;
1330
1331 init_exec_force(init, true);
1332 if (init_exec(init) && devinit->meminit)
1333 devinit->meminit(devinit);
1334 init_exec_force(init, false);
1335}
1336
1337/**
1338 * INIT_RESET - opcode 0x65
1339 *
1340 */
1341static void
1342init_reset(struct nvbios_init *init)
1343{
1344 struct nouveau_bios *bios = init->bios;
1345 u32 reg = nv_ro32(bios, init->offset + 1);
1346 u32 data1 = nv_ro32(bios, init->offset + 5);
1347 u32 data2 = nv_ro32(bios, init->offset + 9);
1348 u32 savepci19;
1349
1350 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1351 init->offset += 13;
1352 init_exec_force(init, true);
1353
1354 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1355 init_wr32(init, reg, data1);
1356 udelay(10);
1357 init_wr32(init, reg, data2);
1358 init_wr32(init, 0x00184c, savepci19);
1359 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1360
1361 init_exec_force(init, false);
1362}
1363
1364/**
1365 * INIT_CONFIGURE_MEM - opcode 0x66
1366 *
1367 */
1368static u16
1369init_configure_mem_clk(struct nvbios_init *init)
1370{
1371 u16 mdata = bmp_mem_init_table(init->bios);
1372 if (mdata)
1373 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1374 return mdata;
1375}
1376
1377static void
1378init_configure_mem(struct nvbios_init *init)
1379{
1380 struct nouveau_bios *bios = init->bios;
1381 u16 mdata, sdata;
1382 u32 addr, data;
1383
1384 trace("CONFIGURE_MEM\n");
1385 init->offset += 1;
1386
1387 if (bios->version.major > 2) {
1388 init_done(init);
1389 return;
1390 }
1391 init_exec_force(init, true);
1392
1393 mdata = init_configure_mem_clk(init);
1394 sdata = bmp_sdr_seq_table(bios);
1395 if (nv_ro08(bios, mdata) & 0x01)
1396 sdata = bmp_ddr_seq_table(bios);
1397 mdata += 6; /* skip to data */
1398
1399 data = init_rdvgai(init, 0x03c4, 0x01);
1400 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1401
1402 while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {
1403 switch (addr) {
1404 case 0x10021c: /* CKE_NORMAL */
1405 case 0x1002d0: /* CMD_REFRESH */
1406 case 0x1002d4: /* CMD_PRECHARGE */
1407 data = 0x00000001;
1408 break;
1409 default:
1410 data = nv_ro32(bios, mdata);
1411 mdata += 4;
1412 if (data == 0xffffffff)
1413 continue;
1414 break;
1415 }
1416
1417 init_wr32(init, addr, data);
1418 }
1419
1420 init_exec_force(init, false);
1421}
1422
1423/**
1424 * INIT_CONFIGURE_CLK - opcode 0x67
1425 *
1426 */
1427static void
1428init_configure_clk(struct nvbios_init *init)
1429{
1430 struct nouveau_bios *bios = init->bios;
1431 u16 mdata, clock;
1432
1433 trace("CONFIGURE_CLK\n");
1434 init->offset += 1;
1435
1436 if (bios->version.major > 2) {
1437 init_done(init);
1438 return;
1439 }
1440 init_exec_force(init, true);
1441
1442 mdata = init_configure_mem_clk(init);
1443
1444 /* NVPLL */
1445 clock = nv_ro16(bios, mdata + 4) * 10;
1446 init_prog_pll(init, 0x680500, clock);
1447
1448 /* MPLL */
1449 clock = nv_ro16(bios, mdata + 2) * 10;
1450 if (nv_ro08(bios, mdata) & 0x01)
1451 clock *= 2;
1452 init_prog_pll(init, 0x680504, clock);
1453
1454 init_exec_force(init, false);
1455}
1456
1457/**
1458 * INIT_CONFIGURE_PREINIT - opcode 0x68
1459 *
1460 */
1461static void
1462init_configure_preinit(struct nvbios_init *init)
1463{
1464 struct nouveau_bios *bios = init->bios;
1465 u32 strap;
1466
1467 trace("CONFIGURE_PREINIT\n");
1468 init->offset += 1;
1469
1470 if (bios->version.major > 2) {
1471 init_done(init);
1472 return;
1473 }
1474 init_exec_force(init, true);
1475
1476 strap = init_rd32(init, 0x101000);
1477 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1478 init_wrvgai(init, 0x03d4, 0x3c, strap);
1479
1480 init_exec_force(init, false);
1481}
1482
1483/**
1484 * INIT_IO - opcode 0x69
1485 *
1486 */
1487static void
1488init_io(struct nvbios_init *init)
1489{
1490 struct nouveau_bios *bios = init->bios;
1491 u16 port = nv_ro16(bios, init->offset + 1);
1492 u8 mask = nv_ro16(bios, init->offset + 3);
1493 u8 data = nv_ro16(bios, init->offset + 4);
1494 u8 value;
1495
1496 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1497 init->offset += 5;
1498
1499 /* ummm.. yes.. should really figure out wtf this is and why it's
1500 * needed some day.. it's almost certainly wrong, but, it also
1501 * somehow makes things work...
1502 */
1503 if (nv_device(init->bios)->card_type >= NV_50 &&
1504 port == 0x03c3 && data == 0x01) {
1505 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1506 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1507 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1508 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1509 mdelay(10);
1510 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1511 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1512 init_wr32(init, 0x614100, 0x00800018);
1513 init_wr32(init, 0x614900, 0x00800018);
1514 mdelay(10);
1515 init_wr32(init, 0x614100, 0x10000018);
1516 init_wr32(init, 0x614900, 0x10000018);
1517 return;
1518 }
1519
1520 value = init_rdport(init, port) & mask;
1521 init_wrport(init, port, data | value);
1522}
1523
1524/**
1525 * INIT_SUB - opcode 0x6b
1526 *
1527 */
1528static void
1529init_sub(struct nvbios_init *init)
1530{
1531 struct nouveau_bios *bios = init->bios;
1532 u8 index = nv_ro08(bios, init->offset + 1);
1533 u16 addr, save;
1534
1535 trace("SUB\t0x%02x\n", index);
1536
1537 addr = init_script(bios, index);
1538 if (addr && init_exec(init)) {
1539 save = init->offset;
1540 init->offset = addr;
1541 if (nvbios_exec(init)) {
1542 error("error parsing sub-table\n");
1543 return;
1544 }
1545 init->offset = save;
1546 }
1547
1548 init->offset += 2;
1549}
1550
1551/**
1552 * INIT_RAM_CONDITION - opcode 0x6d
1553 *
1554 */
1555static void
1556init_ram_condition(struct nvbios_init *init)
1557{
1558 struct nouveau_bios *bios = init->bios;
1559 u8 mask = nv_ro08(bios, init->offset + 1);
1560 u8 value = nv_ro08(bios, init->offset + 2);
1561
1562 trace("RAM_CONDITION\t"
1563 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1564 init->offset += 3;
1565
1566 if ((init_rd32(init, 0x100000) & mask) != value)
1567 init_exec_set(init, false);
1568}
1569
1570/**
1571 * INIT_NV_REG - opcode 0x6e
1572 *
1573 */
1574static void
1575init_nv_reg(struct nvbios_init *init)
1576{
1577 struct nouveau_bios *bios = init->bios;
1578 u32 reg = nv_ro32(bios, init->offset + 1);
1579 u32 mask = nv_ro32(bios, init->offset + 5);
1580 u32 data = nv_ro32(bios, init->offset + 9);
1581
1582 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1583 init->offset += 13;
1584
1585 init_mask(init, reg, ~mask, data);
1586}
1587
1588/**
1589 * INIT_MACRO - opcode 0x6f
1590 *
1591 */
1592static void
1593init_macro(struct nvbios_init *init)
1594{
1595 struct nouveau_bios *bios = init->bios;
1596 u8 macro = nv_ro08(bios, init->offset + 1);
1597 u16 table;
1598
1599 trace("MACRO\t0x%02x\n", macro);
1600
1601 table = init_macro_table(init);
1602 if (table) {
1603 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1604 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1605 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1606 init_wr32(init, addr, data);
1607 }
1608
1609 init->offset += 2;
1610}
1611
1612/**
1613 * INIT_RESUME - opcode 0x72
1614 *
1615 */
1616static void
1617init_resume(struct nvbios_init *init)
1618{
1619 trace("RESUME\n");
1620 init->offset += 1;
1621 init_exec_set(init, true);
1622}
1623
1624/**
1625 * INIT_TIME - opcode 0x74
1626 *
1627 */
1628static void
1629init_time(struct nvbios_init *init)
1630{
1631 struct nouveau_bios *bios = init->bios;
1632 u16 usec = nv_ro16(bios, init->offset + 1);
1633
1634 trace("TIME\t0x%04x\n", usec);
1635 init->offset += 3;
1636
1637 if (init_exec(init)) {
1638 if (usec < 1000)
1639 udelay(usec);
1640 else
1641 mdelay((usec + 900) / 1000);
1642 }
1643}
1644
1645/**
1646 * INIT_CONDITION - opcode 0x75
1647 *
1648 */
1649static void
1650init_condition(struct nvbios_init *init)
1651{
1652 struct nouveau_bios *bios = init->bios;
1653 u8 cond = nv_ro08(bios, init->offset + 1);
1654
1655 trace("CONDITION\t0x%02x\n", cond);
1656 init->offset += 2;
1657
1658 if (!init_condition_met(init, cond))
1659 init_exec_set(init, false);
1660}
1661
1662/**
1663 * INIT_IO_CONDITION - opcode 0x76
1664 *
1665 */
1666static void
1667init_io_condition(struct nvbios_init *init)
1668{
1669 struct nouveau_bios *bios = init->bios;
1670 u8 cond = nv_ro08(bios, init->offset + 1);
1671
1672 trace("IO_CONDITION\t0x%02x\n", cond);
1673 init->offset += 2;
1674
1675 if (!init_io_condition_met(init, cond))
1676 init_exec_set(init, false);
1677}
1678
1679/**
1680 * INIT_INDEX_IO - opcode 0x78
1681 *
1682 */
1683static void
1684init_index_io(struct nvbios_init *init)
1685{
1686 struct nouveau_bios *bios = init->bios;
1687 u16 port = nv_ro16(bios, init->offset + 1);
1688 u8 index = nv_ro16(bios, init->offset + 3);
1689 u8 mask = nv_ro08(bios, init->offset + 4);
1690 u8 data = nv_ro08(bios, init->offset + 5);
1691 u8 value;
1692
1693 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1694 port, index, mask, data);
1695 init->offset += 6;
1696
1697 value = init_rdvgai(init, port, index) & mask;
1698 init_wrvgai(init, port, index, data | value);
1699}
1700
1701/**
1702 * INIT_PLL - opcode 0x79
1703 *
1704 */
1705static void
1706init_pll(struct nvbios_init *init)
1707{
1708 struct nouveau_bios *bios = init->bios;
1709 u32 reg = nv_ro32(bios, init->offset + 1);
1710 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1711
1712 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1713 init->offset += 7;
1714
1715 init_prog_pll(init, reg, freq);
1716}
1717
1718/**
1719 * INIT_ZM_REG - opcode 0x7a
1720 *
1721 */
1722static void
1723init_zm_reg(struct nvbios_init *init)
1724{
1725 struct nouveau_bios *bios = init->bios;
1726 u32 addr = nv_ro32(bios, init->offset + 1);
1727 u32 data = nv_ro32(bios, init->offset + 5);
1728
1729 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1730 init->offset += 9;
1731
1732 if (addr == 0x000200)
1733 data |= 0x00000001;
1734
1735 init_wr32(init, addr, data);
1736}
1737
1738/**
1739 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1740 *
1741 */
1742static void
1743init_ram_restrict_pll(struct nvbios_init *init)
1744{
1745 struct nouveau_bios *bios = init->bios;
1746 u8 type = nv_ro08(bios, init->offset + 1);
1747 u8 count = init_ram_restrict_group_count(init);
1748 u8 strap = init_ram_restrict(init);
1749 u8 cconf;
1750
1751 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1752 init->offset += 2;
1753
1754 for (cconf = 0; cconf < count; cconf++) {
1755 u32 freq = nv_ro32(bios, init->offset);
1756
1757 if (cconf == strap) {
1758 trace("%dkHz *\n", freq);
1759 init_prog_pll(init, type, freq);
1760 } else {
1761 trace("%dkHz\n", freq);
1762 }
1763
1764 init->offset += 4;
1765 }
1766}
1767
1768/**
1769 * INIT_GPIO - opcode 0x8e
1770 *
1771 */
1772static void
1773init_gpio(struct nvbios_init *init)
1774{
1775 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1776
1777 trace("GPIO\n");
1778 init->offset += 1;
1779
1780 if (init_exec(init) && gpio && gpio->reset)
1781 gpio->reset(gpio);
1782}
1783
1784/**
1785 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1786 *
1787 */
1788static void
1789init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1790{
1791 struct nouveau_bios *bios = init->bios;
1792 u32 addr = nv_ro32(bios, init->offset + 1);
1793 u8 incr = nv_ro08(bios, init->offset + 5);
1794 u8 num = nv_ro08(bios, init->offset + 6);
1795 u8 count = init_ram_restrict_group_count(init);
1796 u8 index = init_ram_restrict(init);
1797 u8 i, j;
1798
1799 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1800 "R[%08x] 0x%02x 0x%02x\n", addr, incr, num);
1801 init->offset += 7;
1802
1803 for (i = 0; i < num; i++) {
1804 trace("\tR[0x%06x] = {\n", addr);
1805 for (j = 0; j < count; j++) {
1806 u32 data = nv_ro32(bios, init->offset);
1807
1808 if (j == index) {
1809 trace("\t\t0x%08x *\n", data);
1810 init_wr32(init, addr, data);
1811 } else {
1812 trace("\t\t0x%08x\n", data);
1813 }
1814
1815 init->offset += 4;
1816 }
1817 trace("\t}\n");
1818 addr += incr;
1819 }
1820}
1821
1822/**
1823 * INIT_COPY_ZM_REG - opcode 0x90
1824 *
1825 */
1826static void
1827init_copy_zm_reg(struct nvbios_init *init)
1828{
1829 struct nouveau_bios *bios = init->bios;
1830 u32 sreg = nv_ro32(bios, init->offset + 1);
1831 u32 dreg = nv_ro32(bios, init->offset + 5);
1832
1833 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", sreg, dreg);
1834 init->offset += 9;
1835
1836 init_wr32(init, dreg, init_rd32(init, sreg));
1837}
1838
1839/**
1840 * INIT_ZM_REG_GROUP - opcode 0x91
1841 *
1842 */
1843static void
1844init_zm_reg_group(struct nvbios_init *init)
1845{
1846 struct nouveau_bios *bios = init->bios;
1847 u32 addr = nv_ro32(bios, init->offset + 1);
1848 u8 count = nv_ro08(bios, init->offset + 5);
1849
1850 trace("ZM_REG_GROUP\tR[0x%06x] =\n");
1851 init->offset += 6;
1852
1853 while (count--) {
1854 u32 data = nv_ro32(bios, init->offset);
1855 trace("\t0x%08x\n", data);
1856 init_wr32(init, addr, data);
1857 init->offset += 4;
1858 }
1859}
1860
1861/**
1862 * INIT_XLAT - opcode 0x96
1863 *
1864 */
1865static void
1866init_xlat(struct nvbios_init *init)
1867{
1868 struct nouveau_bios *bios = init->bios;
1869 u32 saddr = nv_ro32(bios, init->offset + 1);
1870 u8 sshift = nv_ro08(bios, init->offset + 5);
1871 u8 smask = nv_ro08(bios, init->offset + 6);
1872 u8 index = nv_ro08(bios, init->offset + 7);
1873 u32 daddr = nv_ro32(bios, init->offset + 8);
1874 u32 dmask = nv_ro32(bios, init->offset + 12);
1875 u8 shift = nv_ro08(bios, init->offset + 16);
1876 u32 data;
1877
1878 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1879 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1880 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1881 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1882 init->offset += 17;
1883
1884 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1885 data = init_xlat_(init, index, data) << shift;
1886 init_mask(init, daddr, ~dmask, data);
1887}
1888
1889/**
1890 * INIT_ZM_MASK_ADD - opcode 0x97
1891 *
1892 */
1893static void
1894init_zm_mask_add(struct nvbios_init *init)
1895{
1896 struct nouveau_bios *bios = init->bios;
1897 u32 addr = nv_ro32(bios, init->offset + 1);
1898 u32 mask = nv_ro32(bios, init->offset + 5);
1899 u32 add = nv_ro32(bios, init->offset + 9);
1900 u32 data;
1901
1902 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1903 init->offset += 13;
1904
1905 data = init_rd32(init, addr) & mask;
1906 data |= ((data + add) & ~mask);
1907 init_wr32(init, addr, data);
1908}
1909
1910/**
1911 * INIT_AUXCH - opcode 0x98
1912 *
1913 */
1914static void
1915init_auxch(struct nvbios_init *init)
1916{
1917 struct nouveau_bios *bios = init->bios;
1918 u32 addr = nv_ro32(bios, init->offset + 1);
1919 u8 count = nv_ro08(bios, init->offset + 5);
1920
1921 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1922 init->offset += 6;
1923
1924 while (count--) {
1925 u8 mask = nv_ro08(bios, init->offset + 0);
1926 u8 data = nv_ro08(bios, init->offset + 1);
1927 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1928 mask = init_rdauxr(init, addr) & mask;
1929 init_wrauxr(init, addr, mask | data);
1930 init->offset += 2;
1931 }
1932}
1933
1934/**
1935 * INIT_AUXCH - opcode 0x99
1936 *
1937 */
1938static void
1939init_zm_auxch(struct nvbios_init *init)
1940{
1941 struct nouveau_bios *bios = init->bios;
1942 u32 addr = nv_ro32(bios, init->offset + 1);
1943 u8 count = nv_ro08(bios, init->offset + 5);
1944
1945 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1946 init->offset += 6;
1947
1948 while (count--) {
1949 u8 data = nv_ro08(bios, init->offset + 0);
1950 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1951 init_wrauxr(init, addr, data);
1952 init->offset += 1;
1953 }
1954}
1955
1956/**
1957 * INIT_I2C_LONG_IF - opcode 0x9a
1958 *
1959 */
1960static void
1961init_i2c_long_if(struct nvbios_init *init)
1962{
1963 struct nouveau_bios *bios = init->bios;
1964 u8 index = nv_ro08(bios, init->offset + 1);
1965 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1966 u8 reglo = nv_ro08(bios, init->offset + 3);
1967 u8 reghi = nv_ro08(bios, init->offset + 4);
1968 u8 mask = nv_ro08(bios, init->offset + 5);
1969 u8 data = nv_ro08(bios, init->offset + 6);
1970 struct nouveau_i2c_port *port;
1971
1972 trace("I2C_LONG_IF\t"
1973 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
1974 index, addr, reglo, reghi, mask, data);
1975 init->offset += 7;
1976
1977 port = init_i2c(init, index);
1978 if (port) {
1979 u8 i[2] = { reghi, reglo };
1980 u8 o[1] = {};
1981 struct i2c_msg msg[] = {
1982 { .addr = addr, .flags = 0, .len = 2, .buf = i },
1983 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
1984 };
1985 int ret;
1986
1987 ret = i2c_transfer(&port->adapter, msg, 2);
1988 if (ret == 2 && ((o[0] & mask) == data))
1989 return;
1990 }
1991
1992 init_exec_set(init, false);
1993}
1994
1995static struct nvbios_init_opcode {
1996 void (*exec)(struct nvbios_init *);
1997} init_opcode[] = {
1998 [0x32] = { init_io_restrict_prog },
1999 [0x33] = { init_repeat },
2000 [0x34] = { init_io_restrict_pll },
2001 [0x36] = { init_end_repeat },
2002 [0x37] = { init_copy },
2003 [0x38] = { init_not },
2004 [0x39] = { init_io_flag_condition },
2005 [0x3a] = { init_dp_condition },
2006 [0x3b] = { init_io_mask_or },
2007 [0x3c] = { init_io_or },
2008 [0x49] = { init_idx_addr_latched },
2009 [0x4a] = { init_io_restrict_pll2 },
2010 [0x4b] = { init_pll2 },
2011 [0x4c] = { init_i2c_byte },
2012 [0x4d] = { init_zm_i2c_byte },
2013 [0x4e] = { init_zm_i2c },
2014 [0x4f] = { init_tmds },
2015 [0x50] = { init_zm_tmds_group },
2016 [0x51] = { init_cr_idx_adr_latch },
2017 [0x52] = { init_cr },
2018 [0x53] = { init_zm_cr },
2019 [0x54] = { init_zm_cr_group },
2020 [0x56] = { init_condition_time },
2021 [0x57] = { init_ltime },
2022 [0x58] = { init_zm_reg_sequence },
2023 [0x5b] = { init_sub_direct },
2024 [0x5c] = { init_jump },
2025 [0x5e] = { init_i2c_if },
2026 [0x5f] = { init_copy_nv_reg },
2027 [0x62] = { init_zm_index_io },
2028 [0x63] = { init_compute_mem },
2029 [0x65] = { init_reset },
2030 [0x66] = { init_configure_mem },
2031 [0x67] = { init_configure_clk },
2032 [0x68] = { init_configure_preinit },
2033 [0x69] = { init_io },
2034 [0x6b] = { init_sub },
2035 [0x6d] = { init_ram_condition },
2036 [0x6e] = { init_nv_reg },
2037 [0x6f] = { init_macro },
2038 [0x71] = { init_done },
2039 [0x72] = { init_resume },
2040 [0x74] = { init_time },
2041 [0x75] = { init_condition },
2042 [0x76] = { init_io_condition },
2043 [0x78] = { init_index_io },
2044 [0x79] = { init_pll },
2045 [0x7a] = { init_zm_reg },
2046 [0x87] = { init_ram_restrict_pll },
2047 [0x8c] = { init_reserved },
2048 [0x8d] = { init_reserved },
2049 [0x8e] = { init_gpio },
2050 [0x8f] = { init_ram_restrict_zm_reg_group },
2051 [0x90] = { init_copy_zm_reg },
2052 [0x91] = { init_zm_reg_group },
2053 [0x92] = { init_reserved },
2054 [0x96] = { init_xlat },
2055 [0x97] = { init_zm_mask_add },
2056 [0x98] = { init_auxch },
2057 [0x99] = { init_zm_auxch },
2058 [0x9a] = { init_i2c_long_if },
2059};
2060
2061#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2062
2063int
2064nvbios_exec(struct nvbios_init *init)
2065{
2066 init->nested++;
2067 while (init->offset) {
2068 u8 opcode = nv_ro08(init->bios, init->offset);
2069 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2070 error("unknown opcode 0x%02x\n", opcode);
2071 return -EINVAL;
2072 }
2073
2074 init_opcode[opcode].exec(init);
2075 }
2076 init->nested--;
2077 return 0;
2078}
2079
2080int
2081nvbios_init(struct nouveau_subdev *subdev, bool execute)
2082{
2083 struct nouveau_bios *bios = nouveau_bios(subdev);
2084 int ret = 0;
2085 int i = -1;
2086 u16 data;
2087
2088 if (execute)
2089 nv_info(bios, "running init tables\n");
2090 while (!ret && (data = (init_script(bios, ++i)))) {
2091 struct nvbios_init init = {
2092 .subdev = subdev,
2093 .bios = bios,
2094 .offset = data,
2095 .outp = NULL,
2096 .crtc = -1,
2097 .execute = execute ? 1 : 0,
2098 };
2099
2100 ret = nvbios_exec(&init);
2101 }
2102
2103 /* the vbios parser will run this right after the normal init
2104 * tables, whereas the binary driver appears to run it later.
2105 */
2106 if (!ret && (data = init_unknown_script(bios))) {
2107 struct nvbios_init init = {
2108 .subdev = subdev,
2109 .bios = bios,
2110 .offset = data,
2111 .outp = NULL,
2112 .crtc = -1,
2113 .execute = execute ? 1 : 0,
2114 };
2115
2116 ret = nvbios_exec(&init);
2117 }
2118
2119 return 0;
2120}
Linux 6.x block layer and io_uring tree(s)