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drm/nouveau: fix command submission to use vmalloc for big allocations
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / core / subdev / bios / init.c
CommitLineData
cb75d97e
BS		 1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
cb75d97e
BS		 5#include <subdev/bios/bmp.h>
6#include <subdev/bios/bit.h>
1ed73166 7#include <subdev/bios/conn.h>
cb75d97e
BS		 8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
1ed73166 10#include <subdev/bios/gpio.h>
cb75d97e
BS		 11#include <subdev/bios/init.h>
12#include <subdev/devinit.h>
cb75d97e
BS		 13#include <subdev/i2c.h>
14#include <subdev/vga.h>
15#include <subdev/gpio.h>
16
17#define bioslog(lvl, fmt, args...) do { \
18 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
19 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
20} while(0)
21#define cont(fmt, args...) do { \
22 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
23 printk(fmt, ##args); \
24} while(0)
25#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
26#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
27#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
28
29/******************************************************************************
30 * init parser control flow helpers
31 *****************************************************************************/
32
33static inline bool
34init_exec(struct nvbios_init *init)
35{
36 return (init->execute == 1) || ((init->execute & 5) == 5);
37}
38
39static inline void
40init_exec_set(struct nvbios_init *init, bool exec)
41{
42 if (exec) init->execute &= 0xfd;
43 else init->execute |= 0x02;
44}
45
46static inline void
47init_exec_inv(struct nvbios_init *init)
48{
49 init->execute ^= 0x02;
50}
51
52static inline void
53init_exec_force(struct nvbios_init *init, bool exec)
54{
55 if (exec) init->execute |= 0x04;
56 else init->execute &= 0xfb;
57}
58
59/******************************************************************************
60 * init parser wrappers for normal register/i2c/whatever accessors
61 *****************************************************************************/
62
63static inline int
64init_or(struct nvbios_init *init)
65{
28ec70f7
BS		 66 if (init_exec(init)) {
67 if (init->outp)
68 return ffs(init->outp->or) - 1;
69 error("script needs OR!!\n");
70 }
cb75d97e
BS		 71 return 0;
72}
73
74static inline int
75init_link(struct nvbios_init *init)
76{
28ec70f7
BS		 77 if (init_exec(init)) {
78 if (init->outp)
79 return !(init->outp->sorconf.link & 1);
80 error("script needs OR link\n");
81 }
cb75d97e
BS		 82 return 0;
83}
84
85static inline int
86init_crtc(struct nvbios_init *init)
87{
28ec70f7
BS		 88 if (init_exec(init)) {
89 if (init->crtc >= 0)
90 return init->crtc;
91 error("script needs crtc\n");
92 }
cb75d97e
BS		 93 return 0;
94}
95
96static u8
97init_conn(struct nvbios_init *init)
98{
99 struct nouveau_bios *bios = init->bios;
28ec70f7
BS		 100 u8 ver, len;
101 u16 conn;
cb75d97e 102
28ec70f7
BS		 103 if (init_exec(init)) {
104 if (init->outp) {
105 conn = init->outp->connector;
106 conn = dcb_conn(bios, conn, &ver, &len);
107 if (conn)
108 return nv_ro08(bios, conn);
109 }
110
111 error("script needs connector type\n");
cb75d97e
BS		 112 }
113
28ec70f7 114 return 0xff;
cb75d97e
BS		 115}
116
117static inline u32
118init_nvreg(struct nvbios_init *init, u32 reg)
119{
120 /* C51 (at least) sometimes has the lower bits set which the VBIOS
121 * interprets to mean that access needs to go through certain IO
122 * ports instead. The NVIDIA binary driver has been seen to access
123 * these through the NV register address, so lets assume we can
124 * do the same
125 */
126 reg &= ~0x00000003;
127
128 /* GF8+ display scripts need register addresses mangled a bit to
129 * select a specific CRTC/OR
130 */
131 if (nv_device(init->bios)->card_type >= NV_50) {
132 if (reg & 0x80000000) {
133 reg += init_crtc(init) * 0x800;
134 reg &= ~0x80000000;
135 }
136
137 if (reg & 0x40000000) {
138 reg += init_or(init) * 0x800;
139 reg &= ~0x40000000;
140 if (reg & 0x20000000) {
141 reg += init_link(init) * 0x80;
142 reg &= ~0x20000000;
143 }
144 }
145 }
146
147 if (reg & ~0x00fffffc)
148 warn("unknown bits in register 0x%08x\n", reg);
149 return reg;
150}
151
152static u32
153init_rd32(struct nvbios_init *init, u32 reg)
154{
155 reg = init_nvreg(init, reg);
156 if (init_exec(init))
157 return nv_rd32(init->subdev, reg);
158 return 0x00000000;
159}
160
161static void
162init_wr32(struct nvbios_init *init, u32 reg, u32 val)
163{
164 reg = init_nvreg(init, reg);
165 if (init_exec(init))
166 nv_wr32(init->subdev, reg, val);
167}
168
169static u32
170init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
171{
172 reg = init_nvreg(init, reg);
173 if (init_exec(init)) {
174 u32 tmp = nv_rd32(init->subdev, reg);
175 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
176 return tmp;
177 }
178 return 0x00000000;
179}
180
181static u8
182init_rdport(struct nvbios_init *init, u16 port)
183{
184 if (init_exec(init))
185 return nv_rdport(init->subdev, init->crtc, port);
186 return 0x00;
187}
188
189static void
190init_wrport(struct nvbios_init *init, u16 port, u8 value)
191{
192 if (init_exec(init))
193 nv_wrport(init->subdev, init->crtc, port, value);
194}
195
196static u8
197init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
198{
199 struct nouveau_subdev *subdev = init->subdev;
200 if (init_exec(init)) {
201 int head = init->crtc < 0 ? 0 : init->crtc;
202 return nv_rdvgai(subdev, head, port, index);
203 }
204 return 0x00;
205}
206
207static void
208init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
209{
210 /* force head 0 for updates to cr44, it only exists on first head */
211 if (nv_device(init->subdev)->card_type < NV_50) {
212 if (port == 0x03d4 && index == 0x44)
213 init->crtc = 0;
214 }
215
216 if (init_exec(init)) {
217 int head = init->crtc < 0 ? 0 : init->crtc;
218 nv_wrvgai(init->subdev, head, port, index, value);
219 }
220
221 /* select head 1 if cr44 write selected it */
222 if (nv_device(init->subdev)->card_type < NV_50) {
223 if (port == 0x03d4 && index == 0x44 && value == 3)
224 init->crtc = 1;
225 }
226}
227
228static struct nouveau_i2c_port *
229init_i2c(struct nvbios_init *init, int index)
230{
231 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
232
233 if (index == 0xff) {
234 index = NV_I2C_DEFAULT(0);
235 if (init->outp && init->outp->i2c_upper_default)
236 index = NV_I2C_DEFAULT(1);
237 } else
238 if (index < 0) {
239 if (!init->outp) {
28ec70f7
BS		 240 if (init_exec(init))
241 error("script needs output for i2c\n");
cb75d97e
BS		 242 return NULL;
243 }
244
476e84e1
BS		 245 if (index == -2 && init->outp->location) {
246 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
247 return i2c->find_type(i2c, index);
248 }
249
cb75d97e
BS		 250 index = init->outp->i2c_index;
251 }
252
253 return i2c->find(i2c, index);
254}
255
256static int
257init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
258{
259 struct nouveau_i2c_port *port = init_i2c(init, index);
260 if (port && init_exec(init))
261 return nv_rdi2cr(port, addr, reg);
262 return -ENODEV;
263}
264
265static int
266init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
267{
268 struct nouveau_i2c_port *port = init_i2c(init, index);
269 if (port && init_exec(init))
270 return nv_wri2cr(port, addr, reg, val);
271 return -ENODEV;
272}
273
274static int
275init_rdauxr(struct nvbios_init *init, u32 addr)
276{
476e84e1 277 struct nouveau_i2c_port *port = init_i2c(init, -2);
cb75d97e
BS		 278 u8 data;
279
280 if (port && init_exec(init)) {
281 int ret = nv_rdaux(port, addr, &data, 1);
282 if (ret)
283 return ret;
284 return data;
285 }
286
287 return -ENODEV;
288}
289
290static int
291init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
292{
476e84e1 293 struct nouveau_i2c_port *port = init_i2c(init, -2);
cb75d97e
BS		 294 if (port && init_exec(init))
295 return nv_wraux(port, addr, &data, 1);
296 return -ENODEV;
297}
298
299static void
300init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
301{
88524bc0
BS		 302 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
303 if (devinit->pll_set && init_exec(init)) {
304 int ret = devinit->pll_set(devinit, id, freq);
cb75d97e
BS		 305 if (ret)
306 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
307 }
308}
309
310/******************************************************************************
311 * parsing of bios structures that are required to execute init tables
312 *****************************************************************************/
313
314static u16
315init_table(struct nouveau_bios *bios, u16 *len)
316{
317 struct bit_entry bit_I;
318
319 if (!bit_entry(bios, 'I', &bit_I)) {
320 *len = bit_I.length;
321 return bit_I.offset;
322 }
323
324 if (bmp_version(bios) >= 0x0510) {
325 *len = 14;
326 return bios->bmp_offset + 75;
327 }
328
329 return 0x0000;
330}
331
332static u16
333init_table_(struct nvbios_init *init, u16 offset, const char *name)
334{
335 struct nouveau_bios *bios = init->bios;
336 u16 len, data = init_table(bios, &len);
337 if (data) {
338 if (len >= offset + 2) {
339 data = nv_ro16(bios, data + offset);
340 if (data)
341 return data;
342
343 warn("%s pointer invalid\n", name);
344 return 0x0000;
345 }
346
347 warn("init data too short for %s pointer", name);
348 return 0x0000;
349 }
350
351 warn("init data not found\n");
352 return 0x0000;
353}
354
355#define init_script_table(b) init_table_((b), 0x00, "script table")
356#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
357#define init_macro_table(b) init_table_((b), 0x04, "macro table")
358#define init_condition_table(b) init_table_((b), 0x06, "condition table")
359#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
360#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
361#define init_function_table(b) init_table_((b), 0x0c, "function table")
362#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
363
364static u16
365init_script(struct nouveau_bios *bios, int index)
366{
367 struct nvbios_init init = { .bios = bios };
368 u16 data;
369
370 if (bmp_version(bios) && bmp_version(bios) < 0x0510) {
371 if (index > 1)
372 return 0x0000;
373
374 data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18);
375 return nv_ro16(bios, data + (index * 2));
376 }
377
378 data = init_script_table(&init);
379 if (data)
380 return nv_ro16(bios, data + (index * 2));
381
382 return 0x0000;
383}
384
385static u16
386init_unknown_script(struct nouveau_bios *bios)
387{
388 u16 len, data = init_table(bios, &len);
389 if (data && len >= 16)
390 return nv_ro16(bios, data + 14);
391 return 0x0000;
392}
393
394static u16
395init_ram_restrict_table(struct nvbios_init *init)
396{
397 struct nouveau_bios *bios = init->bios;
398 struct bit_entry bit_M;
399 u16 data = 0x0000;
400
401 if (!bit_entry(bios, 'M', &bit_M)) {
402 if (bit_M.version == 1 && bit_M.length >= 5)
403 data = nv_ro16(bios, bit_M.offset + 3);
404 if (bit_M.version == 2 && bit_M.length >= 3)
405 data = nv_ro16(bios, bit_M.offset + 1);
406 }
407
408 if (data == 0x0000)
409 warn("ram restrict table not found\n");
410 return data;
411}
412
413static u8
414init_ram_restrict_group_count(struct nvbios_init *init)
415{
416 struct nouveau_bios *bios = init->bios;
417 struct bit_entry bit_M;
418
419 if (!bit_entry(bios, 'M', &bit_M)) {
420 if (bit_M.version == 1 && bit_M.length >= 5)
421 return nv_ro08(bios, bit_M.offset + 2);
422 if (bit_M.version == 2 && bit_M.length >= 3)
423 return nv_ro08(bios, bit_M.offset + 0);
424 }
425
426 return 0x00;
427}
428
5ddf4d4a
BS		 429static u8
430init_ram_restrict_strap(struct nvbios_init *init)
431{
432 /* This appears to be the behaviour of the VBIOS parser, and *is*
433 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
434 * avoid fucking up the memory controller (somehow) by reading it
435 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
436 *
437 * Preserving the non-caching behaviour on earlier chipsets just
438 * in case *not* re-reading the strap causes similar breakage.
439 */
440 if (!init->ramcfg || init->bios->version.major < 0x70)
441 init->ramcfg = init_rd32(init, 0x101000);
442 return (init->ramcfg & 0x00000003c) >> 2;
443}
444
cb75d97e
BS		 445static u8
446init_ram_restrict(struct nvbios_init *init)
447{
5ddf4d4a 448 u8 strap = init_ram_restrict_strap(init);
cb75d97e
BS		 449 u16 table = init_ram_restrict_table(init);
450 if (table)
451 return nv_ro08(init->bios, table + strap);
452 return 0x00;
453}
454
455static u8
456init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
457{
458 struct nouveau_bios *bios = init->bios;
459 u16 table = init_xlat_table(init);
460 if (table) {
461 u16 data = nv_ro16(bios, table + (index * 2));
462 if (data)
463 return nv_ro08(bios, data + offset);
464 warn("xlat table pointer %d invalid\n", index);
465 }
466 return 0x00;
467}
468
469/******************************************************************************
470 * utility functions used by various init opcode handlers
471 *****************************************************************************/
472
473static bool
474init_condition_met(struct nvbios_init *init, u8 cond)
475{
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_condition_table(init);
478 if (table) {
479 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
480 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
481 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
482 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
483 cond, reg, msk, val);
484 return (init_rd32(init, reg) & msk) == val;
485 }
486 return false;
487}
488
489static bool
490init_io_condition_met(struct nvbios_init *init, u8 cond)
491{
492 struct nouveau_bios *bios = init->bios;
493 u16 table = init_io_condition_table(init);
494 if (table) {
495 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
496 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
497 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
498 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
499 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
500 cond, port, index, mask, value);
501 return (init_rdvgai(init, port, index) & mask) == value;
502 }
503 return false;
504}
505
506static bool
507init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
508{
509 struct nouveau_bios *bios = init->bios;
510 u16 table = init_io_flag_condition_table(init);
511 if (table) {
512 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
513 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
514 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
515 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
516 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
517 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
518 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
519 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
520 return (nv_ro08(bios, data + ioval) & dmask) == value;
521 }
522 return false;
523}
524
525static inline u32
526init_shift(u32 data, u8 shift)
527{
528 if (shift < 0x80)
529 return data >> shift;
530 return data << (0x100 - shift);
531}
532
533static u32
534init_tmds_reg(struct nvbios_init *init, u8 tmds)
535{
536 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
537 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
538 * CR58 for CR57 = 0 to index a table of offsets to the basic
539 * 0x6808b0 address.
540 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
541 * CR58 for CR57 = 0 to index a table of offsets to the basic
542 * 0x6808b0 address, and then flip the offset by 8.
543 */
544
545 const int pramdac_offset[13] = {
546 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
547 const u32 pramdac_table[4] = {
548 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
549
550 if (tmds >= 0x80) {
551 if (init->outp) {
552 u32 dacoffset = pramdac_offset[init->outp->or];
553 if (tmds == 0x81)
554 dacoffset ^= 8;
555 return 0x6808b0 + dacoffset;
556 }
557
28ec70f7
BS		 558 if (init_exec(init))
559 error("tmds opcodes need dcb\n");
cb75d97e
BS		 560 } else {
561 if (tmds < ARRAY_SIZE(pramdac_table))
562 return pramdac_table[tmds];
563
564 error("tmds selector 0x%02x unknown\n", tmds);
565 }
566
567 return 0;
568}
569
570/******************************************************************************
571 * init opcode handlers
572 *****************************************************************************/
573
574/**
575 * init_reserved - stub for various unknown/unused single-byte opcodes
576 *
577 */
578static void
579init_reserved(struct nvbios_init *init)
580{
581 u8 opcode = nv_ro08(init->bios, init->offset);
582 trace("RESERVED\t0x%02x\n", opcode);
583 init->offset += 1;
584}
585
586/**
587 * INIT_DONE - opcode 0x71
588 *
589 */
590static void
591init_done(struct nvbios_init *init)
592{
593 trace("DONE\n");
594 init->offset = 0x0000;
595}
596
597/**
598 * INIT_IO_RESTRICT_PROG - opcode 0x32
599 *
600 */
601static void
602init_io_restrict_prog(struct nvbios_init *init)
603{
604 struct nouveau_bios *bios = init->bios;
605 u16 port = nv_ro16(bios, init->offset + 1);
606 u8 index = nv_ro08(bios, init->offset + 3);
607 u8 mask = nv_ro08(bios, init->offset + 4);
608 u8 shift = nv_ro08(bios, init->offset + 5);
609 u8 count = nv_ro08(bios, init->offset + 6);
610 u32 reg = nv_ro32(bios, init->offset + 7);
611 u8 conf, i;
612
613 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
614 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
615 reg, port, index, mask, shift);
616 init->offset += 11;
617
618 conf = (init_rdvgai(init, port, index) & mask) >> shift;
619 for (i = 0; i < count; i++) {
620 u32 data = nv_ro32(bios, init->offset);
621
622 if (i == conf) {
623 trace("\t0x%08x *\n", data);
624 init_wr32(init, reg, data);
625 } else {
626 trace("\t0x%08x\n", data);
627 }
628
629 init->offset += 4;
630 }
631 trace("}]\n");
632}
633
634/**
635 * INIT_REPEAT - opcode 0x33
636 *
637 */
638static void
639init_repeat(struct nvbios_init *init)
640{
641 struct nouveau_bios *bios = init->bios;
642 u8 count = nv_ro08(bios, init->offset + 1);
643 u16 repeat = init->repeat;
644
645 trace("REPEAT\t0x%02x\n", count);
646 init->offset += 2;
647
648 init->repeat = init->offset;
649 init->repend = init->offset;
650 while (count--) {
651 init->offset = init->repeat;
652 nvbios_exec(init);
653 if (count)
654 trace("REPEAT\t0x%02x\n", count);
655 }
656 init->offset = init->repend;
657 init->repeat = repeat;
658}
659
660/**
661 * INIT_IO_RESTRICT_PLL - opcode 0x34
662 *
663 */
664static void
665init_io_restrict_pll(struct nvbios_init *init)
666{
667 struct nouveau_bios *bios = init->bios;
668 u16 port = nv_ro16(bios, init->offset + 1);
669 u8 index = nv_ro08(bios, init->offset + 3);
670 u8 mask = nv_ro08(bios, init->offset + 4);
671 u8 shift = nv_ro08(bios, init->offset + 5);
672 s8 iofc = nv_ro08(bios, init->offset + 6);
673 u8 count = nv_ro08(bios, init->offset + 7);
674 u32 reg = nv_ro32(bios, init->offset + 8);
675 u8 conf, i;
676
677 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
678 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
679 reg, port, index, mask, shift, iofc);
680 init->offset += 12;
681
682 conf = (init_rdvgai(init, port, index) & mask) >> shift;
683 for (i = 0; i < count; i++) {
684 u32 freq = nv_ro16(bios, init->offset) * 10;
685
686 if (i == conf) {
687 trace("\t%dkHz *\n", freq);
688 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
689 freq *= 2;
690 init_prog_pll(init, reg, freq);
691 } else {
692 trace("\t%dkHz\n", freq);
693 }
694
695 init->offset += 2;
696 }
697 trace("}]\n");
698}
699
700/**
701 * INIT_END_REPEAT - opcode 0x36
702 *
703 */
704static void
705init_end_repeat(struct nvbios_init *init)
706{
707 trace("END_REPEAT\n");
708 init->offset += 1;
709
710 if (init->repeat) {
711 init->repend = init->offset;
712 init->offset = 0;
713 }
714}
715
716/**
717 * INIT_COPY - opcode 0x37
718 *
719 */
720static void
721init_copy(struct nvbios_init *init)
722{
723 struct nouveau_bios *bios = init->bios;
724 u32 reg = nv_ro32(bios, init->offset + 1);
725 u8 shift = nv_ro08(bios, init->offset + 5);
726 u8 smask = nv_ro08(bios, init->offset + 6);
727 u16 port = nv_ro16(bios, init->offset + 7);
728 u8 index = nv_ro08(bios, init->offset + 9);
729 u8 mask = nv_ro08(bios, init->offset + 10);
730 u8 data;
731
732 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
733 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
734 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
735 (shift & 0x80) ? (0x100 - shift) : shift, smask);
736 init->offset += 11;
737
738 data = init_rdvgai(init, port, index) & mask;
739 data |= init_shift(init_rd32(init, reg), shift) & smask;
740 init_wrvgai(init, port, index, data);
741}
742
743/**
744 * INIT_NOT - opcode 0x38
745 *
746 */
747static void
748init_not(struct nvbios_init *init)
749{
750 trace("NOT\n");
751 init->offset += 1;
752 init_exec_inv(init);
753}
754
755/**
756 * INIT_IO_FLAG_CONDITION - opcode 0x39
757 *
758 */
759static void
760init_io_flag_condition(struct nvbios_init *init)
761{
762 struct nouveau_bios *bios = init->bios;
763 u8 cond = nv_ro08(bios, init->offset + 1);
764
765 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
766 init->offset += 2;
767
768 if (!init_io_flag_condition_met(init, cond))
769 init_exec_set(init, false);
770}
771
772/**
773 * INIT_DP_CONDITION - opcode 0x3a
774 *
775 */
776static void
777init_dp_condition(struct nvbios_init *init)
778{
779 struct nouveau_bios *bios = init->bios;
65c78660 780 struct nvbios_dpout info;
cb75d97e
BS		 781 u8 cond = nv_ro08(bios, init->offset + 1);
782 u8 unkn = nv_ro08(bios, init->offset + 2);
65c78660 783 u8 ver, hdr, cnt, len;
cb75d97e
BS		 784 u16 data;
785
786 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
787 init->offset += 3;
788
789 switch (cond) {
790 case 0:
791 if (init_conn(init) != DCB_CONNECTOR_eDP)
792 init_exec_set(init, false);
793 break;
794 case 1:
795 case 2:
796 if ( init->outp &&
65c78660
BS		 797 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
798 (init->outp->or << 0) |
799 (init->outp->sorconf.link << 6),
800 &ver, &hdr, &cnt, &len, &info)))
801 {
802 if (!(info.flags & cond))
cb75d97e
BS		 803 init_exec_set(init, false);
804 break;
805 }
806
28ec70f7
BS		 807 if (init_exec(init))
808 warn("script needs dp output table data\n");
cb75d97e
BS		 809 break;
810 case 5:
811 if (!(init_rdauxr(init, 0x0d) & 1))
812 init_exec_set(init, false);
813 break;
814 default:
815 warn("unknown dp condition 0x%02x\n", cond);
816 break;
817 }
818}
819
820/**
821 * INIT_IO_MASK_OR - opcode 0x3b
822 *
823 */
824static void
825init_io_mask_or(struct nvbios_init *init)
826{
827 struct nouveau_bios *bios = init->bios;
828 u8 index = nv_ro08(bios, init->offset + 1);
829 u8 or = init_or(init);
830 u8 data;
831
b9a3140c 832 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
cb75d97e
BS		 833 init->offset += 2;
834
835 data = init_rdvgai(init, 0x03d4, index);
836 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
837}
838
839/**
840 * INIT_IO_OR - opcode 0x3c
841 *
842 */
843static void
844init_io_or(struct nvbios_init *init)
845{
846 struct nouveau_bios *bios = init->bios;
847 u8 index = nv_ro08(bios, init->offset + 1);
848 u8 or = init_or(init);
849 u8 data;
850
b9a3140c 851 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
cb75d97e
BS		 852 init->offset += 2;
853
854 data = init_rdvgai(init, 0x03d4, index);
855 init_wrvgai(init, 0x03d4, index, data | (1 << or));
856}
857
858/**
859 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
860 *
861 */
862static void
863init_idx_addr_latched(struct nvbios_init *init)
864{
865 struct nouveau_bios *bios = init->bios;
866 u32 creg = nv_ro32(bios, init->offset + 1);
867 u32 dreg = nv_ro32(bios, init->offset + 5);
868 u32 mask = nv_ro32(bios, init->offset + 9);
869 u32 data = nv_ro32(bios, init->offset + 13);
870 u8 count = nv_ro08(bios, init->offset + 17);
871
872 trace("INDEX_ADDRESS_LATCHED\t"
873 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
874 creg, dreg, mask, data);
875 init->offset += 18;
876
877 while (count--) {
878 u8 iaddr = nv_ro08(bios, init->offset + 0);
879 u8 idata = nv_ro08(bios, init->offset + 1);
880
881 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
882 init->offset += 2;
883
884 init_wr32(init, dreg, idata);
f6853faa 885 init_mask(init, creg, ~mask, data | iaddr);
cb75d97e
BS		 886 }
887}
888
889/**
890 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
891 *
892 */
893static void
894init_io_restrict_pll2(struct nvbios_init *init)
895{
896 struct nouveau_bios *bios = init->bios;
897 u16 port = nv_ro16(bios, init->offset + 1);
898 u8 index = nv_ro08(bios, init->offset + 3);
899 u8 mask = nv_ro08(bios, init->offset + 4);
900 u8 shift = nv_ro08(bios, init->offset + 5);
901 u8 count = nv_ro08(bios, init->offset + 6);
902 u32 reg = nv_ro32(bios, init->offset + 7);
903 u8 conf, i;
904
905 trace("IO_RESTRICT_PLL2\t"
906 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
907 reg, port, index, mask, shift);
908 init->offset += 11;
909
910 conf = (init_rdvgai(init, port, index) & mask) >> shift;
911 for (i = 0; i < count; i++) {
912 u32 freq = nv_ro32(bios, init->offset);
913 if (i == conf) {
914 trace("\t%dkHz *\n", freq);
915 init_prog_pll(init, reg, freq);
916 } else {
917 trace("\t%dkHz\n", freq);
918 }
919 init->offset += 4;
920 }
921 trace("}]\n");
922}
923
924/**
925 * INIT_PLL2 - opcode 0x4b
926 *
927 */
928static void
929init_pll2(struct nvbios_init *init)
930{
931 struct nouveau_bios *bios = init->bios;
932 u32 reg = nv_ro32(bios, init->offset + 1);
933 u32 freq = nv_ro32(bios, init->offset + 5);
934
935 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
936 init->offset += 9;
937
938 init_prog_pll(init, reg, freq);
939}
940
941/**
942 * INIT_I2C_BYTE - opcode 0x4c
943 *
944 */
945static void
946init_i2c_byte(struct nvbios_init *init)
947{
948 struct nouveau_bios *bios = init->bios;
949 u8 index = nv_ro08(bios, init->offset + 1);
950 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
951 u8 count = nv_ro08(bios, init->offset + 3);
952
953 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
954 init->offset += 4;
955
956 while (count--) {
957 u8 reg = nv_ro08(bios, init->offset + 0);
958 u8 mask = nv_ro08(bios, init->offset + 1);
959 u8 data = nv_ro08(bios, init->offset + 2);
960 int val;
961
962 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
963 init->offset += 3;
964
965 val = init_rdi2cr(init, index, addr, reg);
966 if (val < 0)
967 continue;
968 init_wri2cr(init, index, addr, reg, (val & mask) | data);
969 }
970}
971
972/**
973 * INIT_ZM_I2C_BYTE - opcode 0x4d
974 *
975 */
976static void
977init_zm_i2c_byte(struct nvbios_init *init)
978{
979 struct nouveau_bios *bios = init->bios;
980 u8 index = nv_ro08(bios, init->offset + 1);
981 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
982 u8 count = nv_ro08(bios, init->offset + 3);
983
984 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
985 init->offset += 4;
986
987 while (count--) {
988 u8 reg = nv_ro08(bios, init->offset + 0);
989 u8 data = nv_ro08(bios, init->offset + 1);
990
991 trace("\t[0x%02x] = 0x%02x\n", reg, data);
992 init->offset += 2;
993
994 init_wri2cr(init, index, addr, reg, data);
995 }
996
997}
998
999/**
1000 * INIT_ZM_I2C - opcode 0x4e
1001 *
1002 */
1003static void
1004init_zm_i2c(struct nvbios_init *init)
1005{
1006 struct nouveau_bios *bios = init->bios;
1007 u8 index = nv_ro08(bios, init->offset + 1);
1008 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1009 u8 count = nv_ro08(bios, init->offset + 3);
1010 u8 data[256], i;
1011
1012 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
1013 init->offset += 4;
1014
1015 for (i = 0; i < count; i++) {
1016 data[i] = nv_ro08(bios, init->offset);
1017 trace("\t0x%02x\n", data[i]);
1018 init->offset++;
1019 }
1020
1021 if (init_exec(init)) {
1022 struct nouveau_i2c_port *port = init_i2c(init, index);
1023 struct i2c_msg msg = {
1024 .addr = addr, .flags = 0, .len = count, .buf = data,
1025 };
1026 int ret;
1027
1028 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1029 warn("i2c wr failed, %d\n", ret);
1030 }
1031}
1032
1033/**
1034 * INIT_TMDS - opcode 0x4f
1035 *
1036 */
1037static void
1038init_tmds(struct nvbios_init *init)
1039{
1040 struct nouveau_bios *bios = init->bios;
1041 u8 tmds = nv_ro08(bios, init->offset + 1);
1042 u8 addr = nv_ro08(bios, init->offset + 2);
1043 u8 mask = nv_ro08(bios, init->offset + 3);
1044 u8 data = nv_ro08(bios, init->offset + 4);
1045 u32 reg = init_tmds_reg(init, tmds);
1046
1047 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1048 tmds, addr, mask, data);
1049 init->offset += 5;
1050
1051 if (reg == 0)
1052 return;
1053
1054 init_wr32(init, reg + 0, addr | 0x00010000);
1055 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1056 init_wr32(init, reg + 0, addr);
1057}
1058
1059/**
1060 * INIT_ZM_TMDS_GROUP - opcode 0x50
1061 *
1062 */
1063static void
1064init_zm_tmds_group(struct nvbios_init *init)
1065{
1066 struct nouveau_bios *bios = init->bios;
1067 u8 tmds = nv_ro08(bios, init->offset + 1);
1068 u8 count = nv_ro08(bios, init->offset + 2);
1069 u32 reg = init_tmds_reg(init, tmds);
1070
1071 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1072 init->offset += 3;
1073
1074 while (count--) {
1075 u8 addr = nv_ro08(bios, init->offset + 0);
1076 u8 data = nv_ro08(bios, init->offset + 1);
1077
1078 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1079 init->offset += 2;
1080
1081 init_wr32(init, reg + 4, data);
1082 init_wr32(init, reg + 0, addr);
1083 }
1084}
1085
1086/**
1087 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1088 *
1089 */
1090static void
1091init_cr_idx_adr_latch(struct nvbios_init *init)
1092{
1093 struct nouveau_bios *bios = init->bios;
1094 u8 addr0 = nv_ro08(bios, init->offset + 1);
1095 u8 addr1 = nv_ro08(bios, init->offset + 2);
1096 u8 base = nv_ro08(bios, init->offset + 3);
1097 u8 count = nv_ro08(bios, init->offset + 4);
1098 u8 save0;
1099
1100 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1101 init->offset += 5;
1102
1103 save0 = init_rdvgai(init, 0x03d4, addr0);
1104 while (count--) {
1105 u8 data = nv_ro08(bios, init->offset);
1106
1107 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1108 init->offset += 1;
1109
1110 init_wrvgai(init, 0x03d4, addr0, base++);
1111 init_wrvgai(init, 0x03d4, addr1, data);
1112 }
1113 init_wrvgai(init, 0x03d4, addr0, save0);
1114}
1115
1116/**
1117 * INIT_CR - opcode 0x52
1118 *
1119 */
1120static void
1121init_cr(struct nvbios_init *init)
1122{
1123 struct nouveau_bios *bios = init->bios;
1124 u8 addr = nv_ro08(bios, init->offset + 1);
1125 u8 mask = nv_ro08(bios, init->offset + 2);
1126 u8 data = nv_ro08(bios, init->offset + 3);
1127 u8 val;
1128
1129 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1130 init->offset += 4;
1131
1132 val = init_rdvgai(init, 0x03d4, addr) & mask;
1133 init_wrvgai(init, 0x03d4, addr, val | data);
1134}
1135
1136/**
1137 * INIT_ZM_CR - opcode 0x53
1138 *
1139 */
1140static void
1141init_zm_cr(struct nvbios_init *init)
1142{
1143 struct nouveau_bios *bios = init->bios;
1144 u8 addr = nv_ro08(bios, init->offset + 1);
1145 u8 data = nv_ro08(bios, init->offset + 2);
1146
1147 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1148 init->offset += 3;
1149
1150 init_wrvgai(init, 0x03d4, addr, data);
1151}
1152
1153/**
1154 * INIT_ZM_CR_GROUP - opcode 0x54
1155 *
1156 */
1157static void
1158init_zm_cr_group(struct nvbios_init *init)
1159{
1160 struct nouveau_bios *bios = init->bios;
1161 u8 count = nv_ro08(bios, init->offset + 1);
1162
1163 trace("ZM_CR_GROUP\n");
1164 init->offset += 2;
1165
1166 while (count--) {
1167 u8 addr = nv_ro08(bios, init->offset + 0);
1168 u8 data = nv_ro08(bios, init->offset + 1);
1169
1170 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1171 init->offset += 2;
1172
1173 init_wrvgai(init, 0x03d4, addr, data);
1174 }
1175}
1176
1177/**
1178 * INIT_CONDITION_TIME - opcode 0x56
1179 *
1180 */
1181static void
1182init_condition_time(struct nvbios_init *init)
1183{
1184 struct nouveau_bios *bios = init->bios;
1185 u8 cond = nv_ro08(bios, init->offset + 1);
1186 u8 retry = nv_ro08(bios, init->offset + 2);
1187 u8 wait = min((u16)retry * 50, 100);
1188
1189 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1190 init->offset += 3;
1191
1192 if (!init_exec(init))
1193 return;
1194
1195 while (wait--) {
1196 if (init_condition_met(init, cond))
1197 return;
1198 mdelay(20);
1199 }
1200
1201 init_exec_set(init, false);
1202}
1203
1204/**
1205 * INIT_LTIME - opcode 0x57
1206 *
1207 */
1208static void
1209init_ltime(struct nvbios_init *init)
1210{
1211 struct nouveau_bios *bios = init->bios;
1212 u16 msec = nv_ro16(bios, init->offset + 1);
1213
1214 trace("LTIME\t0x%04x\n", msec);
1215 init->offset += 3;
1216
1217 if (init_exec(init))
1218 mdelay(msec);
1219}
1220
1221/**
1222 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1223 *
1224 */
1225static void
1226init_zm_reg_sequence(struct nvbios_init *init)
1227{
1228 struct nouveau_bios *bios = init->bios;
1229 u32 base = nv_ro32(bios, init->offset + 1);
1230 u8 count = nv_ro08(bios, init->offset + 5);
1231
1232 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1233 init->offset += 6;
1234
1235 while (count--) {
1236 u32 data = nv_ro32(bios, init->offset);
1237
1238 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1239 init->offset += 4;
1240
1241 init_wr32(init, base, data);
1242 base += 4;
1243 }
1244}
1245
1246/**
1247 * INIT_SUB_DIRECT - opcode 0x5b
1248 *
1249 */
1250static void
1251init_sub_direct(struct nvbios_init *init)
1252{
1253 struct nouveau_bios *bios = init->bios;
1254 u16 addr = nv_ro16(bios, init->offset + 1);
1255 u16 save;
1256
1257 trace("SUB_DIRECT\t0x%04x\n", addr);
1258
1259 if (init_exec(init)) {
1260 save = init->offset;
1261 init->offset = addr;
1262 if (nvbios_exec(init)) {
1263 error("error parsing sub-table\n");
1264 return;
1265 }
1266 init->offset = save;
1267 }
1268
1269 init->offset += 3;
1270}
1271
1272/**
1273 * INIT_JUMP - opcode 0x5c
1274 *
1275 */
1276static void
1277init_jump(struct nvbios_init *init)
1278{
1279 struct nouveau_bios *bios = init->bios;
1280 u16 offset = nv_ro16(bios, init->offset + 1);
1281
1282 trace("JUMP\t0x%04x\n", offset);
1283 init->offset = offset;
1284}
1285
1286/**
1287 * INIT_I2C_IF - opcode 0x5e
1288 *
1289 */
1290static void
1291init_i2c_if(struct nvbios_init *init)
1292{
1293 struct nouveau_bios *bios = init->bios;
1294 u8 index = nv_ro08(bios, init->offset + 1);
1295 u8 addr = nv_ro08(bios, init->offset + 2);
1296 u8 reg = nv_ro08(bios, init->offset + 3);
1297 u8 mask = nv_ro08(bios, init->offset + 4);
1298 u8 data = nv_ro08(bios, init->offset + 5);
1299 u8 value;
1300
1301 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1302 index, addr, reg, mask, data);
1303 init->offset += 6;
1304 init_exec_force(init, true);
1305
1306 value = init_rdi2cr(init, index, addr, reg);
1307 if ((value & mask) != data)
1308 init_exec_set(init, false);
1309
1310 init_exec_force(init, false);
1311}
1312
1313/**
1314 * INIT_COPY_NV_REG - opcode 0x5f
1315 *
1316 */
1317static void
1318init_copy_nv_reg(struct nvbios_init *init)
1319{
1320 struct nouveau_bios *bios = init->bios;
1321 u32 sreg = nv_ro32(bios, init->offset + 1);
1322 u8 shift = nv_ro08(bios, init->offset + 5);
1323 u32 smask = nv_ro32(bios, init->offset + 6);
1324 u32 sxor = nv_ro32(bios, init->offset + 10);
1325 u32 dreg = nv_ro32(bios, init->offset + 14);
1326 u32 dmask = nv_ro32(bios, init->offset + 18);
1327 u32 data;
1328
1329 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1330 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1331 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1332 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1333 init->offset += 22;
1334
1335 data = init_shift(init_rd32(init, sreg), shift);
1336 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1337}
1338
1339/**
1340 * INIT_ZM_INDEX_IO - opcode 0x62
1341 *
1342 */
1343static void
1344init_zm_index_io(struct nvbios_init *init)
1345{
1346 struct nouveau_bios *bios = init->bios;
1347 u16 port = nv_ro16(bios, init->offset + 1);
1348 u8 index = nv_ro08(bios, init->offset + 3);
1349 u8 data = nv_ro08(bios, init->offset + 4);
1350
1351 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1352 init->offset += 5;
1353
1354 init_wrvgai(init, port, index, data);
1355}
1356
1357/**
1358 * INIT_COMPUTE_MEM - opcode 0x63
1359 *
1360 */
1361static void
1362init_compute_mem(struct nvbios_init *init)
1363{
1364 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1365
1366 trace("COMPUTE_MEM\n");
1367 init->offset += 1;
1368
1369 init_exec_force(init, true);
1370 if (init_exec(init) && devinit->meminit)
1371 devinit->meminit(devinit);
1372 init_exec_force(init, false);
1373}
1374
1375/**
1376 * INIT_RESET - opcode 0x65
1377 *
1378 */
1379static void
1380init_reset(struct nvbios_init *init)
1381{
1382 struct nouveau_bios *bios = init->bios;
1383 u32 reg = nv_ro32(bios, init->offset + 1);
1384 u32 data1 = nv_ro32(bios, init->offset + 5);
1385 u32 data2 = nv_ro32(bios, init->offset + 9);
1386 u32 savepci19;
1387
1388 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1389 init->offset += 13;
1390 init_exec_force(init, true);
1391
1392 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1393 init_wr32(init, reg, data1);
1394 udelay(10);
1395 init_wr32(init, reg, data2);
1396 init_wr32(init, 0x00184c, savepci19);
1397 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1398
1399 init_exec_force(init, false);
1400}
1401
1402/**
1403 * INIT_CONFIGURE_MEM - opcode 0x66
1404 *
1405 */
1406static u16
1407init_configure_mem_clk(struct nvbios_init *init)
1408{
1409 u16 mdata = bmp_mem_init_table(init->bios);
1410 if (mdata)
1411 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1412 return mdata;
1413}
1414
1415static void
1416init_configure_mem(struct nvbios_init *init)
1417{
1418 struct nouveau_bios *bios = init->bios;
1419 u16 mdata, sdata;
1420 u32 addr, data;
1421
1422 trace("CONFIGURE_MEM\n");
1423 init->offset += 1;
1424
1425 if (bios->version.major > 2) {
1426 init_done(init);
1427 return;
1428 }
1429 init_exec_force(init, true);
1430
1431 mdata = init_configure_mem_clk(init);
1432 sdata = bmp_sdr_seq_table(bios);
1433 if (nv_ro08(bios, mdata) & 0x01)
1434 sdata = bmp_ddr_seq_table(bios);
1435 mdata += 6; /* skip to data */
1436
1437 data = init_rdvgai(init, 0x03c4, 0x01);
1438 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1439
1440 while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {
1441 switch (addr) {
1442 case 0x10021c: /* CKE_NORMAL */
1443 case 0x1002d0: /* CMD_REFRESH */
1444 case 0x1002d4: /* CMD_PRECHARGE */
1445 data = 0x00000001;
1446 break;
1447 default:
1448 data = nv_ro32(bios, mdata);
1449 mdata += 4;
1450 if (data == 0xffffffff)
1451 continue;
1452 break;
1453 }
1454
1455 init_wr32(init, addr, data);
1456 }
1457
1458 init_exec_force(init, false);
1459}
1460
1461/**
1462 * INIT_CONFIGURE_CLK - opcode 0x67
1463 *
1464 */
1465static void
1466init_configure_clk(struct nvbios_init *init)
1467{
1468 struct nouveau_bios *bios = init->bios;
1469 u16 mdata, clock;
1470
1471 trace("CONFIGURE_CLK\n");
1472 init->offset += 1;
1473
1474 if (bios->version.major > 2) {
1475 init_done(init);
1476 return;
1477 }
1478 init_exec_force(init, true);
1479
1480 mdata = init_configure_mem_clk(init);
1481
1482 /* NVPLL */
1483 clock = nv_ro16(bios, mdata + 4) * 10;
1484 init_prog_pll(init, 0x680500, clock);
1485
1486 /* MPLL */
1487 clock = nv_ro16(bios, mdata + 2) * 10;
1488 if (nv_ro08(bios, mdata) & 0x01)
1489 clock *= 2;
1490 init_prog_pll(init, 0x680504, clock);
1491
1492 init_exec_force(init, false);
1493}
1494
1495/**
1496 * INIT_CONFIGURE_PREINIT - opcode 0x68
1497 *
1498 */
1499static void
1500init_configure_preinit(struct nvbios_init *init)
1501{
1502 struct nouveau_bios *bios = init->bios;
1503 u32 strap;
1504
1505 trace("CONFIGURE_PREINIT\n");
1506 init->offset += 1;
1507
1508 if (bios->version.major > 2) {
1509 init_done(init);
1510 return;
1511 }
1512 init_exec_force(init, true);
1513
1514 strap = init_rd32(init, 0x101000);
1515 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1516 init_wrvgai(init, 0x03d4, 0x3c, strap);
1517
1518 init_exec_force(init, false);
1519}
1520
1521/**
1522 * INIT_IO - opcode 0x69
1523 *
1524 */
1525static void
1526init_io(struct nvbios_init *init)
1527{
1528 struct nouveau_bios *bios = init->bios;
1529 u16 port = nv_ro16(bios, init->offset + 1);
1530 u8 mask = nv_ro16(bios, init->offset + 3);
1531 u8 data = nv_ro16(bios, init->offset + 4);
1532 u8 value;
1533
1534 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1535 init->offset += 5;
1536
1537 /* ummm.. yes.. should really figure out wtf this is and why it's
1538 * needed some day.. it's almost certainly wrong, but, it also
1539 * somehow makes things work...
1540 */
1541 if (nv_device(init->bios)->card_type >= NV_50 &&
1542 port == 0x03c3 && data == 0x01) {
1543 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1544 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1545 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1546 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1547 mdelay(10);
1548 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1549 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1550 init_wr32(init, 0x614100, 0x00800018);
1551 init_wr32(init, 0x614900, 0x00800018);
1552 mdelay(10);
1553 init_wr32(init, 0x614100, 0x10000018);
1554 init_wr32(init, 0x614900, 0x10000018);
cb75d97e
BS		 1555 }
1556
1557 value = init_rdport(init, port) & mask;
1558 init_wrport(init, port, data | value);
1559}
1560
1561/**
1562 * INIT_SUB - opcode 0x6b
1563 *
1564 */
1565static void
1566init_sub(struct nvbios_init *init)
1567{
1568 struct nouveau_bios *bios = init->bios;
1569 u8 index = nv_ro08(bios, init->offset + 1);
1570 u16 addr, save;
1571
1572 trace("SUB\t0x%02x\n", index);
1573
1574 addr = init_script(bios, index);
1575 if (addr && init_exec(init)) {
1576 save = init->offset;
1577 init->offset = addr;
1578 if (nvbios_exec(init)) {
1579 error("error parsing sub-table\n");
1580 return;
1581 }
1582 init->offset = save;
1583 }
1584
1585 init->offset += 2;
1586}
1587
1588/**
1589 * INIT_RAM_CONDITION - opcode 0x6d
1590 *
1591 */
1592static void
1593init_ram_condition(struct nvbios_init *init)
1594{
1595 struct nouveau_bios *bios = init->bios;
1596 u8 mask = nv_ro08(bios, init->offset + 1);
1597 u8 value = nv_ro08(bios, init->offset + 2);
1598
1599 trace("RAM_CONDITION\t"
1600 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1601 init->offset += 3;
1602
1603 if ((init_rd32(init, 0x100000) & mask) != value)
1604 init_exec_set(init, false);
1605}
1606
1607/**
1608 * INIT_NV_REG - opcode 0x6e
1609 *
1610 */
1611static void
1612init_nv_reg(struct nvbios_init *init)
1613{
1614 struct nouveau_bios *bios = init->bios;
1615 u32 reg = nv_ro32(bios, init->offset + 1);
1616 u32 mask = nv_ro32(bios, init->offset + 5);
1617 u32 data = nv_ro32(bios, init->offset + 9);
1618
1619 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1620 init->offset += 13;
1621
1622 init_mask(init, reg, ~mask, data);
1623}
1624
1625/**
1626 * INIT_MACRO - opcode 0x6f
1627 *
1628 */
1629static void
1630init_macro(struct nvbios_init *init)
1631{
1632 struct nouveau_bios *bios = init->bios;
1633 u8 macro = nv_ro08(bios, init->offset + 1);
1634 u16 table;
1635
1636 trace("MACRO\t0x%02x\n", macro);
1637
1638 table = init_macro_table(init);
1639 if (table) {
1640 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1641 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1642 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1643 init_wr32(init, addr, data);
1644 }
1645
1646 init->offset += 2;
1647}
1648
1649/**
1650 * INIT_RESUME - opcode 0x72
1651 *
1652 */
1653static void
1654init_resume(struct nvbios_init *init)
1655{
1656 trace("RESUME\n");
1657 init->offset += 1;
1658 init_exec_set(init, true);
1659}
1660
1661/**
1662 * INIT_TIME - opcode 0x74
1663 *
1664 */
1665static void
1666init_time(struct nvbios_init *init)
1667{
1668 struct nouveau_bios *bios = init->bios;
1669 u16 usec = nv_ro16(bios, init->offset + 1);
1670
1671 trace("TIME\t0x%04x\n", usec);
1672 init->offset += 3;
1673
1674 if (init_exec(init)) {
1675 if (usec < 1000)
1676 udelay(usec);
1677 else
1678 mdelay((usec + 900) / 1000);
1679 }
1680}
1681
1682/**
1683 * INIT_CONDITION - opcode 0x75
1684 *
1685 */
1686static void
1687init_condition(struct nvbios_init *init)
1688{
1689 struct nouveau_bios *bios = init->bios;
1690 u8 cond = nv_ro08(bios, init->offset + 1);
1691
1692 trace("CONDITION\t0x%02x\n", cond);
1693 init->offset += 2;
1694
1695 if (!init_condition_met(init, cond))
1696 init_exec_set(init, false);
1697}
1698
1699/**
1700 * INIT_IO_CONDITION - opcode 0x76
1701 *
1702 */
1703static void
1704init_io_condition(struct nvbios_init *init)
1705{
1706 struct nouveau_bios *bios = init->bios;
1707 u8 cond = nv_ro08(bios, init->offset + 1);
1708
1709 trace("IO_CONDITION\t0x%02x\n", cond);
1710 init->offset += 2;
1711
1712 if (!init_io_condition_met(init, cond))
1713 init_exec_set(init, false);
1714}
1715
1716/**
1717 * INIT_INDEX_IO - opcode 0x78
1718 *
1719 */
1720static void
1721init_index_io(struct nvbios_init *init)
1722{
1723 struct nouveau_bios *bios = init->bios;
1724 u16 port = nv_ro16(bios, init->offset + 1);
1725 u8 index = nv_ro16(bios, init->offset + 3);
1726 u8 mask = nv_ro08(bios, init->offset + 4);
1727 u8 data = nv_ro08(bios, init->offset + 5);
1728 u8 value;
1729
1730 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1731 port, index, mask, data);
1732 init->offset += 6;
1733
1734 value = init_rdvgai(init, port, index) & mask;
1735 init_wrvgai(init, port, index, data | value);
1736}
1737
1738/**
1739 * INIT_PLL - opcode 0x79
1740 *
1741 */
1742static void
1743init_pll(struct nvbios_init *init)
1744{
1745 struct nouveau_bios *bios = init->bios;
1746 u32 reg = nv_ro32(bios, init->offset + 1);
1747 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1748
1749 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1750 init->offset += 7;
1751
1752 init_prog_pll(init, reg, freq);
1753}
1754
1755/**
1756 * INIT_ZM_REG - opcode 0x7a
1757 *
1758 */
1759static void
1760init_zm_reg(struct nvbios_init *init)
1761{
1762 struct nouveau_bios *bios = init->bios;
1763 u32 addr = nv_ro32(bios, init->offset + 1);
1764 u32 data = nv_ro32(bios, init->offset + 5);
1765
1766 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1767 init->offset += 9;
1768
1769 if (addr == 0x000200)
1770 data |= 0x00000001;
1771
1772 init_wr32(init, addr, data);
1773}
1774
1775/**
1776 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1777 *
1778 */
1779static void
1780init_ram_restrict_pll(struct nvbios_init *init)
1781{
1782 struct nouveau_bios *bios = init->bios;
1783 u8 type = nv_ro08(bios, init->offset + 1);
1784 u8 count = init_ram_restrict_group_count(init);
1785 u8 strap = init_ram_restrict(init);
1786 u8 cconf;
1787
1788 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1789 init->offset += 2;
1790
1791 for (cconf = 0; cconf < count; cconf++) {
1792 u32 freq = nv_ro32(bios, init->offset);
1793
1794 if (cconf == strap) {
1795 trace("%dkHz *\n", freq);
1796 init_prog_pll(init, type, freq);
1797 } else {
1798 trace("%dkHz\n", freq);
1799 }
1800
1801 init->offset += 4;
1802 }
1803}
1804
1805/**
1806 * INIT_GPIO - opcode 0x8e
1807 *
1808 */
1809static void
1810init_gpio(struct nvbios_init *init)
1811{
1812 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1813
1814 trace("GPIO\n");
1815 init->offset += 1;
1816
1817 if (init_exec(init) && gpio && gpio->reset)
1ed73166 1818 gpio->reset(gpio, DCB_GPIO_UNUSED);
cb75d97e
BS		 1819}
1820
1821/**
1822 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1823 *
1824 */
1825static void
1826init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1827{
1828 struct nouveau_bios *bios = init->bios;
1829 u32 addr = nv_ro32(bios, init->offset + 1);
1830 u8 incr = nv_ro08(bios, init->offset + 5);
1831 u8 num = nv_ro08(bios, init->offset + 6);
1832 u8 count = init_ram_restrict_group_count(init);
1833 u8 index = init_ram_restrict(init);
1834 u8 i, j;
1835
1836 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
bfd8bd1f 1837 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
cb75d97e
BS		 1838 init->offset += 7;
1839
1840 for (i = 0; i < num; i++) {
1841 trace("\tR[0x%06x] = {\n", addr);
1842 for (j = 0; j < count; j++) {
1843 u32 data = nv_ro32(bios, init->offset);
1844
1845 if (j == index) {
1846 trace("\t\t0x%08x *\n", data);
1847 init_wr32(init, addr, data);
1848 } else {
1849 trace("\t\t0x%08x\n", data);
1850 }
1851
1852 init->offset += 4;
1853 }
1854 trace("\t}\n");
1855 addr += incr;
1856 }
1857}
1858
1859/**
1860 * INIT_COPY_ZM_REG - opcode 0x90
1861 *
1862 */
1863static void
1864init_copy_zm_reg(struct nvbios_init *init)
1865{
1866 struct nouveau_bios *bios = init->bios;
1867 u32 sreg = nv_ro32(bios, init->offset + 1);
1868 u32 dreg = nv_ro32(bios, init->offset + 5);
1869
bfd8bd1f 1870 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
cb75d97e
BS		 1871 init->offset += 9;
1872
1873 init_wr32(init, dreg, init_rd32(init, sreg));
1874}
1875
1876/**
1877 * INIT_ZM_REG_GROUP - opcode 0x91
1878 *
1879 */
1880static void
1881init_zm_reg_group(struct nvbios_init *init)
1882{
1883 struct nouveau_bios *bios = init->bios;
1884 u32 addr = nv_ro32(bios, init->offset + 1);
1885 u8 count = nv_ro08(bios, init->offset + 5);
1886
950fbfab 1887 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
cb75d97e
BS		 1888 init->offset += 6;
1889
1890 while (count--) {
1891 u32 data = nv_ro32(bios, init->offset);
1892 trace("\t0x%08x\n", data);
1893 init_wr32(init, addr, data);
1894 init->offset += 4;
1895 }
1896}
1897
1898/**
1899 * INIT_XLAT - opcode 0x96
1900 *
1901 */
1902static void
1903init_xlat(struct nvbios_init *init)
1904{
1905 struct nouveau_bios *bios = init->bios;
1906 u32 saddr = nv_ro32(bios, init->offset + 1);
1907 u8 sshift = nv_ro08(bios, init->offset + 5);
1908 u8 smask = nv_ro08(bios, init->offset + 6);
1909 u8 index = nv_ro08(bios, init->offset + 7);
1910 u32 daddr = nv_ro32(bios, init->offset + 8);
1911 u32 dmask = nv_ro32(bios, init->offset + 12);
1912 u8 shift = nv_ro08(bios, init->offset + 16);
1913 u32 data;
1914
1915 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1916 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1917 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1918 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1919 init->offset += 17;
1920
1921 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1922 data = init_xlat_(init, index, data) << shift;
1923 init_mask(init, daddr, ~dmask, data);
1924}
1925
1926/**
1927 * INIT_ZM_MASK_ADD - opcode 0x97
1928 *
1929 */
1930static void
1931init_zm_mask_add(struct nvbios_init *init)
1932{
1933 struct nouveau_bios *bios = init->bios;
1934 u32 addr = nv_ro32(bios, init->offset + 1);
1935 u32 mask = nv_ro32(bios, init->offset + 5);
1936 u32 add = nv_ro32(bios, init->offset + 9);
1937 u32 data;
1938
1939 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1940 init->offset += 13;
1941
46b47b8a
BS		 1942 data = init_rd32(init, addr);
1943 data = (data & mask) | ((data + add) & ~mask);
cb75d97e
BS		 1944 init_wr32(init, addr, data);
1945}
1946
1947/**
1948 * INIT_AUXCH - opcode 0x98
1949 *
1950 */
1951static void
1952init_auxch(struct nvbios_init *init)
1953{
1954 struct nouveau_bios *bios = init->bios;
1955 u32 addr = nv_ro32(bios, init->offset + 1);
1956 u8 count = nv_ro08(bios, init->offset + 5);
1957
1958 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1959 init->offset += 6;
1960
1961 while (count--) {
1962 u8 mask = nv_ro08(bios, init->offset + 0);
1963 u8 data = nv_ro08(bios, init->offset + 1);
1964 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1965 mask = init_rdauxr(init, addr) & mask;
1966 init_wrauxr(init, addr, mask | data);
1967 init->offset += 2;
1968 }
1969}
1970
1971/**
1972 * INIT_AUXCH - opcode 0x99
1973 *
1974 */
1975static void
1976init_zm_auxch(struct nvbios_init *init)
1977{
1978 struct nouveau_bios *bios = init->bios;
1979 u32 addr = nv_ro32(bios, init->offset + 1);
1980 u8 count = nv_ro08(bios, init->offset + 5);
1981
1982 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1983 init->offset += 6;
1984
1985 while (count--) {
1986 u8 data = nv_ro08(bios, init->offset + 0);
1987 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1988 init_wrauxr(init, addr, data);
1989 init->offset += 1;
1990 }
1991}
1992
1993/**
1994 * INIT_I2C_LONG_IF - opcode 0x9a
1995 *
1996 */
1997static void
1998init_i2c_long_if(struct nvbios_init *init)
1999{
2000 struct nouveau_bios *bios = init->bios;
2001 u8 index = nv_ro08(bios, init->offset + 1);
2002 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
2003 u8 reglo = nv_ro08(bios, init->offset + 3);
2004 u8 reghi = nv_ro08(bios, init->offset + 4);
2005 u8 mask = nv_ro08(bios, init->offset + 5);
2006 u8 data = nv_ro08(bios, init->offset + 6);
2007 struct nouveau_i2c_port *port;
2008
2009 trace("I2C_LONG_IF\t"
2010 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
2011 index, addr, reglo, reghi, mask, data);
2012 init->offset += 7;
2013
2014 port = init_i2c(init, index);
2015 if (port) {
2016 u8 i[2] = { reghi, reglo };
2017 u8 o[1] = {};
2018 struct i2c_msg msg[] = {
2019 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2020 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2021 };
2022 int ret;
2023
2024 ret = i2c_transfer(&port->adapter, msg, 2);
2025 if (ret == 2 && ((o[0] & mask) == data))
2026 return;
2027 }
2028
2029 init_exec_set(init, false);
2030}
2031
1ed73166
BS		 2032/**
2033 * INIT_GPIO_NE - opcode 0xa9
2034 *
2035 */
2036static void
2037init_gpio_ne(struct nvbios_init *init)
2038{
2039 struct nouveau_bios *bios = init->bios;
2040 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2041 struct dcb_gpio_func func;
2042 u8 count = nv_ro08(bios, init->offset + 1);
2043 u8 idx = 0, ver, len;
2044 u16 data, i;
2045
2046 trace("GPIO_NE\t");
2047 init->offset += 2;
2048
2049 for (i = init->offset; i < init->offset + count; i++)
2050 cont("0x%02x ", nv_ro08(bios, i));
2051 cont("\n");
2052
2053 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2054 if (func.func != DCB_GPIO_UNUSED) {
2055 for (i = init->offset; i < init->offset + count; i++) {
2056 if (func.func == nv_ro08(bios, i))
2057 break;
2058 }
2059
2060 trace("\tFUNC[0x%02x]", func.func);
2061 if (i == (init->offset + count)) {
2062 cont(" *");
2063 if (init_exec(init) && gpio && gpio->reset)
2064 gpio->reset(gpio, func.func);
2065 }
2066 cont("\n");
2067 }
2068 }
2069
2070 init->offset += count;
2071}
2072
cb75d97e
BS		 2073static struct nvbios_init_opcode {
2074 void (*exec)(struct nvbios_init *);
2075} init_opcode[] = {
2076 [0x32] = { init_io_restrict_prog },
2077 [0x33] = { init_repeat },
2078 [0x34] = { init_io_restrict_pll },
2079 [0x36] = { init_end_repeat },
2080 [0x37] = { init_copy },
2081 [0x38] = { init_not },
2082 [0x39] = { init_io_flag_condition },
2083 [0x3a] = { init_dp_condition },
2084 [0x3b] = { init_io_mask_or },
2085 [0x3c] = { init_io_or },
2086 [0x49] = { init_idx_addr_latched },
2087 [0x4a] = { init_io_restrict_pll2 },
2088 [0x4b] = { init_pll2 },
2089 [0x4c] = { init_i2c_byte },
2090 [0x4d] = { init_zm_i2c_byte },
2091 [0x4e] = { init_zm_i2c },
2092 [0x4f] = { init_tmds },
2093 [0x50] = { init_zm_tmds_group },
2094 [0x51] = { init_cr_idx_adr_latch },
2095 [0x52] = { init_cr },
2096 [0x53] = { init_zm_cr },
2097 [0x54] = { init_zm_cr_group },
2098 [0x56] = { init_condition_time },
2099 [0x57] = { init_ltime },
2100 [0x58] = { init_zm_reg_sequence },
2101 [0x5b] = { init_sub_direct },
2102 [0x5c] = { init_jump },
2103 [0x5e] = { init_i2c_if },
2104 [0x5f] = { init_copy_nv_reg },
2105 [0x62] = { init_zm_index_io },
2106 [0x63] = { init_compute_mem },
2107 [0x65] = { init_reset },
2108 [0x66] = { init_configure_mem },
2109 [0x67] = { init_configure_clk },
2110 [0x68] = { init_configure_preinit },
2111 [0x69] = { init_io },
2112 [0x6b] = { init_sub },
2113 [0x6d] = { init_ram_condition },
2114 [0x6e] = { init_nv_reg },
2115 [0x6f] = { init_macro },
2116 [0x71] = { init_done },
2117 [0x72] = { init_resume },
2118 [0x74] = { init_time },
2119 [0x75] = { init_condition },
2120 [0x76] = { init_io_condition },
2121 [0x78] = { init_index_io },
2122 [0x79] = { init_pll },
2123 [0x7a] = { init_zm_reg },
2124 [0x87] = { init_ram_restrict_pll },
2125 [0x8c] = { init_reserved },
2126 [0x8d] = { init_reserved },
2127 [0x8e] = { init_gpio },
2128 [0x8f] = { init_ram_restrict_zm_reg_group },
2129 [0x90] = { init_copy_zm_reg },
2130 [0x91] = { init_zm_reg_group },
2131 [0x92] = { init_reserved },
2132 [0x96] = { init_xlat },
2133 [0x97] = { init_zm_mask_add },
2134 [0x98] = { init_auxch },
2135 [0x99] = { init_zm_auxch },
2136 [0x9a] = { init_i2c_long_if },
1ed73166 2137 [0xa9] = { init_gpio_ne },
cb75d97e
BS		 2138};
2139
2140#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2141
2142int
2143nvbios_exec(struct nvbios_init *init)
2144{
2145 init->nested++;
2146 while (init->offset) {
2147 u8 opcode = nv_ro08(init->bios, init->offset);
2148 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2149 error("unknown opcode 0x%02x\n", opcode);
2150 return -EINVAL;
2151 }
2152
2153 init_opcode[opcode].exec(init);
2154 }
2155 init->nested--;
2156 return 0;
2157}
2158
2159int
2160nvbios_init(struct nouveau_subdev *subdev, bool execute)
2161{
2162 struct nouveau_bios *bios = nouveau_bios(subdev);
2163 int ret = 0;
2164 int i = -1;
2165 u16 data;
2166
2167 if (execute)
5addcf0a 2168 nv_suspend(bios, "running init tables\n");
cb75d97e
BS		 2169 while (!ret && (data = (init_script(bios, ++i)))) {
2170 struct nvbios_init init = {
2171 .subdev = subdev,
2172 .bios = bios,
2173 .offset = data,
2174 .outp = NULL,
2175 .crtc = -1,
2176 .execute = execute ? 1 : 0,
2177 };
2178
2179 ret = nvbios_exec(&init);
2180 }
2181
2182 /* the vbios parser will run this right after the normal init
2183 * tables, whereas the binary driver appears to run it later.
2184 */
2185 if (!ret && (data = init_unknown_script(bios))) {
2186 struct nvbios_init init = {
2187 .subdev = subdev,
2188 .bios = bios,
2189 .offset = data,
2190 .outp = NULL,
2191 .crtc = -1,
2192 .execute = execute ? 1 : 0,
2193 };
2194
2195 ret = nvbios_exec(&init);
2196 }
2197
2198 return 0;
2199}
Linux 6.x block layer and io_uring tree(s)