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drm/nouveau: share fence structures between nv10+ and nv50 implementations
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / core / subdev / bios / init.c
CommitLineData
cb75d97e
BS		 1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
cb75d97e
BS		 5#include <subdev/bios/bmp.h>
6#include <subdev/bios/bit.h>
1ed73166 7#include <subdev/bios/conn.h>
cb75d97e
BS		 8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
1ed73166 10#include <subdev/bios/gpio.h>
cb75d97e
BS		 11#include <subdev/bios/init.h>
12#include <subdev/devinit.h>
13#include <subdev/clock.h>
14#include <subdev/i2c.h>
15#include <subdev/vga.h>
16#include <subdev/gpio.h>
17
18#define bioslog(lvl, fmt, args...) do { \
19 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
20 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
21} while(0)
22#define cont(fmt, args...) do { \
23 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
24 printk(fmt, ##args); \
25} while(0)
26#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
27#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
28#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
29
30/******************************************************************************
31 * init parser control flow helpers
32 *****************************************************************************/
33
34static inline bool
35init_exec(struct nvbios_init *init)
36{
37 return (init->execute == 1) || ((init->execute & 5) == 5);
38}
39
40static inline void
41init_exec_set(struct nvbios_init *init, bool exec)
42{
43 if (exec) init->execute &= 0xfd;
44 else init->execute |= 0x02;
45}
46
47static inline void
48init_exec_inv(struct nvbios_init *init)
49{
50 init->execute ^= 0x02;
51}
52
53static inline void
54init_exec_force(struct nvbios_init *init, bool exec)
55{
56 if (exec) init->execute |= 0x04;
57 else init->execute &= 0xfb;
58}
59
60/******************************************************************************
61 * init parser wrappers for normal register/i2c/whatever accessors
62 *****************************************************************************/
63
64static inline int
65init_or(struct nvbios_init *init)
66{
67 if (init->outp)
68 return ffs(init->outp->or) - 1;
69 error("script needs OR!!\n");
70 return 0;
71}
72
73static inline int
74init_link(struct nvbios_init *init)
75{
76 if (init->outp)
77 return !(init->outp->sorconf.link & 1);
78 error("script needs OR link\n");
79 return 0;
80}
81
82static inline int
83init_crtc(struct nvbios_init *init)
84{
85 if (init->crtc >= 0)
86 return init->crtc;
87 error("script needs crtc\n");
88 return 0;
89}
90
91static u8
92init_conn(struct nvbios_init *init)
93{
94 struct nouveau_bios *bios = init->bios;
95
96 if (init->outp) {
97 u8 ver, len;
98 u16 conn = dcb_conn(bios, init->outp->connector, &ver, &len);
99 if (conn)
100 return nv_ro08(bios, conn);
101 }
102
103 error("script needs connector type\n");
104 return 0x00;
105}
106
107static inline u32
108init_nvreg(struct nvbios_init *init, u32 reg)
109{
110 /* C51 (at least) sometimes has the lower bits set which the VBIOS
111 * interprets to mean that access needs to go through certain IO
112 * ports instead. The NVIDIA binary driver has been seen to access
113 * these through the NV register address, so lets assume we can
114 * do the same
115 */
116 reg &= ~0x00000003;
117
118 /* GF8+ display scripts need register addresses mangled a bit to
119 * select a specific CRTC/OR
120 */
121 if (nv_device(init->bios)->card_type >= NV_50) {
122 if (reg & 0x80000000) {
123 reg += init_crtc(init) * 0x800;
124 reg &= ~0x80000000;
125 }
126
127 if (reg & 0x40000000) {
128 reg += init_or(init) * 0x800;
129 reg &= ~0x40000000;
130 if (reg & 0x20000000) {
131 reg += init_link(init) * 0x80;
132 reg &= ~0x20000000;
133 }
134 }
135 }
136
137 if (reg & ~0x00fffffc)
138 warn("unknown bits in register 0x%08x\n", reg);
139 return reg;
140}
141
142static u32
143init_rd32(struct nvbios_init *init, u32 reg)
144{
145 reg = init_nvreg(init, reg);
146 if (init_exec(init))
147 return nv_rd32(init->subdev, reg);
148 return 0x00000000;
149}
150
151static void
152init_wr32(struct nvbios_init *init, u32 reg, u32 val)
153{
154 reg = init_nvreg(init, reg);
155 if (init_exec(init))
156 nv_wr32(init->subdev, reg, val);
157}
158
159static u32
160init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
161{
162 reg = init_nvreg(init, reg);
163 if (init_exec(init)) {
164 u32 tmp = nv_rd32(init->subdev, reg);
165 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
166 return tmp;
167 }
168 return 0x00000000;
169}
170
171static u8
172init_rdport(struct nvbios_init *init, u16 port)
173{
174 if (init_exec(init))
175 return nv_rdport(init->subdev, init->crtc, port);
176 return 0x00;
177}
178
179static void
180init_wrport(struct nvbios_init *init, u16 port, u8 value)
181{
182 if (init_exec(init))
183 nv_wrport(init->subdev, init->crtc, port, value);
184}
185
186static u8
187init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
188{
189 struct nouveau_subdev *subdev = init->subdev;
190 if (init_exec(init)) {
191 int head = init->crtc < 0 ? 0 : init->crtc;
192 return nv_rdvgai(subdev, head, port, index);
193 }
194 return 0x00;
195}
196
197static void
198init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
199{
200 /* force head 0 for updates to cr44, it only exists on first head */
201 if (nv_device(init->subdev)->card_type < NV_50) {
202 if (port == 0x03d4 && index == 0x44)
203 init->crtc = 0;
204 }
205
206 if (init_exec(init)) {
207 int head = init->crtc < 0 ? 0 : init->crtc;
208 nv_wrvgai(init->subdev, head, port, index, value);
209 }
210
211 /* select head 1 if cr44 write selected it */
212 if (nv_device(init->subdev)->card_type < NV_50) {
213 if (port == 0x03d4 && index == 0x44 && value == 3)
214 init->crtc = 1;
215 }
216}
217
218static struct nouveau_i2c_port *
219init_i2c(struct nvbios_init *init, int index)
220{
221 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
222
223 if (index == 0xff) {
224 index = NV_I2C_DEFAULT(0);
225 if (init->outp && init->outp->i2c_upper_default)
226 index = NV_I2C_DEFAULT(1);
227 } else
228 if (index < 0) {
229 if (!init->outp) {
230 error("script needs output for i2c\n");
231 return NULL;
232 }
233
234 index = init->outp->i2c_index;
235 }
236
237 return i2c->find(i2c, index);
238}
239
240static int
241init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
242{
243 struct nouveau_i2c_port *port = init_i2c(init, index);
244 if (port && init_exec(init))
245 return nv_rdi2cr(port, addr, reg);
246 return -ENODEV;
247}
248
249static int
250init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
251{
252 struct nouveau_i2c_port *port = init_i2c(init, index);
253 if (port && init_exec(init))
254 return nv_wri2cr(port, addr, reg, val);
255 return -ENODEV;
256}
257
258static int
259init_rdauxr(struct nvbios_init *init, u32 addr)
260{
261 struct nouveau_i2c_port *port = init_i2c(init, -1);
262 u8 data;
263
264 if (port && init_exec(init)) {
265 int ret = nv_rdaux(port, addr, &data, 1);
266 if (ret)
267 return ret;
268 return data;
269 }
270
271 return -ENODEV;
272}
273
274static int
275init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
276{
277 struct nouveau_i2c_port *port = init_i2c(init, -1);
278 if (port && init_exec(init))
279 return nv_wraux(port, addr, &data, 1);
280 return -ENODEV;
281}
282
283static void
284init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
285{
286 struct nouveau_clock *clk = nouveau_clock(init->bios);
287 if (clk && clk->pll_set && init_exec(init)) {
288 int ret = clk->pll_set(clk, id, freq);
289 if (ret)
290 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
291 }
292}
293
294/******************************************************************************
295 * parsing of bios structures that are required to execute init tables
296 *****************************************************************************/
297
298static u16
299init_table(struct nouveau_bios *bios, u16 *len)
300{
301 struct bit_entry bit_I;
302
303 if (!bit_entry(bios, 'I', &bit_I)) {
304 *len = bit_I.length;
305 return bit_I.offset;
306 }
307
308 if (bmp_version(bios) >= 0x0510) {
309 *len = 14;
310 return bios->bmp_offset + 75;
311 }
312
313 return 0x0000;
314}
315
316static u16
317init_table_(struct nvbios_init *init, u16 offset, const char *name)
318{
319 struct nouveau_bios *bios = init->bios;
320 u16 len, data = init_table(bios, &len);
321 if (data) {
322 if (len >= offset + 2) {
323 data = nv_ro16(bios, data + offset);
324 if (data)
325 return data;
326
327 warn("%s pointer invalid\n", name);
328 return 0x0000;
329 }
330
331 warn("init data too short for %s pointer", name);
332 return 0x0000;
333 }
334
335 warn("init data not found\n");
336 return 0x0000;
337}
338
339#define init_script_table(b) init_table_((b), 0x00, "script table")
340#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
341#define init_macro_table(b) init_table_((b), 0x04, "macro table")
342#define init_condition_table(b) init_table_((b), 0x06, "condition table")
343#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
344#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
345#define init_function_table(b) init_table_((b), 0x0c, "function table")
346#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
347
348static u16
349init_script(struct nouveau_bios *bios, int index)
350{
351 struct nvbios_init init = { .bios = bios };
352 u16 data;
353
354 if (bmp_version(bios) && bmp_version(bios) < 0x0510) {
355 if (index > 1)
356 return 0x0000;
357
358 data = bios->bmp_offset + (bios->version.major < 2 ? 14 : 18);
359 return nv_ro16(bios, data + (index * 2));
360 }
361
362 data = init_script_table(&init);
363 if (data)
364 return nv_ro16(bios, data + (index * 2));
365
366 return 0x0000;
367}
368
369static u16
370init_unknown_script(struct nouveau_bios *bios)
371{
372 u16 len, data = init_table(bios, &len);
373 if (data && len >= 16)
374 return nv_ro16(bios, data + 14);
375 return 0x0000;
376}
377
378static u16
379init_ram_restrict_table(struct nvbios_init *init)
380{
381 struct nouveau_bios *bios = init->bios;
382 struct bit_entry bit_M;
383 u16 data = 0x0000;
384
385 if (!bit_entry(bios, 'M', &bit_M)) {
386 if (bit_M.version == 1 && bit_M.length >= 5)
387 data = nv_ro16(bios, bit_M.offset + 3);
388 if (bit_M.version == 2 && bit_M.length >= 3)
389 data = nv_ro16(bios, bit_M.offset + 1);
390 }
391
392 if (data == 0x0000)
393 warn("ram restrict table not found\n");
394 return data;
395}
396
397static u8
398init_ram_restrict_group_count(struct nvbios_init *init)
399{
400 struct nouveau_bios *bios = init->bios;
401 struct bit_entry bit_M;
402
403 if (!bit_entry(bios, 'M', &bit_M)) {
404 if (bit_M.version == 1 && bit_M.length >= 5)
405 return nv_ro08(bios, bit_M.offset + 2);
406 if (bit_M.version == 2 && bit_M.length >= 3)
407 return nv_ro08(bios, bit_M.offset + 0);
408 }
409
410 return 0x00;
411}
412
5ddf4d4a
BS		 413static u8
414init_ram_restrict_strap(struct nvbios_init *init)
415{
416 /* This appears to be the behaviour of the VBIOS parser, and *is*
417 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
418 * avoid fucking up the memory controller (somehow) by reading it
419 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
420 *
421 * Preserving the non-caching behaviour on earlier chipsets just
422 * in case *not* re-reading the strap causes similar breakage.
423 */
424 if (!init->ramcfg || init->bios->version.major < 0x70)
425 init->ramcfg = init_rd32(init, 0x101000);
426 return (init->ramcfg & 0x00000003c) >> 2;
427}
428
cb75d97e
BS		 429static u8
430init_ram_restrict(struct nvbios_init *init)
431{
5ddf4d4a 432 u8 strap = init_ram_restrict_strap(init);
cb75d97e
BS		 433 u16 table = init_ram_restrict_table(init);
434 if (table)
435 return nv_ro08(init->bios, table + strap);
436 return 0x00;
437}
438
439static u8
440init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
441{
442 struct nouveau_bios *bios = init->bios;
443 u16 table = init_xlat_table(init);
444 if (table) {
445 u16 data = nv_ro16(bios, table + (index * 2));
446 if (data)
447 return nv_ro08(bios, data + offset);
448 warn("xlat table pointer %d invalid\n", index);
449 }
450 return 0x00;
451}
452
453/******************************************************************************
454 * utility functions used by various init opcode handlers
455 *****************************************************************************/
456
457static bool
458init_condition_met(struct nvbios_init *init, u8 cond)
459{
460 struct nouveau_bios *bios = init->bios;
461 u16 table = init_condition_table(init);
462 if (table) {
463 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
464 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
465 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
466 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
467 cond, reg, msk, val);
468 return (init_rd32(init, reg) & msk) == val;
469 }
470 return false;
471}
472
473static bool
474init_io_condition_met(struct nvbios_init *init, u8 cond)
475{
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_io_condition_table(init);
478 if (table) {
479 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
480 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
481 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
482 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
483 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
484 cond, port, index, mask, value);
485 return (init_rdvgai(init, port, index) & mask) == value;
486 }
487 return false;
488}
489
490static bool
491init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
492{
493 struct nouveau_bios *bios = init->bios;
494 u16 table = init_io_flag_condition_table(init);
495 if (table) {
496 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
497 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
498 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
499 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
500 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
501 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
502 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
503 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
504 return (nv_ro08(bios, data + ioval) & dmask) == value;
505 }
506 return false;
507}
508
509static inline u32
510init_shift(u32 data, u8 shift)
511{
512 if (shift < 0x80)
513 return data >> shift;
514 return data << (0x100 - shift);
515}
516
517static u32
518init_tmds_reg(struct nvbios_init *init, u8 tmds)
519{
520 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
521 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
522 * CR58 for CR57 = 0 to index a table of offsets to the basic
523 * 0x6808b0 address.
524 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
525 * CR58 for CR57 = 0 to index a table of offsets to the basic
526 * 0x6808b0 address, and then flip the offset by 8.
527 */
528
529 const int pramdac_offset[13] = {
530 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
531 const u32 pramdac_table[4] = {
532 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
533
534 if (tmds >= 0x80) {
535 if (init->outp) {
536 u32 dacoffset = pramdac_offset[init->outp->or];
537 if (tmds == 0x81)
538 dacoffset ^= 8;
539 return 0x6808b0 + dacoffset;
540 }
541
542 error("tmds opcodes need dcb\n");
543 } else {
544 if (tmds < ARRAY_SIZE(pramdac_table))
545 return pramdac_table[tmds];
546
547 error("tmds selector 0x%02x unknown\n", tmds);
548 }
549
550 return 0;
551}
552
553/******************************************************************************
554 * init opcode handlers
555 *****************************************************************************/
556
557/**
558 * init_reserved - stub for various unknown/unused single-byte opcodes
559 *
560 */
561static void
562init_reserved(struct nvbios_init *init)
563{
564 u8 opcode = nv_ro08(init->bios, init->offset);
565 trace("RESERVED\t0x%02x\n", opcode);
566 init->offset += 1;
567}
568
569/**
570 * INIT_DONE - opcode 0x71
571 *
572 */
573static void
574init_done(struct nvbios_init *init)
575{
576 trace("DONE\n");
577 init->offset = 0x0000;
578}
579
580/**
581 * INIT_IO_RESTRICT_PROG - opcode 0x32
582 *
583 */
584static void
585init_io_restrict_prog(struct nvbios_init *init)
586{
587 struct nouveau_bios *bios = init->bios;
588 u16 port = nv_ro16(bios, init->offset + 1);
589 u8 index = nv_ro08(bios, init->offset + 3);
590 u8 mask = nv_ro08(bios, init->offset + 4);
591 u8 shift = nv_ro08(bios, init->offset + 5);
592 u8 count = nv_ro08(bios, init->offset + 6);
593 u32 reg = nv_ro32(bios, init->offset + 7);
594 u8 conf, i;
595
596 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
597 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
598 reg, port, index, mask, shift);
599 init->offset += 11;
600
601 conf = (init_rdvgai(init, port, index) & mask) >> shift;
602 for (i = 0; i < count; i++) {
603 u32 data = nv_ro32(bios, init->offset);
604
605 if (i == conf) {
606 trace("\t0x%08x *\n", data);
607 init_wr32(init, reg, data);
608 } else {
609 trace("\t0x%08x\n", data);
610 }
611
612 init->offset += 4;
613 }
614 trace("}]\n");
615}
616
617/**
618 * INIT_REPEAT - opcode 0x33
619 *
620 */
621static void
622init_repeat(struct nvbios_init *init)
623{
624 struct nouveau_bios *bios = init->bios;
625 u8 count = nv_ro08(bios, init->offset + 1);
626 u16 repeat = init->repeat;
627
628 trace("REPEAT\t0x%02x\n", count);
629 init->offset += 2;
630
631 init->repeat = init->offset;
632 init->repend = init->offset;
633 while (count--) {
634 init->offset = init->repeat;
635 nvbios_exec(init);
636 if (count)
637 trace("REPEAT\t0x%02x\n", count);
638 }
639 init->offset = init->repend;
640 init->repeat = repeat;
641}
642
643/**
644 * INIT_IO_RESTRICT_PLL - opcode 0x34
645 *
646 */
647static void
648init_io_restrict_pll(struct nvbios_init *init)
649{
650 struct nouveau_bios *bios = init->bios;
651 u16 port = nv_ro16(bios, init->offset + 1);
652 u8 index = nv_ro08(bios, init->offset + 3);
653 u8 mask = nv_ro08(bios, init->offset + 4);
654 u8 shift = nv_ro08(bios, init->offset + 5);
655 s8 iofc = nv_ro08(bios, init->offset + 6);
656 u8 count = nv_ro08(bios, init->offset + 7);
657 u32 reg = nv_ro32(bios, init->offset + 8);
658 u8 conf, i;
659
660 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
661 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
662 reg, port, index, mask, shift, iofc);
663 init->offset += 12;
664
665 conf = (init_rdvgai(init, port, index) & mask) >> shift;
666 for (i = 0; i < count; i++) {
667 u32 freq = nv_ro16(bios, init->offset) * 10;
668
669 if (i == conf) {
670 trace("\t%dkHz *\n", freq);
671 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
672 freq *= 2;
673 init_prog_pll(init, reg, freq);
674 } else {
675 trace("\t%dkHz\n", freq);
676 }
677
678 init->offset += 2;
679 }
680 trace("}]\n");
681}
682
683/**
684 * INIT_END_REPEAT - opcode 0x36
685 *
686 */
687static void
688init_end_repeat(struct nvbios_init *init)
689{
690 trace("END_REPEAT\n");
691 init->offset += 1;
692
693 if (init->repeat) {
694 init->repend = init->offset;
695 init->offset = 0;
696 }
697}
698
699/**
700 * INIT_COPY - opcode 0x37
701 *
702 */
703static void
704init_copy(struct nvbios_init *init)
705{
706 struct nouveau_bios *bios = init->bios;
707 u32 reg = nv_ro32(bios, init->offset + 1);
708 u8 shift = nv_ro08(bios, init->offset + 5);
709 u8 smask = nv_ro08(bios, init->offset + 6);
710 u16 port = nv_ro16(bios, init->offset + 7);
711 u8 index = nv_ro08(bios, init->offset + 9);
712 u8 mask = nv_ro08(bios, init->offset + 10);
713 u8 data;
714
715 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
716 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
717 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
718 (shift & 0x80) ? (0x100 - shift) : shift, smask);
719 init->offset += 11;
720
721 data = init_rdvgai(init, port, index) & mask;
722 data |= init_shift(init_rd32(init, reg), shift) & smask;
723 init_wrvgai(init, port, index, data);
724}
725
726/**
727 * INIT_NOT - opcode 0x38
728 *
729 */
730static void
731init_not(struct nvbios_init *init)
732{
733 trace("NOT\n");
734 init->offset += 1;
735 init_exec_inv(init);
736}
737
738/**
739 * INIT_IO_FLAG_CONDITION - opcode 0x39
740 *
741 */
742static void
743init_io_flag_condition(struct nvbios_init *init)
744{
745 struct nouveau_bios *bios = init->bios;
746 u8 cond = nv_ro08(bios, init->offset + 1);
747
748 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
749 init->offset += 2;
750
751 if (!init_io_flag_condition_met(init, cond))
752 init_exec_set(init, false);
753}
754
755/**
756 * INIT_DP_CONDITION - opcode 0x3a
757 *
758 */
759static void
760init_dp_condition(struct nvbios_init *init)
761{
762 struct nouveau_bios *bios = init->bios;
65c78660 763 struct nvbios_dpout info;
cb75d97e
BS		 764 u8 cond = nv_ro08(bios, init->offset + 1);
765 u8 unkn = nv_ro08(bios, init->offset + 2);
65c78660 766 u8 ver, hdr, cnt, len;
cb75d97e
BS		 767 u16 data;
768
769 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
770 init->offset += 3;
771
772 switch (cond) {
773 case 0:
774 if (init_conn(init) != DCB_CONNECTOR_eDP)
775 init_exec_set(init, false);
776 break;
777 case 1:
778 case 2:
779 if ( init->outp &&
65c78660
BS		 780 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
781 (init->outp->or << 0) |
782 (init->outp->sorconf.link << 6),
783 &ver, &hdr, &cnt, &len, &info)))
784 {
785 if (!(info.flags & cond))
cb75d97e
BS		 786 init_exec_set(init, false);
787 break;
788 }
789
790 warn("script needs dp output table data\n");
791 break;
792 case 5:
793 if (!(init_rdauxr(init, 0x0d) & 1))
794 init_exec_set(init, false);
795 break;
796 default:
797 warn("unknown dp condition 0x%02x\n", cond);
798 break;
799 }
800}
801
802/**
803 * INIT_IO_MASK_OR - opcode 0x3b
804 *
805 */
806static void
807init_io_mask_or(struct nvbios_init *init)
808{
809 struct nouveau_bios *bios = init->bios;
810 u8 index = nv_ro08(bios, init->offset + 1);
811 u8 or = init_or(init);
812 u8 data;
813
814 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)", index, or);
815 init->offset += 2;
816
817 data = init_rdvgai(init, 0x03d4, index);
818 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
819}
820
821/**
822 * INIT_IO_OR - opcode 0x3c
823 *
824 */
825static void
826init_io_or(struct nvbios_init *init)
827{
828 struct nouveau_bios *bios = init->bios;
829 u8 index = nv_ro08(bios, init->offset + 1);
830 u8 or = init_or(init);
831 u8 data;
832
833 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)", index, or);
834 init->offset += 2;
835
836 data = init_rdvgai(init, 0x03d4, index);
837 init_wrvgai(init, 0x03d4, index, data | (1 << or));
838}
839
840/**
841 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
842 *
843 */
844static void
845init_idx_addr_latched(struct nvbios_init *init)
846{
847 struct nouveau_bios *bios = init->bios;
848 u32 creg = nv_ro32(bios, init->offset + 1);
849 u32 dreg = nv_ro32(bios, init->offset + 5);
850 u32 mask = nv_ro32(bios, init->offset + 9);
851 u32 data = nv_ro32(bios, init->offset + 13);
852 u8 count = nv_ro08(bios, init->offset + 17);
853
854 trace("INDEX_ADDRESS_LATCHED\t"
855 "R[0x%06x] : R[0x%06x]\n\tCTRL &= 0x%08x |= 0x%08x\n",
856 creg, dreg, mask, data);
857 init->offset += 18;
858
859 while (count--) {
860 u8 iaddr = nv_ro08(bios, init->offset + 0);
861 u8 idata = nv_ro08(bios, init->offset + 1);
862
863 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
864 init->offset += 2;
865
866 init_wr32(init, dreg, idata);
867 init_mask(init, creg, ~mask, data | idata);
868 }
869}
870
871/**
872 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
873 *
874 */
875static void
876init_io_restrict_pll2(struct nvbios_init *init)
877{
878 struct nouveau_bios *bios = init->bios;
879 u16 port = nv_ro16(bios, init->offset + 1);
880 u8 index = nv_ro08(bios, init->offset + 3);
881 u8 mask = nv_ro08(bios, init->offset + 4);
882 u8 shift = nv_ro08(bios, init->offset + 5);
883 u8 count = nv_ro08(bios, init->offset + 6);
884 u32 reg = nv_ro32(bios, init->offset + 7);
885 u8 conf, i;
886
887 trace("IO_RESTRICT_PLL2\t"
888 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
889 reg, port, index, mask, shift);
890 init->offset += 11;
891
892 conf = (init_rdvgai(init, port, index) & mask) >> shift;
893 for (i = 0; i < count; i++) {
894 u32 freq = nv_ro32(bios, init->offset);
895 if (i == conf) {
896 trace("\t%dkHz *\n", freq);
897 init_prog_pll(init, reg, freq);
898 } else {
899 trace("\t%dkHz\n", freq);
900 }
901 init->offset += 4;
902 }
903 trace("}]\n");
904}
905
906/**
907 * INIT_PLL2 - opcode 0x4b
908 *
909 */
910static void
911init_pll2(struct nvbios_init *init)
912{
913 struct nouveau_bios *bios = init->bios;
914 u32 reg = nv_ro32(bios, init->offset + 1);
915 u32 freq = nv_ro32(bios, init->offset + 5);
916
917 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
918 init->offset += 9;
919
920 init_prog_pll(init, reg, freq);
921}
922
923/**
924 * INIT_I2C_BYTE - opcode 0x4c
925 *
926 */
927static void
928init_i2c_byte(struct nvbios_init *init)
929{
930 struct nouveau_bios *bios = init->bios;
931 u8 index = nv_ro08(bios, init->offset + 1);
932 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
933 u8 count = nv_ro08(bios, init->offset + 3);
934
935 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
936 init->offset += 4;
937
938 while (count--) {
939 u8 reg = nv_ro08(bios, init->offset + 0);
940 u8 mask = nv_ro08(bios, init->offset + 1);
941 u8 data = nv_ro08(bios, init->offset + 2);
942 int val;
943
944 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
945 init->offset += 3;
946
947 val = init_rdi2cr(init, index, addr, reg);
948 if (val < 0)
949 continue;
950 init_wri2cr(init, index, addr, reg, (val & mask) | data);
951 }
952}
953
954/**
955 * INIT_ZM_I2C_BYTE - opcode 0x4d
956 *
957 */
958static void
959init_zm_i2c_byte(struct nvbios_init *init)
960{
961 struct nouveau_bios *bios = init->bios;
962 u8 index = nv_ro08(bios, init->offset + 1);
963 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
964 u8 count = nv_ro08(bios, init->offset + 3);
965
966 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
967 init->offset += 4;
968
969 while (count--) {
970 u8 reg = nv_ro08(bios, init->offset + 0);
971 u8 data = nv_ro08(bios, init->offset + 1);
972
973 trace("\t[0x%02x] = 0x%02x\n", reg, data);
974 init->offset += 2;
975
976 init_wri2cr(init, index, addr, reg, data);
977 }
978
979}
980
981/**
982 * INIT_ZM_I2C - opcode 0x4e
983 *
984 */
985static void
986init_zm_i2c(struct nvbios_init *init)
987{
988 struct nouveau_bios *bios = init->bios;
989 u8 index = nv_ro08(bios, init->offset + 1);
990 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
991 u8 count = nv_ro08(bios, init->offset + 3);
992 u8 data[256], i;
993
994 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
995 init->offset += 4;
996
997 for (i = 0; i < count; i++) {
998 data[i] = nv_ro08(bios, init->offset);
999 trace("\t0x%02x\n", data[i]);
1000 init->offset++;
1001 }
1002
1003 if (init_exec(init)) {
1004 struct nouveau_i2c_port *port = init_i2c(init, index);
1005 struct i2c_msg msg = {
1006 .addr = addr, .flags = 0, .len = count, .buf = data,
1007 };
1008 int ret;
1009
1010 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1011 warn("i2c wr failed, %d\n", ret);
1012 }
1013}
1014
1015/**
1016 * INIT_TMDS - opcode 0x4f
1017 *
1018 */
1019static void
1020init_tmds(struct nvbios_init *init)
1021{
1022 struct nouveau_bios *bios = init->bios;
1023 u8 tmds = nv_ro08(bios, init->offset + 1);
1024 u8 addr = nv_ro08(bios, init->offset + 2);
1025 u8 mask = nv_ro08(bios, init->offset + 3);
1026 u8 data = nv_ro08(bios, init->offset + 4);
1027 u32 reg = init_tmds_reg(init, tmds);
1028
1029 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1030 tmds, addr, mask, data);
1031 init->offset += 5;
1032
1033 if (reg == 0)
1034 return;
1035
1036 init_wr32(init, reg + 0, addr | 0x00010000);
1037 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1038 init_wr32(init, reg + 0, addr);
1039}
1040
1041/**
1042 * INIT_ZM_TMDS_GROUP - opcode 0x50
1043 *
1044 */
1045static void
1046init_zm_tmds_group(struct nvbios_init *init)
1047{
1048 struct nouveau_bios *bios = init->bios;
1049 u8 tmds = nv_ro08(bios, init->offset + 1);
1050 u8 count = nv_ro08(bios, init->offset + 2);
1051 u32 reg = init_tmds_reg(init, tmds);
1052
1053 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1054 init->offset += 3;
1055
1056 while (count--) {
1057 u8 addr = nv_ro08(bios, init->offset + 0);
1058 u8 data = nv_ro08(bios, init->offset + 1);
1059
1060 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1061 init->offset += 2;
1062
1063 init_wr32(init, reg + 4, data);
1064 init_wr32(init, reg + 0, addr);
1065 }
1066}
1067
1068/**
1069 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1070 *
1071 */
1072static void
1073init_cr_idx_adr_latch(struct nvbios_init *init)
1074{
1075 struct nouveau_bios *bios = init->bios;
1076 u8 addr0 = nv_ro08(bios, init->offset + 1);
1077 u8 addr1 = nv_ro08(bios, init->offset + 2);
1078 u8 base = nv_ro08(bios, init->offset + 3);
1079 u8 count = nv_ro08(bios, init->offset + 4);
1080 u8 save0;
1081
1082 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1083 init->offset += 5;
1084
1085 save0 = init_rdvgai(init, 0x03d4, addr0);
1086 while (count--) {
1087 u8 data = nv_ro08(bios, init->offset);
1088
1089 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1090 init->offset += 1;
1091
1092 init_wrvgai(init, 0x03d4, addr0, base++);
1093 init_wrvgai(init, 0x03d4, addr1, data);
1094 }
1095 init_wrvgai(init, 0x03d4, addr0, save0);
1096}
1097
1098/**
1099 * INIT_CR - opcode 0x52
1100 *
1101 */
1102static void
1103init_cr(struct nvbios_init *init)
1104{
1105 struct nouveau_bios *bios = init->bios;
1106 u8 addr = nv_ro08(bios, init->offset + 1);
1107 u8 mask = nv_ro08(bios, init->offset + 2);
1108 u8 data = nv_ro08(bios, init->offset + 3);
1109 u8 val;
1110
1111 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1112 init->offset += 4;
1113
1114 val = init_rdvgai(init, 0x03d4, addr) & mask;
1115 init_wrvgai(init, 0x03d4, addr, val | data);
1116}
1117
1118/**
1119 * INIT_ZM_CR - opcode 0x53
1120 *
1121 */
1122static void
1123init_zm_cr(struct nvbios_init *init)
1124{
1125 struct nouveau_bios *bios = init->bios;
1126 u8 addr = nv_ro08(bios, init->offset + 1);
1127 u8 data = nv_ro08(bios, init->offset + 2);
1128
1129 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1130 init->offset += 3;
1131
1132 init_wrvgai(init, 0x03d4, addr, data);
1133}
1134
1135/**
1136 * INIT_ZM_CR_GROUP - opcode 0x54
1137 *
1138 */
1139static void
1140init_zm_cr_group(struct nvbios_init *init)
1141{
1142 struct nouveau_bios *bios = init->bios;
1143 u8 count = nv_ro08(bios, init->offset + 1);
1144
1145 trace("ZM_CR_GROUP\n");
1146 init->offset += 2;
1147
1148 while (count--) {
1149 u8 addr = nv_ro08(bios, init->offset + 0);
1150 u8 data = nv_ro08(bios, init->offset + 1);
1151
1152 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1153 init->offset += 2;
1154
1155 init_wrvgai(init, 0x03d4, addr, data);
1156 }
1157}
1158
1159/**
1160 * INIT_CONDITION_TIME - opcode 0x56
1161 *
1162 */
1163static void
1164init_condition_time(struct nvbios_init *init)
1165{
1166 struct nouveau_bios *bios = init->bios;
1167 u8 cond = nv_ro08(bios, init->offset + 1);
1168 u8 retry = nv_ro08(bios, init->offset + 2);
1169 u8 wait = min((u16)retry * 50, 100);
1170
1171 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1172 init->offset += 3;
1173
1174 if (!init_exec(init))
1175 return;
1176
1177 while (wait--) {
1178 if (init_condition_met(init, cond))
1179 return;
1180 mdelay(20);
1181 }
1182
1183 init_exec_set(init, false);
1184}
1185
1186/**
1187 * INIT_LTIME - opcode 0x57
1188 *
1189 */
1190static void
1191init_ltime(struct nvbios_init *init)
1192{
1193 struct nouveau_bios *bios = init->bios;
1194 u16 msec = nv_ro16(bios, init->offset + 1);
1195
1196 trace("LTIME\t0x%04x\n", msec);
1197 init->offset += 3;
1198
1199 if (init_exec(init))
1200 mdelay(msec);
1201}
1202
1203/**
1204 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1205 *
1206 */
1207static void
1208init_zm_reg_sequence(struct nvbios_init *init)
1209{
1210 struct nouveau_bios *bios = init->bios;
1211 u32 base = nv_ro32(bios, init->offset + 1);
1212 u8 count = nv_ro08(bios, init->offset + 5);
1213
1214 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1215 init->offset += 6;
1216
1217 while (count--) {
1218 u32 data = nv_ro32(bios, init->offset);
1219
1220 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1221 init->offset += 4;
1222
1223 init_wr32(init, base, data);
1224 base += 4;
1225 }
1226}
1227
1228/**
1229 * INIT_SUB_DIRECT - opcode 0x5b
1230 *
1231 */
1232static void
1233init_sub_direct(struct nvbios_init *init)
1234{
1235 struct nouveau_bios *bios = init->bios;
1236 u16 addr = nv_ro16(bios, init->offset + 1);
1237 u16 save;
1238
1239 trace("SUB_DIRECT\t0x%04x\n", addr);
1240
1241 if (init_exec(init)) {
1242 save = init->offset;
1243 init->offset = addr;
1244 if (nvbios_exec(init)) {
1245 error("error parsing sub-table\n");
1246 return;
1247 }
1248 init->offset = save;
1249 }
1250
1251 init->offset += 3;
1252}
1253
1254/**
1255 * INIT_JUMP - opcode 0x5c
1256 *
1257 */
1258static void
1259init_jump(struct nvbios_init *init)
1260{
1261 struct nouveau_bios *bios = init->bios;
1262 u16 offset = nv_ro16(bios, init->offset + 1);
1263
1264 trace("JUMP\t0x%04x\n", offset);
1265 init->offset = offset;
1266}
1267
1268/**
1269 * INIT_I2C_IF - opcode 0x5e
1270 *
1271 */
1272static void
1273init_i2c_if(struct nvbios_init *init)
1274{
1275 struct nouveau_bios *bios = init->bios;
1276 u8 index = nv_ro08(bios, init->offset + 1);
1277 u8 addr = nv_ro08(bios, init->offset + 2);
1278 u8 reg = nv_ro08(bios, init->offset + 3);
1279 u8 mask = nv_ro08(bios, init->offset + 4);
1280 u8 data = nv_ro08(bios, init->offset + 5);
1281 u8 value;
1282
1283 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1284 index, addr, reg, mask, data);
1285 init->offset += 6;
1286 init_exec_force(init, true);
1287
1288 value = init_rdi2cr(init, index, addr, reg);
1289 if ((value & mask) != data)
1290 init_exec_set(init, false);
1291
1292 init_exec_force(init, false);
1293}
1294
1295/**
1296 * INIT_COPY_NV_REG - opcode 0x5f
1297 *
1298 */
1299static void
1300init_copy_nv_reg(struct nvbios_init *init)
1301{
1302 struct nouveau_bios *bios = init->bios;
1303 u32 sreg = nv_ro32(bios, init->offset + 1);
1304 u8 shift = nv_ro08(bios, init->offset + 5);
1305 u32 smask = nv_ro32(bios, init->offset + 6);
1306 u32 sxor = nv_ro32(bios, init->offset + 10);
1307 u32 dreg = nv_ro32(bios, init->offset + 14);
1308 u32 dmask = nv_ro32(bios, init->offset + 18);
1309 u32 data;
1310
1311 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1312 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1313 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1314 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1315 init->offset += 22;
1316
1317 data = init_shift(init_rd32(init, sreg), shift);
1318 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1319}
1320
1321/**
1322 * INIT_ZM_INDEX_IO - opcode 0x62
1323 *
1324 */
1325static void
1326init_zm_index_io(struct nvbios_init *init)
1327{
1328 struct nouveau_bios *bios = init->bios;
1329 u16 port = nv_ro16(bios, init->offset + 1);
1330 u8 index = nv_ro08(bios, init->offset + 3);
1331 u8 data = nv_ro08(bios, init->offset + 4);
1332
1333 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1334 init->offset += 5;
1335
1336 init_wrvgai(init, port, index, data);
1337}
1338
1339/**
1340 * INIT_COMPUTE_MEM - opcode 0x63
1341 *
1342 */
1343static void
1344init_compute_mem(struct nvbios_init *init)
1345{
1346 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1347
1348 trace("COMPUTE_MEM\n");
1349 init->offset += 1;
1350
1351 init_exec_force(init, true);
1352 if (init_exec(init) && devinit->meminit)
1353 devinit->meminit(devinit);
1354 init_exec_force(init, false);
1355}
1356
1357/**
1358 * INIT_RESET - opcode 0x65
1359 *
1360 */
1361static void
1362init_reset(struct nvbios_init *init)
1363{
1364 struct nouveau_bios *bios = init->bios;
1365 u32 reg = nv_ro32(bios, init->offset + 1);
1366 u32 data1 = nv_ro32(bios, init->offset + 5);
1367 u32 data2 = nv_ro32(bios, init->offset + 9);
1368 u32 savepci19;
1369
1370 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1371 init->offset += 13;
1372 init_exec_force(init, true);
1373
1374 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1375 init_wr32(init, reg, data1);
1376 udelay(10);
1377 init_wr32(init, reg, data2);
1378 init_wr32(init, 0x00184c, savepci19);
1379 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1380
1381 init_exec_force(init, false);
1382}
1383
1384/**
1385 * INIT_CONFIGURE_MEM - opcode 0x66
1386 *
1387 */
1388static u16
1389init_configure_mem_clk(struct nvbios_init *init)
1390{
1391 u16 mdata = bmp_mem_init_table(init->bios);
1392 if (mdata)
1393 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1394 return mdata;
1395}
1396
1397static void
1398init_configure_mem(struct nvbios_init *init)
1399{
1400 struct nouveau_bios *bios = init->bios;
1401 u16 mdata, sdata;
1402 u32 addr, data;
1403
1404 trace("CONFIGURE_MEM\n");
1405 init->offset += 1;
1406
1407 if (bios->version.major > 2) {
1408 init_done(init);
1409 return;
1410 }
1411 init_exec_force(init, true);
1412
1413 mdata = init_configure_mem_clk(init);
1414 sdata = bmp_sdr_seq_table(bios);
1415 if (nv_ro08(bios, mdata) & 0x01)
1416 sdata = bmp_ddr_seq_table(bios);
1417 mdata += 6; /* skip to data */
1418
1419 data = init_rdvgai(init, 0x03c4, 0x01);
1420 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1421
1422 while ((addr = nv_ro32(bios, sdata)) != 0xffffffff) {
1423 switch (addr) {
1424 case 0x10021c: /* CKE_NORMAL */
1425 case 0x1002d0: /* CMD_REFRESH */
1426 case 0x1002d4: /* CMD_PRECHARGE */
1427 data = 0x00000001;
1428 break;
1429 default:
1430 data = nv_ro32(bios, mdata);
1431 mdata += 4;
1432 if (data == 0xffffffff)
1433 continue;
1434 break;
1435 }
1436
1437 init_wr32(init, addr, data);
1438 }
1439
1440 init_exec_force(init, false);
1441}
1442
1443/**
1444 * INIT_CONFIGURE_CLK - opcode 0x67
1445 *
1446 */
1447static void
1448init_configure_clk(struct nvbios_init *init)
1449{
1450 struct nouveau_bios *bios = init->bios;
1451 u16 mdata, clock;
1452
1453 trace("CONFIGURE_CLK\n");
1454 init->offset += 1;
1455
1456 if (bios->version.major > 2) {
1457 init_done(init);
1458 return;
1459 }
1460 init_exec_force(init, true);
1461
1462 mdata = init_configure_mem_clk(init);
1463
1464 /* NVPLL */
1465 clock = nv_ro16(bios, mdata + 4) * 10;
1466 init_prog_pll(init, 0x680500, clock);
1467
1468 /* MPLL */
1469 clock = nv_ro16(bios, mdata + 2) * 10;
1470 if (nv_ro08(bios, mdata) & 0x01)
1471 clock *= 2;
1472 init_prog_pll(init, 0x680504, clock);
1473
1474 init_exec_force(init, false);
1475}
1476
1477/**
1478 * INIT_CONFIGURE_PREINIT - opcode 0x68
1479 *
1480 */
1481static void
1482init_configure_preinit(struct nvbios_init *init)
1483{
1484 struct nouveau_bios *bios = init->bios;
1485 u32 strap;
1486
1487 trace("CONFIGURE_PREINIT\n");
1488 init->offset += 1;
1489
1490 if (bios->version.major > 2) {
1491 init_done(init);
1492 return;
1493 }
1494 init_exec_force(init, true);
1495
1496 strap = init_rd32(init, 0x101000);
1497 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1498 init_wrvgai(init, 0x03d4, 0x3c, strap);
1499
1500 init_exec_force(init, false);
1501}
1502
1503/**
1504 * INIT_IO - opcode 0x69
1505 *
1506 */
1507static void
1508init_io(struct nvbios_init *init)
1509{
1510 struct nouveau_bios *bios = init->bios;
1511 u16 port = nv_ro16(bios, init->offset + 1);
1512 u8 mask = nv_ro16(bios, init->offset + 3);
1513 u8 data = nv_ro16(bios, init->offset + 4);
1514 u8 value;
1515
1516 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1517 init->offset += 5;
1518
1519 /* ummm.. yes.. should really figure out wtf this is and why it's
1520 * needed some day.. it's almost certainly wrong, but, it also
1521 * somehow makes things work...
1522 */
1523 if (nv_device(init->bios)->card_type >= NV_50 &&
1524 port == 0x03c3 && data == 0x01) {
1525 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1526 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1527 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1528 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1529 mdelay(10);
1530 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1531 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1532 init_wr32(init, 0x614100, 0x00800018);
1533 init_wr32(init, 0x614900, 0x00800018);
1534 mdelay(10);
1535 init_wr32(init, 0x614100, 0x10000018);
1536 init_wr32(init, 0x614900, 0x10000018);
cb75d97e
BS		 1537 }
1538
1539 value = init_rdport(init, port) & mask;
1540 init_wrport(init, port, data | value);
1541}
1542
1543/**
1544 * INIT_SUB - opcode 0x6b
1545 *
1546 */
1547static void
1548init_sub(struct nvbios_init *init)
1549{
1550 struct nouveau_bios *bios = init->bios;
1551 u8 index = nv_ro08(bios, init->offset + 1);
1552 u16 addr, save;
1553
1554 trace("SUB\t0x%02x\n", index);
1555
1556 addr = init_script(bios, index);
1557 if (addr && init_exec(init)) {
1558 save = init->offset;
1559 init->offset = addr;
1560 if (nvbios_exec(init)) {
1561 error("error parsing sub-table\n");
1562 return;
1563 }
1564 init->offset = save;
1565 }
1566
1567 init->offset += 2;
1568}
1569
1570/**
1571 * INIT_RAM_CONDITION - opcode 0x6d
1572 *
1573 */
1574static void
1575init_ram_condition(struct nvbios_init *init)
1576{
1577 struct nouveau_bios *bios = init->bios;
1578 u8 mask = nv_ro08(bios, init->offset + 1);
1579 u8 value = nv_ro08(bios, init->offset + 2);
1580
1581 trace("RAM_CONDITION\t"
1582 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1583 init->offset += 3;
1584
1585 if ((init_rd32(init, 0x100000) & mask) != value)
1586 init_exec_set(init, false);
1587}
1588
1589/**
1590 * INIT_NV_REG - opcode 0x6e
1591 *
1592 */
1593static void
1594init_nv_reg(struct nvbios_init *init)
1595{
1596 struct nouveau_bios *bios = init->bios;
1597 u32 reg = nv_ro32(bios, init->offset + 1);
1598 u32 mask = nv_ro32(bios, init->offset + 5);
1599 u32 data = nv_ro32(bios, init->offset + 9);
1600
1601 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1602 init->offset += 13;
1603
1604 init_mask(init, reg, ~mask, data);
1605}
1606
1607/**
1608 * INIT_MACRO - opcode 0x6f
1609 *
1610 */
1611static void
1612init_macro(struct nvbios_init *init)
1613{
1614 struct nouveau_bios *bios = init->bios;
1615 u8 macro = nv_ro08(bios, init->offset + 1);
1616 u16 table;
1617
1618 trace("MACRO\t0x%02x\n", macro);
1619
1620 table = init_macro_table(init);
1621 if (table) {
1622 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1623 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1624 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1625 init_wr32(init, addr, data);
1626 }
1627
1628 init->offset += 2;
1629}
1630
1631/**
1632 * INIT_RESUME - opcode 0x72
1633 *
1634 */
1635static void
1636init_resume(struct nvbios_init *init)
1637{
1638 trace("RESUME\n");
1639 init->offset += 1;
1640 init_exec_set(init, true);
1641}
1642
1643/**
1644 * INIT_TIME - opcode 0x74
1645 *
1646 */
1647static void
1648init_time(struct nvbios_init *init)
1649{
1650 struct nouveau_bios *bios = init->bios;
1651 u16 usec = nv_ro16(bios, init->offset + 1);
1652
1653 trace("TIME\t0x%04x\n", usec);
1654 init->offset += 3;
1655
1656 if (init_exec(init)) {
1657 if (usec < 1000)
1658 udelay(usec);
1659 else
1660 mdelay((usec + 900) / 1000);
1661 }
1662}
1663
1664/**
1665 * INIT_CONDITION - opcode 0x75
1666 *
1667 */
1668static void
1669init_condition(struct nvbios_init *init)
1670{
1671 struct nouveau_bios *bios = init->bios;
1672 u8 cond = nv_ro08(bios, init->offset + 1);
1673
1674 trace("CONDITION\t0x%02x\n", cond);
1675 init->offset += 2;
1676
1677 if (!init_condition_met(init, cond))
1678 init_exec_set(init, false);
1679}
1680
1681/**
1682 * INIT_IO_CONDITION - opcode 0x76
1683 *
1684 */
1685static void
1686init_io_condition(struct nvbios_init *init)
1687{
1688 struct nouveau_bios *bios = init->bios;
1689 u8 cond = nv_ro08(bios, init->offset + 1);
1690
1691 trace("IO_CONDITION\t0x%02x\n", cond);
1692 init->offset += 2;
1693
1694 if (!init_io_condition_met(init, cond))
1695 init_exec_set(init, false);
1696}
1697
1698/**
1699 * INIT_INDEX_IO - opcode 0x78
1700 *
1701 */
1702static void
1703init_index_io(struct nvbios_init *init)
1704{
1705 struct nouveau_bios *bios = init->bios;
1706 u16 port = nv_ro16(bios, init->offset + 1);
1707 u8 index = nv_ro16(bios, init->offset + 3);
1708 u8 mask = nv_ro08(bios, init->offset + 4);
1709 u8 data = nv_ro08(bios, init->offset + 5);
1710 u8 value;
1711
1712 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1713 port, index, mask, data);
1714 init->offset += 6;
1715
1716 value = init_rdvgai(init, port, index) & mask;
1717 init_wrvgai(init, port, index, data | value);
1718}
1719
1720/**
1721 * INIT_PLL - opcode 0x79
1722 *
1723 */
1724static void
1725init_pll(struct nvbios_init *init)
1726{
1727 struct nouveau_bios *bios = init->bios;
1728 u32 reg = nv_ro32(bios, init->offset + 1);
1729 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1730
1731 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1732 init->offset += 7;
1733
1734 init_prog_pll(init, reg, freq);
1735}
1736
1737/**
1738 * INIT_ZM_REG - opcode 0x7a
1739 *
1740 */
1741static void
1742init_zm_reg(struct nvbios_init *init)
1743{
1744 struct nouveau_bios *bios = init->bios;
1745 u32 addr = nv_ro32(bios, init->offset + 1);
1746 u32 data = nv_ro32(bios, init->offset + 5);
1747
1748 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1749 init->offset += 9;
1750
1751 if (addr == 0x000200)
1752 data |= 0x00000001;
1753
1754 init_wr32(init, addr, data);
1755}
1756
1757/**
1758 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1759 *
1760 */
1761static void
1762init_ram_restrict_pll(struct nvbios_init *init)
1763{
1764 struct nouveau_bios *bios = init->bios;
1765 u8 type = nv_ro08(bios, init->offset + 1);
1766 u8 count = init_ram_restrict_group_count(init);
1767 u8 strap = init_ram_restrict(init);
1768 u8 cconf;
1769
1770 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1771 init->offset += 2;
1772
1773 for (cconf = 0; cconf < count; cconf++) {
1774 u32 freq = nv_ro32(bios, init->offset);
1775
1776 if (cconf == strap) {
1777 trace("%dkHz *\n", freq);
1778 init_prog_pll(init, type, freq);
1779 } else {
1780 trace("%dkHz\n", freq);
1781 }
1782
1783 init->offset += 4;
1784 }
1785}
1786
1787/**
1788 * INIT_GPIO - opcode 0x8e
1789 *
1790 */
1791static void
1792init_gpio(struct nvbios_init *init)
1793{
1794 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1795
1796 trace("GPIO\n");
1797 init->offset += 1;
1798
1799 if (init_exec(init) && gpio && gpio->reset)
1ed73166 1800 gpio->reset(gpio, DCB_GPIO_UNUSED);
cb75d97e
BS		 1801}
1802
1803/**
1804 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1805 *
1806 */
1807static void
1808init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1809{
1810 struct nouveau_bios *bios = init->bios;
1811 u32 addr = nv_ro32(bios, init->offset + 1);
1812 u8 incr = nv_ro08(bios, init->offset + 5);
1813 u8 num = nv_ro08(bios, init->offset + 6);
1814 u8 count = init_ram_restrict_group_count(init);
1815 u8 index = init_ram_restrict(init);
1816 u8 i, j;
1817
1818 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
1819 "R[%08x] 0x%02x 0x%02x\n", addr, incr, num);
1820 init->offset += 7;
1821
1822 for (i = 0; i < num; i++) {
1823 trace("\tR[0x%06x] = {\n", addr);
1824 for (j = 0; j < count; j++) {
1825 u32 data = nv_ro32(bios, init->offset);
1826
1827 if (j == index) {
1828 trace("\t\t0x%08x *\n", data);
1829 init_wr32(init, addr, data);
1830 } else {
1831 trace("\t\t0x%08x\n", data);
1832 }
1833
1834 init->offset += 4;
1835 }
1836 trace("\t}\n");
1837 addr += incr;
1838 }
1839}
1840
1841/**
1842 * INIT_COPY_ZM_REG - opcode 0x90
1843 *
1844 */
1845static void
1846init_copy_zm_reg(struct nvbios_init *init)
1847{
1848 struct nouveau_bios *bios = init->bios;
1849 u32 sreg = nv_ro32(bios, init->offset + 1);
1850 u32 dreg = nv_ro32(bios, init->offset + 5);
1851
1852 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", sreg, dreg);
1853 init->offset += 9;
1854
1855 init_wr32(init, dreg, init_rd32(init, sreg));
1856}
1857
1858/**
1859 * INIT_ZM_REG_GROUP - opcode 0x91
1860 *
1861 */
1862static void
1863init_zm_reg_group(struct nvbios_init *init)
1864{
1865 struct nouveau_bios *bios = init->bios;
1866 u32 addr = nv_ro32(bios, init->offset + 1);
1867 u8 count = nv_ro08(bios, init->offset + 5);
1868
1869 trace("ZM_REG_GROUP\tR[0x%06x] =\n");
1870 init->offset += 6;
1871
1872 while (count--) {
1873 u32 data = nv_ro32(bios, init->offset);
1874 trace("\t0x%08x\n", data);
1875 init_wr32(init, addr, data);
1876 init->offset += 4;
1877 }
1878}
1879
1880/**
1881 * INIT_XLAT - opcode 0x96
1882 *
1883 */
1884static void
1885init_xlat(struct nvbios_init *init)
1886{
1887 struct nouveau_bios *bios = init->bios;
1888 u32 saddr = nv_ro32(bios, init->offset + 1);
1889 u8 sshift = nv_ro08(bios, init->offset + 5);
1890 u8 smask = nv_ro08(bios, init->offset + 6);
1891 u8 index = nv_ro08(bios, init->offset + 7);
1892 u32 daddr = nv_ro32(bios, init->offset + 8);
1893 u32 dmask = nv_ro32(bios, init->offset + 12);
1894 u8 shift = nv_ro08(bios, init->offset + 16);
1895 u32 data;
1896
1897 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1898 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1899 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1900 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1901 init->offset += 17;
1902
1903 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1904 data = init_xlat_(init, index, data) << shift;
1905 init_mask(init, daddr, ~dmask, data);
1906}
1907
1908/**
1909 * INIT_ZM_MASK_ADD - opcode 0x97
1910 *
1911 */
1912static void
1913init_zm_mask_add(struct nvbios_init *init)
1914{
1915 struct nouveau_bios *bios = init->bios;
1916 u32 addr = nv_ro32(bios, init->offset + 1);
1917 u32 mask = nv_ro32(bios, init->offset + 5);
1918 u32 add = nv_ro32(bios, init->offset + 9);
1919 u32 data;
1920
1921 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1922 init->offset += 13;
1923
1924 data = init_rd32(init, addr) & mask;
1925 data |= ((data + add) & ~mask);
1926 init_wr32(init, addr, data);
1927}
1928
1929/**
1930 * INIT_AUXCH - opcode 0x98
1931 *
1932 */
1933static void
1934init_auxch(struct nvbios_init *init)
1935{
1936 struct nouveau_bios *bios = init->bios;
1937 u32 addr = nv_ro32(bios, init->offset + 1);
1938 u8 count = nv_ro08(bios, init->offset + 5);
1939
1940 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1941 init->offset += 6;
1942
1943 while (count--) {
1944 u8 mask = nv_ro08(bios, init->offset + 0);
1945 u8 data = nv_ro08(bios, init->offset + 1);
1946 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1947 mask = init_rdauxr(init, addr) & mask;
1948 init_wrauxr(init, addr, mask | data);
1949 init->offset += 2;
1950 }
1951}
1952
1953/**
1954 * INIT_AUXCH - opcode 0x99
1955 *
1956 */
1957static void
1958init_zm_auxch(struct nvbios_init *init)
1959{
1960 struct nouveau_bios *bios = init->bios;
1961 u32 addr = nv_ro32(bios, init->offset + 1);
1962 u8 count = nv_ro08(bios, init->offset + 5);
1963
1964 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1965 init->offset += 6;
1966
1967 while (count--) {
1968 u8 data = nv_ro08(bios, init->offset + 0);
1969 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1970 init_wrauxr(init, addr, data);
1971 init->offset += 1;
1972 }
1973}
1974
1975/**
1976 * INIT_I2C_LONG_IF - opcode 0x9a
1977 *
1978 */
1979static void
1980init_i2c_long_if(struct nvbios_init *init)
1981{
1982 struct nouveau_bios *bios = init->bios;
1983 u8 index = nv_ro08(bios, init->offset + 1);
1984 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1985 u8 reglo = nv_ro08(bios, init->offset + 3);
1986 u8 reghi = nv_ro08(bios, init->offset + 4);
1987 u8 mask = nv_ro08(bios, init->offset + 5);
1988 u8 data = nv_ro08(bios, init->offset + 6);
1989 struct nouveau_i2c_port *port;
1990
1991 trace("I2C_LONG_IF\t"
1992 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
1993 index, addr, reglo, reghi, mask, data);
1994 init->offset += 7;
1995
1996 port = init_i2c(init, index);
1997 if (port) {
1998 u8 i[2] = { reghi, reglo };
1999 u8 o[1] = {};
2000 struct i2c_msg msg[] = {
2001 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2002 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2003 };
2004 int ret;
2005
2006 ret = i2c_transfer(&port->adapter, msg, 2);
2007 if (ret == 2 && ((o[0] & mask) == data))
2008 return;
2009 }
2010
2011 init_exec_set(init, false);
2012}
2013
1ed73166
BS		 2014/**
2015 * INIT_GPIO_NE - opcode 0xa9
2016 *
2017 */
2018static void
2019init_gpio_ne(struct nvbios_init *init)
2020{
2021 struct nouveau_bios *bios = init->bios;
2022 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2023 struct dcb_gpio_func func;
2024 u8 count = nv_ro08(bios, init->offset + 1);
2025 u8 idx = 0, ver, len;
2026 u16 data, i;
2027
2028 trace("GPIO_NE\t");
2029 init->offset += 2;
2030
2031 for (i = init->offset; i < init->offset + count; i++)
2032 cont("0x%02x ", nv_ro08(bios, i));
2033 cont("\n");
2034
2035 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2036 if (func.func != DCB_GPIO_UNUSED) {
2037 for (i = init->offset; i < init->offset + count; i++) {
2038 if (func.func == nv_ro08(bios, i))
2039 break;
2040 }
2041
2042 trace("\tFUNC[0x%02x]", func.func);
2043 if (i == (init->offset + count)) {
2044 cont(" *");
2045 if (init_exec(init) && gpio && gpio->reset)
2046 gpio->reset(gpio, func.func);
2047 }
2048 cont("\n");
2049 }
2050 }
2051
2052 init->offset += count;
2053}
2054
cb75d97e
BS		 2055static struct nvbios_init_opcode {
2056 void (*exec)(struct nvbios_init *);
2057} init_opcode[] = {
2058 [0x32] = { init_io_restrict_prog },
2059 [0x33] = { init_repeat },
2060 [0x34] = { init_io_restrict_pll },
2061 [0x36] = { init_end_repeat },
2062 [0x37] = { init_copy },
2063 [0x38] = { init_not },
2064 [0x39] = { init_io_flag_condition },
2065 [0x3a] = { init_dp_condition },
2066 [0x3b] = { init_io_mask_or },
2067 [0x3c] = { init_io_or },
2068 [0x49] = { init_idx_addr_latched },
2069 [0x4a] = { init_io_restrict_pll2 },
2070 [0x4b] = { init_pll2 },
2071 [0x4c] = { init_i2c_byte },
2072 [0x4d] = { init_zm_i2c_byte },
2073 [0x4e] = { init_zm_i2c },
2074 [0x4f] = { init_tmds },
2075 [0x50] = { init_zm_tmds_group },
2076 [0x51] = { init_cr_idx_adr_latch },
2077 [0x52] = { init_cr },
2078 [0x53] = { init_zm_cr },
2079 [0x54] = { init_zm_cr_group },
2080 [0x56] = { init_condition_time },
2081 [0x57] = { init_ltime },
2082 [0x58] = { init_zm_reg_sequence },
2083 [0x5b] = { init_sub_direct },
2084 [0x5c] = { init_jump },
2085 [0x5e] = { init_i2c_if },
2086 [0x5f] = { init_copy_nv_reg },
2087 [0x62] = { init_zm_index_io },
2088 [0x63] = { init_compute_mem },
2089 [0x65] = { init_reset },
2090 [0x66] = { init_configure_mem },
2091 [0x67] = { init_configure_clk },
2092 [0x68] = { init_configure_preinit },
2093 [0x69] = { init_io },
2094 [0x6b] = { init_sub },
2095 [0x6d] = { init_ram_condition },
2096 [0x6e] = { init_nv_reg },
2097 [0x6f] = { init_macro },
2098 [0x71] = { init_done },
2099 [0x72] = { init_resume },
2100 [0x74] = { init_time },
2101 [0x75] = { init_condition },
2102 [0x76] = { init_io_condition },
2103 [0x78] = { init_index_io },
2104 [0x79] = { init_pll },
2105 [0x7a] = { init_zm_reg },
2106 [0x87] = { init_ram_restrict_pll },
2107 [0x8c] = { init_reserved },
2108 [0x8d] = { init_reserved },
2109 [0x8e] = { init_gpio },
2110 [0x8f] = { init_ram_restrict_zm_reg_group },
2111 [0x90] = { init_copy_zm_reg },
2112 [0x91] = { init_zm_reg_group },
2113 [0x92] = { init_reserved },
2114 [0x96] = { init_xlat },
2115 [0x97] = { init_zm_mask_add },
2116 [0x98] = { init_auxch },
2117 [0x99] = { init_zm_auxch },
2118 [0x9a] = { init_i2c_long_if },
1ed73166 2119 [0xa9] = { init_gpio_ne },
cb75d97e
BS		 2120};
2121
2122#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2123
2124int
2125nvbios_exec(struct nvbios_init *init)
2126{
2127 init->nested++;
2128 while (init->offset) {
2129 u8 opcode = nv_ro08(init->bios, init->offset);
2130 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2131 error("unknown opcode 0x%02x\n", opcode);
2132 return -EINVAL;
2133 }
2134
2135 init_opcode[opcode].exec(init);
2136 }
2137 init->nested--;
2138 return 0;
2139}
2140
2141int
2142nvbios_init(struct nouveau_subdev *subdev, bool execute)
2143{
2144 struct nouveau_bios *bios = nouveau_bios(subdev);
2145 int ret = 0;
2146 int i = -1;
2147 u16 data;
2148
2149 if (execute)
2150 nv_info(bios, "running init tables\n");
2151 while (!ret && (data = (init_script(bios, ++i)))) {
2152 struct nvbios_init init = {
2153 .subdev = subdev,
2154 .bios = bios,
2155 .offset = data,
2156 .outp = NULL,
2157 .crtc = -1,
2158 .execute = execute ? 1 : 0,
2159 };
2160
2161 ret = nvbios_exec(&init);
2162 }
2163
2164 /* the vbios parser will run this right after the normal init
2165 * tables, whereas the binary driver appears to run it later.
2166 */
2167 if (!ret && (data = init_unknown_script(bios))) {
2168 struct nvbios_init init = {
2169 .subdev = subdev,
2170 .bios = bios,
2171 .offset = data,
2172 .outp = NULL,
2173 .crtc = -1,
2174 .execute = execute ? 1 : 0,
2175 };
2176
2177 ret = nvbios_exec(&init);
2178 }
2179
2180 return 0;
2181}
Linux 6.x block layer and io_uring tree(s)