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drm/nouveau/disp: nothing to see here
[linux-2.6-block.git] / drivers / gpu / drm / nouveau / core / subdev / bios / init.c
CommitLineData
cb75d97e
BS		 1#include <core/engine.h>
2#include <core/device.h>
3
4#include <subdev/bios.h>
cb75d97e
BS		 5#include <subdev/bios/bmp.h>
6#include <subdev/bios/bit.h>
1ed73166 7#include <subdev/bios/conn.h>
cb75d97e
BS		 8#include <subdev/bios/dcb.h>
9#include <subdev/bios/dp.h>
1ed73166 10#include <subdev/bios/gpio.h>
cb75d97e 11#include <subdev/bios/init.h>
0a0dc8f5 12#include <subdev/bios/ramcfg.h>
cb75d97e 13#include <subdev/devinit.h>
cb75d97e
BS		 14#include <subdev/i2c.h>
15#include <subdev/vga.h>
16#include <subdev/gpio.h>
17
18#define bioslog(lvl, fmt, args...) do { \
19 nv_printk(init->bios, lvl, "0x%04x[%c]: "fmt, init->offset, \
20 init_exec(init) ? '0' + (init->nested - 1) : ' ', ##args); \
21} while(0)
22#define cont(fmt, args...) do { \
23 if (nv_subdev(init->bios)->debug >= NV_DBG_TRACE) \
24 printk(fmt, ##args); \
25} while(0)
26#define trace(fmt, args...) bioslog(TRACE, fmt, ##args)
27#define warn(fmt, args...) bioslog(WARN, fmt, ##args)
28#define error(fmt, args...) bioslog(ERROR, fmt, ##args)
29
30/******************************************************************************
31 * init parser control flow helpers
32 *****************************************************************************/
33
34static inline bool
35init_exec(struct nvbios_init *init)
36{
37 return (init->execute == 1) || ((init->execute & 5) == 5);
38}
39
40static inline void
41init_exec_set(struct nvbios_init *init, bool exec)
42{
43 if (exec) init->execute &= 0xfd;
44 else init->execute |= 0x02;
45}
46
47static inline void
48init_exec_inv(struct nvbios_init *init)
49{
50 init->execute ^= 0x02;
51}
52
53static inline void
54init_exec_force(struct nvbios_init *init, bool exec)
55{
56 if (exec) init->execute |= 0x04;
57 else init->execute &= 0xfb;
58}
59
60/******************************************************************************
61 * init parser wrappers for normal register/i2c/whatever accessors
62 *****************************************************************************/
63
64static inline int
65init_or(struct nvbios_init *init)
66{
28ec70f7
BS		 67 if (init_exec(init)) {
68 if (init->outp)
69 return ffs(init->outp->or) - 1;
70 error("script needs OR!!\n");
71 }
cb75d97e
BS		 72 return 0;
73}
74
75static inline int
76init_link(struct nvbios_init *init)
77{
28ec70f7
BS		 78 if (init_exec(init)) {
79 if (init->outp)
80 return !(init->outp->sorconf.link & 1);
81 error("script needs OR link\n");
82 }
cb75d97e
BS		 83 return 0;
84}
85
86static inline int
87init_crtc(struct nvbios_init *init)
88{
28ec70f7
BS		 89 if (init_exec(init)) {
90 if (init->crtc >= 0)
91 return init->crtc;
92 error("script needs crtc\n");
93 }
cb75d97e
BS		 94 return 0;
95}
96
97static u8
98init_conn(struct nvbios_init *init)
99{
100 struct nouveau_bios *bios = init->bios;
28ec70f7
BS		 101 u8 ver, len;
102 u16 conn;
cb75d97e 103
28ec70f7
BS		 104 if (init_exec(init)) {
105 if (init->outp) {
106 conn = init->outp->connector;
107 conn = dcb_conn(bios, conn, &ver, &len);
108 if (conn)
109 return nv_ro08(bios, conn);
110 }
111
112 error("script needs connector type\n");
cb75d97e
BS		 113 }
114
28ec70f7 115 return 0xff;
cb75d97e
BS		 116}
117
118static inline u32
119init_nvreg(struct nvbios_init *init, u32 reg)
120{
3219adc2
BS		 121 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
122
cb75d97e
BS		 123 /* C51 (at least) sometimes has the lower bits set which the VBIOS
124 * interprets to mean that access needs to go through certain IO
125 * ports instead. The NVIDIA binary driver has been seen to access
126 * these through the NV register address, so lets assume we can
127 * do the same
128 */
129 reg &= ~0x00000003;
130
131 /* GF8+ display scripts need register addresses mangled a bit to
132 * select a specific CRTC/OR
133 */
134 if (nv_device(init->bios)->card_type >= NV_50) {
135 if (reg & 0x80000000) {
136 reg += init_crtc(init) * 0x800;
137 reg &= ~0x80000000;
138 }
139
140 if (reg & 0x40000000) {
141 reg += init_or(init) * 0x800;
142 reg &= ~0x40000000;
143 if (reg & 0x20000000) {
144 reg += init_link(init) * 0x80;
145 reg &= ~0x20000000;
146 }
147 }
148 }
149
150 if (reg & ~0x00fffffc)
151 warn("unknown bits in register 0x%08x\n", reg);
3219adc2
BS		 152
153 if (devinit->mmio)
154 reg = devinit->mmio(devinit, reg);
cb75d97e
BS		 155 return reg;
156}
157
158static u32
159init_rd32(struct nvbios_init *init, u32 reg)
160{
161 reg = init_nvreg(init, reg);
3219adc2 162 if (reg != ~0 && init_exec(init))
cb75d97e
BS		 163 return nv_rd32(init->subdev, reg);
164 return 0x00000000;
165}
166
167static void
168init_wr32(struct nvbios_init *init, u32 reg, u32 val)
169{
170 reg = init_nvreg(init, reg);
3219adc2 171 if (reg != ~0 && init_exec(init))
cb75d97e
BS		 172 nv_wr32(init->subdev, reg, val);
173}
174
175static u32
176init_mask(struct nvbios_init *init, u32 reg, u32 mask, u32 val)
177{
178 reg = init_nvreg(init, reg);
3219adc2 179 if (reg != ~0 && init_exec(init)) {
cb75d97e
BS		 180 u32 tmp = nv_rd32(init->subdev, reg);
181 nv_wr32(init->subdev, reg, (tmp & ~mask) | val);
182 return tmp;
183 }
184 return 0x00000000;
185}
186
187static u8
188init_rdport(struct nvbios_init *init, u16 port)
189{
190 if (init_exec(init))
191 return nv_rdport(init->subdev, init->crtc, port);
192 return 0x00;
193}
194
195static void
196init_wrport(struct nvbios_init *init, u16 port, u8 value)
197{
198 if (init_exec(init))
199 nv_wrport(init->subdev, init->crtc, port, value);
200}
201
202static u8
203init_rdvgai(struct nvbios_init *init, u16 port, u8 index)
204{
205 struct nouveau_subdev *subdev = init->subdev;
206 if (init_exec(init)) {
207 int head = init->crtc < 0 ? 0 : init->crtc;
208 return nv_rdvgai(subdev, head, port, index);
209 }
210 return 0x00;
211}
212
213static void
214init_wrvgai(struct nvbios_init *init, u16 port, u8 index, u8 value)
215{
216 /* force head 0 for updates to cr44, it only exists on first head */
217 if (nv_device(init->subdev)->card_type < NV_50) {
218 if (port == 0x03d4 && index == 0x44)
219 init->crtc = 0;
220 }
221
222 if (init_exec(init)) {
223 int head = init->crtc < 0 ? 0 : init->crtc;
224 nv_wrvgai(init->subdev, head, port, index, value);
225 }
226
227 /* select head 1 if cr44 write selected it */
228 if (nv_device(init->subdev)->card_type < NV_50) {
229 if (port == 0x03d4 && index == 0x44 && value == 3)
230 init->crtc = 1;
231 }
232}
233
234static struct nouveau_i2c_port *
235init_i2c(struct nvbios_init *init, int index)
236{
237 struct nouveau_i2c *i2c = nouveau_i2c(init->bios);
238
239 if (index == 0xff) {
240 index = NV_I2C_DEFAULT(0);
241 if (init->outp && init->outp->i2c_upper_default)
242 index = NV_I2C_DEFAULT(1);
243 } else
244 if (index < 0) {
245 if (!init->outp) {
28ec70f7
BS		 246 if (init_exec(init))
247 error("script needs output for i2c\n");
cb75d97e
BS		 248 return NULL;
249 }
250
476e84e1
BS		 251 if (index == -2 && init->outp->location) {
252 index = NV_I2C_TYPE_EXTAUX(init->outp->extdev);
253 return i2c->find_type(i2c, index);
254 }
255
cb75d97e
BS		 256 index = init->outp->i2c_index;
257 }
258
259 return i2c->find(i2c, index);
260}
261
262static int
263init_rdi2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg)
264{
265 struct nouveau_i2c_port *port = init_i2c(init, index);
266 if (port && init_exec(init))
267 return nv_rdi2cr(port, addr, reg);
268 return -ENODEV;
269}
270
271static int
272init_wri2cr(struct nvbios_init *init, u8 index, u8 addr, u8 reg, u8 val)
273{
274 struct nouveau_i2c_port *port = init_i2c(init, index);
275 if (port && init_exec(init))
276 return nv_wri2cr(port, addr, reg, val);
277 return -ENODEV;
278}
279
280static int
281init_rdauxr(struct nvbios_init *init, u32 addr)
282{
476e84e1 283 struct nouveau_i2c_port *port = init_i2c(init, -2);
cb75d97e
BS		 284 u8 data;
285
286 if (port && init_exec(init)) {
287 int ret = nv_rdaux(port, addr, &data, 1);
288 if (ret)
289 return ret;
290 return data;
291 }
292
293 return -ENODEV;
294}
295
296static int
297init_wrauxr(struct nvbios_init *init, u32 addr, u8 data)
298{
476e84e1 299 struct nouveau_i2c_port *port = init_i2c(init, -2);
cb75d97e
BS		 300 if (port && init_exec(init))
301 return nv_wraux(port, addr, &data, 1);
302 return -ENODEV;
303}
304
305static void
306init_prog_pll(struct nvbios_init *init, u32 id, u32 freq)
307{
88524bc0
BS		 308 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
309 if (devinit->pll_set && init_exec(init)) {
310 int ret = devinit->pll_set(devinit, id, freq);
cb75d97e
BS		 311 if (ret)
312 warn("failed to prog pll 0x%08x to %dkHz\n", id, freq);
313 }
314}
315
316/******************************************************************************
317 * parsing of bios structures that are required to execute init tables
318 *****************************************************************************/
319
320static u16
321init_table(struct nouveau_bios *bios, u16 *len)
322{
323 struct bit_entry bit_I;
324
325 if (!bit_entry(bios, 'I', &bit_I)) {
326 *len = bit_I.length;
327 return bit_I.offset;
328 }
329
330 if (bmp_version(bios) >= 0x0510) {
331 *len = 14;
332 return bios->bmp_offset + 75;
333 }
334
335 return 0x0000;
336}
337
338static u16
339init_table_(struct nvbios_init *init, u16 offset, const char *name)
340{
341 struct nouveau_bios *bios = init->bios;
342 u16 len, data = init_table(bios, &len);
343 if (data) {
344 if (len >= offset + 2) {
345 data = nv_ro16(bios, data + offset);
346 if (data)
347 return data;
348
349 warn("%s pointer invalid\n", name);
350 return 0x0000;
351 }
352
353 warn("init data too short for %s pointer", name);
354 return 0x0000;
355 }
356
357 warn("init data not found\n");
358 return 0x0000;
359}
360
361#define init_script_table(b) init_table_((b), 0x00, "script table")
362#define init_macro_index_table(b) init_table_((b), 0x02, "macro index table")
363#define init_macro_table(b) init_table_((b), 0x04, "macro table")
364#define init_condition_table(b) init_table_((b), 0x06, "condition table")
365#define init_io_condition_table(b) init_table_((b), 0x08, "io condition table")
366#define init_io_flag_condition_table(b) init_table_((b), 0x0a, "io flag conditon table")
367#define init_function_table(b) init_table_((b), 0x0c, "function table")
368#define init_xlat_table(b) init_table_((b), 0x10, "xlat table");
369
370static u16
371init_script(struct nouveau_bios *bios, int index)
372{
373 struct nvbios_init init = { .bios = bios };
5d2f4767 374 u16 bmp_ver = bmp_version(bios), data;
cb75d97e 375
5d2f4767
IM		 376 if (bmp_ver && bmp_ver < 0x0510) {
377 if (index > 1 || bmp_ver < 0x0100)
cb75d97e
BS		 378 return 0x0000;
379
5d2f4767 380 data = bios->bmp_offset + (bmp_ver < 0x0200 ? 14 : 18);
cb75d97e
BS		 381 return nv_ro16(bios, data + (index * 2));
382 }
383
384 data = init_script_table(&init);
385 if (data)
386 return nv_ro16(bios, data + (index * 2));
387
388 return 0x0000;
389}
390
391static u16
392init_unknown_script(struct nouveau_bios *bios)
393{
394 u16 len, data = init_table(bios, &len);
395 if (data && len >= 16)
396 return nv_ro16(bios, data + 14);
397 return 0x0000;
398}
399
cb75d97e
BS		 400static u8
401init_ram_restrict_group_count(struct nvbios_init *init)
402{
0a0dc8f5 403 return nvbios_ramcfg_count(init->bios);
cb75d97e
BS		 404}
405
5ddf4d4a 406static u8
0a0dc8f5 407init_ram_restrict(struct nvbios_init *init)
5ddf4d4a
BS		 408{
409 /* This appears to be the behaviour of the VBIOS parser, and *is*
410 * important to cache the NV_PEXTDEV_BOOT0 on later chipsets to
411 * avoid fucking up the memory controller (somehow) by reading it
412 * on every INIT_RAM_RESTRICT_ZM_GROUP opcode.
413 *
414 * Preserving the non-caching behaviour on earlier chipsets just
415 * in case *not* re-reading the strap causes similar breakage.
416 */
417 if (!init->ramcfg || init->bios->version.major < 0x70)
0a8649f1 418 init->ramcfg = 0x80000000 | nvbios_ramcfg_index(init->subdev);
0a0dc8f5 419 return (init->ramcfg & 0x7fffffff);
cb75d97e
BS		 420}
421
422static u8
423init_xlat_(struct nvbios_init *init, u8 index, u8 offset)
424{
425 struct nouveau_bios *bios = init->bios;
426 u16 table = init_xlat_table(init);
427 if (table) {
428 u16 data = nv_ro16(bios, table + (index * 2));
429 if (data)
430 return nv_ro08(bios, data + offset);
431 warn("xlat table pointer %d invalid\n", index);
432 }
433 return 0x00;
434}
435
436/******************************************************************************
437 * utility functions used by various init opcode handlers
438 *****************************************************************************/
439
440static bool
441init_condition_met(struct nvbios_init *init, u8 cond)
442{
443 struct nouveau_bios *bios = init->bios;
444 u16 table = init_condition_table(init);
445 if (table) {
446 u32 reg = nv_ro32(bios, table + (cond * 12) + 0);
447 u32 msk = nv_ro32(bios, table + (cond * 12) + 4);
448 u32 val = nv_ro32(bios, table + (cond * 12) + 8);
449 trace("\t[0x%02x] (R[0x%06x] & 0x%08x) == 0x%08x\n",
450 cond, reg, msk, val);
451 return (init_rd32(init, reg) & msk) == val;
452 }
453 return false;
454}
455
456static bool
457init_io_condition_met(struct nvbios_init *init, u8 cond)
458{
459 struct nouveau_bios *bios = init->bios;
460 u16 table = init_io_condition_table(init);
461 if (table) {
462 u16 port = nv_ro16(bios, table + (cond * 5) + 0);
463 u8 index = nv_ro08(bios, table + (cond * 5) + 2);
464 u8 mask = nv_ro08(bios, table + (cond * 5) + 3);
465 u8 value = nv_ro08(bios, table + (cond * 5) + 4);
466 trace("\t[0x%02x] (0x%04x[0x%02x] & 0x%02x) == 0x%02x\n",
467 cond, port, index, mask, value);
468 return (init_rdvgai(init, port, index) & mask) == value;
469 }
470 return false;
471}
472
473static bool
474init_io_flag_condition_met(struct nvbios_init *init, u8 cond)
475{
476 struct nouveau_bios *bios = init->bios;
477 u16 table = init_io_flag_condition_table(init);
478 if (table) {
479 u16 port = nv_ro16(bios, table + (cond * 9) + 0);
480 u8 index = nv_ro08(bios, table + (cond * 9) + 2);
481 u8 mask = nv_ro08(bios, table + (cond * 9) + 3);
482 u8 shift = nv_ro08(bios, table + (cond * 9) + 4);
483 u16 data = nv_ro16(bios, table + (cond * 9) + 5);
484 u8 dmask = nv_ro08(bios, table + (cond * 9) + 7);
485 u8 value = nv_ro08(bios, table + (cond * 9) + 8);
486 u8 ioval = (init_rdvgai(init, port, index) & mask) >> shift;
487 return (nv_ro08(bios, data + ioval) & dmask) == value;
488 }
489 return false;
490}
491
492static inline u32
493init_shift(u32 data, u8 shift)
494{
495 if (shift < 0x80)
496 return data >> shift;
497 return data << (0x100 - shift);
498}
499
500static u32
501init_tmds_reg(struct nvbios_init *init, u8 tmds)
502{
503 /* For mlv < 0x80, it is an index into a table of TMDS base addresses.
504 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
505 * CR58 for CR57 = 0 to index a table of offsets to the basic
506 * 0x6808b0 address.
507 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
508 * CR58 for CR57 = 0 to index a table of offsets to the basic
509 * 0x6808b0 address, and then flip the offset by 8.
510 */
511
512 const int pramdac_offset[13] = {
513 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
514 const u32 pramdac_table[4] = {
515 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
516
517 if (tmds >= 0x80) {
518 if (init->outp) {
519 u32 dacoffset = pramdac_offset[init->outp->or];
520 if (tmds == 0x81)
521 dacoffset ^= 8;
522 return 0x6808b0 + dacoffset;
523 }
524
28ec70f7
BS		 525 if (init_exec(init))
526 error("tmds opcodes need dcb\n");
cb75d97e
BS		 527 } else {
528 if (tmds < ARRAY_SIZE(pramdac_table))
529 return pramdac_table[tmds];
530
531 error("tmds selector 0x%02x unknown\n", tmds);
532 }
533
534 return 0;
535}
536
537/******************************************************************************
538 * init opcode handlers
539 *****************************************************************************/
540
541/**
542 * init_reserved - stub for various unknown/unused single-byte opcodes
543 *
544 */
545static void
546init_reserved(struct nvbios_init *init)
547{
548 u8 opcode = nv_ro08(init->bios, init->offset);
5495e39f
BS		 549 u8 length, i;
550
551 switch (opcode) {
552 case 0xaa:
553 length = 4;
554 break;
555 default:
556 length = 1;
557 break;
558 }
559
560 trace("RESERVED 0x%02x\t", opcode);
561 for (i = 1; i < length; i++)
562 cont(" 0x%02x", nv_ro08(init->bios, init->offset + i));
563 cont("\n");
564 init->offset += length;
cb75d97e
BS		 565}
566
567/**
568 * INIT_DONE - opcode 0x71
569 *
570 */
571static void
572init_done(struct nvbios_init *init)
573{
574 trace("DONE\n");
575 init->offset = 0x0000;
576}
577
578/**
579 * INIT_IO_RESTRICT_PROG - opcode 0x32
580 *
581 */
582static void
583init_io_restrict_prog(struct nvbios_init *init)
584{
585 struct nouveau_bios *bios = init->bios;
586 u16 port = nv_ro16(bios, init->offset + 1);
587 u8 index = nv_ro08(bios, init->offset + 3);
588 u8 mask = nv_ro08(bios, init->offset + 4);
589 u8 shift = nv_ro08(bios, init->offset + 5);
590 u8 count = nv_ro08(bios, init->offset + 6);
591 u32 reg = nv_ro32(bios, init->offset + 7);
592 u8 conf, i;
593
594 trace("IO_RESTRICT_PROG\tR[0x%06x] = "
595 "((0x%04x[0x%02x] & 0x%02x) >> %d) [{\n",
596 reg, port, index, mask, shift);
597 init->offset += 11;
598
599 conf = (init_rdvgai(init, port, index) & mask) >> shift;
600 for (i = 0; i < count; i++) {
601 u32 data = nv_ro32(bios, init->offset);
602
603 if (i == conf) {
604 trace("\t0x%08x *\n", data);
605 init_wr32(init, reg, data);
606 } else {
607 trace("\t0x%08x\n", data);
608 }
609
610 init->offset += 4;
611 }
612 trace("}]\n");
613}
614
615/**
616 * INIT_REPEAT - opcode 0x33
617 *
618 */
619static void
620init_repeat(struct nvbios_init *init)
621{
622 struct nouveau_bios *bios = init->bios;
623 u8 count = nv_ro08(bios, init->offset + 1);
624 u16 repeat = init->repeat;
625
626 trace("REPEAT\t0x%02x\n", count);
627 init->offset += 2;
628
629 init->repeat = init->offset;
630 init->repend = init->offset;
631 while (count--) {
632 init->offset = init->repeat;
633 nvbios_exec(init);
634 if (count)
635 trace("REPEAT\t0x%02x\n", count);
636 }
637 init->offset = init->repend;
638 init->repeat = repeat;
639}
640
641/**
642 * INIT_IO_RESTRICT_PLL - opcode 0x34
643 *
644 */
645static void
646init_io_restrict_pll(struct nvbios_init *init)
647{
648 struct nouveau_bios *bios = init->bios;
649 u16 port = nv_ro16(bios, init->offset + 1);
650 u8 index = nv_ro08(bios, init->offset + 3);
651 u8 mask = nv_ro08(bios, init->offset + 4);
652 u8 shift = nv_ro08(bios, init->offset + 5);
653 s8 iofc = nv_ro08(bios, init->offset + 6);
654 u8 count = nv_ro08(bios, init->offset + 7);
655 u32 reg = nv_ro32(bios, init->offset + 8);
656 u8 conf, i;
657
658 trace("IO_RESTRICT_PLL\tR[0x%06x] =PLL= "
659 "((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) IOFCOND 0x%02x [{\n",
660 reg, port, index, mask, shift, iofc);
661 init->offset += 12;
662
663 conf = (init_rdvgai(init, port, index) & mask) >> shift;
664 for (i = 0; i < count; i++) {
665 u32 freq = nv_ro16(bios, init->offset) * 10;
666
667 if (i == conf) {
668 trace("\t%dkHz *\n", freq);
669 if (iofc > 0 && init_io_flag_condition_met(init, iofc))
670 freq *= 2;
671 init_prog_pll(init, reg, freq);
672 } else {
673 trace("\t%dkHz\n", freq);
674 }
675
676 init->offset += 2;
677 }
678 trace("}]\n");
679}
680
681/**
682 * INIT_END_REPEAT - opcode 0x36
683 *
684 */
685static void
686init_end_repeat(struct nvbios_init *init)
687{
688 trace("END_REPEAT\n");
689 init->offset += 1;
690
691 if (init->repeat) {
692 init->repend = init->offset;
693 init->offset = 0;
694 }
695}
696
697/**
698 * INIT_COPY - opcode 0x37
699 *
700 */
701static void
702init_copy(struct nvbios_init *init)
703{
704 struct nouveau_bios *bios = init->bios;
705 u32 reg = nv_ro32(bios, init->offset + 1);
706 u8 shift = nv_ro08(bios, init->offset + 5);
707 u8 smask = nv_ro08(bios, init->offset + 6);
708 u16 port = nv_ro16(bios, init->offset + 7);
709 u8 index = nv_ro08(bios, init->offset + 9);
710 u8 mask = nv_ro08(bios, init->offset + 10);
711 u8 data;
712
713 trace("COPY\t0x%04x[0x%02x] &= 0x%02x |= "
714 "((R[0x%06x] %s 0x%02x) & 0x%02x)\n",
715 port, index, mask, reg, (shift & 0x80) ? "<<" : ">>",
716 (shift & 0x80) ? (0x100 - shift) : shift, smask);
717 init->offset += 11;
718
719 data = init_rdvgai(init, port, index) & mask;
720 data |= init_shift(init_rd32(init, reg), shift) & smask;
721 init_wrvgai(init, port, index, data);
722}
723
724/**
725 * INIT_NOT - opcode 0x38
726 *
727 */
728static void
729init_not(struct nvbios_init *init)
730{
731 trace("NOT\n");
732 init->offset += 1;
733 init_exec_inv(init);
734}
735
736/**
737 * INIT_IO_FLAG_CONDITION - opcode 0x39
738 *
739 */
740static void
741init_io_flag_condition(struct nvbios_init *init)
742{
743 struct nouveau_bios *bios = init->bios;
744 u8 cond = nv_ro08(bios, init->offset + 1);
745
746 trace("IO_FLAG_CONDITION\t0x%02x\n", cond);
747 init->offset += 2;
748
749 if (!init_io_flag_condition_met(init, cond))
750 init_exec_set(init, false);
751}
752
753/**
754 * INIT_DP_CONDITION - opcode 0x3a
755 *
756 */
757static void
758init_dp_condition(struct nvbios_init *init)
759{
760 struct nouveau_bios *bios = init->bios;
65c78660 761 struct nvbios_dpout info;
cb75d97e
BS		 762 u8 cond = nv_ro08(bios, init->offset + 1);
763 u8 unkn = nv_ro08(bios, init->offset + 2);
65c78660 764 u8 ver, hdr, cnt, len;
cb75d97e
BS		 765 u16 data;
766
767 trace("DP_CONDITION\t0x%02x 0x%02x\n", cond, unkn);
768 init->offset += 3;
769
770 switch (cond) {
771 case 0:
772 if (init_conn(init) != DCB_CONNECTOR_eDP)
773 init_exec_set(init, false);
774 break;
775 case 1:
776 case 2:
777 if ( init->outp &&
65c78660
BS		 778 (data = nvbios_dpout_match(bios, DCB_OUTPUT_DP,
779 (init->outp->or << 0) |
780 (init->outp->sorconf.link << 6),
781 &ver, &hdr, &cnt, &len, &info)))
782 {
783 if (!(info.flags & cond))
cb75d97e
BS		 784 init_exec_set(init, false);
785 break;
786 }
787
28ec70f7
BS		 788 if (init_exec(init))
789 warn("script needs dp output table data\n");
cb75d97e
BS		 790 break;
791 case 5:
792 if (!(init_rdauxr(init, 0x0d) & 1))
793 init_exec_set(init, false);
794 break;
795 default:
796 warn("unknown dp condition 0x%02x\n", cond);
797 break;
798 }
799}
800
801/**
802 * INIT_IO_MASK_OR - opcode 0x3b
803 *
804 */
805static void
806init_io_mask_or(struct nvbios_init *init)
807{
808 struct nouveau_bios *bios = init->bios;
809 u8 index = nv_ro08(bios, init->offset + 1);
810 u8 or = init_or(init);
811 u8 data;
812
b9a3140c 813 trace("IO_MASK_OR\t0x03d4[0x%02x] &= ~(1 << 0x%02x)\n", index, or);
cb75d97e
BS		 814 init->offset += 2;
815
816 data = init_rdvgai(init, 0x03d4, index);
817 init_wrvgai(init, 0x03d4, index, data &= ~(1 << or));
818}
819
820/**
821 * INIT_IO_OR - opcode 0x3c
822 *
823 */
824static void
825init_io_or(struct nvbios_init *init)
826{
827 struct nouveau_bios *bios = init->bios;
828 u8 index = nv_ro08(bios, init->offset + 1);
829 u8 or = init_or(init);
830 u8 data;
831
b9a3140c 832 trace("IO_OR\t0x03d4[0x%02x] |= (1 << 0x%02x)\n", index, or);
cb75d97e
BS		 833 init->offset += 2;
834
835 data = init_rdvgai(init, 0x03d4, index);
836 init_wrvgai(init, 0x03d4, index, data | (1 << or));
837}
838
839/**
840 * INIT_INDEX_ADDRESS_LATCHED - opcode 0x49
841 *
842 */
843static void
844init_idx_addr_latched(struct nvbios_init *init)
845{
846 struct nouveau_bios *bios = init->bios;
847 u32 creg = nv_ro32(bios, init->offset + 1);
848 u32 dreg = nv_ro32(bios, init->offset + 5);
849 u32 mask = nv_ro32(bios, init->offset + 9);
850 u32 data = nv_ro32(bios, init->offset + 13);
851 u8 count = nv_ro08(bios, init->offset + 17);
852
8db3a740
IM		 853 trace("INDEX_ADDRESS_LATCHED\tR[0x%06x] : R[0x%06x]\n", creg, dreg);
854 trace("\tCTRL &= 0x%08x |= 0x%08x\n", mask, data);
cb75d97e
BS		 855 init->offset += 18;
856
857 while (count--) {
858 u8 iaddr = nv_ro08(bios, init->offset + 0);
859 u8 idata = nv_ro08(bios, init->offset + 1);
860
861 trace("\t[0x%02x] = 0x%02x\n", iaddr, idata);
862 init->offset += 2;
863
864 init_wr32(init, dreg, idata);
f6853faa 865 init_mask(init, creg, ~mask, data | iaddr);
cb75d97e
BS		 866 }
867}
868
869/**
870 * INIT_IO_RESTRICT_PLL2 - opcode 0x4a
871 *
872 */
873static void
874init_io_restrict_pll2(struct nvbios_init *init)
875{
876 struct nouveau_bios *bios = init->bios;
877 u16 port = nv_ro16(bios, init->offset + 1);
878 u8 index = nv_ro08(bios, init->offset + 3);
879 u8 mask = nv_ro08(bios, init->offset + 4);
880 u8 shift = nv_ro08(bios, init->offset + 5);
881 u8 count = nv_ro08(bios, init->offset + 6);
882 u32 reg = nv_ro32(bios, init->offset + 7);
883 u8 conf, i;
884
885 trace("IO_RESTRICT_PLL2\t"
886 "R[0x%06x] =PLL= ((0x%04x[0x%02x] & 0x%02x) >> 0x%02x) [{\n",
887 reg, port, index, mask, shift);
888 init->offset += 11;
889
890 conf = (init_rdvgai(init, port, index) & mask) >> shift;
891 for (i = 0; i < count; i++) {
892 u32 freq = nv_ro32(bios, init->offset);
893 if (i == conf) {
894 trace("\t%dkHz *\n", freq);
895 init_prog_pll(init, reg, freq);
896 } else {
897 trace("\t%dkHz\n", freq);
898 }
899 init->offset += 4;
900 }
901 trace("}]\n");
902}
903
904/**
905 * INIT_PLL2 - opcode 0x4b
906 *
907 */
908static void
909init_pll2(struct nvbios_init *init)
910{
911 struct nouveau_bios *bios = init->bios;
912 u32 reg = nv_ro32(bios, init->offset + 1);
913 u32 freq = nv_ro32(bios, init->offset + 5);
914
915 trace("PLL2\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
916 init->offset += 9;
917
918 init_prog_pll(init, reg, freq);
919}
920
921/**
922 * INIT_I2C_BYTE - opcode 0x4c
923 *
924 */
925static void
926init_i2c_byte(struct nvbios_init *init)
927{
928 struct nouveau_bios *bios = init->bios;
929 u8 index = nv_ro08(bios, init->offset + 1);
930 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
931 u8 count = nv_ro08(bios, init->offset + 3);
932
933 trace("I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
934 init->offset += 4;
935
936 while (count--) {
937 u8 reg = nv_ro08(bios, init->offset + 0);
938 u8 mask = nv_ro08(bios, init->offset + 1);
939 u8 data = nv_ro08(bios, init->offset + 2);
940 int val;
941
942 trace("\t[0x%02x] &= 0x%02x |= 0x%02x\n", reg, mask, data);
943 init->offset += 3;
944
945 val = init_rdi2cr(init, index, addr, reg);
946 if (val < 0)
947 continue;
948 init_wri2cr(init, index, addr, reg, (val & mask) | data);
949 }
950}
951
952/**
953 * INIT_ZM_I2C_BYTE - opcode 0x4d
954 *
955 */
956static void
957init_zm_i2c_byte(struct nvbios_init *init)
958{
959 struct nouveau_bios *bios = init->bios;
960 u8 index = nv_ro08(bios, init->offset + 1);
961 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
962 u8 count = nv_ro08(bios, init->offset + 3);
963
964 trace("ZM_I2C_BYTE\tI2C[0x%02x][0x%02x]\n", index, addr);
965 init->offset += 4;
966
967 while (count--) {
968 u8 reg = nv_ro08(bios, init->offset + 0);
969 u8 data = nv_ro08(bios, init->offset + 1);
970
971 trace("\t[0x%02x] = 0x%02x\n", reg, data);
972 init->offset += 2;
973
974 init_wri2cr(init, index, addr, reg, data);
975 }
976
977}
978
979/**
980 * INIT_ZM_I2C - opcode 0x4e
981 *
982 */
983static void
984init_zm_i2c(struct nvbios_init *init)
985{
986 struct nouveau_bios *bios = init->bios;
987 u8 index = nv_ro08(bios, init->offset + 1);
988 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
989 u8 count = nv_ro08(bios, init->offset + 3);
990 u8 data[256], i;
991
992 trace("ZM_I2C\tI2C[0x%02x][0x%02x]\n", index, addr);
993 init->offset += 4;
994
995 for (i = 0; i < count; i++) {
996 data[i] = nv_ro08(bios, init->offset);
997 trace("\t0x%02x\n", data[i]);
998 init->offset++;
999 }
1000
1001 if (init_exec(init)) {
1002 struct nouveau_i2c_port *port = init_i2c(init, index);
1003 struct i2c_msg msg = {
1004 .addr = addr, .flags = 0, .len = count, .buf = data,
1005 };
1006 int ret;
1007
1008 if (port && (ret = i2c_transfer(&port->adapter, &msg, 1)) != 1)
1009 warn("i2c wr failed, %d\n", ret);
1010 }
1011}
1012
1013/**
1014 * INIT_TMDS - opcode 0x4f
1015 *
1016 */
1017static void
1018init_tmds(struct nvbios_init *init)
1019{
1020 struct nouveau_bios *bios = init->bios;
1021 u8 tmds = nv_ro08(bios, init->offset + 1);
1022 u8 addr = nv_ro08(bios, init->offset + 2);
1023 u8 mask = nv_ro08(bios, init->offset + 3);
1024 u8 data = nv_ro08(bios, init->offset + 4);
1025 u32 reg = init_tmds_reg(init, tmds);
1026
1027 trace("TMDS\tT[0x%02x][0x%02x] &= 0x%02x |= 0x%02x\n",
1028 tmds, addr, mask, data);
1029 init->offset += 5;
1030
1031 if (reg == 0)
1032 return;
1033
1034 init_wr32(init, reg + 0, addr | 0x00010000);
1035 init_wr32(init, reg + 4, data | (init_rd32(init, reg + 4) & mask));
1036 init_wr32(init, reg + 0, addr);
1037}
1038
1039/**
1040 * INIT_ZM_TMDS_GROUP - opcode 0x50
1041 *
1042 */
1043static void
1044init_zm_tmds_group(struct nvbios_init *init)
1045{
1046 struct nouveau_bios *bios = init->bios;
1047 u8 tmds = nv_ro08(bios, init->offset + 1);
1048 u8 count = nv_ro08(bios, init->offset + 2);
1049 u32 reg = init_tmds_reg(init, tmds);
1050
1051 trace("TMDS_ZM_GROUP\tT[0x%02x]\n", tmds);
1052 init->offset += 3;
1053
1054 while (count--) {
1055 u8 addr = nv_ro08(bios, init->offset + 0);
1056 u8 data = nv_ro08(bios, init->offset + 1);
1057
1058 trace("\t[0x%02x] = 0x%02x\n", addr, data);
1059 init->offset += 2;
1060
1061 init_wr32(init, reg + 4, data);
1062 init_wr32(init, reg + 0, addr);
1063 }
1064}
1065
1066/**
1067 * INIT_CR_INDEX_ADDRESS_LATCHED - opcode 0x51
1068 *
1069 */
1070static void
1071init_cr_idx_adr_latch(struct nvbios_init *init)
1072{
1073 struct nouveau_bios *bios = init->bios;
1074 u8 addr0 = nv_ro08(bios, init->offset + 1);
1075 u8 addr1 = nv_ro08(bios, init->offset + 2);
1076 u8 base = nv_ro08(bios, init->offset + 3);
1077 u8 count = nv_ro08(bios, init->offset + 4);
1078 u8 save0;
1079
1080 trace("CR_INDEX_ADDR C[%02x] C[%02x]\n", addr0, addr1);
1081 init->offset += 5;
1082
1083 save0 = init_rdvgai(init, 0x03d4, addr0);
1084 while (count--) {
1085 u8 data = nv_ro08(bios, init->offset);
1086
1087 trace("\t\t[0x%02x] = 0x%02x\n", base, data);
1088 init->offset += 1;
1089
1090 init_wrvgai(init, 0x03d4, addr0, base++);
1091 init_wrvgai(init, 0x03d4, addr1, data);
1092 }
1093 init_wrvgai(init, 0x03d4, addr0, save0);
1094}
1095
1096/**
1097 * INIT_CR - opcode 0x52
1098 *
1099 */
1100static void
1101init_cr(struct nvbios_init *init)
1102{
1103 struct nouveau_bios *bios = init->bios;
1104 u8 addr = nv_ro08(bios, init->offset + 1);
1105 u8 mask = nv_ro08(bios, init->offset + 2);
1106 u8 data = nv_ro08(bios, init->offset + 3);
1107 u8 val;
1108
1109 trace("CR\t\tC[0x%02x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1110 init->offset += 4;
1111
1112 val = init_rdvgai(init, 0x03d4, addr) & mask;
1113 init_wrvgai(init, 0x03d4, addr, val | data);
1114}
1115
1116/**
1117 * INIT_ZM_CR - opcode 0x53
1118 *
1119 */
1120static void
1121init_zm_cr(struct nvbios_init *init)
1122{
1123 struct nouveau_bios *bios = init->bios;
1124 u8 addr = nv_ro08(bios, init->offset + 1);
1125 u8 data = nv_ro08(bios, init->offset + 2);
1126
1127 trace("ZM_CR\tC[0x%02x] = 0x%02x\n", addr, data);
1128 init->offset += 3;
1129
1130 init_wrvgai(init, 0x03d4, addr, data);
1131}
1132
1133/**
1134 * INIT_ZM_CR_GROUP - opcode 0x54
1135 *
1136 */
1137static void
1138init_zm_cr_group(struct nvbios_init *init)
1139{
1140 struct nouveau_bios *bios = init->bios;
1141 u8 count = nv_ro08(bios, init->offset + 1);
1142
1143 trace("ZM_CR_GROUP\n");
1144 init->offset += 2;
1145
1146 while (count--) {
1147 u8 addr = nv_ro08(bios, init->offset + 0);
1148 u8 data = nv_ro08(bios, init->offset + 1);
1149
1150 trace("\t\tC[0x%02x] = 0x%02x\n", addr, data);
1151 init->offset += 2;
1152
1153 init_wrvgai(init, 0x03d4, addr, data);
1154 }
1155}
1156
1157/**
1158 * INIT_CONDITION_TIME - opcode 0x56
1159 *
1160 */
1161static void
1162init_condition_time(struct nvbios_init *init)
1163{
1164 struct nouveau_bios *bios = init->bios;
1165 u8 cond = nv_ro08(bios, init->offset + 1);
1166 u8 retry = nv_ro08(bios, init->offset + 2);
1167 u8 wait = min((u16)retry * 50, 100);
1168
1169 trace("CONDITION_TIME\t0x%02x 0x%02x\n", cond, retry);
1170 init->offset += 3;
1171
1172 if (!init_exec(init))
1173 return;
1174
1175 while (wait--) {
1176 if (init_condition_met(init, cond))
1177 return;
1178 mdelay(20);
1179 }
1180
1181 init_exec_set(init, false);
1182}
1183
1184/**
1185 * INIT_LTIME - opcode 0x57
1186 *
1187 */
1188static void
1189init_ltime(struct nvbios_init *init)
1190{
1191 struct nouveau_bios *bios = init->bios;
1192 u16 msec = nv_ro16(bios, init->offset + 1);
1193
1194 trace("LTIME\t0x%04x\n", msec);
1195 init->offset += 3;
1196
1197 if (init_exec(init))
1198 mdelay(msec);
1199}
1200
1201/**
1202 * INIT_ZM_REG_SEQUENCE - opcode 0x58
1203 *
1204 */
1205static void
1206init_zm_reg_sequence(struct nvbios_init *init)
1207{
1208 struct nouveau_bios *bios = init->bios;
1209 u32 base = nv_ro32(bios, init->offset + 1);
1210 u8 count = nv_ro08(bios, init->offset + 5);
1211
1212 trace("ZM_REG_SEQUENCE\t0x%02x\n", count);
1213 init->offset += 6;
1214
1215 while (count--) {
1216 u32 data = nv_ro32(bios, init->offset);
1217
1218 trace("\t\tR[0x%06x] = 0x%08x\n", base, data);
1219 init->offset += 4;
1220
1221 init_wr32(init, base, data);
1222 base += 4;
1223 }
1224}
1225
1226/**
1227 * INIT_SUB_DIRECT - opcode 0x5b
1228 *
1229 */
1230static void
1231init_sub_direct(struct nvbios_init *init)
1232{
1233 struct nouveau_bios *bios = init->bios;
1234 u16 addr = nv_ro16(bios, init->offset + 1);
1235 u16 save;
1236
1237 trace("SUB_DIRECT\t0x%04x\n", addr);
1238
1239 if (init_exec(init)) {
1240 save = init->offset;
1241 init->offset = addr;
1242 if (nvbios_exec(init)) {
1243 error("error parsing sub-table\n");
1244 return;
1245 }
1246 init->offset = save;
1247 }
1248
1249 init->offset += 3;
1250}
1251
1252/**
1253 * INIT_JUMP - opcode 0x5c
1254 *
1255 */
1256static void
1257init_jump(struct nvbios_init *init)
1258{
1259 struct nouveau_bios *bios = init->bios;
1260 u16 offset = nv_ro16(bios, init->offset + 1);
1261
1262 trace("JUMP\t0x%04x\n", offset);
6d60792e
IM		 1263
1264 if (init_exec(init))
1265 init->offset = offset;
1266 else
1267 init->offset += 3;
cb75d97e
BS		 1268}
1269
1270/**
1271 * INIT_I2C_IF - opcode 0x5e
1272 *
1273 */
1274static void
1275init_i2c_if(struct nvbios_init *init)
1276{
1277 struct nouveau_bios *bios = init->bios;
1278 u8 index = nv_ro08(bios, init->offset + 1);
1279 u8 addr = nv_ro08(bios, init->offset + 2);
1280 u8 reg = nv_ro08(bios, init->offset + 3);
1281 u8 mask = nv_ro08(bios, init->offset + 4);
1282 u8 data = nv_ro08(bios, init->offset + 5);
1283 u8 value;
1284
1285 trace("I2C_IF\tI2C[0x%02x][0x%02x][0x%02x] & 0x%02x == 0x%02x\n",
1286 index, addr, reg, mask, data);
1287 init->offset += 6;
1288 init_exec_force(init, true);
1289
1290 value = init_rdi2cr(init, index, addr, reg);
1291 if ((value & mask) != data)
1292 init_exec_set(init, false);
1293
1294 init_exec_force(init, false);
1295}
1296
1297/**
1298 * INIT_COPY_NV_REG - opcode 0x5f
1299 *
1300 */
1301static void
1302init_copy_nv_reg(struct nvbios_init *init)
1303{
1304 struct nouveau_bios *bios = init->bios;
1305 u32 sreg = nv_ro32(bios, init->offset + 1);
1306 u8 shift = nv_ro08(bios, init->offset + 5);
1307 u32 smask = nv_ro32(bios, init->offset + 6);
1308 u32 sxor = nv_ro32(bios, init->offset + 10);
1309 u32 dreg = nv_ro32(bios, init->offset + 14);
1310 u32 dmask = nv_ro32(bios, init->offset + 18);
1311 u32 data;
1312
1313 trace("COPY_NV_REG\tR[0x%06x] &= 0x%08x |= "
1314 "((R[0x%06x] %s 0x%02x) & 0x%08x ^ 0x%08x)\n",
1315 dreg, dmask, sreg, (shift & 0x80) ? "<<" : ">>",
1316 (shift & 0x80) ? (0x100 - shift) : shift, smask, sxor);
1317 init->offset += 22;
1318
1319 data = init_shift(init_rd32(init, sreg), shift);
1320 init_mask(init, dreg, ~dmask, (data & smask) ^ sxor);
1321}
1322
1323/**
1324 * INIT_ZM_INDEX_IO - opcode 0x62
1325 *
1326 */
1327static void
1328init_zm_index_io(struct nvbios_init *init)
1329{
1330 struct nouveau_bios *bios = init->bios;
1331 u16 port = nv_ro16(bios, init->offset + 1);
1332 u8 index = nv_ro08(bios, init->offset + 3);
1333 u8 data = nv_ro08(bios, init->offset + 4);
1334
1335 trace("ZM_INDEX_IO\tI[0x%04x][0x%02x] = 0x%02x\n", port, index, data);
1336 init->offset += 5;
1337
1338 init_wrvgai(init, port, index, data);
1339}
1340
1341/**
1342 * INIT_COMPUTE_MEM - opcode 0x63
1343 *
1344 */
1345static void
1346init_compute_mem(struct nvbios_init *init)
1347{
1348 struct nouveau_devinit *devinit = nouveau_devinit(init->bios);
1349
1350 trace("COMPUTE_MEM\n");
1351 init->offset += 1;
1352
1353 init_exec_force(init, true);
1354 if (init_exec(init) && devinit->meminit)
1355 devinit->meminit(devinit);
1356 init_exec_force(init, false);
1357}
1358
1359/**
1360 * INIT_RESET - opcode 0x65
1361 *
1362 */
1363static void
1364init_reset(struct nvbios_init *init)
1365{
1366 struct nouveau_bios *bios = init->bios;
1367 u32 reg = nv_ro32(bios, init->offset + 1);
1368 u32 data1 = nv_ro32(bios, init->offset + 5);
1369 u32 data2 = nv_ro32(bios, init->offset + 9);
1370 u32 savepci19;
1371
1372 trace("RESET\tR[0x%08x] = 0x%08x, 0x%08x", reg, data1, data2);
1373 init->offset += 13;
1374 init_exec_force(init, true);
1375
1376 savepci19 = init_mask(init, 0x00184c, 0x00000f00, 0x00000000);
1377 init_wr32(init, reg, data1);
1378 udelay(10);
1379 init_wr32(init, reg, data2);
1380 init_wr32(init, 0x00184c, savepci19);
1381 init_mask(init, 0x001850, 0x00000001, 0x00000000);
1382
1383 init_exec_force(init, false);
1384}
1385
1386/**
1387 * INIT_CONFIGURE_MEM - opcode 0x66
1388 *
1389 */
1390static u16
1391init_configure_mem_clk(struct nvbios_init *init)
1392{
1393 u16 mdata = bmp_mem_init_table(init->bios);
1394 if (mdata)
1395 mdata += (init_rdvgai(init, 0x03d4, 0x3c) >> 4) * 66;
1396 return mdata;
1397}
1398
1399static void
1400init_configure_mem(struct nvbios_init *init)
1401{
1402 struct nouveau_bios *bios = init->bios;
1403 u16 mdata, sdata;
1404 u32 addr, data;
1405
1406 trace("CONFIGURE_MEM\n");
1407 init->offset += 1;
1408
1409 if (bios->version.major > 2) {
1410 init_done(init);
1411 return;
1412 }
1413 init_exec_force(init, true);
1414
1415 mdata = init_configure_mem_clk(init);
1416 sdata = bmp_sdr_seq_table(bios);
1417 if (nv_ro08(bios, mdata) & 0x01)
1418 sdata = bmp_ddr_seq_table(bios);
1419 mdata += 6; /* skip to data */
1420
1421 data = init_rdvgai(init, 0x03c4, 0x01);
1422 init_wrvgai(init, 0x03c4, 0x01, data | 0x20);
1423
6b19e47d 1424 for (; (addr = nv_ro32(bios, sdata)) != 0xffffffff; sdata += 4) {
cb75d97e
BS		 1425 switch (addr) {
1426 case 0x10021c: /* CKE_NORMAL */
1427 case 0x1002d0: /* CMD_REFRESH */
1428 case 0x1002d4: /* CMD_PRECHARGE */
1429 data = 0x00000001;
1430 break;
1431 default:
1432 data = nv_ro32(bios, mdata);
1433 mdata += 4;
1434 if (data == 0xffffffff)
1435 continue;
1436 break;
1437 }
1438
1439 init_wr32(init, addr, data);
1440 }
1441
1442 init_exec_force(init, false);
1443}
1444
1445/**
1446 * INIT_CONFIGURE_CLK - opcode 0x67
1447 *
1448 */
1449static void
1450init_configure_clk(struct nvbios_init *init)
1451{
1452 struct nouveau_bios *bios = init->bios;
1453 u16 mdata, clock;
1454
1455 trace("CONFIGURE_CLK\n");
1456 init->offset += 1;
1457
1458 if (bios->version.major > 2) {
1459 init_done(init);
1460 return;
1461 }
1462 init_exec_force(init, true);
1463
1464 mdata = init_configure_mem_clk(init);
1465
1466 /* NVPLL */
1467 clock = nv_ro16(bios, mdata + 4) * 10;
1468 init_prog_pll(init, 0x680500, clock);
1469
1470 /* MPLL */
1471 clock = nv_ro16(bios, mdata + 2) * 10;
1472 if (nv_ro08(bios, mdata) & 0x01)
1473 clock *= 2;
1474 init_prog_pll(init, 0x680504, clock);
1475
1476 init_exec_force(init, false);
1477}
1478
1479/**
1480 * INIT_CONFIGURE_PREINIT - opcode 0x68
1481 *
1482 */
1483static void
1484init_configure_preinit(struct nvbios_init *init)
1485{
1486 struct nouveau_bios *bios = init->bios;
1487 u32 strap;
1488
1489 trace("CONFIGURE_PREINIT\n");
1490 init->offset += 1;
1491
1492 if (bios->version.major > 2) {
1493 init_done(init);
1494 return;
1495 }
1496 init_exec_force(init, true);
1497
1498 strap = init_rd32(init, 0x101000);
1499 strap = ((strap << 2) & 0xf0) | ((strap & 0x40) >> 6);
1500 init_wrvgai(init, 0x03d4, 0x3c, strap);
1501
1502 init_exec_force(init, false);
1503}
1504
1505/**
1506 * INIT_IO - opcode 0x69
1507 *
1508 */
1509static void
1510init_io(struct nvbios_init *init)
1511{
1512 struct nouveau_bios *bios = init->bios;
1513 u16 port = nv_ro16(bios, init->offset + 1);
1514 u8 mask = nv_ro16(bios, init->offset + 3);
1515 u8 data = nv_ro16(bios, init->offset + 4);
1516 u8 value;
1517
1518 trace("IO\t\tI[0x%04x] &= 0x%02x |= 0x%02x\n", port, mask, data);
1519 init->offset += 5;
1520
1521 /* ummm.. yes.. should really figure out wtf this is and why it's
1522 * needed some day.. it's almost certainly wrong, but, it also
1523 * somehow makes things work...
1524 */
1525 if (nv_device(init->bios)->card_type >= NV_50 &&
1526 port == 0x03c3 && data == 0x01) {
1527 init_mask(init, 0x614100, 0xf0800000, 0x00800000);
1528 init_mask(init, 0x00e18c, 0x00020000, 0x00020000);
1529 init_mask(init, 0x614900, 0xf0800000, 0x00800000);
1530 init_mask(init, 0x000200, 0x40000000, 0x00000000);
1531 mdelay(10);
1532 init_mask(init, 0x00e18c, 0x00020000, 0x00000000);
1533 init_mask(init, 0x000200, 0x40000000, 0x40000000);
1534 init_wr32(init, 0x614100, 0x00800018);
1535 init_wr32(init, 0x614900, 0x00800018);
1536 mdelay(10);
1537 init_wr32(init, 0x614100, 0x10000018);
1538 init_wr32(init, 0x614900, 0x10000018);
cb75d97e
BS		 1539 }
1540
1541 value = init_rdport(init, port) & mask;
1542 init_wrport(init, port, data | value);
1543}
1544
1545/**
1546 * INIT_SUB - opcode 0x6b
1547 *
1548 */
1549static void
1550init_sub(struct nvbios_init *init)
1551{
1552 struct nouveau_bios *bios = init->bios;
1553 u8 index = nv_ro08(bios, init->offset + 1);
1554 u16 addr, save;
1555
1556 trace("SUB\t0x%02x\n", index);
1557
1558 addr = init_script(bios, index);
1559 if (addr && init_exec(init)) {
1560 save = init->offset;
1561 init->offset = addr;
1562 if (nvbios_exec(init)) {
1563 error("error parsing sub-table\n");
1564 return;
1565 }
1566 init->offset = save;
1567 }
1568
1569 init->offset += 2;
1570}
1571
1572/**
1573 * INIT_RAM_CONDITION - opcode 0x6d
1574 *
1575 */
1576static void
1577init_ram_condition(struct nvbios_init *init)
1578{
1579 struct nouveau_bios *bios = init->bios;
1580 u8 mask = nv_ro08(bios, init->offset + 1);
1581 u8 value = nv_ro08(bios, init->offset + 2);
1582
1583 trace("RAM_CONDITION\t"
1584 "(R[0x100000] & 0x%02x) == 0x%02x\n", mask, value);
1585 init->offset += 3;
1586
1587 if ((init_rd32(init, 0x100000) & mask) != value)
1588 init_exec_set(init, false);
1589}
1590
1591/**
1592 * INIT_NV_REG - opcode 0x6e
1593 *
1594 */
1595static void
1596init_nv_reg(struct nvbios_init *init)
1597{
1598 struct nouveau_bios *bios = init->bios;
1599 u32 reg = nv_ro32(bios, init->offset + 1);
1600 u32 mask = nv_ro32(bios, init->offset + 5);
1601 u32 data = nv_ro32(bios, init->offset + 9);
1602
1603 trace("NV_REG\tR[0x%06x] &= 0x%08x |= 0x%08x\n", reg, mask, data);
1604 init->offset += 13;
1605
1606 init_mask(init, reg, ~mask, data);
1607}
1608
1609/**
1610 * INIT_MACRO - opcode 0x6f
1611 *
1612 */
1613static void
1614init_macro(struct nvbios_init *init)
1615{
1616 struct nouveau_bios *bios = init->bios;
1617 u8 macro = nv_ro08(bios, init->offset + 1);
1618 u16 table;
1619
1620 trace("MACRO\t0x%02x\n", macro);
1621
1622 table = init_macro_table(init);
1623 if (table) {
1624 u32 addr = nv_ro32(bios, table + (macro * 8) + 0);
1625 u32 data = nv_ro32(bios, table + (macro * 8) + 4);
1626 trace("\t\tR[0x%06x] = 0x%08x\n", addr, data);
1627 init_wr32(init, addr, data);
1628 }
1629
1630 init->offset += 2;
1631}
1632
1633/**
1634 * INIT_RESUME - opcode 0x72
1635 *
1636 */
1637static void
1638init_resume(struct nvbios_init *init)
1639{
1640 trace("RESUME\n");
1641 init->offset += 1;
1642 init_exec_set(init, true);
1643}
1644
1645/**
1646 * INIT_TIME - opcode 0x74
1647 *
1648 */
1649static void
1650init_time(struct nvbios_init *init)
1651{
1652 struct nouveau_bios *bios = init->bios;
1653 u16 usec = nv_ro16(bios, init->offset + 1);
1654
1655 trace("TIME\t0x%04x\n", usec);
1656 init->offset += 3;
1657
1658 if (init_exec(init)) {
1659 if (usec < 1000)
1660 udelay(usec);
1661 else
1662 mdelay((usec + 900) / 1000);
1663 }
1664}
1665
1666/**
1667 * INIT_CONDITION - opcode 0x75
1668 *
1669 */
1670static void
1671init_condition(struct nvbios_init *init)
1672{
1673 struct nouveau_bios *bios = init->bios;
1674 u8 cond = nv_ro08(bios, init->offset + 1);
1675
1676 trace("CONDITION\t0x%02x\n", cond);
1677 init->offset += 2;
1678
1679 if (!init_condition_met(init, cond))
1680 init_exec_set(init, false);
1681}
1682
1683/**
1684 * INIT_IO_CONDITION - opcode 0x76
1685 *
1686 */
1687static void
1688init_io_condition(struct nvbios_init *init)
1689{
1690 struct nouveau_bios *bios = init->bios;
1691 u8 cond = nv_ro08(bios, init->offset + 1);
1692
1693 trace("IO_CONDITION\t0x%02x\n", cond);
1694 init->offset += 2;
1695
1696 if (!init_io_condition_met(init, cond))
1697 init_exec_set(init, false);
1698}
1699
1700/**
1701 * INIT_INDEX_IO - opcode 0x78
1702 *
1703 */
1704static void
1705init_index_io(struct nvbios_init *init)
1706{
1707 struct nouveau_bios *bios = init->bios;
1708 u16 port = nv_ro16(bios, init->offset + 1);
1709 u8 index = nv_ro16(bios, init->offset + 3);
1710 u8 mask = nv_ro08(bios, init->offset + 4);
1711 u8 data = nv_ro08(bios, init->offset + 5);
1712 u8 value;
1713
1714 trace("INDEX_IO\tI[0x%04x][0x%02x] &= 0x%02x |= 0x%02x\n",
1715 port, index, mask, data);
1716 init->offset += 6;
1717
1718 value = init_rdvgai(init, port, index) & mask;
1719 init_wrvgai(init, port, index, data | value);
1720}
1721
1722/**
1723 * INIT_PLL - opcode 0x79
1724 *
1725 */
1726static void
1727init_pll(struct nvbios_init *init)
1728{
1729 struct nouveau_bios *bios = init->bios;
1730 u32 reg = nv_ro32(bios, init->offset + 1);
1731 u32 freq = nv_ro16(bios, init->offset + 5) * 10;
1732
1733 trace("PLL\tR[0x%06x] =PLL= %dkHz\n", reg, freq);
1734 init->offset += 7;
1735
1736 init_prog_pll(init, reg, freq);
1737}
1738
1739/**
1740 * INIT_ZM_REG - opcode 0x7a
1741 *
1742 */
1743static void
1744init_zm_reg(struct nvbios_init *init)
1745{
1746 struct nouveau_bios *bios = init->bios;
1747 u32 addr = nv_ro32(bios, init->offset + 1);
1748 u32 data = nv_ro32(bios, init->offset + 5);
1749
1750 trace("ZM_REG\tR[0x%06x] = 0x%08x\n", addr, data);
1751 init->offset += 9;
1752
1753 if (addr == 0x000200)
1754 data |= 0x00000001;
1755
1756 init_wr32(init, addr, data);
1757}
1758
1759/**
1760 * INIT_RAM_RESTRICT_PLL - opcde 0x87
1761 *
1762 */
1763static void
1764init_ram_restrict_pll(struct nvbios_init *init)
1765{
1766 struct nouveau_bios *bios = init->bios;
1767 u8 type = nv_ro08(bios, init->offset + 1);
1768 u8 count = init_ram_restrict_group_count(init);
1769 u8 strap = init_ram_restrict(init);
1770 u8 cconf;
1771
1772 trace("RAM_RESTRICT_PLL\t0x%02x\n", type);
1773 init->offset += 2;
1774
1775 for (cconf = 0; cconf < count; cconf++) {
1776 u32 freq = nv_ro32(bios, init->offset);
1777
1778 if (cconf == strap) {
1779 trace("%dkHz *\n", freq);
1780 init_prog_pll(init, type, freq);
1781 } else {
1782 trace("%dkHz\n", freq);
1783 }
1784
1785 init->offset += 4;
1786 }
1787}
1788
1789/**
1790 * INIT_GPIO - opcode 0x8e
1791 *
1792 */
1793static void
1794init_gpio(struct nvbios_init *init)
1795{
1796 struct nouveau_gpio *gpio = nouveau_gpio(init->bios);
1797
1798 trace("GPIO\n");
1799 init->offset += 1;
1800
1801 if (init_exec(init) && gpio && gpio->reset)
1ed73166 1802 gpio->reset(gpio, DCB_GPIO_UNUSED);
cb75d97e
BS		 1803}
1804
1805/**
1806 * INIT_RAM_RESTRICT_ZM_GROUP - opcode 0x8f
1807 *
1808 */
1809static void
1810init_ram_restrict_zm_reg_group(struct nvbios_init *init)
1811{
1812 struct nouveau_bios *bios = init->bios;
1813 u32 addr = nv_ro32(bios, init->offset + 1);
1814 u8 incr = nv_ro08(bios, init->offset + 5);
1815 u8 num = nv_ro08(bios, init->offset + 6);
1816 u8 count = init_ram_restrict_group_count(init);
1817 u8 index = init_ram_restrict(init);
1818 u8 i, j;
1819
1820 trace("RAM_RESTRICT_ZM_REG_GROUP\t"
bfd8bd1f 1821 "R[0x%08x] 0x%02x 0x%02x\n", addr, incr, num);
cb75d97e
BS		 1822 init->offset += 7;
1823
1824 for (i = 0; i < num; i++) {
1825 trace("\tR[0x%06x] = {\n", addr);
1826 for (j = 0; j < count; j++) {
1827 u32 data = nv_ro32(bios, init->offset);
1828
1829 if (j == index) {
1830 trace("\t\t0x%08x *\n", data);
1831 init_wr32(init, addr, data);
1832 } else {
1833 trace("\t\t0x%08x\n", data);
1834 }
1835
1836 init->offset += 4;
1837 }
1838 trace("\t}\n");
1839 addr += incr;
1840 }
1841}
1842
1843/**
1844 * INIT_COPY_ZM_REG - opcode 0x90
1845 *
1846 */
1847static void
1848init_copy_zm_reg(struct nvbios_init *init)
1849{
1850 struct nouveau_bios *bios = init->bios;
1851 u32 sreg = nv_ro32(bios, init->offset + 1);
1852 u32 dreg = nv_ro32(bios, init->offset + 5);
1853
bfd8bd1f 1854 trace("COPY_ZM_REG\tR[0x%06x] = R[0x%06x]\n", dreg, sreg);
cb75d97e
BS		 1855 init->offset += 9;
1856
1857 init_wr32(init, dreg, init_rd32(init, sreg));
1858}
1859
1860/**
1861 * INIT_ZM_REG_GROUP - opcode 0x91
1862 *
1863 */
1864static void
1865init_zm_reg_group(struct nvbios_init *init)
1866{
1867 struct nouveau_bios *bios = init->bios;
1868 u32 addr = nv_ro32(bios, init->offset + 1);
1869 u8 count = nv_ro08(bios, init->offset + 5);
1870
950fbfab 1871 trace("ZM_REG_GROUP\tR[0x%06x] =\n", addr);
cb75d97e
BS		 1872 init->offset += 6;
1873
1874 while (count--) {
1875 u32 data = nv_ro32(bios, init->offset);
1876 trace("\t0x%08x\n", data);
1877 init_wr32(init, addr, data);
1878 init->offset += 4;
1879 }
1880}
1881
1882/**
1883 * INIT_XLAT - opcode 0x96
1884 *
1885 */
1886static void
1887init_xlat(struct nvbios_init *init)
1888{
1889 struct nouveau_bios *bios = init->bios;
1890 u32 saddr = nv_ro32(bios, init->offset + 1);
1891 u8 sshift = nv_ro08(bios, init->offset + 5);
1892 u8 smask = nv_ro08(bios, init->offset + 6);
1893 u8 index = nv_ro08(bios, init->offset + 7);
1894 u32 daddr = nv_ro32(bios, init->offset + 8);
1895 u32 dmask = nv_ro32(bios, init->offset + 12);
1896 u8 shift = nv_ro08(bios, init->offset + 16);
1897 u32 data;
1898
1899 trace("INIT_XLAT\tR[0x%06x] &= 0x%08x |= "
1900 "(X%02x((R[0x%06x] %s 0x%02x) & 0x%02x) << 0x%02x)\n",
1901 daddr, dmask, index, saddr, (sshift & 0x80) ? "<<" : ">>",
1902 (sshift & 0x80) ? (0x100 - sshift) : sshift, smask, shift);
1903 init->offset += 17;
1904
1905 data = init_shift(init_rd32(init, saddr), sshift) & smask;
1906 data = init_xlat_(init, index, data) << shift;
1907 init_mask(init, daddr, ~dmask, data);
1908}
1909
1910/**
1911 * INIT_ZM_MASK_ADD - opcode 0x97
1912 *
1913 */
1914static void
1915init_zm_mask_add(struct nvbios_init *init)
1916{
1917 struct nouveau_bios *bios = init->bios;
1918 u32 addr = nv_ro32(bios, init->offset + 1);
1919 u32 mask = nv_ro32(bios, init->offset + 5);
1920 u32 add = nv_ro32(bios, init->offset + 9);
1921 u32 data;
1922
1923 trace("ZM_MASK_ADD\tR[0x%06x] &= 0x%08x += 0x%08x\n", addr, mask, add);
1924 init->offset += 13;
1925
46b47b8a
BS		 1926 data = init_rd32(init, addr);
1927 data = (data & mask) | ((data + add) & ~mask);
cb75d97e
BS		 1928 init_wr32(init, addr, data);
1929}
1930
1931/**
1932 * INIT_AUXCH - opcode 0x98
1933 *
1934 */
1935static void
1936init_auxch(struct nvbios_init *init)
1937{
1938 struct nouveau_bios *bios = init->bios;
1939 u32 addr = nv_ro32(bios, init->offset + 1);
1940 u8 count = nv_ro08(bios, init->offset + 5);
1941
1942 trace("AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1943 init->offset += 6;
1944
1945 while (count--) {
1946 u8 mask = nv_ro08(bios, init->offset + 0);
1947 u8 data = nv_ro08(bios, init->offset + 1);
1948 trace("\tAUX[0x%08x] &= 0x%02x |= 0x%02x\n", addr, mask, data);
1949 mask = init_rdauxr(init, addr) & mask;
1950 init_wrauxr(init, addr, mask | data);
1951 init->offset += 2;
1952 }
1953}
1954
1955/**
1956 * INIT_AUXCH - opcode 0x99
1957 *
1958 */
1959static void
1960init_zm_auxch(struct nvbios_init *init)
1961{
1962 struct nouveau_bios *bios = init->bios;
1963 u32 addr = nv_ro32(bios, init->offset + 1);
1964 u8 count = nv_ro08(bios, init->offset + 5);
1965
1966 trace("ZM_AUXCH\tAUX[0x%08x] 0x%02x\n", addr, count);
1967 init->offset += 6;
1968
1969 while (count--) {
1970 u8 data = nv_ro08(bios, init->offset + 0);
1971 trace("\tAUX[0x%08x] = 0x%02x\n", addr, data);
1972 init_wrauxr(init, addr, data);
1973 init->offset += 1;
1974 }
1975}
1976
1977/**
1978 * INIT_I2C_LONG_IF - opcode 0x9a
1979 *
1980 */
1981static void
1982init_i2c_long_if(struct nvbios_init *init)
1983{
1984 struct nouveau_bios *bios = init->bios;
1985 u8 index = nv_ro08(bios, init->offset + 1);
1986 u8 addr = nv_ro08(bios, init->offset + 2) >> 1;
1987 u8 reglo = nv_ro08(bios, init->offset + 3);
1988 u8 reghi = nv_ro08(bios, init->offset + 4);
1989 u8 mask = nv_ro08(bios, init->offset + 5);
1990 u8 data = nv_ro08(bios, init->offset + 6);
1991 struct nouveau_i2c_port *port;
1992
1993 trace("I2C_LONG_IF\t"
1994 "I2C[0x%02x][0x%02x][0x%02x%02x] & 0x%02x == 0x%02x\n",
1995 index, addr, reglo, reghi, mask, data);
1996 init->offset += 7;
1997
1998 port = init_i2c(init, index);
1999 if (port) {
2000 u8 i[2] = { reghi, reglo };
2001 u8 o[1] = {};
2002 struct i2c_msg msg[] = {
2003 { .addr = addr, .flags = 0, .len = 2, .buf = i },
2004 { .addr = addr, .flags = I2C_M_RD, .len = 1, .buf = o }
2005 };
2006 int ret;
2007
2008 ret = i2c_transfer(&port->adapter, msg, 2);
2009 if (ret == 2 && ((o[0] & mask) == data))
2010 return;
2011 }
2012
2013 init_exec_set(init, false);
2014}
2015
1ed73166
BS		 2016/**
2017 * INIT_GPIO_NE - opcode 0xa9
2018 *
2019 */
2020static void
2021init_gpio_ne(struct nvbios_init *init)
2022{
2023 struct nouveau_bios *bios = init->bios;
2024 struct nouveau_gpio *gpio = nouveau_gpio(bios);
2025 struct dcb_gpio_func func;
2026 u8 count = nv_ro08(bios, init->offset + 1);
2027 u8 idx = 0, ver, len;
2028 u16 data, i;
2029
2030 trace("GPIO_NE\t");
2031 init->offset += 2;
2032
2033 for (i = init->offset; i < init->offset + count; i++)
2034 cont("0x%02x ", nv_ro08(bios, i));
2035 cont("\n");
2036
2037 while ((data = dcb_gpio_parse(bios, 0, idx++, &ver, &len, &func))) {
2038 if (func.func != DCB_GPIO_UNUSED) {
2039 for (i = init->offset; i < init->offset + count; i++) {
2040 if (func.func == nv_ro08(bios, i))
2041 break;
2042 }
2043
2044 trace("\tFUNC[0x%02x]", func.func);
2045 if (i == (init->offset + count)) {
2046 cont(" *");
2047 if (init_exec(init) && gpio && gpio->reset)
2048 gpio->reset(gpio, func.func);
2049 }
2050 cont("\n");
2051 }
2052 }
2053
2054 init->offset += count;
2055}
2056
cb75d97e
BS		 2057static struct nvbios_init_opcode {
2058 void (*exec)(struct nvbios_init *);
2059} init_opcode[] = {
2060 [0x32] = { init_io_restrict_prog },
2061 [0x33] = { init_repeat },
2062 [0x34] = { init_io_restrict_pll },
2063 [0x36] = { init_end_repeat },
2064 [0x37] = { init_copy },
2065 [0x38] = { init_not },
2066 [0x39] = { init_io_flag_condition },
2067 [0x3a] = { init_dp_condition },
2068 [0x3b] = { init_io_mask_or },
2069 [0x3c] = { init_io_or },
2070 [0x49] = { init_idx_addr_latched },
2071 [0x4a] = { init_io_restrict_pll2 },
2072 [0x4b] = { init_pll2 },
2073 [0x4c] = { init_i2c_byte },
2074 [0x4d] = { init_zm_i2c_byte },
2075 [0x4e] = { init_zm_i2c },
2076 [0x4f] = { init_tmds },
2077 [0x50] = { init_zm_tmds_group },
2078 [0x51] = { init_cr_idx_adr_latch },
2079 [0x52] = { init_cr },
2080 [0x53] = { init_zm_cr },
2081 [0x54] = { init_zm_cr_group },
2082 [0x56] = { init_condition_time },
2083 [0x57] = { init_ltime },
2084 [0x58] = { init_zm_reg_sequence },
2085 [0x5b] = { init_sub_direct },
2086 [0x5c] = { init_jump },
2087 [0x5e] = { init_i2c_if },
2088 [0x5f] = { init_copy_nv_reg },
2089 [0x62] = { init_zm_index_io },
2090 [0x63] = { init_compute_mem },
2091 [0x65] = { init_reset },
2092 [0x66] = { init_configure_mem },
2093 [0x67] = { init_configure_clk },
2094 [0x68] = { init_configure_preinit },
2095 [0x69] = { init_io },
2096 [0x6b] = { init_sub },
2097 [0x6d] = { init_ram_condition },
2098 [0x6e] = { init_nv_reg },
2099 [0x6f] = { init_macro },
2100 [0x71] = { init_done },
2101 [0x72] = { init_resume },
2102 [0x74] = { init_time },
2103 [0x75] = { init_condition },
2104 [0x76] = { init_io_condition },
2105 [0x78] = { init_index_io },
2106 [0x79] = { init_pll },
2107 [0x7a] = { init_zm_reg },
2108 [0x87] = { init_ram_restrict_pll },
2109 [0x8c] = { init_reserved },
2110 [0x8d] = { init_reserved },
2111 [0x8e] = { init_gpio },
2112 [0x8f] = { init_ram_restrict_zm_reg_group },
2113 [0x90] = { init_copy_zm_reg },
2114 [0x91] = { init_zm_reg_group },
2115 [0x92] = { init_reserved },
2116 [0x96] = { init_xlat },
2117 [0x97] = { init_zm_mask_add },
2118 [0x98] = { init_auxch },
2119 [0x99] = { init_zm_auxch },
2120 [0x9a] = { init_i2c_long_if },
1ed73166 2121 [0xa9] = { init_gpio_ne },
5495e39f 2122 [0xaa] = { init_reserved },
cb75d97e
BS		 2123};
2124
2125#define init_opcode_nr (sizeof(init_opcode) / sizeof(init_opcode[0]))
2126
2127int
2128nvbios_exec(struct nvbios_init *init)
2129{
2130 init->nested++;
2131 while (init->offset) {
2132 u8 opcode = nv_ro08(init->bios, init->offset);
2133 if (opcode >= init_opcode_nr || !init_opcode[opcode].exec) {
2134 error("unknown opcode 0x%02x\n", opcode);
2135 return -EINVAL;
2136 }
2137
2138 init_opcode[opcode].exec(init);
2139 }
2140 init->nested--;
2141 return 0;
2142}
2143
2144int
2145nvbios_init(struct nouveau_subdev *subdev, bool execute)
2146{
2147 struct nouveau_bios *bios = nouveau_bios(subdev);
2148 int ret = 0;
2149 int i = -1;
2150 u16 data;
2151
2152 if (execute)
c52f4fa6 2153 nv_info(bios, "running init tables\n");
cb75d97e
BS		 2154 while (!ret && (data = (init_script(bios, ++i)))) {
2155 struct nvbios_init init = {
2156 .subdev = subdev,
2157 .bios = bios,
2158 .offset = data,
2159 .outp = NULL,
2160 .crtc = -1,
2161 .execute = execute ? 1 : 0,
2162 };
2163
2164 ret = nvbios_exec(&init);
2165 }
2166
2167 /* the vbios parser will run this right after the normal init
2168 * tables, whereas the binary driver appears to run it later.
2169 */
2170 if (!ret && (data = init_unknown_script(bios))) {
2171 struct nvbios_init init = {
2172 .subdev = subdev,
2173 .bios = bios,
2174 .offset = data,
2175 .outp = NULL,
2176 .crtc = -1,
2177 .execute = execute ? 1 : 0,
2178 };
2179
2180 ret = nvbios_exec(&init);
2181 }
2182
3db0fdb4 2183 return ret;
cb75d97e 2184}
Linux 6.x block layer and io_uring tree(s)