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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
[linux-2.6-block.git] / drivers / gpu / drm / msm / adreno / a4xx.xml.h
CommitLineData
bc00ae02
RC		 1#ifndef A4XX_XML
2#define A4XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
8217e97a 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
a2272e48 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
2d3584eb 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
a2272e48
RC		 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 11518 bytes, from 2016-02-10 21:03:25)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 16166 bytes, from 2016-02-11 21:20:31)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83967 bytes, from 2016-02-10 17:07:21)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 109916 bytes, from 2016-02-20 18:44:48)
8217e97a 18- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
bc00ae02 19
a2272e48 20Copyright (C) 2013-2016 by the following authors:
bc00ae02 21- Rob Clark <robdclark@gmail.com> (robclark)
a2272e48 22- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
bc00ae02
RC		 23
24Permission is hereby granted, free of charge, to any person obtaining
25a copy of this software and associated documentation files (the
26"Software"), to deal in the Software without restriction, including
27without limitation the rights to use, copy, modify, merge, publish,
28distribute, sublicense, and/or sell copies of the Software, and to
29permit persons to whom the Software is furnished to do so, subject to
30the following conditions:
31
32The above copyright notice and this permission notice (including the
33next paragraph) shall be included in all copies or substantial
34portions of the Software.
35
36THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
38MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
39IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
40LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
41OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
42WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
43*/
44
45
46enum a4xx_color_fmt {
47 RB4_A8_UNORM = 1,
af6cb4c1
RC		 48 RB4_R8_UNORM = 2,
49 RB4_R4G4B4A4_UNORM = 8,
50 RB4_R5G5B5A1_UNORM = 10,
a2272e48 51 RB4_R5G6B5_UNORM = 14,
af6cb4c1
RC		 52 RB4_R8G8_UNORM = 15,
53 RB4_R8G8_SNORM = 16,
54 RB4_R8G8_UINT = 17,
55 RB4_R8G8_SINT = 18,
a2272e48
RC		 56 RB4_R16_UNORM = 19,
57 RB4_R16_SNORM = 20,
af6cb4c1
RC		 58 RB4_R16_FLOAT = 21,
59 RB4_R16_UINT = 22,
60 RB4_R16_SINT = 23,
bc00ae02
RC		 61 RB4_R8G8B8_UNORM = 25,
62 RB4_R8G8B8A8_UNORM = 26,
af6cb4c1
RC		 63 RB4_R8G8B8A8_SNORM = 28,
64 RB4_R8G8B8A8_UINT = 29,
65 RB4_R8G8B8A8_SINT = 30,
66 RB4_R10G10B10A2_UNORM = 31,
67 RB4_R10G10B10A2_UINT = 34,
68 RB4_R11G11B10_FLOAT = 39,
a2272e48
RC		 69 RB4_R16G16_UNORM = 40,
70 RB4_R16G16_SNORM = 41,
af6cb4c1
RC		 71 RB4_R16G16_FLOAT = 42,
72 RB4_R16G16_UINT = 43,
73 RB4_R16G16_SINT = 44,
74 RB4_R32_FLOAT = 45,
75 RB4_R32_UINT = 46,
76 RB4_R32_SINT = 47,
a2272e48
RC		 77 RB4_R16G16B16A16_UNORM = 52,
78 RB4_R16G16B16A16_SNORM = 53,
af6cb4c1
RC		 79 RB4_R16G16B16A16_FLOAT = 54,
80 RB4_R16G16B16A16_UINT = 55,
81 RB4_R16G16B16A16_SINT = 56,
82 RB4_R32G32_FLOAT = 57,
83 RB4_R32G32_UINT = 58,
84 RB4_R32G32_SINT = 59,
85 RB4_R32G32B32A32_FLOAT = 60,
86 RB4_R32G32B32A32_UINT = 61,
87 RB4_R32G32B32A32_SINT = 62,
bc00ae02
RC		 88};
89
90enum a4xx_tile_mode {
91 TILE4_LINEAR = 0,
92 TILE4_3 = 3,
93};
94
95enum a4xx_rb_blend_opcode {
96 BLEND_DST_PLUS_SRC = 0,
97 BLEND_SRC_MINUS_DST = 1,
98 BLEND_DST_MINUS_SRC = 2,
99 BLEND_MIN_DST_SRC = 3,
100 BLEND_MAX_DST_SRC = 4,
101};
102
103enum a4xx_vtx_fmt {
8a264743
RC		 104 VFMT4_32_FLOAT = 1,
105 VFMT4_32_32_FLOAT = 2,
106 VFMT4_32_32_32_FLOAT = 3,
107 VFMT4_32_32_32_32_FLOAT = 4,
108 VFMT4_16_FLOAT = 5,
109 VFMT4_16_16_FLOAT = 6,
110 VFMT4_16_16_16_FLOAT = 7,
111 VFMT4_16_16_16_16_FLOAT = 8,
112 VFMT4_32_FIXED = 9,
113 VFMT4_32_32_FIXED = 10,
114 VFMT4_32_32_32_FIXED = 11,
115 VFMT4_32_32_32_32_FIXED = 12,
a2272e48 116 VFMT4_11_11_10_FLOAT = 13,
8a264743
RC		 117 VFMT4_16_SINT = 16,
118 VFMT4_16_16_SINT = 17,
119 VFMT4_16_16_16_SINT = 18,
120 VFMT4_16_16_16_16_SINT = 19,
121 VFMT4_16_UINT = 20,
122 VFMT4_16_16_UINT = 21,
123 VFMT4_16_16_16_UINT = 22,
124 VFMT4_16_16_16_16_UINT = 23,
125 VFMT4_16_SNORM = 24,
126 VFMT4_16_16_SNORM = 25,
127 VFMT4_16_16_16_SNORM = 26,
128 VFMT4_16_16_16_16_SNORM = 27,
129 VFMT4_16_UNORM = 28,
130 VFMT4_16_16_UNORM = 29,
131 VFMT4_16_16_16_UNORM = 30,
132 VFMT4_16_16_16_16_UNORM = 31,
af6cb4c1
RC		 133 VFMT4_32_UINT = 32,
134 VFMT4_32_32_UINT = 33,
135 VFMT4_32_32_32_UINT = 34,
136 VFMT4_32_32_32_32_UINT = 35,
137 VFMT4_32_SINT = 36,
8a264743 138 VFMT4_32_32_SINT = 37,
af6cb4c1
RC		 139 VFMT4_32_32_32_SINT = 38,
140 VFMT4_32_32_32_32_SINT = 39,
8a264743
RC		 141 VFMT4_8_UINT = 40,
142 VFMT4_8_8_UINT = 41,
143 VFMT4_8_8_8_UINT = 42,
144 VFMT4_8_8_8_8_UINT = 43,
145 VFMT4_8_UNORM = 44,
146 VFMT4_8_8_UNORM = 45,
147 VFMT4_8_8_8_UNORM = 46,
148 VFMT4_8_8_8_8_UNORM = 47,
149 VFMT4_8_SINT = 48,
150 VFMT4_8_8_SINT = 49,
151 VFMT4_8_8_8_SINT = 50,
152 VFMT4_8_8_8_8_SINT = 51,
153 VFMT4_8_SNORM = 52,
154 VFMT4_8_8_SNORM = 53,
155 VFMT4_8_8_8_SNORM = 54,
156 VFMT4_8_8_8_8_SNORM = 55,
a2272e48
RC		 157 VFMT4_10_10_10_2_UINT = 56,
158 VFMT4_10_10_10_2_UNORM = 57,
159 VFMT4_10_10_10_2_SINT = 58,
160 VFMT4_10_10_10_2_SNORM = 59,
161 VFMT4_2_10_10_10_UINT = 60,
162 VFMT4_2_10_10_10_UNORM = 61,
163 VFMT4_2_10_10_10_SINT = 62,
164 VFMT4_2_10_10_10_SNORM = 63,
bc00ae02
RC		 165};
166
167enum a4xx_tex_fmt {
8a264743 168 TFMT4_A8_UNORM = 3,
8a264743 169 TFMT4_8_UNORM = 4,
8217e97a 170 TFMT4_8_SNORM = 5,
8217e97a 171 TFMT4_8_UINT = 6,
8217e97a 172 TFMT4_8_SINT = 7,
a2272e48
RC		 173 TFMT4_4_4_4_4_UNORM = 8,
174 TFMT4_5_5_5_1_UNORM = 9,
175 TFMT4_5_6_5_UNORM = 11,
176 TFMT4_L8_A8_UNORM = 13,
177 TFMT4_8_8_UNORM = 14,
178 TFMT4_8_8_SNORM = 15,
179 TFMT4_8_8_UINT = 16,
af6cb4c1 180 TFMT4_8_8_SINT = 17,
a2272e48
RC		 181 TFMT4_16_UNORM = 18,
182 TFMT4_16_SNORM = 19,
183 TFMT4_16_FLOAT = 20,
af6cb4c1 184 TFMT4_16_UINT = 21,
af6cb4c1 185 TFMT4_16_SINT = 22,
a2272e48
RC		 186 TFMT4_8_8_8_8_UNORM = 28,
187 TFMT4_8_8_8_8_SNORM = 29,
188 TFMT4_8_8_8_8_UINT = 30,
189 TFMT4_8_8_8_8_SINT = 31,
190 TFMT4_9_9_9_E5_FLOAT = 32,
191 TFMT4_10_10_10_2_UNORM = 33,
192 TFMT4_10_10_10_2_UINT = 34,
193 TFMT4_11_11_10_FLOAT = 37,
194 TFMT4_16_16_UNORM = 38,
195 TFMT4_16_16_SNORM = 39,
196 TFMT4_16_16_FLOAT = 40,
197 TFMT4_16_16_UINT = 41,
af6cb4c1 198 TFMT4_16_16_SINT = 42,
a2272e48 199 TFMT4_32_FLOAT = 43,
af6cb4c1 200 TFMT4_32_UINT = 44,
af6cb4c1 201 TFMT4_32_SINT = 45,
a2272e48
RC		 202 TFMT4_16_16_16_16_UNORM = 51,
203 TFMT4_16_16_16_16_SNORM = 52,
8a264743 204 TFMT4_16_16_16_16_FLOAT = 53,
a2272e48
RC		 205 TFMT4_16_16_16_16_UINT = 54,
206 TFMT4_16_16_16_16_SINT = 55,
8a264743 207 TFMT4_32_32_FLOAT = 56,
a2272e48
RC		 208 TFMT4_32_32_UINT = 57,
209 TFMT4_32_32_SINT = 58,
210 TFMT4_32_32_32_FLOAT = 59,
211 TFMT4_32_32_32_UINT = 60,
212 TFMT4_32_32_32_SINT = 61,
8a264743 213 TFMT4_32_32_32_32_FLOAT = 63,
a2272e48
RC		 214 TFMT4_32_32_32_32_UINT = 64,
215 TFMT4_32_32_32_32_SINT = 65,
216 TFMT4_X8Z24_UNORM = 71,
217 TFMT4_DXT1 = 86,
218 TFMT4_DXT3 = 87,
219 TFMT4_DXT5 = 88,
220 TFMT4_RGTC1_UNORM = 90,
221 TFMT4_RGTC1_SNORM = 91,
222 TFMT4_RGTC2_UNORM = 94,
223 TFMT4_RGTC2_SNORM = 95,
224 TFMT4_BPTC_UFLOAT = 97,
225 TFMT4_BPTC_FLOAT = 98,
226 TFMT4_BPTC = 99,
af6cb4c1
RC		 227 TFMT4_ATC_RGB = 100,
228 TFMT4_ATC_RGBA_EXPLICIT = 101,
229 TFMT4_ATC_RGBA_INTERPOLATED = 102,
230 TFMT4_ETC2_RG11_UNORM = 103,
231 TFMT4_ETC2_RG11_SNORM = 104,
232 TFMT4_ETC2_R11_UNORM = 105,
233 TFMT4_ETC2_R11_SNORM = 106,
234 TFMT4_ETC1 = 107,
235 TFMT4_ETC2_RGB8 = 108,
236 TFMT4_ETC2_RGBA8 = 109,
237 TFMT4_ETC2_RGB8A1 = 110,
238 TFMT4_ASTC_4x4 = 111,
239 TFMT4_ASTC_5x4 = 112,
240 TFMT4_ASTC_5x5 = 113,
241 TFMT4_ASTC_6x5 = 114,
242 TFMT4_ASTC_6x6 = 115,
243 TFMT4_ASTC_8x5 = 116,
244 TFMT4_ASTC_8x6 = 117,
245 TFMT4_ASTC_8x8 = 118,
246 TFMT4_ASTC_10x5 = 119,
247 TFMT4_ASTC_10x6 = 120,
248 TFMT4_ASTC_10x8 = 121,
249 TFMT4_ASTC_10x10 = 122,
250 TFMT4_ASTC_12x10 = 123,
251 TFMT4_ASTC_12x12 = 124,
8a264743
RC		 252};
253
254enum a4xx_tex_fetchsize {
255 TFETCH4_1_BYTE = 0,
256 TFETCH4_2_BYTE = 1,
257 TFETCH4_4_BYTE = 2,
258 TFETCH4_8_BYTE = 3,
259 TFETCH4_16_BYTE = 4,
bc00ae02
RC		 260};
261
262enum a4xx_depth_format {
263 DEPTH4_NONE = 0,
264 DEPTH4_16 = 1,
265 DEPTH4_24_8 = 2,
2d3584eb 266 DEPTH4_32 = 3,
bc00ae02
RC		 267};
268
af6cb4c1
RC		 269enum a4xx_tess_spacing {
270 EQUAL_SPACING = 0,
271 ODD_SPACING = 2,
272 EVEN_SPACING = 3,
273};
274
a2272e48
RC		 275enum a4xx_ccu_perfcounter_select {
276 CCU_BUSY_CYCLES = 0,
277 CCU_RB_DEPTH_RETURN_STALL = 2,
278 CCU_RB_COLOR_RETURN_STALL = 3,
279 CCU_DEPTH_BLOCKS = 6,
280 CCU_COLOR_BLOCKS = 7,
281 CCU_DEPTH_BLOCK_HIT = 8,
282 CCU_COLOR_BLOCK_HIT = 9,
283 CCU_DEPTH_FLAG1_COUNT = 10,
284 CCU_DEPTH_FLAG2_COUNT = 11,
285 CCU_DEPTH_FLAG3_COUNT = 12,
286 CCU_DEPTH_FLAG4_COUNT = 13,
287 CCU_COLOR_FLAG1_COUNT = 14,
288 CCU_COLOR_FLAG2_COUNT = 15,
289 CCU_COLOR_FLAG3_COUNT = 16,
290 CCU_COLOR_FLAG4_COUNT = 17,
291 CCU_PARTIAL_BLOCK_READ = 18,
292};
293
294enum a4xx_cp_perfcounter_select {
295 CP_ALWAYS_COUNT = 0,
296 CP_BUSY = 1,
297 CP_PFP_IDLE = 2,
298 CP_PFP_BUSY_WORKING = 3,
299 CP_PFP_STALL_CYCLES_ANY = 4,
300 CP_PFP_STARVE_CYCLES_ANY = 5,
301 CP_PFP_STARVED_PER_LOAD_ADDR = 6,
302 CP_PFP_STALLED_PER_STORE_ADDR = 7,
303 CP_PFP_PC_PROFILE = 8,
304 CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
305 CP_PFP_COND_INDIRECT_DISCARDED = 10,
306 CP_LONG_RESUMPTIONS = 11,
307 CP_RESUME_CYCLES = 12,
308 CP_RESUME_TO_BOUNDARY_CYCLES = 13,
309 CP_LONG_PREEMPTIONS = 14,
310 CP_PREEMPT_CYCLES = 15,
311 CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
312 CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
313 CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
314 CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
315 CP_ME_FIFO_FULL_ME_BUSY = 20,
316 CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
317 CP_ME_WAITING_FOR_PACKETS = 22,
318 CP_ME_BUSY_WORKING = 23,
319 CP_ME_STARVE_CYCLES_ANY = 24,
320 CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
321 CP_ME_STALL_CYCLES_PER_PROFILE = 26,
322 CP_ME_PC_PROFILE = 27,
323 CP_RCIU_FIFO_EMPTY = 28,
324 CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
325 CP_RCIU_FIFO_FULL = 30,
326 CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
327 CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
328 CP_RCIU_FIFO_FULL_OTHER = 33,
329 CP_AHB_IDLE = 34,
330 CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
331 CP_AHB_STALL_ON_GRANT_SPLIT = 36,
332 CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
333 CP_AHB_BUSY_WORKING = 38,
334 CP_AHB_BUSY_STALL_ON_HRDY = 39,
335 CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
336};
337
338enum a4xx_gras_ras_perfcounter_select {
339 RAS_SUPER_TILES = 0,
340 RAS_8X8_TILES = 1,
341 RAS_4X4_TILES = 2,
342 RAS_BUSY_CYCLES = 3,
343 RAS_STALL_CYCLES_BY_RB = 4,
344 RAS_STALL_CYCLES_BY_VSC = 5,
345 RAS_STARVE_CYCLES_BY_TSE = 6,
346 RAS_SUPERTILE_CYCLES = 7,
347 RAS_TILE_CYCLES = 8,
348 RAS_FULLY_COVERED_SUPER_TILES = 9,
349 RAS_FULLY_COVERED_8X8_TILES = 10,
350 RAS_4X4_PRIM = 11,
351 RAS_8X4_4X8_PRIM = 12,
352 RAS_8X8_PRIM = 13,
353};
354
355enum a4xx_gras_tse_perfcounter_select {
356 TSE_INPUT_PRIM = 0,
357 TSE_INPUT_NULL_PRIM = 1,
358 TSE_TRIVAL_REJ_PRIM = 2,
359 TSE_CLIPPED_PRIM = 3,
360 TSE_NEW_PRIM = 4,
361 TSE_ZERO_AREA_PRIM = 5,
362 TSE_FACENESS_CULLED_PRIM = 6,
363 TSE_ZERO_PIXEL_PRIM = 7,
364 TSE_OUTPUT_NULL_PRIM = 8,
365 TSE_OUTPUT_VISIBLE_PRIM = 9,
366 TSE_PRE_CLIP_PRIM = 10,
367 TSE_POST_CLIP_PRIM = 11,
368 TSE_BUSY_CYCLES = 12,
369 TSE_PC_STARVE = 13,
370 TSE_RAS_STALL = 14,
371 TSE_STALL_BARYPLANE_FIFO_FULL = 15,
372 TSE_STALL_ZPLANE_FIFO_FULL = 16,
373};
374
375enum a4xx_hlsq_perfcounter_select {
376 HLSQ_SP_VS_STAGE_CONSTANT = 0,
377 HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
378 HLSQ_SP_FS_STAGE_CONSTANT = 2,
379 HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
380 HLSQ_TP_STATE = 4,
381 HLSQ_QUADS = 5,
382 HLSQ_PIXELS = 6,
383 HLSQ_VERTICES = 7,
384 HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
385 HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
386 HLSQ_BUSY_CYCLES = 15,
387 HLSQ_STALL_CYCLES_SP_STATE = 16,
388 HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
389 HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
390 HLSQ_STALL_CYCLES_UCHE = 19,
391 HLSQ_RBBM_LOAD_CYCLES = 20,
392 HLSQ_DI_TO_VS_START_SP = 21,
393 HLSQ_DI_TO_FS_START_SP = 22,
394 HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
395 HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
396 HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
397 HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
398 HLSQ_UCHE_LATENCY_CYCLES = 27,
399 HLSQ_UCHE_LATENCY_COUNT = 28,
400 HLSQ_STARVE_CYCLES_VFD = 29,
401};
402
403enum a4xx_pc_perfcounter_select {
404 PC_VIS_STREAMS_LOADED = 0,
405 PC_VPC_PRIMITIVES = 2,
406 PC_DEAD_PRIM = 3,
407 PC_LIVE_PRIM = 4,
408 PC_DEAD_DRAWCALLS = 5,
409 PC_LIVE_DRAWCALLS = 6,
410 PC_VERTEX_MISSES = 7,
411 PC_STALL_CYCLES_VFD = 9,
412 PC_STALL_CYCLES_TSE = 10,
413 PC_STALL_CYCLES_UCHE = 11,
414 PC_WORKING_CYCLES = 12,
415 PC_IA_VERTICES = 13,
416 PC_GS_PRIMITIVES = 14,
417 PC_HS_INVOCATIONS = 15,
418 PC_DS_INVOCATIONS = 16,
419 PC_DS_PRIMITIVES = 17,
420 PC_STARVE_CYCLES_FOR_INDEX = 20,
421 PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
422 PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
423 PC_STALL_CYCLES_TESS = 23,
424 PC_STARVE_CYCLES_FOR_POSITION = 24,
425 PC_MODE0_DRAWCALL = 25,
426 PC_MODE1_DRAWCALL = 26,
427 PC_MODE2_DRAWCALL = 27,
428 PC_MODE3_DRAWCALL = 28,
429 PC_MODE4_DRAWCALL = 29,
430 PC_PREDICATED_DEAD_DRAWCALL = 30,
431 PC_STALL_CYCLES_BY_TSE_ONLY = 31,
432 PC_STALL_CYCLES_BY_VPC_ONLY = 32,
433 PC_VPC_POS_DATA_TRANSACTION = 33,
434 PC_BUSY_CYCLES = 34,
435 PC_STARVE_CYCLES_DI = 35,
436 PC_STALL_CYCLES_VPC = 36,
437 TESS_WORKING_CYCLES = 37,
438 TESS_NUM_CYCLES_SETUP_WORKING = 38,
439 TESS_NUM_CYCLES_PTGEN_WORKING = 39,
440 TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
441 TESS_BUSY_CYCLES = 41,
442 TESS_STARVE_CYCLES_PC = 42,
443 TESS_STALL_CYCLES_PC = 43,
444};
445
446enum a4xx_pwr_perfcounter_select {
447 PWR_CORE_CLOCK_CYCLES = 0,
448 PWR_BUSY_CLOCK_CYCLES = 1,
449};
450
451enum a4xx_rb_perfcounter_select {
452 RB_BUSY_CYCLES = 0,
453 RB_BUSY_CYCLES_BINNING = 1,
454 RB_BUSY_CYCLES_RENDERING = 2,
455 RB_BUSY_CYCLES_RESOLVE = 3,
456 RB_STARVE_CYCLES_BY_SP = 4,
457 RB_STARVE_CYCLES_BY_RAS = 5,
458 RB_STARVE_CYCLES_BY_MARB = 6,
459 RB_STALL_CYCLES_BY_MARB = 7,
460 RB_STALL_CYCLES_BY_HLSQ = 8,
461 RB_RB_RB_MARB_DATA = 9,
462 RB_SP_RB_QUAD = 10,
463 RB_RAS_RB_Z_QUADS = 11,
464 RB_GMEM_CH0_READ = 12,
465 RB_GMEM_CH1_READ = 13,
466 RB_GMEM_CH0_WRITE = 14,
467 RB_GMEM_CH1_WRITE = 15,
468 RB_CP_CONTEXT_DONE = 16,
469 RB_CP_CACHE_FLUSH = 17,
470 RB_CP_ZPASS_DONE = 18,
471 RB_STALL_FIFO0_FULL = 19,
472 RB_STALL_FIFO1_FULL = 20,
473 RB_STALL_FIFO2_FULL = 21,
474 RB_STALL_FIFO3_FULL = 22,
475 RB_RB_HLSQ_TRANSACTIONS = 23,
476 RB_Z_READ = 24,
477 RB_Z_WRITE = 25,
478 RB_C_READ = 26,
479 RB_C_WRITE = 27,
480 RB_C_READ_LATENCY = 28,
481 RB_Z_READ_LATENCY = 29,
482 RB_STALL_BY_UCHE = 30,
483 RB_MARB_UCHE_TRANSACTIONS = 31,
484 RB_CACHE_STALL_MISS = 32,
485 RB_CACHE_STALL_FIFO_FULL = 33,
486 RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
487 RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
488 RB_SAMPLER_UNITS_ACTIVE = 36,
489 RB_TOTAL_PASS = 38,
490 RB_Z_PASS = 39,
491 RB_Z_FAIL = 40,
492 RB_S_FAIL = 41,
493 RB_POWER0 = 42,
494 RB_POWER1 = 43,
495 RB_POWER2 = 44,
496 RB_POWER3 = 45,
497 RB_POWER4 = 46,
498 RB_POWER5 = 47,
499 RB_POWER6 = 48,
500 RB_POWER7 = 49,
501};
502
503enum a4xx_rbbm_perfcounter_select {
504 RBBM_ALWAYS_ON = 0,
505 RBBM_VBIF_BUSY = 1,
506 RBBM_TSE_BUSY = 2,
507 RBBM_RAS_BUSY = 3,
508 RBBM_PC_DCALL_BUSY = 4,
509 RBBM_PC_VSD_BUSY = 5,
510 RBBM_VFD_BUSY = 6,
511 RBBM_VPC_BUSY = 7,
512 RBBM_UCHE_BUSY = 8,
513 RBBM_VSC_BUSY = 9,
514 RBBM_HLSQ_BUSY = 10,
515 RBBM_ANY_RB_BUSY = 11,
516 RBBM_ANY_TPL1_BUSY = 12,
517 RBBM_ANY_SP_BUSY = 13,
518 RBBM_ANY_MARB_BUSY = 14,
519 RBBM_ANY_ARB_BUSY = 15,
520 RBBM_AHB_STATUS_BUSY = 16,
521 RBBM_AHB_STATUS_STALLED = 17,
522 RBBM_AHB_STATUS_TXFR = 18,
523 RBBM_AHB_STATUS_TXFR_SPLIT = 19,
524 RBBM_AHB_STATUS_TXFR_ERROR = 20,
525 RBBM_AHB_STATUS_LONG_STALL = 21,
526 RBBM_STATUS_MASKED = 22,
527 RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
528 RBBM_TESS_BUSY = 24,
529 RBBM_COM_BUSY = 25,
530 RBBM_DCOM_BUSY = 32,
531 RBBM_ANY_CCU_BUSY = 33,
532 RBBM_DPM_BUSY = 34,
533};
534
535enum a4xx_sp_perfcounter_select {
536 SP_LM_LOAD_INSTRUCTIONS = 0,
537 SP_LM_STORE_INSTRUCTIONS = 1,
538 SP_LM_ATOMICS = 2,
539 SP_GM_LOAD_INSTRUCTIONS = 3,
540 SP_GM_STORE_INSTRUCTIONS = 4,
541 SP_GM_ATOMICS = 5,
542 SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
543 SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
544 SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
545 SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
546 SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
547 SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
548 SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
549 SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
550 SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
551 SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
552 SP_VS_INSTRUCTIONS = 17,
553 SP_FS_INSTRUCTIONS = 18,
554 SP_ADDR_LOCK_COUNT = 19,
555 SP_UCHE_READ_TRANS = 20,
556 SP_UCHE_WRITE_TRANS = 21,
557 SP_EXPORT_VPC_TRANS = 22,
558 SP_EXPORT_RB_TRANS = 23,
559 SP_PIXELS_KILLED = 24,
560 SP_ICL1_REQUESTS = 25,
561 SP_ICL1_MISSES = 26,
562 SP_ICL0_REQUESTS = 27,
563 SP_ICL0_MISSES = 28,
564 SP_ALU_WORKING_CYCLES = 29,
565 SP_EFU_WORKING_CYCLES = 30,
566 SP_STALL_CYCLES_BY_VPC = 31,
567 SP_STALL_CYCLES_BY_TP = 32,
568 SP_STALL_CYCLES_BY_UCHE = 33,
569 SP_STALL_CYCLES_BY_RB = 34,
570 SP_BUSY_CYCLES = 35,
571 SP_HS_INSTRUCTIONS = 36,
572 SP_DS_INSTRUCTIONS = 37,
573 SP_GS_INSTRUCTIONS = 38,
574 SP_CS_INSTRUCTIONS = 39,
575 SP_SCHEDULER_NON_WORKING = 40,
576 SP_WAVE_CONTEXTS = 41,
577 SP_WAVE_CONTEXT_CYCLES = 42,
578 SP_POWER0 = 43,
579 SP_POWER1 = 44,
580 SP_POWER2 = 45,
581 SP_POWER3 = 46,
582 SP_POWER4 = 47,
583 SP_POWER5 = 48,
584 SP_POWER6 = 49,
585 SP_POWER7 = 50,
586 SP_POWER8 = 51,
587 SP_POWER9 = 52,
588 SP_POWER10 = 53,
589 SP_POWER11 = 54,
590 SP_POWER12 = 55,
591 SP_POWER13 = 56,
592 SP_POWER14 = 57,
593 SP_POWER15 = 58,
594};
595
596enum a4xx_tp_perfcounter_select {
597 TP_L1_REQUESTS = 0,
598 TP_L1_MISSES = 1,
599 TP_QUADS_OFFSET = 8,
600 TP_QUAD_SHADOW = 9,
601 TP_QUADS_ARRAY = 10,
602 TP_QUADS_GRADIENT = 11,
603 TP_QUADS_1D2D = 12,
604 TP_QUADS_3DCUBE = 13,
605 TP_BUSY_CYCLES = 16,
606 TP_STALL_CYCLES_BY_ARB = 17,
607 TP_STATE_CACHE_REQUESTS = 20,
608 TP_STATE_CACHE_MISSES = 21,
609 TP_POWER0 = 22,
610 TP_POWER1 = 23,
611 TP_POWER2 = 24,
612 TP_POWER3 = 25,
613 TP_POWER4 = 26,
614 TP_POWER5 = 27,
615 TP_POWER6 = 28,
616 TP_POWER7 = 29,
617};
618
619enum a4xx_uche_perfcounter_select {
620 UCHE_VBIF_READ_BEATS_TP = 0,
621 UCHE_VBIF_READ_BEATS_VFD = 1,
622 UCHE_VBIF_READ_BEATS_HLSQ = 2,
623 UCHE_VBIF_READ_BEATS_MARB = 3,
624 UCHE_VBIF_READ_BEATS_SP = 4,
625 UCHE_READ_REQUESTS_TP = 5,
626 UCHE_READ_REQUESTS_VFD = 6,
627 UCHE_READ_REQUESTS_HLSQ = 7,
628 UCHE_READ_REQUESTS_MARB = 8,
629 UCHE_READ_REQUESTS_SP = 9,
630 UCHE_WRITE_REQUESTS_MARB = 10,
631 UCHE_WRITE_REQUESTS_SP = 11,
632 UCHE_TAG_CHECK_FAILS = 12,
633 UCHE_EVICTS = 13,
634 UCHE_FLUSHES = 14,
635 UCHE_VBIF_LATENCY_CYCLES = 15,
636 UCHE_VBIF_LATENCY_SAMPLES = 16,
637 UCHE_BUSY_CYCLES = 17,
638 UCHE_VBIF_READ_BEATS_PC = 18,
639 UCHE_READ_REQUESTS_PC = 19,
640 UCHE_WRITE_REQUESTS_VPC = 20,
641 UCHE_STALL_BY_VBIF = 21,
642 UCHE_WRITE_REQUESTS_VSC = 22,
643 UCHE_POWER0 = 23,
644 UCHE_POWER1 = 24,
645 UCHE_POWER2 = 25,
646 UCHE_POWER3 = 26,
647 UCHE_POWER4 = 27,
648 UCHE_POWER5 = 28,
649 UCHE_POWER6 = 29,
650 UCHE_POWER7 = 30,
651};
652
653enum a4xx_vbif_perfcounter_select {
654 AXI_READ_REQUESTS_ID_0 = 0,
655 AXI_READ_REQUESTS_ID_1 = 1,
656 AXI_READ_REQUESTS_ID_2 = 2,
657 AXI_READ_REQUESTS_ID_3 = 3,
658 AXI_READ_REQUESTS_ID_4 = 4,
659 AXI_READ_REQUESTS_ID_5 = 5,
660 AXI_READ_REQUESTS_ID_6 = 6,
661 AXI_READ_REQUESTS_ID_7 = 7,
662 AXI_READ_REQUESTS_ID_8 = 8,
663 AXI_READ_REQUESTS_ID_9 = 9,
664 AXI_READ_REQUESTS_ID_10 = 10,
665 AXI_READ_REQUESTS_ID_11 = 11,
666 AXI_READ_REQUESTS_ID_12 = 12,
667 AXI_READ_REQUESTS_ID_13 = 13,
668 AXI_READ_REQUESTS_ID_14 = 14,
669 AXI_READ_REQUESTS_ID_15 = 15,
670 AXI0_READ_REQUESTS_TOTAL = 16,
671 AXI1_READ_REQUESTS_TOTAL = 17,
672 AXI2_READ_REQUESTS_TOTAL = 18,
673 AXI3_READ_REQUESTS_TOTAL = 19,
674 AXI_READ_REQUESTS_TOTAL = 20,
675 AXI_WRITE_REQUESTS_ID_0 = 21,
676 AXI_WRITE_REQUESTS_ID_1 = 22,
677 AXI_WRITE_REQUESTS_ID_2 = 23,
678 AXI_WRITE_REQUESTS_ID_3 = 24,
679 AXI_WRITE_REQUESTS_ID_4 = 25,
680 AXI_WRITE_REQUESTS_ID_5 = 26,
681 AXI_WRITE_REQUESTS_ID_6 = 27,
682 AXI_WRITE_REQUESTS_ID_7 = 28,
683 AXI_WRITE_REQUESTS_ID_8 = 29,
684 AXI_WRITE_REQUESTS_ID_9 = 30,
685 AXI_WRITE_REQUESTS_ID_10 = 31,
686 AXI_WRITE_REQUESTS_ID_11 = 32,
687 AXI_WRITE_REQUESTS_ID_12 = 33,
688 AXI_WRITE_REQUESTS_ID_13 = 34,
689 AXI_WRITE_REQUESTS_ID_14 = 35,
690 AXI_WRITE_REQUESTS_ID_15 = 36,
691 AXI0_WRITE_REQUESTS_TOTAL = 37,
692 AXI1_WRITE_REQUESTS_TOTAL = 38,
693 AXI2_WRITE_REQUESTS_TOTAL = 39,
694 AXI3_WRITE_REQUESTS_TOTAL = 40,
695 AXI_WRITE_REQUESTS_TOTAL = 41,
696 AXI_TOTAL_REQUESTS = 42,
697 AXI_READ_DATA_BEATS_ID_0 = 43,
698 AXI_READ_DATA_BEATS_ID_1 = 44,
699 AXI_READ_DATA_BEATS_ID_2 = 45,
700 AXI_READ_DATA_BEATS_ID_3 = 46,
701 AXI_READ_DATA_BEATS_ID_4 = 47,
702 AXI_READ_DATA_BEATS_ID_5 = 48,
703 AXI_READ_DATA_BEATS_ID_6 = 49,
704 AXI_READ_DATA_BEATS_ID_7 = 50,
705 AXI_READ_DATA_BEATS_ID_8 = 51,
706 AXI_READ_DATA_BEATS_ID_9 = 52,
707 AXI_READ_DATA_BEATS_ID_10 = 53,
708 AXI_READ_DATA_BEATS_ID_11 = 54,
709 AXI_READ_DATA_BEATS_ID_12 = 55,
710 AXI_READ_DATA_BEATS_ID_13 = 56,
711 AXI_READ_DATA_BEATS_ID_14 = 57,
712 AXI_READ_DATA_BEATS_ID_15 = 58,
713 AXI0_READ_DATA_BEATS_TOTAL = 59,
714 AXI1_READ_DATA_BEATS_TOTAL = 60,
715 AXI2_READ_DATA_BEATS_TOTAL = 61,
716 AXI3_READ_DATA_BEATS_TOTAL = 62,
717 AXI_READ_DATA_BEATS_TOTAL = 63,
718 AXI_WRITE_DATA_BEATS_ID_0 = 64,
719 AXI_WRITE_DATA_BEATS_ID_1 = 65,
720 AXI_WRITE_DATA_BEATS_ID_2 = 66,
721 AXI_WRITE_DATA_BEATS_ID_3 = 67,
722 AXI_WRITE_DATA_BEATS_ID_4 = 68,
723 AXI_WRITE_DATA_BEATS_ID_5 = 69,
724 AXI_WRITE_DATA_BEATS_ID_6 = 70,
725 AXI_WRITE_DATA_BEATS_ID_7 = 71,
726 AXI_WRITE_DATA_BEATS_ID_8 = 72,
727 AXI_WRITE_DATA_BEATS_ID_9 = 73,
728 AXI_WRITE_DATA_BEATS_ID_10 = 74,
729 AXI_WRITE_DATA_BEATS_ID_11 = 75,
730 AXI_WRITE_DATA_BEATS_ID_12 = 76,
731 AXI_WRITE_DATA_BEATS_ID_13 = 77,
732 AXI_WRITE_DATA_BEATS_ID_14 = 78,
733 AXI_WRITE_DATA_BEATS_ID_15 = 79,
734 AXI0_WRITE_DATA_BEATS_TOTAL = 80,
735 AXI1_WRITE_DATA_BEATS_TOTAL = 81,
736 AXI2_WRITE_DATA_BEATS_TOTAL = 82,
737 AXI3_WRITE_DATA_BEATS_TOTAL = 83,
738 AXI_WRITE_DATA_BEATS_TOTAL = 84,
739 AXI_DATA_BEATS_TOTAL = 85,
740 CYCLES_HELD_OFF_ID_0 = 86,
741 CYCLES_HELD_OFF_ID_1 = 87,
742 CYCLES_HELD_OFF_ID_2 = 88,
743 CYCLES_HELD_OFF_ID_3 = 89,
744 CYCLES_HELD_OFF_ID_4 = 90,
745 CYCLES_HELD_OFF_ID_5 = 91,
746 CYCLES_HELD_OFF_ID_6 = 92,
747 CYCLES_HELD_OFF_ID_7 = 93,
748 CYCLES_HELD_OFF_ID_8 = 94,
749 CYCLES_HELD_OFF_ID_9 = 95,
750 CYCLES_HELD_OFF_ID_10 = 96,
751 CYCLES_HELD_OFF_ID_11 = 97,
752 CYCLES_HELD_OFF_ID_12 = 98,
753 CYCLES_HELD_OFF_ID_13 = 99,
754 CYCLES_HELD_OFF_ID_14 = 100,
755 CYCLES_HELD_OFF_ID_15 = 101,
756 AXI_READ_REQUEST_HELD_OFF = 102,
757 AXI_WRITE_REQUEST_HELD_OFF = 103,
758 AXI_REQUEST_HELD_OFF = 104,
759 AXI_WRITE_DATA_HELD_OFF = 105,
760 OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
761 OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
762 OCMEM_AXI_REQUEST_HELD_OFF = 108,
763 OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
764 ELAPSED_CYCLES_DDR = 110,
765 ELAPSED_CYCLES_OCMEM = 111,
766};
767
768enum a4xx_vfd_perfcounter_select {
769 VFD_UCHE_BYTE_FETCHED = 0,
770 VFD_UCHE_TRANS = 1,
771 VFD_FETCH_INSTRUCTIONS = 3,
772 VFD_BUSY_CYCLES = 5,
773 VFD_STALL_CYCLES_UCHE = 6,
774 VFD_STALL_CYCLES_HLSQ = 7,
775 VFD_STALL_CYCLES_VPC_BYPASS = 8,
776 VFD_STALL_CYCLES_VPC_ALLOC = 9,
777 VFD_MODE_0_FIBERS = 13,
778 VFD_MODE_1_FIBERS = 14,
779 VFD_MODE_2_FIBERS = 15,
780 VFD_MODE_3_FIBERS = 16,
781 VFD_MODE_4_FIBERS = 17,
782 VFD_BFIFO_STALL = 18,
783 VFD_NUM_VERTICES_TOTAL = 19,
784 VFD_PACKER_FULL = 20,
785 VFD_UCHE_REQUEST_FIFO_FULL = 21,
786 VFD_STARVE_CYCLES_PC = 22,
787 VFD_STARVE_CYCLES_UCHE = 23,
788};
789
790enum a4xx_vpc_perfcounter_select {
791 VPC_SP_LM_COMPONENTS = 2,
792 VPC_SP0_LM_BYTES = 3,
793 VPC_SP1_LM_BYTES = 4,
794 VPC_SP2_LM_BYTES = 5,
795 VPC_SP3_LM_BYTES = 6,
796 VPC_WORKING_CYCLES = 7,
797 VPC_STALL_CYCLES_LM = 8,
798 VPC_STARVE_CYCLES_RAS = 9,
799 VPC_STREAMOUT_CYCLES = 10,
800 VPC_UCHE_TRANSACTIONS = 12,
801 VPC_STALL_CYCLES_UCHE = 13,
802 VPC_BUSY_CYCLES = 14,
803 VPC_STARVE_CYCLES_SP = 15,
804};
805
806enum a4xx_vsc_perfcounter_select {
807 VSC_BUSY_CYCLES = 0,
808 VSC_WORKING_CYCLES = 1,
809 VSC_STALL_CYCLES_UCHE = 2,
810 VSC_STARVE_CYCLES_RAS = 3,
811 VSC_EOT_NUM = 4,
812};
813
bc00ae02
RC		 814enum a4xx_tex_filter {
815 A4XX_TEX_NEAREST = 0,
816 A4XX_TEX_LINEAR = 1,
af6cb4c1 817 A4XX_TEX_ANISO = 2,
bc00ae02
RC		 818};
819
820enum a4xx_tex_clamp {
821 A4XX_TEX_REPEAT = 0,
822 A4XX_TEX_CLAMP_TO_EDGE = 1,
823 A4XX_TEX_MIRROR_REPEAT = 2,
8217e97a
RC		 824 A4XX_TEX_CLAMP_TO_BORDER = 3,
825 A4XX_TEX_MIRROR_CLAMP = 4,
bc00ae02
RC		 826};
827
af6cb4c1
RC		 828enum a4xx_tex_aniso {
829 A4XX_TEX_ANISO_1 = 0,
830 A4XX_TEX_ANISO_2 = 1,
831 A4XX_TEX_ANISO_4 = 2,
832 A4XX_TEX_ANISO_8 = 3,
833 A4XX_TEX_ANISO_16 = 4,
834};
835
bc00ae02
RC		 836enum a4xx_tex_swiz {
837 A4XX_TEX_X = 0,
838 A4XX_TEX_Y = 1,
839 A4XX_TEX_Z = 2,
840 A4XX_TEX_W = 3,
841 A4XX_TEX_ZERO = 4,
842 A4XX_TEX_ONE = 5,
843};
844
845enum a4xx_tex_type {
846 A4XX_TEX_1D = 0,
847 A4XX_TEX_2D = 1,
848 A4XX_TEX_CUBE = 2,
849 A4XX_TEX_3D = 3,
850};
851
852#define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
853#define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
854static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
855{
856 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
857}
858#define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
859#define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
860#define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
861#define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
862#define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
863#define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
864#define A4XX_INT0_VFD_ERROR 0x00000040
865#define A4XX_INT0_CP_SW_INT 0x00000080
866#define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
867#define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
868#define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
869#define A4XX_INT0_CP_HW_FAULT 0x00000800
870#define A4XX_INT0_CP_DMA 0x00001000
871#define A4XX_INT0_CP_IB2_INT 0x00002000
872#define A4XX_INT0_CP_IB1_INT 0x00004000
873#define A4XX_INT0_CP_RB_INT 0x00008000
874#define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
875#define A4XX_INT0_CP_RB_DONE_TS 0x00020000
876#define A4XX_INT0_CP_VS_DONE_TS 0x00040000
877#define A4XX_INT0_CP_PS_DONE_TS 0x00080000
878#define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
879#define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
880#define A4XX_INT0_MISC_HANG_DETECT 0x01000000
881#define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
882#define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
883
884#define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
885
886#define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
887
888#define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
889
890#define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
891
892#define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
893
894#define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
895
896#define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
897
898#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
899
a2272e48
RC		 900#define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf
901
902#define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0
903
904#define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1
905
bc00ae02
RC		 906#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
907
908#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
909#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
910#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
911static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
912{
913 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
914}
915#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
916#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
917static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
918{
919 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
920}
921
922#define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
923
924#define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
925
926#define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
927
928#define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
929
930#define REG_A4XX_RB_MODE_CONTROL 0x000020a0
931#define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
932#define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
933static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
934{
935 return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
936}
937#define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
938#define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
939static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
940{
941 return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
942}
943
944#define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
945#define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
946#define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
947
948#define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
949#define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
950#define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
951#define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
952static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
953{
954 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
955}
956
8a264743
RC		 957#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
958#define A4XX_RB_RENDER_CONTROL2_XCOORD 0x00000001
959#define A4XX_RB_RENDER_CONTROL2_YCOORD 0x00000002
960#define A4XX_RB_RENDER_CONTROL2_ZCOORD 0x00000004
961#define A4XX_RB_RENDER_CONTROL2_WCOORD 0x00000008
af6cb4c1 962#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
8a264743 963#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
af6cb4c1 964#define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
8a264743
RC		 965#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
966#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
967static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
bc00ae02 968{
8a264743 969 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
bc00ae02 970}
af6cb4c1 971#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
8a264743 972#define A4XX_RB_RENDER_CONTROL2_VARYING 0x00001000
bc00ae02
RC		 973
974static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
975
976static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
977#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
978#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
979#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
a2272e48
RC		 980#define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
981#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
982#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
983static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
984{
985 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
986}
bc00ae02
RC		 987#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
988#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
989static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
990{
991 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
992}
993
994static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
995#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
996#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
997static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
998{
999 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
1000}
af6cb4c1
RC		 1001#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
1002#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
1003static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
1004{
1005 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
1006}
bc00ae02
RC		 1007#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
1008#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
1009static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1010{
1011 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
1012}
1013#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
1014#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
1015static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
1016{
1017 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
1018}
af6cb4c1 1019#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
2d3584eb 1020#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
bc00ae02
RC		 1021#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
1022static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
1023{
1024 return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
1025}
1026
1027static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
1028
1029static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
2d3584eb 1030#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
bc00ae02
RC		 1031#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
1032static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
1033{
1034 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
1035}
1036
1037static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
1038#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
1039#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
1040static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
1041{
1042 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
1043}
1044#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
1045#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
1046static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
1047{
1048 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1049}
1050#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
1051#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
1052static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
1053{
1054 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
1055}
1056#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
1057#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
1058static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
1059{
1060 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
1061}
1062#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
1063#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
1064static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a4xx_rb_blend_opcode val)
1065{
1066 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1067}
1068#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
1069#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
1070static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1071{
1072 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1073}
1074
a2272e48
RC		 1075#define REG_A4XX_RB_BLEND_RED 0x000020f0
1076#define A4XX_RB_BLEND_RED_UINT__MASK 0x0000ffff
8a264743
RC		 1077#define A4XX_RB_BLEND_RED_UINT__SHIFT 0
1078static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
1079{
1080 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
1081}
1082#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1083#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
1084static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1085{
1086 return ((util_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1087}
1088
a2272e48
RC		 1089#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
1090#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
1091#define A4XX_RB_BLEND_RED_F32__SHIFT 0
1092static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1093{
1094 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
1095}
1096
1097#define REG_A4XX_RB_BLEND_GREEN 0x000020f2
1098#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x0000ffff
8a264743
RC		 1099#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
1100static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
1101{
1102 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
1103}
1104#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1105#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1106static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1107{
1108 return ((util_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1109}
1110
a2272e48
RC		 1111#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
1112#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
1113#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
1114static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1115{
1116 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
1117}
1118
1119#define REG_A4XX_RB_BLEND_BLUE 0x000020f4
1120#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x0000ffff
8a264743
RC		 1121#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
1122static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
1123{
1124 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
1125}
1126#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1127#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1128static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1129{
1130 return ((util_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1131}
1132
a2272e48
RC		 1133#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
1134#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
1135#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
1136static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1137{
1138 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
1139}
1140
8a264743 1141#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
a2272e48 1142#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x0000ffff
8a264743
RC		 1143#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
1144static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1145{
1146 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
1147}
1148#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1149#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1150static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1151{
1152 return ((util_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1153}
1154
a2272e48
RC		 1155#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
1156#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
1157#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
1158static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
1159{
1160 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
1161}
1162
bc00ae02 1163#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
8a264743
RC		 1164#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
1165#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
1166static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
1167{
1168 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
1169}
bc00ae02
RC		 1170#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
1171#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
1172#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
1173static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
1174{
1175 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
1176}
1177
1178#define REG_A4XX_RB_FS_OUTPUT 0x000020f9
af6cb4c1
RC		 1179#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
1180#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
1181static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
1182{
1183 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
1184}
a2272e48 1185#define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
bc00ae02
RC		 1186#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
1187#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
1188static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
1189{
1190 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
1191}
1192
2d3584eb
RC		 1193#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
1194#define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
1195#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
1196#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
1197static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
1198{
1199 return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
1200}
1201
af6cb4c1
RC		 1202#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
1203#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
1204#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
1205static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
bc00ae02 1206{
af6cb4c1
RC		 1207 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
1208}
1209#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
1210#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
1211static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
1212{
1213 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
1214}
1215#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
1216#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
1217static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
1218{
1219 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
1220}
1221#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
1222#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
1223static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
1224{
1225 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
1226}
1227#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
1228#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
1229static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
1230{
1231 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
1232}
1233#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
1234#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
1235static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
1236{
1237 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
1238}
1239#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
1240#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
1241static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
1242{
1243 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
1244}
1245#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
1246#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
1247static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
1248{
1249 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
bc00ae02
RC		 1250}
1251
1252#define REG_A4XX_RB_COPY_CONTROL 0x000020fc
1253#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
1254#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
1255static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
1256{
1257 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
1258}
1259#define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
1260#define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
1261static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
1262{
1263 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
1264}
1265#define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
1266#define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
1267static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1268{
1269 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1270}
1271#define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
1272#define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
1273static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
1274{
1275 return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
1276}
1277
1278#define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
8a264743
RC		 1279#define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
1280#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
bc00ae02
RC		 1281static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
1282{
8a264743 1283 return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
bc00ae02
RC		 1284}
1285
1286#define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
1287#define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
1288#define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
1289static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
1290{
1291 return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
1292}
1293
1294#define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
1295#define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
1296#define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
1297static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
1298{
1299 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1300}
1301#define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1302#define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
1303static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1304{
1305 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
1306}
1307#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
1308#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
1309static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1310{
1311 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1312}
1313#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1314#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
1315static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
1316{
1317 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
1318}
1319#define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1320#define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
1321static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
1322{
1323 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
1324}
1325#define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
1326#define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
1327static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
1328{
1329 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
1330}
1331
1332#define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
af6cb4c1
RC		 1333#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1334#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
1335static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
1336{
1337 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
1338}
bc00ae02
RC		 1339#define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
1340
1341#define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
1342#define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1343#define A4XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1344#define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1345#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1346#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
1347static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1348{
1349 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1350}
1351#define A4XX_RB_DEPTH_CONTROL_BF_ENABLE 0x00000080
1352#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
a2272e48 1353#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
bc00ae02
RC		 1354#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1355
1356#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
1357
1358#define REG_A4XX_RB_DEPTH_INFO 0x00002103
1359#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
1360#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1361static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
1362{
1363 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1364}
1365#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
1366#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
1367static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1368{
1369 return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1370}
1371
1372#define REG_A4XX_RB_DEPTH_PITCH 0x00002104
1373#define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
1374#define A4XX_RB_DEPTH_PITCH__SHIFT 0
1375static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
1376{
8a264743 1377 return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
bc00ae02
RC		 1378}
1379
1380#define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
1381#define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
1382#define A4XX_RB_DEPTH_PITCH2__SHIFT 0
1383static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
1384{
8a264743 1385 return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
bc00ae02
RC		 1386}
1387
1388#define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
1389#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1390#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1391#define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1392#define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1393#define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
1394static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
1395{
1396 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
1397}
1398#define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1399#define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
1400static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
1401{
1402 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
1403}
1404#define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1405#define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
1406static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
1407{
1408 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
1409}
1410#define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1411#define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
1412static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
1413{
1414 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
1415}
1416#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1417#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
1418static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
1419{
1420 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
1421}
1422#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1423#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
1424static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
1425{
1426 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
1427}
1428#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1429#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
1430static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
1431{
1432 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
1433}
1434#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1435#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
1436static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
1437{
1438 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1439}
1440
1441#define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
1442#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
1443
2d3584eb
RC		 1444#define REG_A4XX_RB_STENCIL_INFO 0x00002108
1445#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
1446#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
1447#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
1448static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
1449{
1450 return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
1451}
1452
1453#define REG_A4XX_RB_STENCIL_PITCH 0x00002109
1454#define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
1455#define A4XX_RB_STENCIL_PITCH__SHIFT 0
1456static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
1457{
1458 return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
1459}
1460
bc00ae02
RC		 1461#define REG_A4XX_RB_STENCILREFMASK 0x0000210b
1462#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1463#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1464static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1465{
1466 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
1467}
1468#define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1469#define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
1470static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1471{
1472 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1473}
1474#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1475#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
1476static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1477{
1478 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1479}
1480
1481#define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
1482#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1483#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1484static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1485{
1486 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1487}
1488#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1489#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
1490static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1491{
1492 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1493}
1494#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1495#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
1496static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1497{
1498 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1499}
1500
1501#define REG_A4XX_RB_BIN_OFFSET 0x0000210d
1502#define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
1503#define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
1504#define A4XX_RB_BIN_OFFSET_X__SHIFT 0
1505static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
1506{
1507 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
1508}
1509#define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
1510#define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
1511static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
1512{
1513 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
1514}
1515
8a264743
RC		 1516static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1517
1518static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1519
1520static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
bc00ae02
RC		 1521
1522#define REG_A4XX_RBBM_HW_VERSION 0x00000000
1523
1524#define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
1525
1526static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1527
1528static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1529
1530static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1531
1532static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1533
1534static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1535
1536static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1537
1538static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1539
1540static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1541
1542#define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
1543
1544#define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
1545
1546#define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
1547
1548#define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
1549
1550#define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
1551
1552#define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
1553
1554#define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
1555
1556#define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
1557
1558#define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
1559
1560#define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
1561
1562#define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
1563
1564#define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
1565
1566#define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
1567
1568#define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
1569
1570#define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
1571
1572#define REG_A4XX_RBBM_AHB_CTL0 0x00000023
1573
1574#define REG_A4XX_RBBM_AHB_CTL1 0x00000024
1575
1576#define REG_A4XX_RBBM_AHB_CMD 0x00000025
1577
1578#define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
1579
1580#define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
1581
1582#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
1583
1584#define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
1585
1586#define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
1587
1588#define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
1589
1590#define REG_A4XX_RBBM_INT_0_MASK 0x00000037
1591
1592#define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
1593
1594#define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
1595
1596#define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
1597
1598#define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
1599
1600#define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1601
1602#define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
1603
1604#define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
1605
1606#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1607
1608#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1609
1610#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1611
1612#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1613
a2272e48
RC		 1614#define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098
1615#define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001
1616#define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000
1617
bc00ae02
RC		 1618#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1619
a2272e48
RC		 1620#define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d
1621
1622#define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e
1623
1624#define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f
1625
1626#define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0
1627
1628#define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1
1629
1630#define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2
1631
1632#define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3
1633
1634#define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4
1635
1636#define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5
1637
1638#define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6
1639
1640#define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7
1641
1642#define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8
1643
1644#define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9
1645
1646#define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa
1647
1648#define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab
1649
1650#define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac
1651
1652#define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad
1653
1654#define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae
1655
1656#define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af
1657
1658#define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0
1659
1660#define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1
1661
1662#define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2
1663
1664#define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3
1665
1666#define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4
1667
1668#define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5
1669
1670#define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6
1671
1672#define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7
1673
1674#define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8
1675
1676#define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9
1677
1678#define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba
1679
1680#define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb
1681
1682#define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc
1683
1684#define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd
1685
1686#define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be
1687
1688#define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf
1689
1690#define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0
1691
1692#define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1
1693
1694#define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2
1695
1696#define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3
1697
1698#define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4
1699
1700#define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5
1701
1702#define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6
1703
1704#define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7
1705
1706#define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8
1707
1708#define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9
1709
1710#define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca
1711
1712#define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb
1713
1714#define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc
1715
1716#define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd
1717
1718#define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce
1719
1720#define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf
1721
1722#define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0
1723
1724#define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1
1725
1726#define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2
1727
1728#define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3
1729
1730#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4
1731
1732#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5
1733
1734#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6
1735
1736#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7
1737
1738#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8
1739
1740#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9
1741
1742#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da
1743
1744#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db
1745
1746#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc
1747
1748#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd
1749
1750#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de
1751
1752#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df
1753
1754#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0
1755
1756#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1
1757
1758#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2
1759
1760#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3
1761
1762#define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4
1763
1764#define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5
1765
1766#define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6
1767
1768#define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7
1769
1770#define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8
1771
1772#define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9
1773
1774#define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea
1775
1776#define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb
1777
1778#define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec
1779
1780#define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed
1781
1782#define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee
1783
1784#define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef
1785
1786#define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0
1787
1788#define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1
1789
1790#define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2
1791
1792#define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3
1793
1794#define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4
1795
1796#define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5
1797
1798#define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6
1799
1800#define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7
1801
1802#define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8
1803
1804#define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9
1805
1806#define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa
1807
1808#define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb
1809
1810#define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc
1811
1812#define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd
1813
1814#define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe
1815
1816#define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff
1817
1818#define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100
1819
1820#define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101
1821
1822#define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102
1823
1824#define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103
1825
1826#define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104
1827
1828#define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105
1829
1830#define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106
1831
1832#define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107
1833
1834#define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108
1835
1836#define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109
1837
1838#define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a
1839
1840#define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b
1841
1842#define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c
1843
1844#define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d
1845
1846#define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e
1847
1848#define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f
1849
1850#define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110
1851
1852#define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111
1853
1854#define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112
1855
1856#define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113
1857
1858#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
1859
1860#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
1861
1862#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
1863
1864#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
1865
1866#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
1867
1868#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
1869
1870#define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118
1871
1872#define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119
1873
1874#define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a
1875
1876#define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b
1877
1878#define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c
1879
1880#define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d
1881
1882#define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e
1883
1884#define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f
1885
1886#define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120
1887
1888#define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121
1889
1890#define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122
1891
1892#define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123
1893
1894#define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124
1895
1896#define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125
1897
1898#define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126
1899
1900#define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127
1901
1902#define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128
1903
1904#define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129
1905
1906#define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a
1907
1908#define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b
1909
1910#define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c
1911
1912#define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d
1913
1914#define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e
1915
1916#define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f
1917
1918#define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130
1919
1920#define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131
1921
1922#define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132
1923
1924#define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133
1925
1926#define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134
1927
1928#define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135
1929
1930#define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136
1931
1932#define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137
1933
1934#define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138
1935
1936#define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139
1937
1938#define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a
1939
1940#define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b
1941
1942#define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c
1943
1944#define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d
1945
1946#define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e
1947
1948#define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f
1949
1950#define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140
1951
1952#define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141
1953
1954#define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142
1955
1956#define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143
1957
1958#define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144
1959
1960#define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145
1961
1962#define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146
1963
1964#define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147
1965
1966#define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148
1967
1968#define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149
1969
1970#define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a
1971
1972#define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b
1973
1974#define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c
1975
1976#define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d
1977
1978#define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e
1979
1980#define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f
1981
1982#define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166
1983
1984#define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167
1985
1986#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
1987
1988#define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169
1989
1990#define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e
1991
1992#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
1993
bc00ae02
RC		 1994static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1995
1996static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
1997
1998static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; }
1999
2000static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2001
2002static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2003
2004static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2005
2006static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2007
2008static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2009
2010static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2011
2012static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2013
2014static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2015
2016static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2017
2018static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2019
2020static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2021
2022static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2023
2024static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2025
2026#define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
2027
2028#define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
2029
2030#define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
2031
2032#define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
2033
2034#define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
2035
2036#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
2037
2038static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2039
2040static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2041
a2272e48
RC		 2042#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099
2043
2044#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
2045
bc00ae02
RC		 2046#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
2047
2048#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
2049
2050#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
2051
2052#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
2053
2054#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
2055
2056#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
2057
2058#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
2059
a2272e48
RC		 2060#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176
2061
2062#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177
2063
2064#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178
2065
2066#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179
2067
bc00ae02
RC		 2068#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
2069
2070#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
2071
2072#define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
2073
2074#define REG_A4XX_RBBM_AHB_STATUS 0x00000189
2075
2076#define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
2077
2078#define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
2079
2080#define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
2081
2082#define REG_A4XX_RBBM_STATUS 0x00000191
2083#define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
2084#define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
2085#define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
2086#define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
2087#define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
2088#define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
2089#define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
2090#define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
2091#define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
2092#define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
2093#define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
2094#define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
2095#define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
2096#define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
2097#define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
2098#define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
2099#define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
2100#define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
2101#define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
2102#define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
2103#define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
2104
2105#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
2106
a2272e48
RC		 2107#define REG_A4XX_RBBM_POWER_STATUS 0x000001b0
2108#define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000
2109
2110#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8
2111
bc00ae02
RC		 2112#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
2113
2114#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
2115
2116#define REG_A4XX_CP_RB_BASE 0x00000200
2117
2118#define REG_A4XX_CP_RB_CNTL 0x00000201
2119
2120#define REG_A4XX_CP_RB_WPTR 0x00000205
2121
2122#define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
2123
2124#define REG_A4XX_CP_RB_RPTR 0x00000204
2125
2126#define REG_A4XX_CP_IB1_BASE 0x00000206
2127
2128#define REG_A4XX_CP_IB1_BUFSZ 0x00000207
2129
2130#define REG_A4XX_CP_IB2_BASE 0x00000208
2131
2132#define REG_A4XX_CP_IB2_BUFSZ 0x00000209
2133
af6cb4c1
RC		 2134#define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
2135
2136#define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
2137
bc00ae02
RC		 2138#define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
2139
2140#define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
2141
2142#define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
2143
2144#define REG_A4XX_CP_ROQ_ADDR 0x0000021c
2145
2146#define REG_A4XX_CP_ROQ_DATA 0x0000021d
2147
af6cb4c1 2148#define REG_A4XX_CP_MEQ_ADDR 0x0000021e
bc00ae02 2149
af6cb4c1 2150#define REG_A4XX_CP_MEQ_DATA 0x0000021f
bc00ae02
RC		 2151
2152#define REG_A4XX_CP_MERCIU_ADDR 0x00000220
2153
2154#define REG_A4XX_CP_MERCIU_DATA 0x00000221
2155
2156#define REG_A4XX_CP_MERCIU_DATA2 0x00000222
2157
2158#define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
2159
2160#define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
2161
2162#define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
2163
2164#define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
2165
2166#define REG_A4XX_CP_ME_RAM_DATA 0x00000227
2167
2168#define REG_A4XX_CP_PREEMPT 0x0000022a
2169
2170#define REG_A4XX_CP_CNTL 0x0000022c
2171
2172#define REG_A4XX_CP_ME_CNTL 0x0000022d
2173
2174#define REG_A4XX_CP_DEBUG 0x0000022e
2175
2176#define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
2177
2178#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
2179
2180#define REG_A4XX_CP_PROTECT_REG_0 0x00000240
2181
2182static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2183
2184static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2185
2186#define REG_A4XX_CP_PROTECT_CTRL 0x00000250
2187
2188#define REG_A4XX_CP_ST_BASE 0x000004c0
2189
2190#define REG_A4XX_CP_STQ_AVAIL 0x000004ce
2191
2192#define REG_A4XX_CP_MERCIU_STAT 0x000004d0
2193
2194#define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
2195
2196#define REG_A4XX_CP_HW_FAULT 0x000004d8
2197
2198#define REG_A4XX_CP_PROTECT_STATUS 0x000004da
2199
2200#define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
2201
2202#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
2203
a2272e48
RC		 2204#define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501
2205
2206#define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502
2207
2208#define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503
2209
2210#define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504
2211
2212#define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505
2213
2214#define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506
2215
2216#define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507
2217
bc00ae02
RC		 2218#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
2219
2220static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2221
2222static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2223
2224#define REG_A4XX_SP_VS_STATUS 0x00000ec0
2225
af6cb4c1
RC		 2226#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
2227
a2272e48
RC		 2228#define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4
2229
2230#define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5
2231
2232#define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6
2233
2234#define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7
2235
2236#define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8
2237
2238#define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9
2239
2240#define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca
2241
2242#define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb
2243
2244#define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc
2245
2246#define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd
2247
2248#define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece
2249
bc00ae02
RC		 2250#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
2251
2252#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
2253#define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
2254
2255#define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
af6cb4c1
RC		 2256#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
2257#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
2258#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
bc00ae02
RC		 2259
2260#define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
2261#define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
2262#define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
2263static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2264{
2265 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
2266}
2267#define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
2268#define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
2269#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2270#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2271static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2272{
2273 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2274}
2275#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
2276#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2277static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2278{
2279 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2280}
2281#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2282#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2283static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2284{
2285 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2286}
2287#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2288#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
2289static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2290{
2291 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2292}
2293#define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2294#define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
2295
2296#define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
2297#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2298#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2299static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2300{
2301 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
2302}
2303#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
2304#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
2305static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2306{
2307 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2308}
2309
2310#define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
2311#define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
2312#define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
2313static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
2314{
2315 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
2316}
2317#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
2318#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
2319static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2320{
2321 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2322}
2323#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
2324#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
2325static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2326{
2327 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2328}
2329
2330static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2331
2332static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2333#define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
2334#define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
2335static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2336{
2337 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
2338}
2339#define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2340#define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
2341static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2342{
2343 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2344}
2345#define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
2346#define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
2347static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2348{
2349 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
2350}
2351#define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2352#define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
2353static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2354{
2355 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2356}
2357
2358static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2359
2360static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2361#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2362#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
2363static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2364{
2365 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2366}
2367#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2368#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
2369static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2370{
2371 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2372}
2373#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2374#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
2375static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2376{
2377 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2378}
2379#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2380#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
2381static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2382{
2383 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2384}
2385
2386#define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
2387#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2388#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2389static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2390{
2391 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2392}
2393#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2394#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2395static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2396{
2397 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2398}
2399
2400#define REG_A4XX_SP_VS_OBJ_START 0x000022e1
2401
2402#define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
2403
2404#define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
2405
2406#define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
2407
2408#define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
2409#define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
2410#define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
2411static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2412{
2413 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
2414}
2415#define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
2416#define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
2417#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2418#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2419static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2420{
2421 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2422}
2423#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0003fc00
2424#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2425static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2426{
2427 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2428}
2429#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2430#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2431static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2432{
2433 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2434}
2435#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2436#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
2437static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2438{
2439 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2440}
2441#define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2442#define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
2443
2444#define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
2445#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2446#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2447static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2448{
2449 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
2450}
8a264743 2451#define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
bc00ae02 2452#define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
8a264743 2453#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
bc00ae02
RC		 2454
2455#define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
2456#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2457#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2458static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2459{
2460 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2461}
2462#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2463#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2464static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2465{
2466 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2467}
2468
2469#define REG_A4XX_SP_FS_OBJ_START 0x000022eb
2470
2471#define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
2472
2473#define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
2474
2475#define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
2476
2477#define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
af6cb4c1
RC		 2478#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
2479#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
2480static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
2481{
2482 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
2483}
bc00ae02
RC		 2484#define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
2485#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
2486#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
2487static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
2488{
2489 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
2490}
af6cb4c1
RC		 2491#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
2492#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
2493static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
2494{
2495 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
2496}
bc00ae02
RC		 2497
2498static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2499
2500static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2501#define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
2502#define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
2503static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
2504{
2505 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
2506}
2507#define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
2508#define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
2509#define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
2510static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
2511{
2512 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
2513}
2d3584eb 2514#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
bc00ae02 2515
af6cb4c1
RC		 2516#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
2517
2518#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
2519
2520#define REG_A4XX_SP_CS_OBJ_START 0x00002302
2521
2522#define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
2523
2524#define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
2525
2526#define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
2527
2528#define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
2529
bc00ae02
RC		 2530#define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
2531#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2532#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2533static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2534{
2535 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2536}
2537#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2538#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2539static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2540{
2541 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2542}
2543
af6cb4c1
RC		 2544#define REG_A4XX_SP_HS_OBJ_START 0x0000230e
2545
2546#define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
2547
2548#define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
2549
2550#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
2551
2d3584eb
RC		 2552#define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
2553#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
2554#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
2555static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
2556{
2557 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
2558}
2559#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2560#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
2561static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2562{
2563 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
2564}
2565
2566static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2567
2568static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2569#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
2570#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
2571static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
2572{
2573 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
2574}
2575#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2576#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
2577static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
2578{
2579 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
2580}
2581#define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
2582#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
2583static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
2584{
2585 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
2586}
2587#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2588#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
2589static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
2590{
2591 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
2592}
2593
2594static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2595
2596static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2597#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2598#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
2599static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
2600{
2601 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
2602}
2603#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2604#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
2605static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
2606{
2607 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
2608}
2609#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2610#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
2611static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
2612{
2613 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
2614}
2615#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2616#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
2617static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
2618{
2619 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
2620}
2621
bc00ae02
RC		 2622#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
2623#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2624#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2625static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2626{
2627 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2628}
2629#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2630#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2631static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2632{
2633 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2634}
2635
af6cb4c1
RC		 2636#define REG_A4XX_SP_DS_OBJ_START 0x00002335
2637
2638#define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
2639
2640#define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
2641
2642#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
2643
2d3584eb
RC		 2644#define REG_A4XX_SP_GS_PARAM_REG 0x00002341
2645#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
2646#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
2647static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
2648{
2649 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
2650}
2651#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
2652#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
2653static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
2654{
2655 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
2656}
2657#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2658#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
2659static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2660{
2661 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
2662}
2663
2664static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2665
2666static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2667#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
2668#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
2669static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
2670{
2671 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
2672}
2673#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2674#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
2675static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
2676{
2677 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
2678}
2679#define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
2680#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
2681static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
2682{
2683 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
2684}
2685#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2686#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
2687static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
2688{
2689 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
2690}
2691
2692static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2693
2694static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2695#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2696#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
2697static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
2698{
2699 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
2700}
2701#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2702#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
2703static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
2704{
2705 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
2706}
2707#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2708#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
2709static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
2710{
2711 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
2712}
2713#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2714#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
2715static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
2716{
2717 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
2718}
2719
bc00ae02
RC		 2720#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
2721#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2722#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2723static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2724{
2725 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2726}
2727#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2728#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2729static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2730{
2731 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2732}
2733
af6cb4c1
RC		 2734#define REG_A4XX_SP_GS_OBJ_START 0x0000235c
2735
2736#define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
2737
2738#define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
2739
bc00ae02
RC		 2740#define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
2741
2742#define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
2743
2744#define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
2745
2746#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
2747
a2272e48
RC		 2748#define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65
2749
2750#define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66
2751
2752#define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67
2753
bc00ae02
RC		 2754#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
2755
2756#define REG_A4XX_VPC_ATTR 0x00002140
2757#define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
2758#define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
2759static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
2760{
2761 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
2762}
2763#define A4XX_VPC_ATTR_PSIZE 0x00000200
2764#define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
2765#define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
2766static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
2767{
2768 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
2769}
2770#define A4XX_VPC_ATTR_ENABLE 0x02000000
2771
2772#define REG_A4XX_VPC_PACK 0x00002141
2773#define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
2774#define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
2775static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
2776{
2777 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
2778}
2779#define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
2780#define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
2781static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
2782{
2783 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
2784}
2785#define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
2786#define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
2787static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
2788{
2789 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
2790}
2791
2792static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2793
2794static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2795
2796static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2797
2798static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2799
2800#define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
2801
2802#define REG_A4XX_VSC_BIN_SIZE 0x00000c00
2803#define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
2804#define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2805static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2806{
2807 return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
2808}
2809#define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
2810#define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
2811static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2812{
2813 return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
2814}
2815
2816#define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
2817
2818#define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
2819
2820#define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
2821
2822static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2823
2824static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2825#define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2826#define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
2827static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2828{
2829 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
2830}
2831#define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2832#define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
2833static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2834{
2835 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2836}
2837#define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
2838#define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
2839static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2840{
2841 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
2842}
2843#define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
2844#define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
2845static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2846{
2847 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
2848}
2849
2850static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2851
2852static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2853
2854static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2855
2856static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2857
2858#define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
2859
2860#define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
2861
2862#define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
2863
2864#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
2865
a2272e48
RC		 2866#define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43
2867
2868#define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44
2869
2870#define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45
2871
2872#define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46
2873
2874#define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47
2875
2876#define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48
2877
2878#define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49
2879
bc00ae02
RC		 2880#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
2881
af6cb4c1
RC		 2882#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
2883
2884#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
2885
bc00ae02
RC		 2886#define REG_A4XX_VFD_CONTROL_0 0x00002200
2887#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
2888#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
2889static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
2890{
2891 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
2892}
2893#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
2894#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
2895static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
2896{
2897 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
2898}
2899#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
2900#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
2901static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
2902{
2903 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
2904}
2905#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
2906#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
2907static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
2908{
2909 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
2910}
2911
2912#define REG_A4XX_VFD_CONTROL_1 0x00002201
2913#define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
2914#define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
2915static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
2916{
2917 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
2918}
2919#define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
2920#define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
2921static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
2922{
2923 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
2924}
2925#define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
2926#define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
2927static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
2928{
2929 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
2930}
2931
2932#define REG_A4XX_VFD_CONTROL_2 0x00002202
2933
2934#define REG_A4XX_VFD_CONTROL_3 0x00002203
8a264743
RC		 2935#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
2936#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
2937static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
2938{
2939 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
2940}
2d3584eb
RC		 2941#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
2942#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
2943static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
2944{
2945 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
2946}
2947#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
2948#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
2949static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
2950{
2951 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
2952}
bc00ae02
RC		 2953
2954#define REG_A4XX_VFD_CONTROL_4 0x00002204
2955
2956#define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
2957
2958static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; }
2959
2960static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
2961#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
2962#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
2963static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
2964{
2965 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
2966}
2967#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
2968#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
2969static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
2970{
2971 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
2972}
2973#define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
8a264743 2974#define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
bc00ae02
RC		 2975
2976static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
2977
2978static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
2979#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
2980#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
2981static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
2982{
2983 return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
2984}
2985
2986static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
8a264743
RC		 2987#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
2988#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
2989static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
2990{
2991 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
2992}
bc00ae02
RC		 2993
2994static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; }
2995
2996static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
2997#define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
2998#define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
2999static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
3000{
3001 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
3002}
3003#define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
3004#define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
3005#define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
3006static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
3007{
3008 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
3009}
3010#define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
3011#define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
3012static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
3013{
3014 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
3015}
8a264743 3016#define A4XX_VFD_DECODE_INSTR_INT 0x00100000
bc00ae02
RC		 3017#define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
3018#define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
3019static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3020{
3021 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
3022}
3023#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
3024#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
3025static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
3026{
3027 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
3028}
3029#define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
3030#define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
3031
3032#define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
3033
af6cb4c1
RC		 3034#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
3035
a2272e48
RC		 3036#define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04
3037
3038#define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05
3039
3040#define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06
3041
3042#define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07
3043
3044#define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08
3045
3046#define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09
3047
3048#define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a
3049
bc00ae02
RC		 3050#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
3051
3052#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
3053
af6cb4c1
RC		 3054#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
3055#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
3056#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
3057static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
3058{
3059 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
3060}
3061#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
3062#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
3063static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
3064{
3065 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
3066}
3067#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
3068#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
3069static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
3070{
3071 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
3072}
3073#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
3074#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
3075static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
3076{
3077 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
3078}
3079
3080#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
3081
3082#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
3083
3084#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
3085
3086#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
3087
3088#define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
3089
3090#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
3091
3092#define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
3093
3094#define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
3095
bc00ae02
RC		 3096#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
3097
3098#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
3099
3100#define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
3101
3102#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
3103
a2272e48
RC		 3104#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89
3105
3106#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a
3107
bc00ae02
RC		 3108#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
3109
a2272e48
RC		 3110#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c
3111
3112#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d
3113
3114#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e
3115
3116#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f
3117
bc00ae02 3118#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
a2272e48
RC		 3119#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
3120#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
bc00ae02
RC		 3121
3122#define REG_A4XX_GRAS_CLEAR_CNTL 0x00002003
3123#define A4XX_GRAS_CLEAR_CNTL_NOT_FASTCLEAR 0x00000001
3124
3125#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
3126#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
3127#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
3128static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
3129{
3130 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
3131}
3132#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
3133#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
3134static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
3135{
3136 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
3137}
3138
3139#define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
3140#define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
3141#define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
3142static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
3143{
3144 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
3145}
3146
3147#define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
3148#define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
3149#define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
3150static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
3151{
3152 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
3153}
3154
3155#define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
3156#define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
3157#define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
3158static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
3159{
3160 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
3161}
3162
3163#define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
3164#define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
3165#define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
3166static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
3167{
3168 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
3169}
3170
3171#define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
3172#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
3173#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
3174static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
3175{
3176 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
3177}
3178
3179#define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
3180#define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
3181#define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
3182static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
3183{
3184 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
3185}
3186
3187#define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
3188#define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
3189#define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
3190static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
3191{
3192 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
3193}
3194#define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
3195#define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
3196static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
3197{
3198 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
3199}
3200
3201#define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
3202#define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
3203#define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
3204static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
3205{
3206 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
3207}
3208
3209#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
3210#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
a2272e48 3211#define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008
bc00ae02
RC		 3212
3213#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
3214#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
3215#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
3216static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
3217{
3218 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
3219}
3220
3221#define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
3222#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
3223#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
3224static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
3225{
3226 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
3227}
3228
af6cb4c1
RC		 3229#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
3230#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
3231#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
3232static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
3233{
3234 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
3235}
3236
8a264743
RC		 3237#define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
3238#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
3239#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
3240static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
3241{
3242 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
3243}
3244
3245#define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
3246#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
3247#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
3248#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
3249#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
3250#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
3251static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
3252{
3253 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
3254}
3255#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
3256#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
3257
3258#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
3259#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
3260#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
3261static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
3262{
3263 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
3264}
3265#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
3266#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
3267static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
3268{
3269 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
3270}
3271#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
3272#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
3273#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
3274static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
3275{
3276 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
3277}
bc00ae02
RC		 3278
3279#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
3280#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3281#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
3282#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
3283static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
3284{
3285 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
3286}
3287#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
3288#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
3289static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
3290{
3291 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
3292}
3293
3294#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
3295#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3296#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
3297#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
3298static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
3299{
3300 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
3301}
3302#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
3303#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
3304static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
3305{
3306 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
3307}
3308
3309#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
3310#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3311#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
3312#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
3313static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3314{
3315 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3316}
3317#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
3318#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
3319static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3320{
3321 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3322}
3323
3324#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
3325#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3326#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
3327#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
3328static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3329{
3330 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3331}
3332#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
3333#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
3334static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3335{
3336 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3337}
3338
8a264743
RC		 3339#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
3340#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
3341#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
3342#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
3343static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
bc00ae02 3344{
8a264743 3345 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
bc00ae02 3346}
8a264743
RC		 3347#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
3348#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
3349static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
bc00ae02 3350{
8a264743 3351 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
bc00ae02 3352}
bc00ae02 3353
8a264743
RC		 3354#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
3355#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
3356#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
3357#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
3358static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
bc00ae02 3359{
8a264743 3360 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
bc00ae02 3361}
8a264743
RC		 3362#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
3363#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
3364static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
bc00ae02 3365{
8a264743 3366 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
bc00ae02
RC		 3367}
3368
3369#define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
3370
3371#define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
3372
3373#define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
3374
3375#define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
3376
3377#define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
3378
3379#define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
3380
3381#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
3382
a2272e48
RC		 3383#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e
3384
3385#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f
3386
3387#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90
3388
3389#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91
3390
3391#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92
3392
3393#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93
3394
3395#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94
3396
bc00ae02
RC		 3397#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
3398
3399#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
3400
3401#define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
3402
af6cb4c1
RC		 3403#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
3404
bc00ae02
RC		 3405#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
3406
a2272e48
RC		 3407#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06
3408
3409#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07
3410
3411#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08
3412
3413#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09
3414
3415#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a
3416
3417#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b
3418
3419#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c
3420
3421#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d
3422
bc00ae02
RC		 3423#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
3424#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
3425#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
3426static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
3427{
3428 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
3429}
3430#define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
3431#define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
3432#define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
3433#define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
3434#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
3435#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
3436static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
3437{
3438 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
3439}
3440#define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
3441#define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
3442#define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
3443#define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
3444
3445#define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
3446#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
3447#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
3448static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
3449{
3450 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
3451}
3452#define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
3453#define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
8a264743
RC		 3454#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
3455#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
3456static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
3457{
3458 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
3459}
af6cb4c1
RC		 3460#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
3461#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
3462static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
3463{
3464 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
3465}
bc00ae02
RC		 3466
3467#define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
3468#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
3469#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
3470static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
3471{
3472 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
3473}
8a264743
RC		 3474#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
3475#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
3476static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
3477{
3478 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
3479}
af6cb4c1
RC		 3480#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
3481#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
3482static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
3483{
3484 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
3485}
3486#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
3487#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
3488static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
3489{
3490 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
3491}
bc00ae02
RC		 3492
3493#define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
3494#define A4XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
3495#define A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
3496static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
3497{
3498 return ((val) << A4XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_REGID__MASK;
3499}
3500
af6cb4c1
RC		 3501#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
3502
bc00ae02
RC		 3503#define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
3504#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3505#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3506static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3507{
3508 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
3509}
3510#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
3511#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3512static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3513{
3514 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3515}
af6cb4c1 3516#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
bc00ae02
RC		 3517#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3518#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3519static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3520{
3521 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3522}
3523#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3524#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3525static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3526{
3527 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
3528}
3529
3530#define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
3531#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3532#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3533static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3534{
3535 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
3536}
3537#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
3538#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3539static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3540{
3541 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3542}
af6cb4c1 3543#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
bc00ae02
RC		 3544#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3545#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3546static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3547{
3548 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3549}
3550#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3551#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3552static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3553{
3554 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
3555}
3556
3557#define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
3558#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3559#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3560static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3561{
3562 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
3563}
3564#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
3565#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3566static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3567{
3568 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3569}
af6cb4c1 3570#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
bc00ae02
RC		 3571#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3572#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3573static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3574{
3575 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3576}
3577#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3578#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3579static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3580{
3581 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
3582}
3583
3584#define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
3585#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3586#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3587static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3588{
3589 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
3590}
3591#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
3592#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3593static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3594{
3595 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3596}
af6cb4c1 3597#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
bc00ae02
RC		 3598#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3599#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3600static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3601{
3602 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3603}
3604#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3605#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3606static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3607{
3608 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
3609}
3610
3611#define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
3612#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3613#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3614static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3615{
3616 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
3617}
3618#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x0000ff00
3619#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3620static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3621{
3622 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3623}
af6cb4c1 3624#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
bc00ae02
RC		 3625#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3626#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3627static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3628{
3629 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3630}
3631#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3632#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3633static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3634{
3635 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
3636}
3637
af6cb4c1
RC		 3638#define REG_A4XX_HLSQ_CS_CONTROL 0x000023ca
3639
3640#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
3641
3642#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
3643
3644#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
3645
3646#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
3647
3648#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
3649
3650#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
3651
3652#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
3653
3654#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
3655
3656#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
3657
3658#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
3659
3660#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
3661
3662#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
3663
3664#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
3665
3666#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
3667
bc00ae02
RC		 3668#define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
3669
3670#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
3671#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
3672
3673#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
3674
3675#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
3676
a2272e48
RC		 3677#define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11
3678
3679#define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12
3680
3681#define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13
3682
3683#define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14
3684
3685#define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15
3686
3687#define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16
3688
bc00ae02
RC		 3689#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
3690
3691#define REG_A4XX_PC_BIN_BASE 0x000021c0
3692
3693#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
af6cb4c1
RC		 3694#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
3695#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
3696static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
3697{
3698 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
3699}
3700#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
bc00ae02
RC		 3701#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
3702#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
3703
a2272e48
RC		 3704#define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
3705#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3706#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
3707static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3708{
3709 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
3710}
3711#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
3712#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3
3713static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3714{
3715 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
3716}
3717#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
bc00ae02
RC		 3718
3719#define REG_A4XX_PC_RESTART_INDEX 0x000021c6
3720
3721#define REG_A4XX_PC_GS_PARAM 0x000021e5
af6cb4c1
RC		 3722#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3723#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
3724static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3725{
3726 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3727}
3728#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
3729#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
3730static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3731{
3732 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
3733}
3734#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
3735#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
3736static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3737{
3738 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
3739}
3740#define A4XX_PC_GS_PARAM_LAYER 0x80000000
bc00ae02
RC		 3741
3742#define REG_A4XX_PC_HS_PARAM 0x000021e7
af6cb4c1
RC		 3743#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
3744#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
3745static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3746{
3747 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3748}
3749#define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
3750#define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
3751static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3752{
3753 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
3754}
3755#define A4XX_PC_HS_PARAM_PRIMTYPE__MASK 0x01800000
3756#define A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT 23
3757static inline uint32_t A4XX_PC_HS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3758{
3759 return ((val) << A4XX_PC_HS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_HS_PARAM_PRIMTYPE__MASK;
3760}
bc00ae02
RC		 3761
3762#define REG_A4XX_VBIF_VERSION 0x00003000
3763
3764#define REG_A4XX_VBIF_CLKON 0x00003001
3765#define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
3766
3767#define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
3768
3769#define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
3770
3771#define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
3772
3773#define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
3774
3775#define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
3776
3777#define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
3778
3779#define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
3780
3781#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
3782
3783#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
3784
3785#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
3786
3787#define REG_A4XX_UNKNOWN_0D01 0x00000d01
3788
bc00ae02
RC		 3789#define REG_A4XX_UNKNOWN_0E42 0x00000e42
3790
3791#define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
3792
bc00ae02
RC		 3793#define REG_A4XX_UNKNOWN_2001 0x00002001
3794
3795#define REG_A4XX_UNKNOWN_209B 0x0000209b
3796
3797#define REG_A4XX_UNKNOWN_20EF 0x000020ef
3798
bc00ae02
RC		 3799#define REG_A4XX_UNKNOWN_2152 0x00002152
3800
3801#define REG_A4XX_UNKNOWN_2153 0x00002153
3802
3803#define REG_A4XX_UNKNOWN_2154 0x00002154
3804
3805#define REG_A4XX_UNKNOWN_2155 0x00002155
3806
3807#define REG_A4XX_UNKNOWN_2156 0x00002156
3808
3809#define REG_A4XX_UNKNOWN_2157 0x00002157
3810
3811#define REG_A4XX_UNKNOWN_21C3 0x000021c3
3812
3813#define REG_A4XX_UNKNOWN_21E6 0x000021e6
3814
3815#define REG_A4XX_UNKNOWN_2209 0x00002209
3816
3817#define REG_A4XX_UNKNOWN_22D7 0x000022d7
3818
2d3584eb
RC		 3819#define REG_A4XX_UNKNOWN_2352 0x00002352
3820
bc00ae02 3821#define REG_A4XX_TEX_SAMP_0 0x00000000
8a264743 3822#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
bc00ae02
RC		 3823#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
3824#define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
3825static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
3826{
3827 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
3828}
3829#define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
3830#define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
3831static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
3832{
3833 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
3834}
3835#define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
3836#define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
3837static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
3838{
3839 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
3840}
3841#define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
3842#define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
3843static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
3844{
3845 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
3846}
3847#define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
3848#define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
3849static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
3850{
3851 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
3852}
af6cb4c1
RC		 3853#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
3854#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
3855static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
3856{
3857 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
3858}
a2272e48
RC		 3859#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
3860#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
3861static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
3862{
3863 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
3864}
bc00ae02
RC		 3865
3866#define REG_A4XX_TEX_SAMP_1 0x00000001
3867#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
3868#define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
3869static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
3870{
3871 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
3872}
a2272e48 3873#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
8a264743
RC		 3874#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
3875#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
bc00ae02
RC		 3876#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
3877#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
3878static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
3879{
8a264743 3880 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
bc00ae02
RC		 3881}
3882#define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
3883#define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
3884static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
3885{
8a264743 3886 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
bc00ae02
RC		 3887}
3888
3889#define REG_A4XX_TEX_CONST_0 0x00000000
3890#define A4XX_TEX_CONST_0_TILED 0x00000001
af6cb4c1 3891#define A4XX_TEX_CONST_0_SRGB 0x00000004
bc00ae02
RC		 3892#define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
3893#define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
3894static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
3895{
3896 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
3897}
3898#define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
3899#define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
3900static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
3901{
3902 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
3903}
3904#define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
3905#define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
3906static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
3907{
3908 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
3909}
3910#define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
3911#define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
3912static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
3913{
3914 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
3915}
8a264743
RC		 3916#define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
3917#define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
3918static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
3919{
3920 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
3921}
bc00ae02
RC		 3922#define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
3923#define A4XX_TEX_CONST_0_FMT__SHIFT 22
3924static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
3925{
3926 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
3927}
3928#define A4XX_TEX_CONST_0_TYPE__MASK 0x60000000
3929#define A4XX_TEX_CONST_0_TYPE__SHIFT 29
3930static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
3931{
3932 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
3933}
3934
3935#define REG_A4XX_TEX_CONST_1 0x00000001
3936#define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
3937#define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
3938static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
3939{
3940 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
3941}
a2272e48 3942#define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
bc00ae02
RC		 3943#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
3944static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
3945{
3946 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
3947}
3948
3949#define REG_A4XX_TEX_CONST_2 0x00000002
8a264743
RC		 3950#define A4XX_TEX_CONST_2_FETCHSIZE__MASK 0x0000000f
3951#define A4XX_TEX_CONST_2_FETCHSIZE__SHIFT 0
3952static inline uint32_t A4XX_TEX_CONST_2_FETCHSIZE(enum a4xx_tex_fetchsize val)
3953{
3954 return ((val) << A4XX_TEX_CONST_2_FETCHSIZE__SHIFT) & A4XX_TEX_CONST_2_FETCHSIZE__MASK;
3955}
bc00ae02
RC		 3956#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
3957#define A4XX_TEX_CONST_2_PITCH__SHIFT 9
3958static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
3959{
3960 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
3961}
3962#define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
3963#define A4XX_TEX_CONST_2_SWAP__SHIFT 30
3964static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
3965{
3966 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
3967}
3968
3969#define REG_A4XX_TEX_CONST_3 0x00000003
8a264743 3970#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
bc00ae02
RC		 3971#define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
3972static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
3973{
3974 return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
3975}
8a264743
RC		 3976#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
3977#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
3978static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
3979{
3980 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
3981}
bc00ae02
RC		 3982
3983#define REG_A4XX_TEX_CONST_4 0x00000004
8a264743
RC		 3984#define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
3985#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
3986static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
3987{
3988 return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
3989}
3990#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
3991#define A4XX_TEX_CONST_4_BASE__SHIFT 5
bc00ae02
RC		 3992static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
3993{
8a264743 3994 return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
bc00ae02
RC		 3995}
3996
3997#define REG_A4XX_TEX_CONST_5 0x00000005
3998
3999#define REG_A4XX_TEX_CONST_6 0x00000006
4000
4001#define REG_A4XX_TEX_CONST_7 0x00000007
4002
4003
4004#endif /* A4XX_XML */
Linux 6.x block layer and io_uring tree(s)