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907b28c5 CW |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
26 | ||
6daccb0b CW |
27 | #include <linux/pm_runtime.h> |
28 | ||
907b28c5 CW |
29 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
30 | ||
6af5d92f CW |
31 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
32 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) | |
33 | ||
34 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) | |
35 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) | |
36 | ||
37 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
38 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) | |
39 | ||
40 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) | |
41 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) | |
42 | ||
43 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) | |
44 | ||
b2ec142c PZ |
45 | static void |
46 | assert_device_not_suspended(struct drm_i915_private *dev_priv) | |
47 | { | |
2b387059 CW |
48 | WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, |
49 | "Device suspended\n"); | |
b2ec142c | 50 | } |
6af5d92f | 51 | |
907b28c5 CW |
52 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
53 | { | |
907b28c5 CW |
54 | /* w/a for a sporadic read returning 0 by waiting for the GT |
55 | * thread to wake up. | |
56 | */ | |
eb88bd1b VS |
57 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & |
58 | GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500)) | |
907b28c5 CW |
59 | DRM_ERROR("GT thread status wait timed out\n"); |
60 | } | |
61 | ||
62 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) | |
63 | { | |
6af5d92f CW |
64 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
65 | /* something from same cacheline, but !FORCEWAKE */ | |
66 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 CW |
67 | } |
68 | ||
c8d9a590 | 69 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
b2cff0db | 70 | int fw_engine) |
907b28c5 | 71 | { |
6af5d92f | 72 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
907b28c5 CW |
73 | FORCEWAKE_ACK_TIMEOUT_MS)) |
74 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
75 | ||
6af5d92f CW |
76 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
77 | /* something from same cacheline, but !FORCEWAKE */ | |
78 | __raw_posting_read(dev_priv, ECOBUS); | |
907b28c5 | 79 | |
6af5d92f | 80 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
907b28c5 CW |
81 | FORCEWAKE_ACK_TIMEOUT_MS)) |
82 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
83 | ||
84 | /* WaRsForcewakeWaitTC0:snb */ | |
85 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
86 | } | |
87 | ||
6a68735a | 88 | static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
907b28c5 | 89 | { |
6af5d92f | 90 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
907b28c5 | 91 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 92 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
93 | } |
94 | ||
6a68735a | 95 | static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
b2cff0db | 96 | int fw_engine) |
907b28c5 CW |
97 | { |
98 | u32 forcewake_ack; | |
99 | ||
f98cd096 | 100 | if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev)) |
907b28c5 CW |
101 | forcewake_ack = FORCEWAKE_ACK_HSW; |
102 | else | |
103 | forcewake_ack = FORCEWAKE_MT_ACK; | |
104 | ||
6af5d92f | 105 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
907b28c5 CW |
106 | FORCEWAKE_ACK_TIMEOUT_MS)) |
107 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
108 | ||
6af5d92f CW |
109 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
110 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 111 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 112 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 | 113 | |
6af5d92f | 114 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
907b28c5 CW |
115 | FORCEWAKE_ACK_TIMEOUT_MS)) |
116 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
117 | ||
118 | /* WaRsForcewakeWaitTC0:ivb,hsw */ | |
c549f738 | 119 | __gen6_gt_wait_for_thread_c0(dev_priv); |
907b28c5 CW |
120 | } |
121 | ||
122 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
123 | { | |
124 | u32 gtfifodbg; | |
6af5d92f CW |
125 | |
126 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); | |
90f256b5 VS |
127 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
128 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); | |
907b28c5 CW |
129 | } |
130 | ||
c8d9a590 | 131 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
b2cff0db | 132 | int fw_engine) |
907b28c5 | 133 | { |
6af5d92f | 134 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
907b28c5 | 135 | /* something from same cacheline, but !FORCEWAKE */ |
6af5d92f | 136 | __raw_posting_read(dev_priv, ECOBUS); |
907b28c5 CW |
137 | gen6_gt_check_fifodbg(dev_priv); |
138 | } | |
139 | ||
6a68735a | 140 | static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, |
b2cff0db | 141 | int fw_engine) |
907b28c5 | 142 | { |
6af5d92f CW |
143 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
144 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
907b28c5 | 145 | /* something from same cacheline, but !FORCEWAKE_MT */ |
6af5d92f | 146 | __raw_posting_read(dev_priv, ECOBUS); |
6a68735a MK |
147 | |
148 | if (IS_GEN7(dev_priv->dev)) | |
149 | gen6_gt_check_fifodbg(dev_priv); | |
907b28c5 CW |
150 | } |
151 | ||
152 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) | |
153 | { | |
154 | int ret = 0; | |
155 | ||
5135d64b D |
156 | /* On VLV, FIFO will be shared by both SW and HW. |
157 | * So, we need to read the FREE_ENTRIES everytime */ | |
158 | if (IS_VALLEYVIEW(dev_priv->dev)) | |
159 | dev_priv->uncore.fifo_count = | |
160 | __raw_i915_read32(dev_priv, GTFIFOCTL) & | |
161 | GT_FIFO_FREE_ENTRIES_MASK; | |
162 | ||
907b28c5 CW |
163 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
164 | int loop = 500; | |
46520e2b | 165 | u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
907b28c5 CW |
166 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
167 | udelay(10); | |
46520e2b | 168 | fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
907b28c5 CW |
169 | } |
170 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
171 | ++ret; | |
172 | dev_priv->uncore.fifo_count = fifo; | |
173 | } | |
174 | dev_priv->uncore.fifo_count--; | |
175 | ||
176 | return ret; | |
177 | } | |
178 | ||
179 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) | |
180 | { | |
6af5d92f CW |
181 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
182 | _MASKED_BIT_DISABLE(0xffff)); | |
05adaf1f JN |
183 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
184 | _MASKED_BIT_DISABLE(0xffff)); | |
907b28c5 | 185 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
6af5d92f | 186 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
907b28c5 CW |
187 | } |
188 | ||
940aece4 | 189 | static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, |
b2cff0db | 190 | int fw_engine) |
907b28c5 | 191 | { |
940aece4 D |
192 | /* Check for Render Engine */ |
193 | if (FORCEWAKE_RENDER & fw_engine) { | |
95009861 MK |
194 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
195 | FORCEWAKE_ACK_VLV) & | |
196 | FORCEWAKE_KERNEL) == 0, | |
197 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
198 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); | |
940aece4 D |
199 | |
200 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, | |
201 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
202 | ||
203 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
204 | FORCEWAKE_ACK_VLV) & | |
205 | FORCEWAKE_KERNEL), | |
206 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
207 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); | |
208 | } | |
907b28c5 | 209 | |
940aece4 D |
210 | /* Check for Media Engine */ |
211 | if (FORCEWAKE_MEDIA & fw_engine) { | |
95009861 MK |
212 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
213 | FORCEWAKE_ACK_MEDIA_VLV) & | |
214 | FORCEWAKE_KERNEL) == 0, | |
215 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
216 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); | |
940aece4 D |
217 | |
218 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
219 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
220 | ||
221 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
222 | FORCEWAKE_ACK_MEDIA_VLV) & | |
223 | FORCEWAKE_KERNEL), | |
224 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
225 | DRM_ERROR("Timed out: waiting for media to ack.\n"); | |
226 | } | |
907b28c5 CW |
227 | } |
228 | ||
940aece4 | 229 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
b2cff0db | 230 | int fw_engine) |
907b28c5 | 231 | { |
940aece4 D |
232 | /* Check for Render Engine */ |
233 | if (FORCEWAKE_RENDER & fw_engine) | |
234 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, | |
235 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
236 | ||
237 | ||
238 | /* Check for Media Engine */ | |
239 | if (FORCEWAKE_MEDIA & fw_engine) | |
240 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | |
241 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
242 | ||
ab53c267 VS |
243 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
244 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); | |
245 | if (!IS_CHERRYVIEW(dev_priv->dev)) | |
246 | gen6_gt_check_fifodbg(dev_priv); | |
940aece4 D |
247 | } |
248 | ||
38cff0b1 ZW |
249 | static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
250 | { | |
251 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, | |
252 | _MASKED_BIT_DISABLE(0xffff)); | |
253 | ||
254 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, | |
255 | _MASKED_BIT_DISABLE(0xffff)); | |
256 | ||
257 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, | |
258 | _MASKED_BIT_DISABLE(0xffff)); | |
259 | } | |
260 | ||
261 | static void | |
262 | __gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) | |
263 | { | |
264 | /* Check for Render Engine */ | |
265 | if (FORCEWAKE_RENDER & fw_engine) { | |
266 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
267 | FORCEWAKE_ACK_RENDER_GEN9) & | |
268 | FORCEWAKE_KERNEL) == 0, | |
269 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
270 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); | |
271 | ||
272 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, | |
273 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
274 | ||
275 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
276 | FORCEWAKE_ACK_RENDER_GEN9) & | |
277 | FORCEWAKE_KERNEL), | |
278 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
279 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); | |
280 | } | |
281 | ||
282 | /* Check for Media Engine */ | |
283 | if (FORCEWAKE_MEDIA & fw_engine) { | |
284 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
285 | FORCEWAKE_ACK_MEDIA_GEN9) & | |
286 | FORCEWAKE_KERNEL) == 0, | |
287 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
288 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); | |
289 | ||
290 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, | |
291 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
292 | ||
293 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
294 | FORCEWAKE_ACK_MEDIA_GEN9) & | |
295 | FORCEWAKE_KERNEL), | |
296 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
297 | DRM_ERROR("Timed out: waiting for Media to ack.\n"); | |
298 | } | |
299 | ||
300 | /* Check for Blitter Engine */ | |
301 | if (FORCEWAKE_BLITTER & fw_engine) { | |
302 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
303 | FORCEWAKE_ACK_BLITTER_GEN9) & | |
304 | FORCEWAKE_KERNEL) == 0, | |
305 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
306 | DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n"); | |
307 | ||
308 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, | |
309 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
310 | ||
311 | if (wait_for_atomic((__raw_i915_read32(dev_priv, | |
312 | FORCEWAKE_ACK_BLITTER_GEN9) & | |
313 | FORCEWAKE_KERNEL), | |
314 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
315 | DRM_ERROR("Timed out: waiting for Blitter to ack.\n"); | |
316 | } | |
317 | } | |
318 | ||
319 | static void | |
320 | __gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) | |
321 | { | |
322 | /* Check for Render Engine */ | |
323 | if (FORCEWAKE_RENDER & fw_engine) | |
324 | __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9, | |
325 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
326 | ||
327 | /* Check for Media Engine */ | |
328 | if (FORCEWAKE_MEDIA & fw_engine) | |
329 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9, | |
330 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
331 | ||
332 | /* Check for Blitter Engine */ | |
333 | if (FORCEWAKE_BLITTER & fw_engine) | |
334 | __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9, | |
335 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
336 | } | |
337 | ||
b2cff0db | 338 | static void gen6_force_wake_timer(unsigned long arg) |
38cff0b1 | 339 | { |
b2cff0db CW |
340 | struct intel_uncore_forcewake_domain *domain = (void *)arg; |
341 | unsigned long irqflags; | |
38cff0b1 | 342 | |
b2cff0db | 343 | assert_device_not_suspended(domain->i915); |
38cff0b1 | 344 | |
b2cff0db CW |
345 | spin_lock_irqsave(&domain->i915->uncore.lock, irqflags); |
346 | if (WARN_ON(domain->wake_count == 0)) | |
347 | domain->wake_count++; | |
348 | ||
349 | if (--domain->wake_count == 0) | |
350 | domain->i915->uncore.funcs.force_wake_put(domain->i915, | |
351 | 1 << domain->id); | |
352 | ||
353 | spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags); | |
38cff0b1 ZW |
354 | } |
355 | ||
b2cff0db | 356 | void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
38cff0b1 | 357 | { |
b2cff0db CW |
358 | struct drm_i915_private *dev_priv = dev->dev_private; |
359 | unsigned long irqflags, fw = 0; | |
360 | struct intel_uncore_forcewake_domain *domain; | |
361 | int id, active_domains, retry_count = 100; | |
38cff0b1 | 362 | |
b2cff0db CW |
363 | /* Hold uncore.lock across reset to prevent any register access |
364 | * with forcewake not set correctly. Wait until all pending | |
365 | * timers are run before holding. | |
366 | */ | |
367 | while (1) { | |
368 | active_domains = 0; | |
38cff0b1 | 369 | |
b2cff0db CW |
370 | for_each_fw_domain(domain, dev_priv, id) { |
371 | if (del_timer_sync(&domain->timer) == 0) | |
372 | continue; | |
38cff0b1 | 373 | |
b2cff0db CW |
374 | gen6_force_wake_timer((unsigned long)domain); |
375 | } | |
aec347ab | 376 | |
b2cff0db | 377 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
b2ec142c | 378 | |
b2cff0db CW |
379 | for_each_fw_domain(domain, dev_priv, id) { |
380 | if (timer_pending(&domain->timer)) | |
381 | active_domains |= (1 << id); | |
382 | } | |
3123fcaf | 383 | |
b2cff0db CW |
384 | if (active_domains == 0) |
385 | break; | |
aec347ab | 386 | |
b2cff0db CW |
387 | if (--retry_count == 0) { |
388 | DRM_ERROR("Timed out waiting for forcewake timers to finish\n"); | |
389 | break; | |
390 | } | |
0294ae7b | 391 | |
b2cff0db CW |
392 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
393 | cond_resched(); | |
394 | } | |
0294ae7b | 395 | |
b2cff0db CW |
396 | WARN_ON(active_domains); |
397 | ||
398 | for_each_fw_domain(domain, dev_priv, id) | |
399 | if (domain->wake_count) | |
400 | fw |= 1 << id; | |
401 | ||
402 | if (fw) | |
403 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw); | |
ef46e0d2 | 404 | |
0a089e33 | 405 | if (IS_VALLEYVIEW(dev)) |
ef46e0d2 | 406 | vlv_force_wake_reset(dev_priv); |
0a089e33 | 407 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
ef46e0d2 | 408 | __gen6_gt_force_wake_reset(dev_priv); |
0a089e33 | 409 | |
f98cd096 | 410 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) |
6a68735a | 411 | __gen7_gt_force_wake_mt_reset(dev_priv); |
0294ae7b | 412 | |
38cff0b1 ZW |
413 | if (IS_GEN9(dev)) |
414 | __gen9_gt_force_wake_mt_reset(dev_priv); | |
415 | ||
0294ae7b | 416 | if (restore) { /* If reset with a user forcewake, try to restore */ |
0294ae7b CW |
417 | if (fw) |
418 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); | |
419 | ||
420 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
421 | dev_priv->uncore.fifo_count = | |
422 | __raw_i915_read32(dev_priv, GTFIFOCTL) & | |
423 | GT_FIFO_FREE_ENTRIES_MASK; | |
0294ae7b CW |
424 | } |
425 | ||
b2cff0db CW |
426 | if (!restore) |
427 | assert_force_wake_inactive(dev_priv); | |
428 | ||
0294ae7b | 429 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
ef46e0d2 DV |
430 | } |
431 | ||
ed493883 ID |
432 | static void __intel_uncore_early_sanitize(struct drm_device *dev, |
433 | bool restore_forcewake) | |
907b28c5 CW |
434 | { |
435 | struct drm_i915_private *dev_priv = dev->dev_private; | |
436 | ||
437 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) | |
6af5d92f | 438 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
18ce3994 | 439 | |
1d2866ba | 440 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
18ce3994 BW |
441 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { |
442 | /* The docs do not explain exactly how the calculation can be | |
443 | * made. It is somewhat guessable, but for now, it's always | |
444 | * 128MB. | |
445 | * NB: We can't write IDICR yet because we do not have gt funcs | |
446 | * set up */ | |
447 | dev_priv->ellc_size = 128; | |
448 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); | |
449 | } | |
907b28c5 | 450 | |
97058870 VS |
451 | /* clear out old GT FIFO errors */ |
452 | if (IS_GEN6(dev) || IS_GEN7(dev)) | |
453 | __raw_i915_write32(dev_priv, GTFIFODBG, | |
454 | __raw_i915_read32(dev_priv, GTFIFODBG)); | |
455 | ||
10018603 | 456 | intel_uncore_forcewake_reset(dev, restore_forcewake); |
521198a2 MK |
457 | } |
458 | ||
ed493883 ID |
459 | void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) |
460 | { | |
461 | __intel_uncore_early_sanitize(dev, restore_forcewake); | |
462 | i915_check_and_clear_faults(dev); | |
463 | } | |
464 | ||
521198a2 MK |
465 | void intel_uncore_sanitize(struct drm_device *dev) |
466 | { | |
907b28c5 CW |
467 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
468 | intel_disable_gt_powersave(dev); | |
469 | } | |
470 | ||
471 | /* | |
472 | * Generally this is called implicitly by the register read function. However, | |
473 | * if some sequence requires the GT to not power down then this function should | |
474 | * be called at the beginning of the sequence followed by a call to | |
475 | * gen6_gt_force_wake_put() at the end of the sequence. | |
476 | */ | |
b2cff0db CW |
477 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
478 | unsigned fw_domains) | |
907b28c5 CW |
479 | { |
480 | unsigned long irqflags; | |
b2cff0db CW |
481 | struct intel_uncore_forcewake_domain *domain; |
482 | int id; | |
907b28c5 | 483 | |
ab484f8f BW |
484 | if (!dev_priv->uncore.funcs.force_wake_get) |
485 | return; | |
486 | ||
6daccb0b | 487 | WARN_ON(dev_priv->pm.suspended); |
c8c8fb33 | 488 | |
b2cff0db CW |
489 | fw_domains &= dev_priv->uncore.fw_domains; |
490 | ||
6daccb0b | 491 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
38cff0b1 | 492 | |
b2cff0db CW |
493 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { |
494 | if (domain->wake_count++) | |
495 | fw_domains &= ~(1 << id); | |
6daccb0b | 496 | } |
940aece4 | 497 | |
b2cff0db CW |
498 | if (fw_domains) |
499 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
500 | ||
907b28c5 CW |
501 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
502 | } | |
503 | ||
504 | /* | |
505 | * see gen6_gt_force_wake_get() | |
506 | */ | |
b2cff0db CW |
507 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
508 | unsigned fw_domains) | |
907b28c5 CW |
509 | { |
510 | unsigned long irqflags; | |
b2cff0db CW |
511 | struct intel_uncore_forcewake_domain *domain; |
512 | int id; | |
907b28c5 | 513 | |
ab484f8f BW |
514 | if (!dev_priv->uncore.funcs.force_wake_put) |
515 | return; | |
516 | ||
b2cff0db CW |
517 | fw_domains &= dev_priv->uncore.fw_domains; |
518 | ||
6daccb0b CW |
519 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
520 | ||
b2cff0db CW |
521 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) { |
522 | if (WARN_ON(domain->wake_count == 0)) | |
523 | continue; | |
524 | ||
525 | if (--domain->wake_count) | |
526 | continue; | |
527 | ||
528 | domain->wake_count++; | |
529 | mod_timer_pinned(&domain->timer, jiffies + 1); | |
aec347ab | 530 | } |
dc9fb09c | 531 | |
907b28c5 CW |
532 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
533 | } | |
534 | ||
e998c40f PZ |
535 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv) |
536 | { | |
b2cff0db CW |
537 | struct intel_uncore_forcewake_domain *domain; |
538 | int i; | |
539 | ||
e998c40f PZ |
540 | if (!dev_priv->uncore.funcs.force_wake_get) |
541 | return; | |
542 | ||
b2cff0db CW |
543 | for_each_fw_domain(domain, dev_priv, i) |
544 | WARN_ON(domain->wake_count); | |
e998c40f PZ |
545 | } |
546 | ||
907b28c5 CW |
547 | /* We give fast paths for the really cool registers */ |
548 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
ab484f8f | 549 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
907b28c5 | 550 | |
1938e59a | 551 | #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) |
38fb6a40 | 552 | |
1938e59a D |
553 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
554 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
555 | REG_RANGE((reg), 0x5000, 0x8000) || \ | |
556 | REG_RANGE((reg), 0xB000, 0x12000) || \ | |
557 | REG_RANGE((reg), 0x2E000, 0x30000)) | |
558 | ||
559 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ | |
560 | (REG_RANGE((reg), 0x12000, 0x14000) || \ | |
561 | REG_RANGE((reg), 0x22000, 0x24000) || \ | |
562 | REG_RANGE((reg), 0x30000, 0x40000)) | |
563 | ||
564 | #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ | |
565 | (REG_RANGE((reg), 0x2000, 0x4000) || \ | |
db5ff4ac | 566 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
1938e59a | 567 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
db5ff4ac | 568 | REG_RANGE((reg), 0xB000, 0xB480) || \ |
1938e59a D |
569 | REG_RANGE((reg), 0xE000, 0xE800)) |
570 | ||
571 | #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ | |
572 | (REG_RANGE((reg), 0x8800, 0x8900) || \ | |
573 | REG_RANGE((reg), 0xD000, 0xD800) || \ | |
574 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
575 | REG_RANGE((reg), 0x1A000, 0x1C000) || \ | |
576 | REG_RANGE((reg), 0x1E800, 0x1EA00) || \ | |
db5ff4ac | 577 | REG_RANGE((reg), 0x30000, 0x38000)) |
1938e59a D |
578 | |
579 | #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ | |
580 | (REG_RANGE((reg), 0x4000, 0x5000) || \ | |
581 | REG_RANGE((reg), 0x8000, 0x8300) || \ | |
582 | REG_RANGE((reg), 0x8500, 0x8600) || \ | |
583 | REG_RANGE((reg), 0x9000, 0xB000) || \ | |
db5ff4ac | 584 | REG_RANGE((reg), 0xF000, 0x10000)) |
38fb6a40 | 585 | |
4597a88a | 586 | #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \ |
8ee558d8 | 587 | REG_RANGE((reg), 0xB00, 0x2000) |
4597a88a ZW |
588 | |
589 | #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
590 | (REG_RANGE((reg), 0x2000, 0x2700) || \ |
591 | REG_RANGE((reg), 0x3000, 0x4000) || \ | |
4597a88a | 592 | REG_RANGE((reg), 0x5200, 0x8000) || \ |
8ee558d8 | 593 | REG_RANGE((reg), 0x8140, 0x8160) || \ |
4597a88a ZW |
594 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
595 | REG_RANGE((reg), 0x8C00, 0x8D00) || \ | |
596 | REG_RANGE((reg), 0xB000, 0xB480) || \ | |
8ee558d8 AG |
597 | REG_RANGE((reg), 0xE000, 0xE900) || \ |
598 | REG_RANGE((reg), 0x24400, 0x24800)) | |
4597a88a ZW |
599 | |
600 | #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \ | |
8ee558d8 AG |
601 | (REG_RANGE((reg), 0x8130, 0x8140) || \ |
602 | REG_RANGE((reg), 0x8800, 0x8A00) || \ | |
4597a88a ZW |
603 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
604 | REG_RANGE((reg), 0x12000, 0x14000) || \ | |
605 | REG_RANGE((reg), 0x1A000, 0x1EA00) || \ | |
606 | REG_RANGE((reg), 0x30000, 0x40000)) | |
607 | ||
608 | #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \ | |
609 | REG_RANGE((reg), 0x9400, 0x9800) | |
610 | ||
611 | #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \ | |
612 | ((reg) < 0x40000 &&\ | |
613 | !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \ | |
614 | !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \ | |
615 | !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \ | |
616 | !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) | |
617 | ||
907b28c5 CW |
618 | static void |
619 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
620 | { | |
621 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
622 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
623 | * hence harmless to write 0 into. */ | |
6af5d92f | 624 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
907b28c5 CW |
625 | } |
626 | ||
627 | static void | |
5978118c PZ |
628 | hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, |
629 | bool before) | |
907b28c5 | 630 | { |
5978118c PZ |
631 | const char *op = read ? "reading" : "writing to"; |
632 | const char *when = before ? "before" : "after"; | |
633 | ||
634 | if (!i915.mmio_debug) | |
635 | return; | |
636 | ||
ab484f8f | 637 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
5978118c PZ |
638 | WARN(1, "Unclaimed register detected %s %s register 0x%x\n", |
639 | when, op, reg); | |
6af5d92f | 640 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
641 | } |
642 | } | |
643 | ||
644 | static void | |
5978118c | 645 | hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv) |
907b28c5 | 646 | { |
5978118c PZ |
647 | if (i915.mmio_debug) |
648 | return; | |
649 | ||
ab484f8f | 650 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
5978118c | 651 | DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem."); |
6af5d92f | 652 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
653 | } |
654 | } | |
655 | ||
51f67885 | 656 | #define GEN2_READ_HEADER(x) \ |
5d738795 | 657 | u##x val = 0; \ |
51f67885 | 658 | assert_device_not_suspended(dev_priv); |
5d738795 | 659 | |
51f67885 | 660 | #define GEN2_READ_FOOTER \ |
5d738795 BW |
661 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
662 | return val | |
663 | ||
51f67885 | 664 | #define __gen2_read(x) \ |
0b274481 | 665 | static u##x \ |
51f67885 CW |
666 | gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
667 | GEN2_READ_HEADER(x); \ | |
3967018e | 668 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 669 | GEN2_READ_FOOTER; \ |
3967018e BW |
670 | } |
671 | ||
672 | #define __gen5_read(x) \ | |
673 | static u##x \ | |
674 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
51f67885 | 675 | GEN2_READ_HEADER(x); \ |
3967018e BW |
676 | ilk_dummy_write(dev_priv); \ |
677 | val = __raw_i915_read##x(dev_priv, reg); \ | |
51f67885 | 678 | GEN2_READ_FOOTER; \ |
3967018e BW |
679 | } |
680 | ||
51f67885 CW |
681 | __gen5_read(8) |
682 | __gen5_read(16) | |
683 | __gen5_read(32) | |
684 | __gen5_read(64) | |
685 | __gen2_read(8) | |
686 | __gen2_read(16) | |
687 | __gen2_read(32) | |
688 | __gen2_read(64) | |
689 | ||
690 | #undef __gen5_read | |
691 | #undef __gen2_read | |
692 | ||
693 | #undef GEN2_READ_FOOTER | |
694 | #undef GEN2_READ_HEADER | |
695 | ||
696 | #define GEN6_READ_HEADER(x) \ | |
697 | unsigned long irqflags; \ | |
698 | u##x val = 0; \ | |
699 | assert_device_not_suspended(dev_priv); \ | |
700 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
701 | ||
702 | #define GEN6_READ_FOOTER \ | |
703 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
704 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ | |
705 | return val | |
706 | ||
b2cff0db CW |
707 | static inline void __force_wake_get(struct drm_i915_private *dev_priv, |
708 | unsigned fw_domains) | |
709 | { | |
710 | struct intel_uncore_forcewake_domain *domain; | |
711 | int i; | |
712 | ||
713 | if (WARN_ON(!fw_domains)) | |
714 | return; | |
715 | ||
716 | /* Ideally GCC would be constant-fold and eliminate this loop */ | |
717 | for_each_fw_domain_mask(domain, fw_domains, dev_priv, i) { | |
718 | if (domain->wake_count) { | |
719 | fw_domains &= ~(1 << i); | |
720 | continue; | |
721 | } | |
722 | ||
723 | domain->wake_count++; | |
724 | mod_timer_pinned(&domain->timer, jiffies + 1); | |
725 | } | |
726 | ||
727 | if (fw_domains) | |
728 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains); | |
729 | } | |
730 | ||
3967018e BW |
731 | #define __gen6_read(x) \ |
732 | static u##x \ | |
733 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
51f67885 | 734 | GEN6_READ_HEADER(x); \ |
5978118c | 735 | hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ |
b2cff0db CW |
736 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) \ |
737 | __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ | |
dc9fb09c | 738 | val = __raw_i915_read##x(dev_priv, reg); \ |
5978118c | 739 | hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ |
51f67885 | 740 | GEN6_READ_FOOTER; \ |
907b28c5 CW |
741 | } |
742 | ||
940aece4 D |
743 | #define __vlv_read(x) \ |
744 | static u##x \ | |
745 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
51f67885 | 746 | GEN6_READ_HEADER(x); \ |
b2cff0db CW |
747 | if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \ |
748 | __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ | |
749 | else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \ | |
750 | __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \ | |
6fe72865 | 751 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 752 | GEN6_READ_FOOTER; \ |
940aece4 D |
753 | } |
754 | ||
1938e59a D |
755 | #define __chv_read(x) \ |
756 | static u##x \ | |
757 | chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
51f67885 | 758 | GEN6_READ_HEADER(x); \ |
b2cff0db CW |
759 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \ |
760 | __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ | |
761 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \ | |
762 | __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \ | |
763 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \ | |
764 | __force_wake_get(dev_priv, \ | |
765 | FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \ | |
1938e59a | 766 | val = __raw_i915_read##x(dev_priv, reg); \ |
51f67885 | 767 | GEN6_READ_FOOTER; \ |
1938e59a | 768 | } |
940aece4 | 769 | |
4597a88a ZW |
770 | #define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \ |
771 | ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg)) | |
772 | ||
773 | #define __gen9_read(x) \ | |
774 | static u##x \ | |
775 | gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ | |
b2cff0db | 776 | unsigned fw_engine; \ |
51f67885 | 777 | GEN6_READ_HEADER(x); \ |
b2cff0db CW |
778 | if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) \ |
779 | fw_engine = 0; \ | |
780 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \ | |
781 | fw_engine = FORCEWAKE_RENDER; \ | |
782 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \ | |
783 | fw_engine = FORCEWAKE_MEDIA; \ | |
784 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \ | |
785 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ | |
786 | else \ | |
787 | fw_engine = FORCEWAKE_BLITTER; \ | |
788 | if (fw_engine) \ | |
789 | __force_wake_get(dev_priv, fw_engine); \ | |
790 | val = __raw_i915_read##x(dev_priv, reg); \ | |
51f67885 | 791 | GEN6_READ_FOOTER; \ |
4597a88a ZW |
792 | } |
793 | ||
794 | __gen9_read(8) | |
795 | __gen9_read(16) | |
796 | __gen9_read(32) | |
797 | __gen9_read(64) | |
1938e59a D |
798 | __chv_read(8) |
799 | __chv_read(16) | |
800 | __chv_read(32) | |
801 | __chv_read(64) | |
940aece4 D |
802 | __vlv_read(8) |
803 | __vlv_read(16) | |
804 | __vlv_read(32) | |
805 | __vlv_read(64) | |
3967018e BW |
806 | __gen6_read(8) |
807 | __gen6_read(16) | |
808 | __gen6_read(32) | |
809 | __gen6_read(64) | |
3967018e | 810 | |
4597a88a | 811 | #undef __gen9_read |
1938e59a | 812 | #undef __chv_read |
940aece4 | 813 | #undef __vlv_read |
3967018e | 814 | #undef __gen6_read |
51f67885 CW |
815 | #undef GEN6_READ_FOOTER |
816 | #undef GEN6_READ_HEADER | |
5d738795 | 817 | |
51f67885 | 818 | #define GEN2_WRITE_HEADER \ |
5d738795 | 819 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
6f0ea9e2 | 820 | assert_device_not_suspended(dev_priv); \ |
907b28c5 | 821 | |
51f67885 | 822 | #define GEN2_WRITE_FOOTER |
0d965301 | 823 | |
51f67885 | 824 | #define __gen2_write(x) \ |
0b274481 | 825 | static void \ |
51f67885 CW |
826 | gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
827 | GEN2_WRITE_HEADER; \ | |
4032ef43 | 828 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 829 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
830 | } |
831 | ||
832 | #define __gen5_write(x) \ | |
833 | static void \ | |
834 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
51f67885 | 835 | GEN2_WRITE_HEADER; \ |
4032ef43 BW |
836 | ilk_dummy_write(dev_priv); \ |
837 | __raw_i915_write##x(dev_priv, reg, val); \ | |
51f67885 | 838 | GEN2_WRITE_FOOTER; \ |
4032ef43 BW |
839 | } |
840 | ||
51f67885 CW |
841 | __gen5_write(8) |
842 | __gen5_write(16) | |
843 | __gen5_write(32) | |
844 | __gen5_write(64) | |
845 | __gen2_write(8) | |
846 | __gen2_write(16) | |
847 | __gen2_write(32) | |
848 | __gen2_write(64) | |
849 | ||
850 | #undef __gen5_write | |
851 | #undef __gen2_write | |
852 | ||
853 | #undef GEN2_WRITE_FOOTER | |
854 | #undef GEN2_WRITE_HEADER | |
855 | ||
856 | #define GEN6_WRITE_HEADER \ | |
857 | unsigned long irqflags; \ | |
858 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ | |
859 | assert_device_not_suspended(dev_priv); \ | |
860 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) | |
861 | ||
862 | #define GEN6_WRITE_FOOTER \ | |
863 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) | |
864 | ||
4032ef43 BW |
865 | #define __gen6_write(x) \ |
866 | static void \ | |
867 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
868 | u32 __fifo_ret = 0; \ | |
51f67885 | 869 | GEN6_WRITE_HEADER; \ |
4032ef43 BW |
870 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
871 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
872 | } \ | |
873 | __raw_i915_write##x(dev_priv, reg, val); \ | |
874 | if (unlikely(__fifo_ret)) { \ | |
875 | gen6_gt_check_fifodbg(dev_priv); \ | |
876 | } \ | |
51f67885 | 877 | GEN6_WRITE_FOOTER; \ |
4032ef43 BW |
878 | } |
879 | ||
880 | #define __hsw_write(x) \ | |
881 | static void \ | |
882 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
907b28c5 | 883 | u32 __fifo_ret = 0; \ |
51f67885 | 884 | GEN6_WRITE_HEADER; \ |
907b28c5 CW |
885 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
886 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
887 | } \ | |
5978118c | 888 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
6af5d92f | 889 | __raw_i915_write##x(dev_priv, reg, val); \ |
907b28c5 CW |
890 | if (unlikely(__fifo_ret)) { \ |
891 | gen6_gt_check_fifodbg(dev_priv); \ | |
892 | } \ | |
5978118c PZ |
893 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
894 | hsw_unclaimed_reg_detect(dev_priv); \ | |
51f67885 | 895 | GEN6_WRITE_FOOTER; \ |
907b28c5 | 896 | } |
3967018e | 897 | |
ab2aa47e BW |
898 | static const u32 gen8_shadowed_regs[] = { |
899 | FORCEWAKE_MT, | |
900 | GEN6_RPNSWREQ, | |
901 | GEN6_RC_VIDEO_FREQ, | |
902 | RING_TAIL(RENDER_RING_BASE), | |
903 | RING_TAIL(GEN6_BSD_RING_BASE), | |
904 | RING_TAIL(VEBOX_RING_BASE), | |
905 | RING_TAIL(BLT_RING_BASE), | |
906 | /* TODO: Other registers are not yet used */ | |
907 | }; | |
908 | ||
909 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) | |
910 | { | |
911 | int i; | |
912 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) | |
913 | if (reg == gen8_shadowed_regs[i]) | |
914 | return true; | |
915 | ||
916 | return false; | |
917 | } | |
918 | ||
919 | #define __gen8_write(x) \ | |
920 | static void \ | |
921 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
51f67885 | 922 | GEN6_WRITE_HEADER; \ |
66bc2cab | 923 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
b2cff0db CW |
924 | if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \ |
925 | __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ | |
926 | __raw_i915_write##x(dev_priv, reg, val); \ | |
66bc2cab PZ |
927 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
928 | hsw_unclaimed_reg_detect(dev_priv); \ | |
51f67885 | 929 | GEN6_WRITE_FOOTER; \ |
ab2aa47e BW |
930 | } |
931 | ||
1938e59a D |
932 | #define __chv_write(x) \ |
933 | static void \ | |
934 | chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ | |
1938e59a | 935 | bool shadowed = is_gen8_shadowed(dev_priv, reg); \ |
51f67885 | 936 | GEN6_WRITE_HEADER; \ |
1938e59a | 937 | if (!shadowed) { \ |
b2cff0db CW |
938 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \ |
939 | __force_wake_get(dev_priv, FORCEWAKE_RENDER); \ | |
940 | else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \ | |
941 | __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \ | |
942 | else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \ | |
943 | __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \ | |
1938e59a | 944 | } \ |
1938e59a | 945 | __raw_i915_write##x(dev_priv, reg, val); \ |
51f67885 | 946 | GEN6_WRITE_FOOTER; \ |
1938e59a D |
947 | } |
948 | ||
7c859007 ZW |
949 | static const u32 gen9_shadowed_regs[] = { |
950 | RING_TAIL(RENDER_RING_BASE), | |
951 | RING_TAIL(GEN6_BSD_RING_BASE), | |
952 | RING_TAIL(VEBOX_RING_BASE), | |
953 | RING_TAIL(BLT_RING_BASE), | |
954 | FORCEWAKE_BLITTER_GEN9, | |
955 | FORCEWAKE_RENDER_GEN9, | |
956 | FORCEWAKE_MEDIA_GEN9, | |
957 | GEN6_RPNSWREQ, | |
958 | GEN6_RC_VIDEO_FREQ, | |
959 | /* TODO: Other registers are not yet used */ | |
960 | }; | |
961 | ||
962 | static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg) | |
963 | { | |
964 | int i; | |
965 | for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++) | |
966 | if (reg == gen9_shadowed_regs[i]) | |
967 | return true; | |
968 | ||
969 | return false; | |
970 | } | |
971 | ||
4597a88a ZW |
972 | #define __gen9_write(x) \ |
973 | static void \ | |
974 | gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \ | |
975 | bool trace) { \ | |
b2cff0db | 976 | unsigned fw_engine; \ |
51f67885 | 977 | GEN6_WRITE_HEADER; \ |
b2cff0db CW |
978 | if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \ |
979 | is_gen9_shadowed(dev_priv, reg)) \ | |
980 | fw_engine = 0; \ | |
981 | else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \ | |
982 | fw_engine = FORCEWAKE_RENDER; \ | |
983 | else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \ | |
984 | fw_engine = FORCEWAKE_MEDIA; \ | |
985 | else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \ | |
986 | fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \ | |
987 | else \ | |
988 | fw_engine = FORCEWAKE_BLITTER; \ | |
989 | if (fw_engine) \ | |
990 | __force_wake_get(dev_priv, fw_engine); \ | |
991 | __raw_i915_write##x(dev_priv, reg, val); \ | |
51f67885 | 992 | GEN6_WRITE_FOOTER; \ |
4597a88a ZW |
993 | } |
994 | ||
995 | __gen9_write(8) | |
996 | __gen9_write(16) | |
997 | __gen9_write(32) | |
998 | __gen9_write(64) | |
1938e59a D |
999 | __chv_write(8) |
1000 | __chv_write(16) | |
1001 | __chv_write(32) | |
1002 | __chv_write(64) | |
ab2aa47e BW |
1003 | __gen8_write(8) |
1004 | __gen8_write(16) | |
1005 | __gen8_write(32) | |
1006 | __gen8_write(64) | |
4032ef43 BW |
1007 | __hsw_write(8) |
1008 | __hsw_write(16) | |
1009 | __hsw_write(32) | |
1010 | __hsw_write(64) | |
1011 | __gen6_write(8) | |
1012 | __gen6_write(16) | |
1013 | __gen6_write(32) | |
1014 | __gen6_write(64) | |
4032ef43 | 1015 | |
4597a88a | 1016 | #undef __gen9_write |
1938e59a | 1017 | #undef __chv_write |
ab2aa47e | 1018 | #undef __gen8_write |
4032ef43 BW |
1019 | #undef __hsw_write |
1020 | #undef __gen6_write | |
51f67885 CW |
1021 | #undef GEN6_WRITE_FOOTER |
1022 | #undef GEN6_WRITE_HEADER | |
907b28c5 | 1023 | |
43d942a7 YZ |
1024 | #define ASSIGN_WRITE_MMIO_VFUNCS(x) \ |
1025 | do { \ | |
1026 | dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ | |
1027 | dev_priv->uncore.funcs.mmio_writew = x##_write16; \ | |
1028 | dev_priv->uncore.funcs.mmio_writel = x##_write32; \ | |
1029 | dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ | |
1030 | } while (0) | |
1031 | ||
1032 | #define ASSIGN_READ_MMIO_VFUNCS(x) \ | |
1033 | do { \ | |
1034 | dev_priv->uncore.funcs.mmio_readb = x##_read8; \ | |
1035 | dev_priv->uncore.funcs.mmio_readw = x##_read16; \ | |
1036 | dev_priv->uncore.funcs.mmio_readl = x##_read32; \ | |
1037 | dev_priv->uncore.funcs.mmio_readq = x##_read64; \ | |
1038 | } while (0) | |
1039 | ||
0b274481 BW |
1040 | void intel_uncore_init(struct drm_device *dev) |
1041 | { | |
1042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b2cff0db CW |
1043 | struct intel_uncore_forcewake_domain *domain; |
1044 | int i; | |
0b274481 | 1045 | |
ed493883 | 1046 | __intel_uncore_early_sanitize(dev, false); |
05efeebd | 1047 | |
38cff0b1 ZW |
1048 | if (IS_GEN9(dev)) { |
1049 | dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get; | |
1050 | dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put; | |
b2cff0db CW |
1051 | dev_priv->uncore.fw_domains = FORCEWAKE_RENDER | |
1052 | FORCEWAKE_BLITTER | FORCEWAKE_MEDIA; | |
38cff0b1 | 1053 | } else if (IS_VALLEYVIEW(dev)) { |
940aece4 D |
1054 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
1055 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; | |
b2cff0db | 1056 | dev_priv->uncore.fw_domains = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; |
f98cd096 | 1057 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
6a68735a MK |
1058 | dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; |
1059 | dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; | |
b2cff0db | 1060 | dev_priv->uncore.fw_domains = FORCEWAKE_RENDER; |
0b274481 BW |
1061 | } else if (IS_IVYBRIDGE(dev)) { |
1062 | u32 ecobus; | |
1063 | ||
1064 | /* IVB configs may use multi-threaded forcewake */ | |
1065 | ||
1066 | /* A small trick here - if the bios hasn't configured | |
1067 | * MT forcewake, and if the device is in RC6, then | |
1068 | * force_wake_mt_get will not wake the device and the | |
1069 | * ECOBUS read will return zero. Which will be | |
1070 | * (correctly) interpreted by the test below as MT | |
1071 | * forcewake being disabled. | |
1072 | */ | |
1073 | mutex_lock(&dev->struct_mutex); | |
6a68735a | 1074 | __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); |
0b274481 | 1075 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
6a68735a | 1076 | __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); |
0b274481 BW |
1077 | mutex_unlock(&dev->struct_mutex); |
1078 | ||
1079 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
1080 | dev_priv->uncore.funcs.force_wake_get = | |
6a68735a | 1081 | __gen7_gt_force_wake_mt_get; |
0b274481 | 1082 | dev_priv->uncore.funcs.force_wake_put = |
6a68735a | 1083 | __gen7_gt_force_wake_mt_put; |
0b274481 BW |
1084 | } else { |
1085 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); | |
1086 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
1087 | dev_priv->uncore.funcs.force_wake_get = | |
1088 | __gen6_gt_force_wake_get; | |
1089 | dev_priv->uncore.funcs.force_wake_put = | |
1090 | __gen6_gt_force_wake_put; | |
1091 | } | |
b2cff0db | 1092 | dev_priv->uncore.fw_domains = FORCEWAKE_RENDER; |
0b274481 BW |
1093 | } else if (IS_GEN6(dev)) { |
1094 | dev_priv->uncore.funcs.force_wake_get = | |
1095 | __gen6_gt_force_wake_get; | |
1096 | dev_priv->uncore.funcs.force_wake_put = | |
1097 | __gen6_gt_force_wake_put; | |
b2cff0db CW |
1098 | dev_priv->uncore.fw_domains = FORCEWAKE_RENDER; |
1099 | } | |
1100 | ||
1101 | for_each_fw_domain(domain, dev_priv, i) { | |
1102 | domain->i915 = dev_priv; | |
1103 | domain->id = i; | |
1104 | ||
1105 | setup_timer(&domain->timer, gen6_force_wake_timer, | |
1106 | (unsigned long)domain); | |
0b274481 BW |
1107 | } |
1108 | ||
3967018e | 1109 | switch (INTEL_INFO(dev)->gen) { |
ab2aa47e | 1110 | default: |
5f77eeb0 | 1111 | MISSING_CASE(INTEL_INFO(dev)->gen); |
4597a88a ZW |
1112 | return; |
1113 | case 9: | |
1114 | ASSIGN_WRITE_MMIO_VFUNCS(gen9); | |
1115 | ASSIGN_READ_MMIO_VFUNCS(gen9); | |
1116 | break; | |
1117 | case 8: | |
1938e59a | 1118 | if (IS_CHERRYVIEW(dev)) { |
43d942a7 YZ |
1119 | ASSIGN_WRITE_MMIO_VFUNCS(chv); |
1120 | ASSIGN_READ_MMIO_VFUNCS(chv); | |
1938e59a D |
1121 | |
1122 | } else { | |
43d942a7 YZ |
1123 | ASSIGN_WRITE_MMIO_VFUNCS(gen8); |
1124 | ASSIGN_READ_MMIO_VFUNCS(gen6); | |
1938e59a | 1125 | } |
ab2aa47e | 1126 | break; |
3967018e BW |
1127 | case 7: |
1128 | case 6: | |
4032ef43 | 1129 | if (IS_HASWELL(dev)) { |
43d942a7 | 1130 | ASSIGN_WRITE_MMIO_VFUNCS(hsw); |
4032ef43 | 1131 | } else { |
43d942a7 | 1132 | ASSIGN_WRITE_MMIO_VFUNCS(gen6); |
4032ef43 | 1133 | } |
940aece4 D |
1134 | |
1135 | if (IS_VALLEYVIEW(dev)) { | |
43d942a7 | 1136 | ASSIGN_READ_MMIO_VFUNCS(vlv); |
940aece4 | 1137 | } else { |
43d942a7 | 1138 | ASSIGN_READ_MMIO_VFUNCS(gen6); |
940aece4 | 1139 | } |
3967018e BW |
1140 | break; |
1141 | case 5: | |
43d942a7 YZ |
1142 | ASSIGN_WRITE_MMIO_VFUNCS(gen5); |
1143 | ASSIGN_READ_MMIO_VFUNCS(gen5); | |
3967018e BW |
1144 | break; |
1145 | case 4: | |
1146 | case 3: | |
1147 | case 2: | |
51f67885 CW |
1148 | ASSIGN_WRITE_MMIO_VFUNCS(gen2); |
1149 | ASSIGN_READ_MMIO_VFUNCS(gen2); | |
3967018e BW |
1150 | break; |
1151 | } | |
ed493883 ID |
1152 | |
1153 | i915_check_and_clear_faults(dev); | |
0b274481 | 1154 | } |
43d942a7 YZ |
1155 | #undef ASSIGN_WRITE_MMIO_VFUNCS |
1156 | #undef ASSIGN_READ_MMIO_VFUNCS | |
0b274481 BW |
1157 | |
1158 | void intel_uncore_fini(struct drm_device *dev) | |
1159 | { | |
0b274481 BW |
1160 | /* Paranoia: make sure we have disabled everything before we exit. */ |
1161 | intel_uncore_sanitize(dev); | |
0294ae7b | 1162 | intel_uncore_forcewake_reset(dev, false); |
0b274481 BW |
1163 | } |
1164 | ||
af76ae44 DL |
1165 | #define GEN_RANGE(l, h) GENMASK(h, l) |
1166 | ||
907b28c5 CW |
1167 | static const struct register_whitelist { |
1168 | uint64_t offset; | |
1169 | uint32_t size; | |
af76ae44 DL |
1170 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
1171 | uint32_t gen_bitmask; | |
907b28c5 | 1172 | } whitelist[] = { |
c3f59a67 | 1173 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) }, |
907b28c5 CW |
1174 | }; |
1175 | ||
1176 | int i915_reg_read_ioctl(struct drm_device *dev, | |
1177 | void *data, struct drm_file *file) | |
1178 | { | |
1179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1180 | struct drm_i915_reg_read *reg = data; | |
1181 | struct register_whitelist const *entry = whitelist; | |
cf67c70f | 1182 | int i, ret = 0; |
907b28c5 CW |
1183 | |
1184 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
1185 | if (entry->offset == reg->offset && | |
1186 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | |
1187 | break; | |
1188 | } | |
1189 | ||
1190 | if (i == ARRAY_SIZE(whitelist)) | |
1191 | return -EINVAL; | |
1192 | ||
cf67c70f PZ |
1193 | intel_runtime_pm_get(dev_priv); |
1194 | ||
907b28c5 CW |
1195 | switch (entry->size) { |
1196 | case 8: | |
1197 | reg->val = I915_READ64(reg->offset); | |
1198 | break; | |
1199 | case 4: | |
1200 | reg->val = I915_READ(reg->offset); | |
1201 | break; | |
1202 | case 2: | |
1203 | reg->val = I915_READ16(reg->offset); | |
1204 | break; | |
1205 | case 1: | |
1206 | reg->val = I915_READ8(reg->offset); | |
1207 | break; | |
1208 | default: | |
5f77eeb0 | 1209 | MISSING_CASE(entry->size); |
cf67c70f PZ |
1210 | ret = -EINVAL; |
1211 | goto out; | |
907b28c5 CW |
1212 | } |
1213 | ||
cf67c70f PZ |
1214 | out: |
1215 | intel_runtime_pm_put(dev_priv); | |
1216 | return ret; | |
907b28c5 CW |
1217 | } |
1218 | ||
b6359918 MK |
1219 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
1220 | void *data, struct drm_file *file) | |
1221 | { | |
1222 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1223 | struct drm_i915_reset_stats *args = data; | |
1224 | struct i915_ctx_hang_stats *hs; | |
273497e5 | 1225 | struct intel_context *ctx; |
b6359918 MK |
1226 | int ret; |
1227 | ||
661df041 MK |
1228 | if (args->flags || args->pad) |
1229 | return -EINVAL; | |
1230 | ||
821d66dd | 1231 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) |
b6359918 MK |
1232 | return -EPERM; |
1233 | ||
1234 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
1235 | if (ret) | |
1236 | return ret; | |
1237 | ||
41bde553 BW |
1238 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
1239 | if (IS_ERR(ctx)) { | |
b6359918 | 1240 | mutex_unlock(&dev->struct_mutex); |
41bde553 | 1241 | return PTR_ERR(ctx); |
b6359918 | 1242 | } |
41bde553 | 1243 | hs = &ctx->hang_stats; |
b6359918 MK |
1244 | |
1245 | if (capable(CAP_SYS_ADMIN)) | |
1246 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); | |
1247 | else | |
1248 | args->reset_count = 0; | |
1249 | ||
1250 | args->batch_active = hs->batch_active; | |
1251 | args->batch_pending = hs->batch_pending; | |
1252 | ||
1253 | mutex_unlock(&dev->struct_mutex); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
59ea9054 | 1258 | static int i915_reset_complete(struct drm_device *dev) |
907b28c5 CW |
1259 | { |
1260 | u8 gdrst; | |
59ea9054 | 1261 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1262 | return (gdrst & GRDOM_RESET_STATUS) == 0; |
907b28c5 CW |
1263 | } |
1264 | ||
59ea9054 | 1265 | static int i915_do_reset(struct drm_device *dev) |
907b28c5 | 1266 | { |
73bbf6bd | 1267 | /* assert reset for at least 20 usec */ |
59ea9054 | 1268 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
73bbf6bd | 1269 | udelay(20); |
59ea9054 | 1270 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
907b28c5 | 1271 | |
59ea9054 | 1272 | return wait_for(i915_reset_complete(dev), 500); |
73bbf6bd VS |
1273 | } |
1274 | ||
1275 | static int g4x_reset_complete(struct drm_device *dev) | |
1276 | { | |
1277 | u8 gdrst; | |
59ea9054 | 1278 | pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst); |
73bbf6bd | 1279 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
907b28c5 CW |
1280 | } |
1281 | ||
408d4b9e VS |
1282 | static int g33_do_reset(struct drm_device *dev) |
1283 | { | |
408d4b9e VS |
1284 | pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE); |
1285 | return wait_for(g4x_reset_complete(dev), 500); | |
1286 | } | |
1287 | ||
fa4f53c4 VS |
1288 | static int g4x_do_reset(struct drm_device *dev) |
1289 | { | |
1290 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1291 | int ret; | |
1292 | ||
59ea9054 | 1293 | pci_write_config_byte(dev->pdev, I915_GDRST, |
fa4f53c4 | 1294 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
73bbf6bd | 1295 | ret = wait_for(g4x_reset_complete(dev), 500); |
fa4f53c4 VS |
1296 | if (ret) |
1297 | return ret; | |
1298 | ||
1299 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1300 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); | |
1301 | POSTING_READ(VDECCLK_GATE_D); | |
1302 | ||
59ea9054 | 1303 | pci_write_config_byte(dev->pdev, I915_GDRST, |
fa4f53c4 | 1304 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
73bbf6bd | 1305 | ret = wait_for(g4x_reset_complete(dev), 500); |
fa4f53c4 VS |
1306 | if (ret) |
1307 | return ret; | |
1308 | ||
1309 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ | |
1310 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); | |
1311 | POSTING_READ(VDECCLK_GATE_D); | |
1312 | ||
59ea9054 | 1313 | pci_write_config_byte(dev->pdev, I915_GDRST, 0); |
fa4f53c4 VS |
1314 | |
1315 | return 0; | |
1316 | } | |
1317 | ||
907b28c5 CW |
1318 | static int ironlake_do_reset(struct drm_device *dev) |
1319 | { | |
1320 | struct drm_i915_private *dev_priv = dev->dev_private; | |
907b28c5 CW |
1321 | int ret; |
1322 | ||
907b28c5 | 1323 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
0f08ffd6 | 1324 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
f67deb72 | 1325 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
b3a3f03d | 1326 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
907b28c5 CW |
1327 | if (ret) |
1328 | return ret; | |
1329 | ||
907b28c5 | 1330 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
0f08ffd6 | 1331 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
9aa7250f VS |
1332 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
1333 | ILK_GRDOM_RESET_ENABLE) == 0, 500); | |
1334 | if (ret) | |
1335 | return ret; | |
1336 | ||
1337 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0); | |
1338 | ||
1339 | return 0; | |
907b28c5 CW |
1340 | } |
1341 | ||
1342 | static int gen6_do_reset(struct drm_device *dev) | |
1343 | { | |
1344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1345 | int ret; | |
907b28c5 CW |
1346 | |
1347 | /* Reset the chip */ | |
1348 | ||
1349 | /* GEN6_GDRST is not in the gt power well, no need to check | |
1350 | * for fifo space for the write or forcewake the chip for | |
1351 | * the read | |
1352 | */ | |
6af5d92f | 1353 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
907b28c5 CW |
1354 | |
1355 | /* Spin waiting for the device to ack the reset request */ | |
6af5d92f | 1356 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
907b28c5 | 1357 | |
0294ae7b | 1358 | intel_uncore_forcewake_reset(dev, true); |
5babf0fc | 1359 | |
907b28c5 CW |
1360 | return ret; |
1361 | } | |
1362 | ||
1363 | int intel_gpu_reset(struct drm_device *dev) | |
1364 | { | |
542c184f RB |
1365 | if (INTEL_INFO(dev)->gen >= 6) |
1366 | return gen6_do_reset(dev); | |
1367 | else if (IS_GEN5(dev)) | |
1368 | return ironlake_do_reset(dev); | |
1369 | else if (IS_G4X(dev)) | |
1370 | return g4x_do_reset(dev); | |
408d4b9e VS |
1371 | else if (IS_G33(dev)) |
1372 | return g33_do_reset(dev); | |
1373 | else if (INTEL_INFO(dev)->gen >= 3) | |
59ea9054 | 1374 | return i915_do_reset(dev); |
542c184f RB |
1375 | else |
1376 | return -ENODEV; | |
907b28c5 CW |
1377 | } |
1378 | ||
907b28c5 CW |
1379 | void intel_uncore_check_errors(struct drm_device *dev) |
1380 | { | |
1381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1382 | ||
1383 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && | |
6af5d92f | 1384 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
907b28c5 | 1385 | DRM_ERROR("Unclaimed register before interrupt\n"); |
6af5d92f | 1386 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
907b28c5 CW |
1387 | } |
1388 | } |