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drm/i915: Create MMIO virtual functions
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_uncore.c
CommitLineData
907b28c5
CW		 1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "i915_drv.h"
25#include "intel_drv.h"
26
27#define FORCEWAKE_ACK_TIMEOUT_MS 2
28
6af5d92f
CW		 29#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
43
907b28c5
CW		 44static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
45{
46 u32 gt_thread_status_mask;
47
48 if (IS_HASWELL(dev_priv->dev))
49 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
50 else
51 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
52
53 /* w/a for a sporadic read returning 0 by waiting for the GT
54 * thread to wake up.
55 */
6af5d92f 56 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
907b28c5
CW		 57 DRM_ERROR("GT thread status wait timed out\n");
58}
59
60static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
61{
6af5d92f
CW		 62 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
63 /* something from same cacheline, but !FORCEWAKE */
64 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 65}
66
67static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
68{
6af5d92f 69 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
907b28c5
CW		 70 FORCEWAKE_ACK_TIMEOUT_MS))
71 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
72
6af5d92f
CW		 73 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
74 /* something from same cacheline, but !FORCEWAKE */
75 __raw_posting_read(dev_priv, ECOBUS);
907b28c5 76
6af5d92f 77 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
907b28c5
CW		 78 FORCEWAKE_ACK_TIMEOUT_MS))
79 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
80
81 /* WaRsForcewakeWaitTC0:snb */
82 __gen6_gt_wait_for_thread_c0(dev_priv);
83}
84
85static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
86{
6af5d92f 87 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
907b28c5 88 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 89 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 90}
91
92static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
93{
94 u32 forcewake_ack;
95
96 if (IS_HASWELL(dev_priv->dev))
97 forcewake_ack = FORCEWAKE_ACK_HSW;
98 else
99 forcewake_ack = FORCEWAKE_MT_ACK;
100
6af5d92f 101 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
907b28c5
CW		 102 FORCEWAKE_ACK_TIMEOUT_MS))
103 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
104
6af5d92f
CW		 105 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
106 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
907b28c5 107 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 108 __raw_posting_read(dev_priv, ECOBUS);
907b28c5 109
6af5d92f 110 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
907b28c5
CW		 111 FORCEWAKE_ACK_TIMEOUT_MS))
112 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
113
114 /* WaRsForcewakeWaitTC0:ivb,hsw */
115 __gen6_gt_wait_for_thread_c0(dev_priv);
116}
117
118static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
119{
120 u32 gtfifodbg;
6af5d92f
CW		 121
122 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
907b28c5
CW		 123 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
124 "MMIO read or write has been dropped %x\n", gtfifodbg))
6af5d92f 125 __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
907b28c5
CW		 126}
127
128static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
129{
6af5d92f 130 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
907b28c5 131 /* something from same cacheline, but !FORCEWAKE */
6af5d92f 132 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 133 gen6_gt_check_fifodbg(dev_priv);
134}
135
136static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
137{
6af5d92f
CW		 138 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
139 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
907b28c5 140 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 141 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 142 gen6_gt_check_fifodbg(dev_priv);
143}
144
145static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
146{
147 int ret = 0;
148
149 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
150 int loop = 500;
6af5d92f 151 u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
907b28c5
CW		 152 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
153 udelay(10);
6af5d92f 154 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
907b28c5
CW		 155 }
156 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
157 ++ret;
158 dev_priv->uncore.fifo_count = fifo;
159 }
160 dev_priv->uncore.fifo_count--;
161
162 return ret;
163}
164
165static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
166{
6af5d92f
CW		 167 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
168 _MASKED_BIT_DISABLE(0xffff));
907b28c5 169 /* something from same cacheline, but !FORCEWAKE_VLV */
6af5d92f 170 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
907b28c5
CW		 171}
172
173static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
174{
6af5d92f 175 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
907b28c5
CW		 176 FORCEWAKE_ACK_TIMEOUT_MS))
177 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
178
6af5d92f
CW		 179 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
180 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
181 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
907b28c5
CW		 182 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
183
6af5d92f 184 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
907b28c5
CW		 185 FORCEWAKE_ACK_TIMEOUT_MS))
186 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
187
6af5d92f 188 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) &
907b28c5
CW		 189 FORCEWAKE_KERNEL),
190 FORCEWAKE_ACK_TIMEOUT_MS))
191 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
192
193 /* WaRsForcewakeWaitTC0:vlv */
194 __gen6_gt_wait_for_thread_c0(dev_priv);
195}
196
197static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
198{
6af5d92f
CW		 199 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
200 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
201 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
907b28c5
CW		 202 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
203 /* The below doubles as a POSTING_READ */
204 gen6_gt_check_fifodbg(dev_priv);
205}
206
aec347ab
CW		 207static void gen6_force_wake_work(struct work_struct *work)
208{
209 struct drm_i915_private *dev_priv =
210 container_of(work, typeof(*dev_priv), uncore.force_wake_work.work);
211 unsigned long irqflags;
212
213 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
214 if (--dev_priv->uncore.forcewake_count == 0)
215 dev_priv->uncore.funcs.force_wake_put(dev_priv);
216 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
217}
218
907b28c5
CW		 219void intel_uncore_early_sanitize(struct drm_device *dev)
220{
221 struct drm_i915_private *dev_priv = dev->dev_private;
222
223 if (HAS_FPGA_DBG_UNCLAIMED(dev))
6af5d92f 224 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
18ce3994
BW		 225
226 if (IS_HASWELL(dev) &&
227 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
228 /* The docs do not explain exactly how the calculation can be
229 * made. It is somewhat guessable, but for now, it's always
230 * 128MB.
231 * NB: We can't write IDICR yet because we do not have gt funcs
232 * set up */
233 dev_priv->ellc_size = 128;
234 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
235 }
907b28c5
CW		 236}
237
521198a2 238static void intel_uncore_forcewake_reset(struct drm_device *dev)
907b28c5
CW		 239{
240 struct drm_i915_private *dev_priv = dev->dev_private;
241
242 if (IS_VALLEYVIEW(dev)) {
243 vlv_force_wake_reset(dev_priv);
244 } else if (INTEL_INFO(dev)->gen >= 6) {
245 __gen6_gt_force_wake_reset(dev_priv);
246 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
247 __gen6_gt_force_wake_mt_reset(dev_priv);
248 }
521198a2
MK		 249}
250
251void intel_uncore_sanitize(struct drm_device *dev)
252{
02f4c9e0
CML		 253 struct drm_i915_private *dev_priv = dev->dev_private;
254 u32 reg_val;
255
521198a2 256 intel_uncore_forcewake_reset(dev);
907b28c5
CW		 257
258 /* BIOS often leaves RC6 enabled, but disable it for hw init */
259 intel_disable_gt_powersave(dev);
02f4c9e0
CML		 260
261 /* Turn off power gate, require especially for the BIOS less system */
262 if (IS_VALLEYVIEW(dev)) {
263
264 mutex_lock(&dev_priv->rps.hw_lock);
265 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
266
267 if (reg_val & (RENDER_PWRGT | MEDIA_PWRGT | DISP2D_PWRGT))
268 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
269
270 mutex_unlock(&dev_priv->rps.hw_lock);
271
272 }
907b28c5
CW		 273}
274
275/*
276 * Generally this is called implicitly by the register read function. However,
277 * if some sequence requires the GT to not power down then this function should
278 * be called at the beginning of the sequence followed by a call to
279 * gen6_gt_force_wake_put() at the end of the sequence.
280 */
281void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
282{
283 unsigned long irqflags;
284
285 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
286 if (dev_priv->uncore.forcewake_count++ == 0)
287 dev_priv->uncore.funcs.force_wake_get(dev_priv);
288 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
289}
290
291/*
292 * see gen6_gt_force_wake_get()
293 */
294void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
295{
296 unsigned long irqflags;
297
298 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
aec347ab
CW		 299 if (--dev_priv->uncore.forcewake_count == 0) {
300 dev_priv->uncore.forcewake_count++;
301 mod_delayed_work(dev_priv->wq,
302 &dev_priv->uncore.force_wake_work,
303 1);
304 }
907b28c5
CW		 305 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
306}
307
308/* We give fast paths for the really cool registers */
309#define NEEDS_FORCE_WAKE(dev_priv, reg) \
310 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
311 ((reg) < 0x40000) && \
312 ((reg) != FORCEWAKE))
313
314static void
315ilk_dummy_write(struct drm_i915_private *dev_priv)
316{
317 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
318 * the chip from rc6 before touching it for real. MI_MODE is masked,
319 * hence harmless to write 0 into. */
6af5d92f 320 __raw_i915_write32(dev_priv, MI_MODE, 0);
907b28c5
CW		 321}
322
323static void
324hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
325{
326 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
6af5d92f 327 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
907b28c5
CW		 328 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
329 reg);
6af5d92f 330 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 331 }
332}
333
334static void
335hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
336{
337 if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) &&
6af5d92f 338 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
907b28c5 339 DRM_ERROR("Unclaimed write to %x\n", reg);
6af5d92f 340 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 341 }
342}
343
6af5d92f 344#define __i915_read(x) \
0b274481
BW		 345static u##x \
346i915_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
907b28c5
CW		 347 unsigned long irqflags; \
348 u##x val = 0; \
349 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
a7f31ee0 350 if (dev_priv->info->gen == 5) \
907b28c5
CW		 351 ilk_dummy_write(dev_priv); \
352 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
353 if (dev_priv->uncore.forcewake_count == 0) \
354 dev_priv->uncore.funcs.force_wake_get(dev_priv); \
6af5d92f 355 val = __raw_i915_read##x(dev_priv, reg); \
907b28c5
CW		 356 if (dev_priv->uncore.forcewake_count == 0) \
357 dev_priv->uncore.funcs.force_wake_put(dev_priv); \
358 } else { \
6af5d92f 359 val = __raw_i915_read##x(dev_priv, reg); \
907b28c5
CW		 360 } \
361 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
ed71f1b4 362 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
907b28c5
CW		 363 return val; \
364}
365
6af5d92f
CW		 366__i915_read(8)
367__i915_read(16)
368__i915_read(32)
369__i915_read(64)
907b28c5
CW		 370#undef __i915_read
371
6af5d92f 372#define __i915_write(x) \
0b274481
BW		 373static void \
374i915_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
907b28c5
CW		 375 unsigned long irqflags; \
376 u32 __fifo_ret = 0; \
ed71f1b4 377 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
907b28c5
CW		 378 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \
379 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
380 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
381 } \
a7f31ee0 382 if (dev_priv->info->gen == 5) \
907b28c5
CW		 383 ilk_dummy_write(dev_priv); \
384 hsw_unclaimed_reg_clear(dev_priv, reg); \
6af5d92f 385 __raw_i915_write##x(dev_priv, reg, val); \
907b28c5
CW		 386 if (unlikely(__fifo_ret)) { \
387 gen6_gt_check_fifodbg(dev_priv); \
388 } \
389 hsw_unclaimed_reg_check(dev_priv, reg); \
390 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
391}
6af5d92f
CW		 392__i915_write(8)
393__i915_write(16)
394__i915_write(32)
395__i915_write(64)
907b28c5
CW		 396#undef __i915_write
397
0b274481
BW		 398void intel_uncore_init(struct drm_device *dev)
399{
400 struct drm_i915_private *dev_priv = dev->dev_private;
401
402 INIT_DELAYED_WORK(&dev_priv->uncore.force_wake_work,
403 gen6_force_wake_work);
404
405 if (IS_VALLEYVIEW(dev)) {
406 dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get;
407 dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put;
408 } else if (IS_HASWELL(dev)) {
409 dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
410 dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
411 } else if (IS_IVYBRIDGE(dev)) {
412 u32 ecobus;
413
414 /* IVB configs may use multi-threaded forcewake */
415
416 /* A small trick here - if the bios hasn't configured
417 * MT forcewake, and if the device is in RC6, then
418 * force_wake_mt_get will not wake the device and the
419 * ECOBUS read will return zero. Which will be
420 * (correctly) interpreted by the test below as MT
421 * forcewake being disabled.
422 */
423 mutex_lock(&dev->struct_mutex);
424 __gen6_gt_force_wake_mt_get(dev_priv);
425 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
426 __gen6_gt_force_wake_mt_put(dev_priv);
427 mutex_unlock(&dev->struct_mutex);
428
429 if (ecobus & FORCEWAKE_MT_ENABLE) {
430 dev_priv->uncore.funcs.force_wake_get =
431 __gen6_gt_force_wake_mt_get;
432 dev_priv->uncore.funcs.force_wake_put =
433 __gen6_gt_force_wake_mt_put;
434 } else {
435 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
436 DRM_INFO("when using vblank-synced partial screen updates.\n");
437 dev_priv->uncore.funcs.force_wake_get =
438 __gen6_gt_force_wake_get;
439 dev_priv->uncore.funcs.force_wake_put =
440 __gen6_gt_force_wake_put;
441 }
442 } else if (IS_GEN6(dev)) {
443 dev_priv->uncore.funcs.force_wake_get =
444 __gen6_gt_force_wake_get;
445 dev_priv->uncore.funcs.force_wake_put =
446 __gen6_gt_force_wake_put;
447 }
448
449 dev_priv->uncore.funcs.mmio_readb = i915_read8;
450 dev_priv->uncore.funcs.mmio_readw = i915_read16;
451 dev_priv->uncore.funcs.mmio_readl = i915_read32;
452 dev_priv->uncore.funcs.mmio_readq = i915_read64;
453 dev_priv->uncore.funcs.mmio_writeb = i915_write8;
454 dev_priv->uncore.funcs.mmio_writew = i915_write16;
455 dev_priv->uncore.funcs.mmio_writel = i915_write32;
456 dev_priv->uncore.funcs.mmio_writeq = i915_write64;
457}
458
459void intel_uncore_fini(struct drm_device *dev)
460{
461 struct drm_i915_private *dev_priv = dev->dev_private;
462
463 flush_delayed_work(&dev_priv->uncore.force_wake_work);
464
465 /* Paranoia: make sure we have disabled everything before we exit. */
466 intel_uncore_sanitize(dev);
467}
468
907b28c5
CW		 469static const struct register_whitelist {
470 uint64_t offset;
471 uint32_t size;
472 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
473} whitelist[] = {
474 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
475};
476
477int i915_reg_read_ioctl(struct drm_device *dev,
478 void *data, struct drm_file *file)
479{
480 struct drm_i915_private *dev_priv = dev->dev_private;
481 struct drm_i915_reg_read *reg = data;
482 struct register_whitelist const *entry = whitelist;
483 int i;
484
485 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
486 if (entry->offset == reg->offset &&
487 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
488 break;
489 }
490
491 if (i == ARRAY_SIZE(whitelist))
492 return -EINVAL;
493
494 switch (entry->size) {
495 case 8:
496 reg->val = I915_READ64(reg->offset);
497 break;
498 case 4:
499 reg->val = I915_READ(reg->offset);
500 break;
501 case 2:
502 reg->val = I915_READ16(reg->offset);
503 break;
504 case 1:
505 reg->val = I915_READ8(reg->offset);
506 break;
507 default:
508 WARN_ON(1);
509 return -EINVAL;
510 }
511
512 return 0;
513}
514
907b28c5
CW		 515static int i965_reset_complete(struct drm_device *dev)
516{
517 u8 gdrst;
518 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
519 return (gdrst & GRDOM_RESET_ENABLE) == 0;
520}
521
522static int i965_do_reset(struct drm_device *dev)
523{
524 int ret;
525
526 /*
527 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
528 * well as the reset bit (GR/bit 0). Setting the GR bit
529 * triggers the reset; when done, the hardware will clear it.
530 */
531 pci_write_config_byte(dev->pdev, I965_GDRST,
532 GRDOM_RENDER | GRDOM_RESET_ENABLE);
533 ret = wait_for(i965_reset_complete(dev), 500);
534 if (ret)
535 return ret;
536
537 /* We can't reset render&media without also resetting display ... */
538 pci_write_config_byte(dev->pdev, I965_GDRST,
539 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
540
541 ret = wait_for(i965_reset_complete(dev), 500);
542 if (ret)
543 return ret;
544
545 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
546
547 return 0;
548}
549
550static int ironlake_do_reset(struct drm_device *dev)
551{
552 struct drm_i915_private *dev_priv = dev->dev_private;
553 u32 gdrst;
554 int ret;
555
556 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
557 gdrst &= ~GRDOM_MASK;
558 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
559 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
560 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
561 if (ret)
562 return ret;
563
564 /* We can't reset render&media without also resetting display ... */
565 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
566 gdrst &= ~GRDOM_MASK;
567 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
568 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
569 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
570}
571
572static int gen6_do_reset(struct drm_device *dev)
573{
574 struct drm_i915_private *dev_priv = dev->dev_private;
575 int ret;
576 unsigned long irqflags;
577
578 /* Hold uncore.lock across reset to prevent any register access
579 * with forcewake not set correctly
580 */
581 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
582
583 /* Reset the chip */
584
585 /* GEN6_GDRST is not in the gt power well, no need to check
586 * for fifo space for the write or forcewake the chip for
587 * the read
588 */
6af5d92f 589 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
907b28c5
CW		 590
591 /* Spin waiting for the device to ack the reset request */
6af5d92f 592 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
907b28c5 593
521198a2
MK		 594 intel_uncore_forcewake_reset(dev);
595
907b28c5
CW		 596 /* If reset with a user forcewake, try to restore, otherwise turn it off */
597 if (dev_priv->uncore.forcewake_count)
598 dev_priv->uncore.funcs.force_wake_get(dev_priv);
599 else
600 dev_priv->uncore.funcs.force_wake_put(dev_priv);
601
602 /* Restore fifo count */
6af5d92f 603 dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES);
907b28c5
CW		 604
605 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
606 return ret;
607}
608
609int intel_gpu_reset(struct drm_device *dev)
610{
611 switch (INTEL_INFO(dev)->gen) {
612 case 7:
613 case 6: return gen6_do_reset(dev);
614 case 5: return ironlake_do_reset(dev);
615 case 4: return i965_do_reset(dev);
907b28c5
CW		 616 default: return -ENODEV;
617 }
618}
619
620void intel_uncore_clear_errors(struct drm_device *dev)
621{
622 struct drm_i915_private *dev_priv = dev->dev_private;
623
6af5d92f 624 /* XXX needs spinlock around caller's grouping */
907b28c5 625 if (HAS_FPGA_DBG_UNCLAIMED(dev))
6af5d92f 626 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 627}
628
629void intel_uncore_check_errors(struct drm_device *dev)
630{
631 struct drm_i915_private *dev_priv = dev->dev_private;
632
633 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
6af5d92f 634 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
907b28c5 635 DRM_ERROR("Unclaimed register before interrupt\n");
6af5d92f 636 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 637 }
638}
Linux 6.x block layer and io_uring tree(s)