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drm/i915: restore the early forcewake cleanup
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_tv.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 *
27 */
28
29/** @file
30 * Integrated TV-out support for the 915GM and 945GM.
31 */
32
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945
JB		 38#include "i915_drv.h"
39
40enum tv_margin {
41 TV_MARGIN_LEFT, TV_MARGIN_TOP,
42 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
43};
44
45/** Private structure for the integrated TV support */
ea5b213a
CW		 46struct intel_tv {
47 struct intel_encoder base;
48
79e53945 49 int type;
763a4a01 50 const char *tv_format;
79e53945
JB		 51 int margin[4];
52 u32 save_TV_H_CTL_1;
53 u32 save_TV_H_CTL_2;
54 u32 save_TV_H_CTL_3;
55 u32 save_TV_V_CTL_1;
56 u32 save_TV_V_CTL_2;
57 u32 save_TV_V_CTL_3;
58 u32 save_TV_V_CTL_4;
59 u32 save_TV_V_CTL_5;
60 u32 save_TV_V_CTL_6;
61 u32 save_TV_V_CTL_7;
62 u32 save_TV_SC_CTL_1, save_TV_SC_CTL_2, save_TV_SC_CTL_3;
63
64 u32 save_TV_CSC_Y;
65 u32 save_TV_CSC_Y2;
66 u32 save_TV_CSC_U;
67 u32 save_TV_CSC_U2;
68 u32 save_TV_CSC_V;
69 u32 save_TV_CSC_V2;
70 u32 save_TV_CLR_KNOBS;
71 u32 save_TV_CLR_LEVEL;
72 u32 save_TV_WIN_POS;
73 u32 save_TV_WIN_SIZE;
74 u32 save_TV_FILTER_CTL_1;
75 u32 save_TV_FILTER_CTL_2;
76 u32 save_TV_FILTER_CTL_3;
77
78 u32 save_TV_H_LUMA[60];
79 u32 save_TV_H_CHROMA[60];
80 u32 save_TV_V_LUMA[43];
81 u32 save_TV_V_CHROMA[43];
82
83 u32 save_TV_DAC;
84 u32 save_TV_CTL;
85};
86
87struct video_levels {
88 int blank, black, burst;
89};
90
91struct color_conversion {
92 u16 ry, gy, by, ay;
93 u16 ru, gu, bu, au;
94 u16 rv, gv, bv, av;
95};
96
97static const u32 filter_table[] = {
98 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
99 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
100 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
101 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
102 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
103 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
104 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
105 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
106 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
107 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
108 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
109 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
110 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
111 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
112 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
113 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
114 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
115 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
116 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
117 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
118 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
119 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
120 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
121 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
122 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
123 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
124 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
125 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
126 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
127 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
128 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
129 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
130 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
131 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
132 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
133 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
134 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
135 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
136 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
137 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
138 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
139 0x2D002CC0, 0x30003640, 0x2D0036C0,
140 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
141 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
142 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
143 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
144 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
145 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
146 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
147 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
148 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
149 0x28003100, 0x28002F00, 0x00003100,
150};
151
152/*
153 * Color conversion values have 3 separate fixed point formats:
154 *
155 * 10 bit fields (ay, au)
156 * 1.9 fixed point (b.bbbbbbbbb)
157 * 11 bit fields (ry, by, ru, gu, gv)
158 * exp.mantissa (ee.mmmmmmmmm)
159 * ee = 00 = 10^-1 (0.mmmmmmmmm)
160 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
161 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
162 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
163 * 12 bit fields (gy, rv, bu)
164 * exp.mantissa (eee.mmmmmmmmm)
165 * eee = 000 = 10^-1 (0.mmmmmmmmm)
166 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
167 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
168 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
169 * eee = 100 = reserved
170 * eee = 101 = reserved
171 * eee = 110 = reserved
172 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
173 *
174 * Saturation and contrast are 8 bits, with their own representation:
175 * 8 bit field (saturation, contrast)
176 * exp.mantissa (ee.mmmmmm)
177 * ee = 00 = 10^-1 (0.mmmmmm)
178 * ee = 01 = 10^0 (m.mmmmm)
179 * ee = 10 = 10^1 (mm.mmmm)
180 * ee = 11 = 10^2 (mmm.mmm)
181 *
182 * Simple conversion function:
183 *
184 * static u32
185 * float_to_csc_11(float f)
186 * {
187 * u32 exp;
188 * u32 mant;
189 * u32 ret;
190 *
191 * if (f < 0)
192 * f = -f;
193 *
194 * if (f >= 1) {
195 * exp = 0x7;
0206e353 196 * mant = 1 << 8;
79e53945
JB		 197 * } else {
198 * for (exp = 0; exp < 3 && f < 0.5; exp++)
0206e353 199 * f *= 2.0;
79e53945
JB		 200 * mant = (f * (1 << 9) + 0.5);
201 * if (mant >= (1 << 9))
202 * mant = (1 << 9) - 1;
203 * }
204 * ret = (exp << 9) | mant;
205 * return ret;
206 * }
207 */
208
209/*
210 * Behold, magic numbers! If we plant them they might grow a big
211 * s-video cable to the sky... or something.
212 *
213 * Pre-converted to appropriate hex value.
214 */
215
216/*
217 * PAL & NTSC values for composite & s-video connections
218 */
219static const struct color_conversion ntsc_m_csc_composite = {
220 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 221 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
222 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 223};
224
225static const struct video_levels ntsc_m_levels_composite = {
226 .blank = 225, .black = 267, .burst = 113,
227};
228
229static const struct color_conversion ntsc_m_csc_svideo = {
ba01079c
ZW		 230 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
231 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
232 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 233};
234
235static const struct video_levels ntsc_m_levels_svideo = {
236 .blank = 266, .black = 316, .burst = 133,
237};
238
239static const struct color_conversion ntsc_j_csc_composite = {
240 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
ba01079c
ZW		 241 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
242 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
79e53945
JB		 243};
244
245static const struct video_levels ntsc_j_levels_composite = {
246 .blank = 225, .black = 225, .burst = 113,
247};
248
249static const struct color_conversion ntsc_j_csc_svideo = {
250 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
ba01079c
ZW		 251 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
252 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
79e53945
JB		 253};
254
255static const struct video_levels ntsc_j_levels_svideo = {
256 .blank = 266, .black = 266, .burst = 133,
257};
258
259static const struct color_conversion pal_csc_composite = {
260 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
ba01079c
ZW		 261 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
262 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
79e53945
JB		 263};
264
265static const struct video_levels pal_levels_composite = {
266 .blank = 237, .black = 237, .burst = 118,
267};
268
269static const struct color_conversion pal_csc_svideo = {
270 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
ba01079c
ZW		 271 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
272 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
79e53945
JB		 273};
274
275static const struct video_levels pal_levels_svideo = {
276 .blank = 280, .black = 280, .burst = 139,
277};
278
279static const struct color_conversion pal_m_csc_composite = {
280 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 281 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
282 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 283};
284
285static const struct video_levels pal_m_levels_composite = {
286 .blank = 225, .black = 267, .burst = 113,
287};
288
289static const struct color_conversion pal_m_csc_svideo = {
ba01079c
ZW		 290 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
291 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
292 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 293};
294
295static const struct video_levels pal_m_levels_svideo = {
296 .blank = 266, .black = 316, .burst = 133,
297};
298
299static const struct color_conversion pal_n_csc_composite = {
300 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 301 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
302 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 303};
304
305static const struct video_levels pal_n_levels_composite = {
306 .blank = 225, .black = 267, .burst = 118,
307};
308
309static const struct color_conversion pal_n_csc_svideo = {
ba01079c
ZW		 310 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
311 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
312 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 313};
314
315static const struct video_levels pal_n_levels_svideo = {
316 .blank = 266, .black = 316, .burst = 139,
317};
318
319/*
320 * Component connections
321 */
322static const struct color_conversion sdtv_csc_yprpb = {
ba01079c
ZW		 323 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
324 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
325 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
79e53945
JB		 326};
327
328static const struct color_conversion sdtv_csc_rgb = {
329 .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
330 .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
331 .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
332};
333
334static const struct color_conversion hdtv_csc_yprpb = {
ba01079c
ZW		 335 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
336 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
337 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
79e53945
JB		 338};
339
340static const struct color_conversion hdtv_csc_rgb = {
341 .ry = 0x0000, .gy = 0x0f00, .by = 0x0000, .ay = 0x0166,
342 .ru = 0x0000, .gu = 0x0000, .bu = 0x0f00, .au = 0x0166,
343 .rv = 0x0f00, .gv = 0x0000, .bv = 0x0000, .av = 0x0166,
344};
345
346static const struct video_levels component_levels = {
347 .blank = 279, .black = 279, .burst = 0,
348};
349
350
351struct tv_mode {
763a4a01 352 const char *name;
79e53945
JB		 353 int clock;
354 int refresh; /* in millihertz (for precision) */
355 u32 oversample;
356 int hsync_end, hblank_start, hblank_end, htotal;
357 bool progressive, trilevel_sync, component_only;
358 int vsync_start_f1, vsync_start_f2, vsync_len;
359 bool veq_ena;
360 int veq_start_f1, veq_start_f2, veq_len;
361 int vi_end_f1, vi_end_f2, nbr_end;
362 bool burst_ena;
363 int hburst_start, hburst_len;
364 int vburst_start_f1, vburst_end_f1;
365 int vburst_start_f2, vburst_end_f2;
366 int vburst_start_f3, vburst_end_f3;
367 int vburst_start_f4, vburst_end_f4;
368 /*
369 * subcarrier programming
370 */
371 int dda2_size, dda3_size, dda1_inc, dda2_inc, dda3_inc;
372 u32 sc_reset;
373 bool pal_burst;
374 /*
375 * blank/black levels
376 */
377 const struct video_levels *composite_levels, *svideo_levels;
378 const struct color_conversion *composite_color, *svideo_color;
379 const u32 *filter_table;
380 int max_srcw;
381};
382
383
384/*
385 * Sub carrier DDA
386 *
387 * I think this works as follows:
388 *
389 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
390 *
391 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
392 *
393 * So,
394 * dda1_ideal = subcarrier/pixel * 4096
395 * dda1_inc = floor (dda1_ideal)
396 * dda2 = dda1_ideal - dda1_inc
397 *
398 * then pick a ratio for dda2 that gives the closest approximation. If
399 * you can't get close enough, you can play with dda3 as well. This
400 * seems likely to happen when dda2 is small as the jumps would be larger
401 *
402 * To invert this,
403 *
404 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
405 *
406 * The constants below were all computed using a 107.520MHz clock
407 */
408
409/**
410 * Register programming values for TV modes.
411 *
412 * These values account for -1s required.
413 */
414
005568be 415static const struct tv_mode tv_modes[] = {
79e53945
JB		 416 {
417 .name = "NTSC-M",
ba01079c 418 .clock = 108000,
23bd15ec 419 .refresh = 59940,
79e53945
JB		 420 .oversample = TV_OVERSAMPLE_8X,
421 .component_only = 0,
422 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
423
424 .hsync_end = 64, .hblank_end = 124,
425 .hblank_start = 836, .htotal = 857,
426
427 .progressive = false, .trilevel_sync = false,
428
429 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
430 .vsync_len = 6,
431
0206e353 432 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 433 .veq_start_f2 = 1, .veq_len = 18,
434
435 .vi_end_f1 = 20, .vi_end_f2 = 21,
436 .nbr_end = 240,
437
438 .burst_ena = true,
439 .hburst_start = 72, .hburst_len = 34,
440 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
441 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
442 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
443 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
444
445 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 446 .dda1_inc = 135,
447 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 448 .dda3_inc = 0, .dda3_size = 0,
449 .sc_reset = TV_SC_RESET_EVERY_4,
450 .pal_burst = false,
451
452 .composite_levels = &ntsc_m_levels_composite,
453 .composite_color = &ntsc_m_csc_composite,
454 .svideo_levels = &ntsc_m_levels_svideo,
455 .svideo_color = &ntsc_m_csc_svideo,
456
457 .filter_table = filter_table,
458 },
459 {
460 .name = "NTSC-443",
ba01079c 461 .clock = 108000,
23bd15ec 462 .refresh = 59940,
79e53945
JB		 463 .oversample = TV_OVERSAMPLE_8X,
464 .component_only = 0,
465 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
466 .hsync_end = 64, .hblank_end = 124,
467 .hblank_start = 836, .htotal = 857,
468
469 .progressive = false, .trilevel_sync = false,
470
471 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
472 .vsync_len = 6,
473
0206e353 474 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 475 .veq_start_f2 = 1, .veq_len = 18,
476
477 .vi_end_f1 = 20, .vi_end_f2 = 21,
478 .nbr_end = 240,
479
3ca87e82 480 .burst_ena = true,
79e53945
JB		 481 .hburst_start = 72, .hburst_len = 34,
482 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
483 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
484 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
485 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
486
487 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
488 .dda1_inc = 168,
ba01079c
ZW		 489 .dda2_inc = 4093, .dda2_size = 27456,
490 .dda3_inc = 310, .dda3_size = 525,
491 .sc_reset = TV_SC_RESET_NEVER,
492 .pal_burst = false,
79e53945
JB		 493
494 .composite_levels = &ntsc_m_levels_composite,
495 .composite_color = &ntsc_m_csc_composite,
496 .svideo_levels = &ntsc_m_levels_svideo,
497 .svideo_color = &ntsc_m_csc_svideo,
498
499 .filter_table = filter_table,
500 },
501 {
502 .name = "NTSC-J",
ba01079c 503 .clock = 108000,
23bd15ec 504 .refresh = 59940,
79e53945
JB		 505 .oversample = TV_OVERSAMPLE_8X,
506 .component_only = 0,
507
508 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
509 .hsync_end = 64, .hblank_end = 124,
510 .hblank_start = 836, .htotal = 857,
511
512 .progressive = false, .trilevel_sync = false,
513
514 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
515 .vsync_len = 6,
516
0206e353 517 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 518 .veq_start_f2 = 1, .veq_len = 18,
519
520 .vi_end_f1 = 20, .vi_end_f2 = 21,
521 .nbr_end = 240,
522
523 .burst_ena = true,
524 .hburst_start = 72, .hburst_len = 34,
525 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
526 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
527 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
528 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
529
530 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 531 .dda1_inc = 135,
532 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 533 .dda3_inc = 0, .dda3_size = 0,
534 .sc_reset = TV_SC_RESET_EVERY_4,
535 .pal_burst = false,
536
537 .composite_levels = &ntsc_j_levels_composite,
538 .composite_color = &ntsc_j_csc_composite,
539 .svideo_levels = &ntsc_j_levels_svideo,
540 .svideo_color = &ntsc_j_csc_svideo,
541
542 .filter_table = filter_table,
543 },
544 {
545 .name = "PAL-M",
ba01079c 546 .clock = 108000,
23bd15ec 547 .refresh = 59940,
79e53945
JB		 548 .oversample = TV_OVERSAMPLE_8X,
549 .component_only = 0,
550
551 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
552 .hsync_end = 64, .hblank_end = 124,
553 .hblank_start = 836, .htotal = 857,
554
555 .progressive = false, .trilevel_sync = false,
556
557 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
558 .vsync_len = 6,
559
0206e353 560 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 561 .veq_start_f2 = 1, .veq_len = 18,
562
563 .vi_end_f1 = 20, .vi_end_f2 = 21,
564 .nbr_end = 240,
565
566 .burst_ena = true,
567 .hburst_start = 72, .hburst_len = 34,
568 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
569 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
570 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
571 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
572
573 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 574 .dda1_inc = 135,
575 .dda2_inc = 16704, .dda2_size = 27456,
79e53945 576 .dda3_inc = 0, .dda3_size = 0,
ba01079c
ZW		 577 .sc_reset = TV_SC_RESET_EVERY_8,
578 .pal_burst = true,
79e53945
JB		 579
580 .composite_levels = &pal_m_levels_composite,
581 .composite_color = &pal_m_csc_composite,
582 .svideo_levels = &pal_m_levels_svideo,
583 .svideo_color = &pal_m_csc_svideo,
584
585 .filter_table = filter_table,
586 },
587 {
588 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
589 .name = "PAL-N",
ba01079c 590 .clock = 108000,
23bd15ec 591 .refresh = 50000,
79e53945
JB		 592 .oversample = TV_OVERSAMPLE_8X,
593 .component_only = 0,
594
595 .hsync_end = 64, .hblank_end = 128,
596 .hblank_start = 844, .htotal = 863,
597
598 .progressive = false, .trilevel_sync = false,
599
600
601 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
602 .vsync_len = 6,
603
0206e353 604 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 605 .veq_start_f2 = 1, .veq_len = 18,
606
607 .vi_end_f1 = 24, .vi_end_f2 = 25,
608 .nbr_end = 286,
609
610 .burst_ena = true,
0206e353 611 .hburst_start = 73, .hburst_len = 34,
79e53945
JB		 612 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
613 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
614 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
615 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
616
617
618 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
ba01079c
ZW		 619 .dda1_inc = 135,
620 .dda2_inc = 23578, .dda2_size = 27648,
621 .dda3_inc = 134, .dda3_size = 625,
79e53945
JB		 622 .sc_reset = TV_SC_RESET_EVERY_8,
623 .pal_burst = true,
624
625 .composite_levels = &pal_n_levels_composite,
626 .composite_color = &pal_n_csc_composite,
627 .svideo_levels = &pal_n_levels_svideo,
628 .svideo_color = &pal_n_csc_svideo,
629
630 .filter_table = filter_table,
631 },
632 {
633 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
634 .name = "PAL",
ba01079c 635 .clock = 108000,
23bd15ec 636 .refresh = 50000,
79e53945
JB		 637 .oversample = TV_OVERSAMPLE_8X,
638 .component_only = 0,
639
ba01079c 640 .hsync_end = 64, .hblank_end = 142,
79e53945
JB		 641 .hblank_start = 844, .htotal = 863,
642
643 .progressive = false, .trilevel_sync = false,
644
645 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
646 .vsync_len = 5,
647
0206e353 648 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 649 .veq_start_f2 = 1, .veq_len = 15,
650
651 .vi_end_f1 = 24, .vi_end_f2 = 25,
652 .nbr_end = 286,
653
654 .burst_ena = true,
655 .hburst_start = 73, .hburst_len = 32,
656 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
657 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
658 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
659 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
660
661 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
662 .dda1_inc = 168,
ba01079c
ZW		 663 .dda2_inc = 4122, .dda2_size = 27648,
664 .dda3_inc = 67, .dda3_size = 625,
79e53945
JB		 665 .sc_reset = TV_SC_RESET_EVERY_8,
666 .pal_burst = true,
667
668 .composite_levels = &pal_levels_composite,
669 .composite_color = &pal_csc_composite,
670 .svideo_levels = &pal_levels_svideo,
671 .svideo_color = &pal_csc_svideo,
672
673 .filter_table = filter_table,
674 },
9589919f
RV		 675 {
676 .name = "480p",
677 .clock = 107520,
678 .refresh = 59940,
679 .oversample = TV_OVERSAMPLE_4X,
680 .component_only = 1,
681
682 .hsync_end = 64, .hblank_end = 122,
683 .hblank_start = 842, .htotal = 857,
684
685 .progressive = true, .trilevel_sync = false,
686
687 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
688 .vsync_len = 12,
689
690 .veq_ena = false,
691
692 .vi_end_f1 = 44, .vi_end_f2 = 44,
693 .nbr_end = 479,
694
695 .burst_ena = false,
696
697 .filter_table = filter_table,
698 },
699 {
700 .name = "576p",
701 .clock = 107520,
702 .refresh = 50000,
703 .oversample = TV_OVERSAMPLE_4X,
704 .component_only = 1,
705
706 .hsync_end = 64, .hblank_end = 139,
707 .hblank_start = 859, .htotal = 863,
708
709 .progressive = true, .trilevel_sync = false,
710
711 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
712 .vsync_len = 10,
713
714 .veq_ena = false,
715
716 .vi_end_f1 = 48, .vi_end_f2 = 48,
717 .nbr_end = 575,
718
719 .burst_ena = false,
720
721 .filter_table = filter_table,
722 },
79e53945
JB		 723 {
724 .name = "720p@60Hz",
725 .clock = 148800,
726 .refresh = 60000,
727 .oversample = TV_OVERSAMPLE_2X,
728 .component_only = 1,
729
730 .hsync_end = 80, .hblank_end = 300,
731 .hblank_start = 1580, .htotal = 1649,
732
0206e353 733 .progressive = true, .trilevel_sync = true,
79e53945
JB		 734
735 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
736 .vsync_len = 10,
737
738 .veq_ena = false,
739
740 .vi_end_f1 = 29, .vi_end_f2 = 29,
741 .nbr_end = 719,
742
743 .burst_ena = false,
744
745 .filter_table = filter_table,
746 },
79e53945
JB		 747 {
748 .name = "720p@50Hz",
749 .clock = 148800,
750 .refresh = 50000,
751 .oversample = TV_OVERSAMPLE_2X,
752 .component_only = 1,
753
754 .hsync_end = 80, .hblank_end = 300,
755 .hblank_start = 1580, .htotal = 1979,
756
0206e353 757 .progressive = true, .trilevel_sync = true,
79e53945
JB		 758
759 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
760 .vsync_len = 10,
761
762 .veq_ena = false,
763
764 .vi_end_f1 = 29, .vi_end_f2 = 29,
765 .nbr_end = 719,
766
767 .burst_ena = false,
768
769 .filter_table = filter_table,
770 .max_srcw = 800
771 },
772 {
773 .name = "1080i@50Hz",
774 .clock = 148800,
23bd15ec 775 .refresh = 50000,
79e53945
JB		 776 .oversample = TV_OVERSAMPLE_2X,
777 .component_only = 1,
778
779 .hsync_end = 88, .hblank_end = 235,
780 .hblank_start = 2155, .htotal = 2639,
781
0206e353 782 .progressive = false, .trilevel_sync = true,
79e53945
JB		 783
784 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
785 .vsync_len = 10,
786
0206e353 787 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 788 .veq_start_f2 = 4, .veq_len = 10,
789
790
791 .vi_end_f1 = 21, .vi_end_f2 = 22,
792 .nbr_end = 539,
793
794 .burst_ena = false,
795
796 .filter_table = filter_table,
797 },
798 {
799 .name = "1080i@60Hz",
800 .clock = 148800,
23bd15ec 801 .refresh = 60000,
79e53945
JB		 802 .oversample = TV_OVERSAMPLE_2X,
803 .component_only = 1,
804
805 .hsync_end = 88, .hblank_end = 235,
806 .hblank_start = 2155, .htotal = 2199,
807
0206e353 808 .progressive = false, .trilevel_sync = true,
79e53945
JB		 809
810 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
811 .vsync_len = 10,
812
0206e353 813 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 814 .veq_start_f2 = 4, .veq_len = 10,
815
816
817 .vi_end_f1 = 21, .vi_end_f2 = 22,
818 .nbr_end = 539,
819
820 .burst_ena = false,
821
79e53945
JB		 822 .filter_table = filter_table,
823 },
824};
825
cd91ef23 826static struct intel_tv *enc_to_tv(struct intel_encoder *encoder)
ea5b213a 827{
cd91ef23 828 return container_of(encoder, struct intel_tv, base);
ea5b213a
CW		 829}
830
df0e9248
CW		 831static struct intel_tv *intel_attached_tv(struct drm_connector *connector)
832{
cd91ef23 833 return enc_to_tv(intel_attached_encoder(connector));
df0e9248
CW		 834}
835
9a8ee983
DV		 836static bool
837intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
838{
839 struct drm_device *dev = encoder->base.dev;
840 struct drm_i915_private *dev_priv = dev->dev_private;
841 u32 tmp = I915_READ(TV_CTL);
842
843 if (!(tmp & TV_ENC_ENABLE))
844 return false;
845
846 *pipe = PORT_TO_PIPE(tmp);
847
848 return true;
849}
850
79e53945 851static void
6b5756a0 852intel_enable_tv(struct intel_encoder *encoder)
79e53945 853{
6b5756a0 854 struct drm_device *dev = encoder->base.dev;
79e53945
JB		 855 struct drm_i915_private *dev_priv = dev->dev_private;
856
6b5756a0
DV		 857 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
858}
859
860static void
861intel_disable_tv(struct intel_encoder *encoder)
862{
863 struct drm_device *dev = encoder->base.dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865
866 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
79e53945
JB		 867}
868
79e53945 869static const struct tv_mode *
763a4a01 870intel_tv_mode_lookup(const char *tv_format)
79e53945
JB		 871{
872 int i;
873
3801a7fd 874 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
79e53945
JB		 875 const struct tv_mode *tv_mode = &tv_modes[i];
876
877 if (!strcmp(tv_format, tv_mode->name))
878 return tv_mode;
879 }
880 return NULL;
881}
882
883static const struct tv_mode *
763a4a01 884intel_tv_mode_find(struct intel_tv *intel_tv)
79e53945 885{
ea5b213a 886 return intel_tv_mode_lookup(intel_tv->tv_format);
79e53945
JB		 887}
888
889static enum drm_mode_status
763a4a01
CW		 890intel_tv_mode_valid(struct drm_connector *connector,
891 struct drm_display_mode *mode)
79e53945 892{
df0e9248 893 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 894 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
79e53945
JB		 895
896 /* Ensure TV refresh is close to desired refresh */
0d0884ce
ZY		 897 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
898 < 1000)
79e53945 899 return MODE_OK;
763a4a01 900
79e53945
JB		 901 return MODE_CLOCK_RANGE;
902}
903
904
905static bool
5d2d38dd
DV		 906intel_tv_compute_config(struct intel_encoder *encoder,
907 struct intel_crtc_config *pipe_config)
79e53945 908{
cd91ef23 909 struct intel_tv *intel_tv = enc_to_tv(encoder);
ea5b213a 910 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
79e53945
JB		 911
912 if (!tv_mode)
913 return false;
914
241bfc38 915 pipe_config->adjusted_mode.crtc_clock = tv_mode->clock;
5d2d38dd
DV		 916 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
917 pipe_config->pipe_bpp = 8*3;
918
1062b815
DV		 919 /* TV has it's own notion of sync and other mode flags, so clear them. */
920 pipe_config->adjusted_mode.flags = 0;
921
922 /*
923 * FIXME: We don't check whether the input mode is actually what we want
924 * or whether userspace is doing something stupid.
925 */
926
79e53945
JB		 927 return true;
928}
929
cd91ef23 930static void intel_tv_mode_set(struct intel_encoder *encoder)
79e53945 931{
cd91ef23 932 struct drm_device *dev = encoder->base.dev;
79e53945 933 struct drm_i915_private *dev_priv = dev->dev_private;
cd91ef23
DV		 934 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
935 struct intel_tv *intel_tv = enc_to_tv(encoder);
ea5b213a 936 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
79e53945
JB		 937 u32 tv_ctl;
938 u32 hctl1, hctl2, hctl3;
939 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
940 u32 scctl1, scctl2, scctl3;
941 int i, j;
942 const struct video_levels *video_levels;
943 const struct color_conversion *color_conversion;
944 bool burst_ena;
9db4a9c7 945 int pipe = intel_crtc->pipe;
79e53945
JB		 946
947 if (!tv_mode)
948 return; /* can't happen (mode_prepare prevents this) */
949
d2d9f232
ZW		 950 tv_ctl = I915_READ(TV_CTL);
951 tv_ctl &= TV_CTL_SAVE;
79e53945 952
ea5b213a 953 switch (intel_tv->type) {
79e53945
JB		 954 default:
955 case DRM_MODE_CONNECTOR_Unknown:
956 case DRM_MODE_CONNECTOR_Composite:
957 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
958 video_levels = tv_mode->composite_levels;
959 color_conversion = tv_mode->composite_color;
960 burst_ena = tv_mode->burst_ena;
961 break;
962 case DRM_MODE_CONNECTOR_Component:
963 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
964 video_levels = &component_levels;
965 if (tv_mode->burst_ena)
966 color_conversion = &sdtv_csc_yprpb;
967 else
968 color_conversion = &hdtv_csc_yprpb;
969 burst_ena = false;
970 break;
971 case DRM_MODE_CONNECTOR_SVIDEO:
972 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
973 video_levels = tv_mode->svideo_levels;
974 color_conversion = tv_mode->svideo_color;
975 burst_ena = tv_mode->burst_ena;
976 break;
977 }
978 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
979 (tv_mode->htotal << TV_HTOTAL_SHIFT);
980
981 hctl2 = (tv_mode->hburst_start << 16) |
982 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
983
984 if (burst_ena)
985 hctl2 |= TV_BURST_ENA;
986
987 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
988 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
989
990 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
991 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
992 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
993
994 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
995 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
996 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
997
998 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
999 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
1000 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
1001
1002 if (tv_mode->veq_ena)
1003 vctl3 |= TV_EQUAL_ENA;
1004
1005 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
1006 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
1007
1008 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
1009 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
1010
1011 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
1012 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1013
1014 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1015 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1016
1017 if (intel_crtc->pipe == 1)
1018 tv_ctl |= TV_ENC_PIPEB_SELECT;
1019 tv_ctl |= tv_mode->oversample;
1020
1021 if (tv_mode->progressive)
1022 tv_ctl |= TV_PROGRESSIVE;
1023 if (tv_mode->trilevel_sync)
1024 tv_ctl |= TV_TRILEVEL_SYNC;
1025 if (tv_mode->pal_burst)
1026 tv_ctl |= TV_PAL_BURST;
d271817b 1027
79e53945 1028 scctl1 = 0;
d271817b 1029 if (tv_mode->dda1_inc)
79e53945 1030 scctl1 |= TV_SC_DDA1_EN;
79e53945
JB		 1031 if (tv_mode->dda2_inc)
1032 scctl1 |= TV_SC_DDA2_EN;
79e53945
JB		 1033 if (tv_mode->dda3_inc)
1034 scctl1 |= TV_SC_DDA3_EN;
79e53945 1035 scctl1 |= tv_mode->sc_reset;
d271817b
CW		 1036 if (video_levels)
1037 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
79e53945
JB		 1038 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1039
1040 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1041 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1042
1043 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1044 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1045
1046 /* Enable two fixes for the chips that need them. */
ffbab09b 1047 if (dev->pdev->device < 0x2772)
79e53945
JB		 1048 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1049
1050 I915_WRITE(TV_H_CTL_1, hctl1);
1051 I915_WRITE(TV_H_CTL_2, hctl2);
1052 I915_WRITE(TV_H_CTL_3, hctl3);
1053 I915_WRITE(TV_V_CTL_1, vctl1);
1054 I915_WRITE(TV_V_CTL_2, vctl2);
1055 I915_WRITE(TV_V_CTL_3, vctl3);
1056 I915_WRITE(TV_V_CTL_4, vctl4);
1057 I915_WRITE(TV_V_CTL_5, vctl5);
1058 I915_WRITE(TV_V_CTL_6, vctl6);
1059 I915_WRITE(TV_V_CTL_7, vctl7);
1060 I915_WRITE(TV_SC_CTL_1, scctl1);
1061 I915_WRITE(TV_SC_CTL_2, scctl2);
1062 I915_WRITE(TV_SC_CTL_3, scctl3);
1063
1064 if (color_conversion) {
1065 I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
1066 color_conversion->gy);
0206e353 1067 I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
79e53945
JB		 1068 color_conversion->ay);
1069 I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
1070 color_conversion->gu);
1071 I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
1072 color_conversion->au);
1073 I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
1074 color_conversion->gv);
1075 I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
1076 color_conversion->av);
1077 }
1078
a6c45cf0 1079 if (INTEL_INFO(dev)->gen >= 4)
d2d9f232
ZW		 1080 I915_WRITE(TV_CLR_KNOBS, 0x00404000);
1081 else
1082 I915_WRITE(TV_CLR_KNOBS, 0x00606000);
1083
79e53945
JB		 1084 if (video_levels)
1085 I915_WRITE(TV_CLR_LEVEL,
1086 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1087 (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
1088 {
9db4a9c7 1089 int pipeconf_reg = PIPECONF(pipe);
ccacfec6 1090 int dspcntr_reg = DSPCNTR(intel_crtc->plane);
79e53945
JB		 1091 int pipeconf = I915_READ(pipeconf_reg);
1092 int dspcntr = I915_READ(dspcntr_reg);
79e53945
JB		 1093 int xpos = 0x0, ypos = 0x0;
1094 unsigned int xsize, ysize;
1095 /* Pipe must be off here */
1096 I915_WRITE(dspcntr_reg, dspcntr & ~DISPLAY_PLANE_ENABLE);
1dba99f4 1097 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
79e53945
JB		 1098
1099 /* Wait for vblank for the disable to take effect */
a6c45cf0 1100 if (IS_GEN2(dev))
9d0498a2 1101 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1102
5eddb70b 1103 I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE);
79e53945 1104 /* Wait for vblank for the disable to take effect. */
58e10eb9 1105 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
79e53945
JB		 1106
1107 /* Filter ctl must be set before TV_WIN_SIZE */
1108 I915_WRITE(TV_FILTER_CTL_1, TV_AUTO_SCALE);
1109 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
1110 if (tv_mode->progressive)
1111 ysize = tv_mode->nbr_end + 1;
1112 else
1113 ysize = 2*tv_mode->nbr_end + 1;
1114
ea5b213a
CW		 1115 xpos += intel_tv->margin[TV_MARGIN_LEFT];
1116 ypos += intel_tv->margin[TV_MARGIN_TOP];
1117 xsize -= (intel_tv->margin[TV_MARGIN_LEFT] +
1118 intel_tv->margin[TV_MARGIN_RIGHT]);
1119 ysize -= (intel_tv->margin[TV_MARGIN_TOP] +
1120 intel_tv->margin[TV_MARGIN_BOTTOM]);
79e53945
JB		 1121 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
1122 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
1123
1124 I915_WRITE(pipeconf_reg, pipeconf);
1125 I915_WRITE(dspcntr_reg, dspcntr);
1dba99f4 1126 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
79e53945
JB		 1127 }
1128
1129 j = 0;
1130 for (i = 0; i < 60; i++)
1131 I915_WRITE(TV_H_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1132 for (i = 0; i < 60; i++)
1133 I915_WRITE(TV_H_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
1134 for (i = 0; i < 43; i++)
1135 I915_WRITE(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
1136 for (i = 0; i < 43; i++)
1137 I915_WRITE(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
b8ed2a4f 1138 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
79e53945
JB		 1139 I915_WRITE(TV_CTL, tv_ctl);
1140}
1141
1142static const struct drm_display_mode reported_modes[] = {
1143 {
1144 .name = "NTSC 480i",
1145 .clock = 107520,
1146 .hdisplay = 1280,
1147 .hsync_start = 1368,
1148 .hsync_end = 1496,
1149 .htotal = 1712,
1150
1151 .vdisplay = 1024,
1152 .vsync_start = 1027,
1153 .vsync_end = 1034,
1154 .vtotal = 1104,
1155 .type = DRM_MODE_TYPE_DRIVER,
1156 },
1157};
1158
1159/**
1160 * Detects TV presence by checking for load.
1161 *
1162 * Requires that the current pipe's DPLL is active.
1163
1164 * \return true if TV is connected.
1165 * \return false if TV is disconnected.
1166 */
1167static int
0206e353 1168intel_tv_detect_type(struct intel_tv *intel_tv,
8102e126 1169 struct drm_connector *connector)
79e53945 1170{
4ef69c7a 1171 struct drm_encoder *encoder = &intel_tv->base.base;
835bff7e
KP		 1172 struct drm_crtc *crtc = encoder->crtc;
1173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945
JB		 1174 struct drm_device *dev = encoder->dev;
1175 struct drm_i915_private *dev_priv = dev->dev_private;
1176 unsigned long irqflags;
1177 u32 tv_ctl, save_tv_ctl;
1178 u32 tv_dac, save_tv_dac;
974b9331 1179 int type;
79e53945
JB		 1180
1181 /* Disable TV interrupts around load detect or we'll recurse */
8102e126
CW		 1182 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1183 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1184 i915_disable_pipestat(dev_priv, 0,
1185 PIPE_HOTPLUG_INTERRUPT_ENABLE |
1186 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1187 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1188 }
79e53945 1189
974b9331
CW		 1190 save_tv_dac = tv_dac = I915_READ(TV_DAC);
1191 save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
1192
1193 /* Poll for TV detection */
1194 tv_ctl &= ~(TV_ENC_ENABLE | TV_TEST_MODE_MASK);
8ed9a5bc 1195 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
835bff7e
KP		 1196 if (intel_crtc->pipe == 1)
1197 tv_ctl |= TV_ENC_PIPEB_SELECT;
1198 else
1199 tv_ctl &= ~TV_ENC_PIPEB_SELECT;
974b9331
CW		 1200
1201 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
8ed9a5bc 1202 tv_dac |= (TVDAC_STATE_CHG_EN |
1203 TVDAC_A_SENSE_CTL |
1204 TVDAC_B_SENSE_CTL |
1205 TVDAC_C_SENSE_CTL |
1206 DAC_CTL_OVERRIDE |
1207 DAC_A_0_7_V |
1208 DAC_B_0_7_V |
1209 DAC_C_0_7_V);
974b9331 1210
d42c9e2c
DV		 1211
1212 /*
1213 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1214 * the TV is misdetected. This is hardware requirement.
1215 */
1216 if (IS_GM45(dev))
1217 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1218 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1219
8ed9a5bc 1220 I915_WRITE(TV_CTL, tv_ctl);
1221 I915_WRITE(TV_DAC, tv_dac);
4f233eff 1222 POSTING_READ(TV_DAC);
4f233eff 1223
29e1316a
CW		 1224 intel_wait_for_vblank(intel_tv->base.base.dev,
1225 to_intel_crtc(intel_tv->base.base.crtc)->pipe);
1226
974b9331 1227 type = -1;
2bf71160
KP		 1228 tv_dac = I915_READ(TV_DAC);
1229 DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
1230 /*
1231 * A B C
1232 * 0 1 1 Composite
1233 * 1 0 X svideo
1234 * 0 0 0 Component
1235 */
1236 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1237 DRM_DEBUG_KMS("Detected Composite TV connection\n");
1238 type = DRM_MODE_CONNECTOR_Composite;
1239 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1240 DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1241 type = DRM_MODE_CONNECTOR_SVIDEO;
1242 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1243 DRM_DEBUG_KMS("Detected Component TV connection\n");
1244 type = DRM_MODE_CONNECTOR_Component;
1245 } else {
1246 DRM_DEBUG_KMS("Unrecognised TV connection\n");
1247 type = -1;
79e53945
JB		 1248 }
1249
974b9331
CW		 1250 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1251 I915_WRITE(TV_CTL, save_tv_ctl);
bf2125e2
DV		 1252 POSTING_READ(TV_CTL);
1253
1254 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
1255 intel_wait_for_vblank(intel_tv->base.base.dev,
1256 to_intel_crtc(intel_tv->base.base.crtc)->pipe);
974b9331 1257
79e53945 1258 /* Restore interrupt config */
8102e126
CW		 1259 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
1260 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1261 i915_enable_pipestat(dev_priv, 0,
1262 PIPE_HOTPLUG_INTERRUPT_ENABLE |
1263 PIPE_HOTPLUG_TV_INTERRUPT_ENABLE);
1264 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1265 }
79e53945
JB		 1266
1267 return type;
1268}
1269
213c2e64
ML		 1270/*
1271 * Here we set accurate tv format according to connector type
1272 * i.e Component TV should not be assigned by NTSC or PAL
1273 */
1274static void intel_tv_find_better_format(struct drm_connector *connector)
1275{
df0e9248 1276 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 1277 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
213c2e64
ML		 1278 int i;
1279
ea5b213a 1280 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
213c2e64
ML		 1281 tv_mode->component_only)
1282 return;
1283
1284
1285 for (i = 0; i < sizeof(tv_modes) / sizeof(*tv_modes); i++) {
1286 tv_mode = tv_modes + i;
1287
ea5b213a 1288 if ((intel_tv->type == DRM_MODE_CONNECTOR_Component) ==
213c2e64
ML		 1289 tv_mode->component_only)
1290 break;
1291 }
1292
ea5b213a 1293 intel_tv->tv_format = tv_mode->name;
662595df 1294 drm_object_property_set_value(&connector->base,
213c2e64
ML		 1295 connector->dev->mode_config.tv_mode_property, i);
1296}
1297
79e53945
JB		 1298/**
1299 * Detect the TV connection.
1300 *
1301 * Currently this always returns CONNECTOR_STATUS_UNKNOWN, as we need to be sure
1302 * we have a pipe programmed in order to probe the TV.
1303 */
1304static enum drm_connector_status
930a9e28 1305intel_tv_detect(struct drm_connector *connector, bool force)
79e53945 1306{
79e53945 1307 struct drm_display_mode mode;
df0e9248 1308 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 1309 int type;
79e53945 1310
164c8598
CW		 1311 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
1312 connector->base.id, drm_get_connector_name(connector),
1313 force);
1314
79e53945 1315 mode = reported_modes[0];
79e53945 1316
38de45c5 1317 if (force) {
8261b191 1318 struct intel_load_detect_pipe tmp;
ea5b213a 1319
d2434ab7 1320 if (intel_get_load_detect_pipe(connector, &mode, &tmp)) {
8102e126 1321 type = intel_tv_detect_type(intel_tv, connector);
d2434ab7 1322 intel_release_load_detect_pipe(connector, &tmp);
79e53945 1323 } else
7b334fcb
CW		 1324 return connector_status_unknown;
1325 } else
1326 return connector->status;
bf5a269a 1327
79e53945
JB		 1328 if (type < 0)
1329 return connector_status_disconnected;
1330
d5627663 1331 intel_tv->type = type;
213c2e64 1332 intel_tv_find_better_format(connector);
d5627663 1333
79e53945
JB		 1334 return connector_status_connected;
1335}
1336
763a4a01
CW		 1337static const struct input_res {
1338 const char *name;
79e53945 1339 int w, h;
763a4a01 1340} input_res_table[] = {
79e53945
JB		 1341 {"640x480", 640, 480},
1342 {"800x600", 800, 600},
1343 {"1024x768", 1024, 768},
1344 {"1280x1024", 1280, 1024},
1345 {"848x480", 848, 480},
1346 {"1280x720", 1280, 720},
1347 {"1920x1080", 1920, 1080},
1348};
1349
bcae2ca8 1350/*
1351 * Chose preferred mode according to line number of TV format
1352 */
1353static void
1354intel_tv_chose_preferred_modes(struct drm_connector *connector,
1355 struct drm_display_mode *mode_ptr)
1356{
df0e9248 1357 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 1358 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
bcae2ca8 1359
1360 if (tv_mode->nbr_end < 480 && mode_ptr->vdisplay == 480)
1361 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1362 else if (tv_mode->nbr_end > 480) {
1363 if (tv_mode->progressive == true && tv_mode->nbr_end < 720) {
1364 if (mode_ptr->vdisplay == 720)
1365 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1366 } else if (mode_ptr->vdisplay == 1080)
1367 mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
1368 }
1369}
1370
79e53945
JB		 1371/**
1372 * Stub get_modes function.
1373 *
1374 * This should probably return a set of fixed modes, unless we can figure out
1375 * how to probe modes off of TV connections.
1376 */
1377
1378static int
1379intel_tv_get_modes(struct drm_connector *connector)
1380{
1381 struct drm_display_mode *mode_ptr;
df0e9248 1382 struct intel_tv *intel_tv = intel_attached_tv(connector);
ea5b213a 1383 const struct tv_mode *tv_mode = intel_tv_mode_find(intel_tv);
02c5dd98
ZW		 1384 int j, count = 0;
1385 u64 tmp;
79e53945 1386
04ad327f 1387 for (j = 0; j < ARRAY_SIZE(input_res_table);
79e53945 1388 j++) {
763a4a01 1389 const struct input_res *input = &input_res_table[j];
79e53945
JB		 1390 unsigned int hactive_s = input->w;
1391 unsigned int vactive_s = input->h;
1392
1393 if (tv_mode->max_srcw && input->w > tv_mode->max_srcw)
1394 continue;
1395
1396 if (input->w > 1024 && (!tv_mode->progressive
1397 && !tv_mode->component_only))
1398 continue;
1399
02c5dd98
ZW		 1400 mode_ptr = drm_mode_create(connector->dev);
1401 if (!mode_ptr)
1402 continue;
79e53945
JB		 1403 strncpy(mode_ptr->name, input->name, DRM_DISPLAY_MODE_LEN);
1404
1405 mode_ptr->hdisplay = hactive_s;
1406 mode_ptr->hsync_start = hactive_s + 1;
1407 mode_ptr->hsync_end = hactive_s + 64;
1408 if (mode_ptr->hsync_end <= mode_ptr->hsync_start)
1409 mode_ptr->hsync_end = mode_ptr->hsync_start + 1;
1410 mode_ptr->htotal = hactive_s + 96;
1411
1412 mode_ptr->vdisplay = vactive_s;
1413 mode_ptr->vsync_start = vactive_s + 1;
1414 mode_ptr->vsync_end = vactive_s + 32;
1415 if (mode_ptr->vsync_end <= mode_ptr->vsync_start)
1416 mode_ptr->vsync_end = mode_ptr->vsync_start + 1;
1417 mode_ptr->vtotal = vactive_s + 33;
1418
02c5dd98
ZW		 1419 tmp = (u64) tv_mode->refresh * mode_ptr->vtotal;
1420 tmp *= mode_ptr->htotal;
1421 tmp = div_u64(tmp, 1000000);
1422 mode_ptr->clock = (int) tmp;
79e53945
JB		 1423
1424 mode_ptr->type = DRM_MODE_TYPE_DRIVER;
bcae2ca8 1425 intel_tv_chose_preferred_modes(connector, mode_ptr);
79e53945 1426 drm_mode_probed_add(connector, mode_ptr);
02c5dd98 1427 count++;
79e53945
JB		 1428 }
1429
02c5dd98 1430 return count;
79e53945
JB		 1431}
1432
1433static void
0206e353 1434intel_tv_destroy(struct drm_connector *connector)
79e53945 1435{
79e53945 1436 drm_connector_cleanup(connector);
0c41ee2b 1437 kfree(connector);
79e53945
JB		 1438}
1439
1440
1441static int
1442intel_tv_set_property(struct drm_connector *connector, struct drm_property *property,
1443 uint64_t val)
1444{
1445 struct drm_device *dev = connector->dev;
df0e9248
CW		 1446 struct intel_tv *intel_tv = intel_attached_tv(connector);
1447 struct drm_crtc *crtc = intel_tv->base.base.crtc;
79e53945 1448 int ret = 0;
ebcc8f2e 1449 bool changed = false;
79e53945 1450
662595df 1451 ret = drm_object_property_set_value(&connector->base, property, val);
79e53945
JB		 1452 if (ret < 0)
1453 goto out;
1454
ebcc8f2e 1455 if (property == dev->mode_config.tv_left_margin_property &&
ea5b213a
CW		 1456 intel_tv->margin[TV_MARGIN_LEFT] != val) {
1457 intel_tv->margin[TV_MARGIN_LEFT] = val;
ebcc8f2e
ZW		 1458 changed = true;
1459 } else if (property == dev->mode_config.tv_right_margin_property &&
ea5b213a
CW		 1460 intel_tv->margin[TV_MARGIN_RIGHT] != val) {
1461 intel_tv->margin[TV_MARGIN_RIGHT] = val;
ebcc8f2e
ZW		 1462 changed = true;
1463 } else if (property == dev->mode_config.tv_top_margin_property &&
ea5b213a
CW		 1464 intel_tv->margin[TV_MARGIN_TOP] != val) {
1465 intel_tv->margin[TV_MARGIN_TOP] = val;
ebcc8f2e
ZW		 1466 changed = true;
1467 } else if (property == dev->mode_config.tv_bottom_margin_property &&
ea5b213a
CW		 1468 intel_tv->margin[TV_MARGIN_BOTTOM] != val) {
1469 intel_tv->margin[TV_MARGIN_BOTTOM] = val;
ebcc8f2e
ZW		 1470 changed = true;
1471 } else if (property == dev->mode_config.tv_mode_property) {
2991196f 1472 if (val >= ARRAY_SIZE(tv_modes)) {
79e53945
JB		 1473 ret = -EINVAL;
1474 goto out;
1475 }
ea5b213a 1476 if (!strcmp(intel_tv->tv_format, tv_modes[val].name))
ebcc8f2e
ZW		 1477 goto out;
1478
ea5b213a 1479 intel_tv->tv_format = tv_modes[val].name;
ebcc8f2e 1480 changed = true;
79e53945
JB		 1481 } else {
1482 ret = -EINVAL;
1483 goto out;
1484 }
1485
7d6ff785 1486 if (changed && crtc)
c0c36b94 1487 intel_crtc_restore_mode(crtc);
79e53945
JB		 1488out:
1489 return ret;
1490}
1491
79e53945 1492static const struct drm_connector_funcs intel_tv_connector_funcs = {
6b5756a0 1493 .dpms = intel_connector_dpms,
79e53945
JB		 1494 .detect = intel_tv_detect,
1495 .destroy = intel_tv_destroy,
1496 .set_property = intel_tv_set_property,
1497 .fill_modes = drm_helper_probe_single_connector_modes,
1498};
1499
1500static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
1501 .mode_valid = intel_tv_mode_valid,
1502 .get_modes = intel_tv_get_modes,
df0e9248 1503 .best_encoder = intel_best_encoder,
79e53945
JB		 1504};
1505
79e53945 1506static const struct drm_encoder_funcs intel_tv_enc_funcs = {
ea5b213a 1507 .destroy = intel_encoder_destroy,
79e53945
JB		 1508};
1509
c3561438
ZY		 1510/*
1511 * Enumerate the child dev array parsed from VBT to check whether
1512 * the integrated TV is present.
1513 * If it is present, return 1.
1514 * If it is not present, return false.
1515 * If no child dev is parsed from VBT, it assumes that the TV is present.
1516 */
6e36595a 1517static int tv_is_present_in_vbt(struct drm_device *dev)
c3561438
ZY		 1518{
1519 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 1520 union child_device_config *p_child;
c3561438
ZY		 1521 int i, ret;
1522
41aa3448 1523 if (!dev_priv->vbt.child_dev_num)
c3561438
ZY		 1524 return 1;
1525
1526 ret = 0;
41aa3448
RV		 1527 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
1528 p_child = dev_priv->vbt.child_dev + i;
c3561438
ZY		 1529 /*
1530 * If the device type is not TV, continue.
1531 */
768f69c9
PZ		 1532 if (p_child->old.device_type != DEVICE_TYPE_INT_TV &&
1533 p_child->old.device_type != DEVICE_TYPE_TV)
c3561438
ZY		 1534 continue;
1535 /* Only when the addin_offset is non-zero, it is regarded
1536 * as present.
1537 */
768f69c9 1538 if (p_child->old.addin_offset) {
c3561438
ZY		 1539 ret = 1;
1540 break;
1541 }
1542 }
1543 return ret;
1544}
79e53945
JB		 1545
1546void
1547intel_tv_init(struct drm_device *dev)
1548{
1549 struct drm_i915_private *dev_priv = dev->dev_private;
1550 struct drm_connector *connector;
ea5b213a 1551 struct intel_tv *intel_tv;
21d40d37 1552 struct intel_encoder *intel_encoder;
0c41ee2b 1553 struct intel_connector *intel_connector;
79e53945 1554 u32 tv_dac_on, tv_dac_off, save_tv_dac;
763a4a01 1555 char *tv_format_names[ARRAY_SIZE(tv_modes)];
79e53945
JB		 1556 int i, initial_mode = 0;
1557
1558 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1559 return;
1560
c3561438
ZY		 1561 if (!tv_is_present_in_vbt(dev)) {
1562 DRM_DEBUG_KMS("Integrated TV is not present.\n");
1563 return;
1564 }
79e53945 1565 /* Even if we have an encoder we may not have a connector */
41aa3448 1566 if (!dev_priv->vbt.int_tv_support)
79e53945
JB		 1567 return;
1568
1569 /*
1570 * Sanity check the TV output by checking to see if the
1571 * DAC register holds a value
1572 */
1573 save_tv_dac = I915_READ(TV_DAC);
1574
1575 I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1576 tv_dac_on = I915_READ(TV_DAC);
1577
1578 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1579 tv_dac_off = I915_READ(TV_DAC);
1580
1581 I915_WRITE(TV_DAC, save_tv_dac);
1582
1583 /*
1584 * If the register does not hold the state change enable
1585 * bit, (either as a 0 or a 1), assume it doesn't really
1586 * exist
1587 */
1588 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1589 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1590 return;
1591
b14c5679 1592 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL);
ea5b213a 1593 if (!intel_tv) {
79e53945
JB		 1594 return;
1595 }
f8aed700 1596
b14c5679 1597 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
0c41ee2b 1598 if (!intel_connector) {
ea5b213a 1599 kfree(intel_tv);
0c41ee2b
ZW		 1600 return;
1601 }
1602
ea5b213a 1603 intel_encoder = &intel_tv->base;
0c41ee2b 1604 connector = &intel_connector->base;
79e53945 1605
8102e126
CW		 1606 /* The documentation, for the older chipsets at least, recommend
1607 * using a polling method rather than hotplug detection for TVs.
1608 * This is because in order to perform the hotplug detection, the PLLs
1609 * for the TV must be kept alive increasing power drain and starving
1610 * bandwidth from other encoders. Notably for instance, it causes
1611 * pipe underruns on Crestline when this encoder is supposedly idle.
1612 *
1613 * More recent chipsets favour HDMI rather than integrated S-Video.
1614 */
821450c6 1615 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
8102e126 1616
79e53945
JB		 1617 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1618 DRM_MODE_CONNECTOR_SVIDEO);
1619
4ef69c7a 1620 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
79e53945
JB		 1621 DRM_MODE_ENCODER_TVDAC);
1622
5d2d38dd 1623 intel_encoder->compute_config = intel_tv_compute_config;
cd91ef23 1624 intel_encoder->mode_set = intel_tv_mode_set;
6b5756a0
DV		 1625 intel_encoder->enable = intel_enable_tv;
1626 intel_encoder->disable = intel_disable_tv;
9a8ee983
DV		 1627 intel_encoder->get_hw_state = intel_tv_get_hw_state;
1628 intel_connector->get_hw_state = intel_connector_get_hw_state;
6b5756a0 1629
df0e9248 1630 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37
EA		 1631 intel_encoder->type = INTEL_OUTPUT_TVOUT;
1632 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
66a9278e 1633 intel_encoder->cloneable = false;
4ef69c7a
CW		 1634 intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1));
1635 intel_encoder->base.possible_clones = (1 << INTEL_OUTPUT_TVOUT);
ea5b213a 1636 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
79e53945
JB		 1637
1638 /* BIOS margin values */
ea5b213a
CW		 1639 intel_tv->margin[TV_MARGIN_LEFT] = 54;
1640 intel_tv->margin[TV_MARGIN_TOP] = 36;
1641 intel_tv->margin[TV_MARGIN_RIGHT] = 46;
1642 intel_tv->margin[TV_MARGIN_BOTTOM] = 37;
79e53945 1643
763a4a01 1644 intel_tv->tv_format = tv_modes[initial_mode].name;
79e53945 1645
79e53945
JB		 1646 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1647 connector->interlace_allowed = false;
1648 connector->doublescan_allowed = false;
1649
1650 /* Create TV properties then attach current values */
2991196f 1651 for (i = 0; i < ARRAY_SIZE(tv_modes); i++)
763a4a01
CW		 1652 tv_format_names[i] = (char *)tv_modes[i].name;
1653 drm_mode_create_tv_properties(dev,
1654 ARRAY_SIZE(tv_modes),
1655 tv_format_names);
79e53945 1656
662595df 1657 drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property,
79e53945 1658 initial_mode);
662595df 1659 drm_object_attach_property(&connector->base,
79e53945 1660 dev->mode_config.tv_left_margin_property,
ea5b213a 1661 intel_tv->margin[TV_MARGIN_LEFT]);
662595df 1662 drm_object_attach_property(&connector->base,
79e53945 1663 dev->mode_config.tv_top_margin_property,
ea5b213a 1664 intel_tv->margin[TV_MARGIN_TOP]);
662595df 1665 drm_object_attach_property(&connector->base,
79e53945 1666 dev->mode_config.tv_right_margin_property,
ea5b213a 1667 intel_tv->margin[TV_MARGIN_RIGHT]);
662595df 1668 drm_object_attach_property(&connector->base,
79e53945 1669 dev->mode_config.tv_bottom_margin_property,
ea5b213a 1670 intel_tv->margin[TV_MARGIN_BOTTOM]);
79e53945
JB		 1671 drm_sysfs_connector_add(connector);
1672}
Linux 6.x block layer and io_uring tree(s)