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drm/i915: extract intel_pipe_crc.h from intel_drv.h
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_tv.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2008 Intel Corporation
3 * Jesse Barnes <jesse.barnes@intel.com>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 *
27 */
28
29/** @file
30 * Integrated TV-out support for the 915GM and 945GM.
31 */
32
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
760285e7 36#include <drm/i915_drm.h>
ec7f29ff 37
79e53945 38#include "i915_drv.h"
ec7f29ff
JN		 39#include "intel_connector.h"
40#include "intel_drv.h"
79e53945
JB		 41
42enum tv_margin {
43 TV_MARGIN_LEFT, TV_MARGIN_TOP,
44 TV_MARGIN_RIGHT, TV_MARGIN_BOTTOM
45};
46
ea5b213a
CW		 47struct intel_tv {
48 struct intel_encoder base;
49
79e53945 50 int type;
79e53945
JB		 51};
52
53struct video_levels {
db49296b
TU		 54 u16 blank, black;
55 u8 burst;
79e53945
JB		 56};
57
58struct color_conversion {
59 u16 ry, gy, by, ay;
60 u16 ru, gu, bu, au;
61 u16 rv, gv, bv, av;
62};
63
64static const u32 filter_table[] = {
65 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
66 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
67 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
68 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
69 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
70 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
71 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
72 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
73 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
74 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
75 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
76 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
77 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
78 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
79 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
80 0xB1403000, 0x2E203500, 0x35002E20, 0x3000B140,
81 0x35A0B160, 0x2DC02E80, 0xB1403480, 0xB1603000,
82 0x2EA03640, 0x34002D80, 0x3000B120, 0x36E0B160,
83 0x2D202EF0, 0xB1203380, 0xB1603000, 0x2F303780,
84 0x33002CC0, 0x3000B100, 0x3820B160, 0x2C802F50,
85 0xB10032A0, 0xB1603000, 0x2F9038C0, 0x32202C20,
86 0x3000B0E0, 0x3980B160, 0x2BC02FC0, 0xB0E031C0,
87 0xB1603000, 0x2FF03A20, 0x31602B60, 0xB020B0C0,
88 0x3AE0B160, 0x2B001810, 0xB0C03120, 0xB140B020,
89 0x18283BA0, 0x30C02A80, 0xB020B0A0, 0x3C60B140,
90 0x2A201838, 0xB0A03080, 0xB120B020, 0x18383D20,
91 0x304029C0, 0xB040B080, 0x3DE0B100, 0x29601848,
92 0xB0803000, 0xB100B040, 0x18483EC0, 0xB0402900,
93 0xB040B060, 0x3F80B0C0, 0x28801858, 0xB060B080,
94 0xB0A0B060, 0x18602820, 0xB0A02820, 0x0000B060,
95 0x36403000, 0x2D002CC0, 0x30003640, 0x2D0036C0,
96 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
97 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
98 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
99 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
100 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
101 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
102 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
103 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
104 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
105 0x28003100, 0x28002F00, 0x00003100, 0x36403000,
106 0x2D002CC0, 0x30003640, 0x2D0036C0,
107 0x35C02CC0, 0x37403000, 0x2C802D40, 0x30003540,
108 0x2D8037C0, 0x34C02C40, 0x38403000, 0x2BC02E00,
109 0x30003440, 0x2E2038C0, 0x34002B80, 0x39803000,
110 0x2B402E40, 0x30003380, 0x2E603A00, 0x33402B00,
111 0x3A803040, 0x2A802EA0, 0x30403300, 0x2EC03B40,
112 0x32802A40, 0x3C003040, 0x2A002EC0, 0x30803240,
113 0x2EC03C80, 0x320029C0, 0x3D403080, 0x29402F00,
114 0x308031C0, 0x2F203DC0, 0x31802900, 0x3E8030C0,
115 0x28802F40, 0x30C03140, 0x2F203F40, 0x31402840,
116 0x28003100, 0x28002F00, 0x00003100,
117};
118
119/*
120 * Color conversion values have 3 separate fixed point formats:
121 *
122 * 10 bit fields (ay, au)
123 * 1.9 fixed point (b.bbbbbbbbb)
124 * 11 bit fields (ry, by, ru, gu, gv)
125 * exp.mantissa (ee.mmmmmmmmm)
126 * ee = 00 = 10^-1 (0.mmmmmmmmm)
127 * ee = 01 = 10^-2 (0.0mmmmmmmmm)
128 * ee = 10 = 10^-3 (0.00mmmmmmmmm)
129 * ee = 11 = 10^-4 (0.000mmmmmmmmm)
130 * 12 bit fields (gy, rv, bu)
131 * exp.mantissa (eee.mmmmmmmmm)
132 * eee = 000 = 10^-1 (0.mmmmmmmmm)
133 * eee = 001 = 10^-2 (0.0mmmmmmmmm)
134 * eee = 010 = 10^-3 (0.00mmmmmmmmm)
135 * eee = 011 = 10^-4 (0.000mmmmmmmmm)
136 * eee = 100 = reserved
137 * eee = 101 = reserved
138 * eee = 110 = reserved
139 * eee = 111 = 10^0 (m.mmmmmmmm) (only usable for 1.0 representation)
140 *
141 * Saturation and contrast are 8 bits, with their own representation:
142 * 8 bit field (saturation, contrast)
143 * exp.mantissa (ee.mmmmmm)
144 * ee = 00 = 10^-1 (0.mmmmmm)
145 * ee = 01 = 10^0 (m.mmmmm)
146 * ee = 10 = 10^1 (mm.mmmm)
147 * ee = 11 = 10^2 (mmm.mmm)
148 *
149 * Simple conversion function:
150 *
151 * static u32
152 * float_to_csc_11(float f)
153 * {
154 * u32 exp;
155 * u32 mant;
156 * u32 ret;
157 *
158 * if (f < 0)
159 * f = -f;
160 *
161 * if (f >= 1) {
162 * exp = 0x7;
0206e353 163 * mant = 1 << 8;
79e53945
JB		 164 * } else {
165 * for (exp = 0; exp < 3 && f < 0.5; exp++)
0206e353 166 * f *= 2.0;
79e53945
JB		 167 * mant = (f * (1 << 9) + 0.5);
168 * if (mant >= (1 << 9))
169 * mant = (1 << 9) - 1;
170 * }
171 * ret = (exp << 9) | mant;
172 * return ret;
173 * }
174 */
175
176/*
177 * Behold, magic numbers! If we plant them they might grow a big
178 * s-video cable to the sky... or something.
179 *
180 * Pre-converted to appropriate hex value.
181 */
182
183/*
184 * PAL & NTSC values for composite & s-video connections
185 */
186static const struct color_conversion ntsc_m_csc_composite = {
187 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 188 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
189 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 190};
191
192static const struct video_levels ntsc_m_levels_composite = {
193 .blank = 225, .black = 267, .burst = 113,
194};
195
196static const struct color_conversion ntsc_m_csc_svideo = {
ba01079c
ZW		 197 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
198 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
199 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 200};
201
202static const struct video_levels ntsc_m_levels_svideo = {
203 .blank = 266, .black = 316, .burst = 133,
204};
205
206static const struct color_conversion ntsc_j_csc_composite = {
207 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0119,
ba01079c
ZW		 208 .ru = 0x074c, .gu = 0x0546, .bu = 0x05ec, .au = 0x0200,
209 .rv = 0x035a, .gv = 0x0322, .bv = 0x06e1, .av = 0x0200,
79e53945
JB		 210};
211
212static const struct video_levels ntsc_j_levels_composite = {
213 .blank = 225, .black = 225, .burst = 113,
214};
215
216static const struct color_conversion ntsc_j_csc_svideo = {
217 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x014c,
ba01079c
ZW		 218 .ru = 0x0788, .gu = 0x0581, .bu = 0x0322, .au = 0x0200,
219 .rv = 0x0399, .gv = 0x0356, .bv = 0x070a, .av = 0x0200,
79e53945
JB		 220};
221
222static const struct video_levels ntsc_j_levels_svideo = {
223 .blank = 266, .black = 266, .burst = 133,
224};
225
226static const struct color_conversion pal_csc_composite = {
227 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0113,
ba01079c
ZW		 228 .ru = 0x0745, .gu = 0x053f, .bu = 0x05e1, .au = 0x0200,
229 .rv = 0x0353, .gv = 0x031c, .bv = 0x06dc, .av = 0x0200,
79e53945
JB		 230};
231
232static const struct video_levels pal_levels_composite = {
233 .blank = 237, .black = 237, .burst = 118,
234};
235
236static const struct color_conversion pal_csc_svideo = {
237 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
ba01079c
ZW		 238 .ru = 0x0780, .gu = 0x0579, .bu = 0x031c, .au = 0x0200,
239 .rv = 0x0390, .gv = 0x034f, .bv = 0x0705, .av = 0x0200,
79e53945
JB		 240};
241
242static const struct video_levels pal_levels_svideo = {
243 .blank = 280, .black = 280, .burst = 139,
244};
245
246static const struct color_conversion pal_m_csc_composite = {
247 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 248 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
249 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 250};
251
252static const struct video_levels pal_m_levels_composite = {
253 .blank = 225, .black = 267, .burst = 113,
254};
255
256static const struct color_conversion pal_m_csc_svideo = {
ba01079c
ZW		 257 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
258 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
259 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 260};
261
262static const struct video_levels pal_m_levels_svideo = {
263 .blank = 266, .black = 316, .burst = 133,
264};
265
266static const struct color_conversion pal_n_csc_composite = {
267 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0104,
ba01079c
ZW		 268 .ru = 0x0733, .gu = 0x052d, .bu = 0x05c7, .au = 0x0200,
269 .rv = 0x0340, .gv = 0x030c, .bv = 0x06d0, .av = 0x0200,
79e53945
JB		 270};
271
272static const struct video_levels pal_n_levels_composite = {
273 .blank = 225, .black = 267, .burst = 118,
274};
275
276static const struct color_conversion pal_n_csc_svideo = {
ba01079c
ZW		 277 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0133,
278 .ru = 0x076a, .gu = 0x0564, .bu = 0x030d, .au = 0x0200,
279 .rv = 0x037a, .gv = 0x033d, .bv = 0x06f6, .av = 0x0200,
79e53945
JB		 280};
281
282static const struct video_levels pal_n_levels_svideo = {
283 .blank = 266, .black = 316, .burst = 139,
284};
285
286/*
287 * Component connections
288 */
289static const struct color_conversion sdtv_csc_yprpb = {
ba01079c
ZW		 290 .ry = 0x0332, .gy = 0x012d, .by = 0x07d3, .ay = 0x0145,
291 .ru = 0x0559, .gu = 0x0353, .bu = 0x0100, .au = 0x0200,
292 .rv = 0x0100, .gv = 0x03ad, .bv = 0x074d, .av = 0x0200,
79e53945
JB		 293};
294
79e53945 295static const struct color_conversion hdtv_csc_yprpb = {
ba01079c
ZW		 296 .ry = 0x05b3, .gy = 0x016e, .by = 0x0728, .ay = 0x0145,
297 .ru = 0x07d5, .gu = 0x038b, .bu = 0x0100, .au = 0x0200,
298 .rv = 0x0100, .gv = 0x03d1, .bv = 0x06bc, .av = 0x0200,
79e53945
JB		 299};
300
79e53945
JB		 301static const struct video_levels component_levels = {
302 .blank = 279, .black = 279, .burst = 0,
303};
304
305
306struct tv_mode {
763a4a01 307 const char *name;
db49296b
TU		 308
309 u32 clock;
310 u16 refresh; /* in millihertz (for precision) */
4f503798 311 u8 oversample;
db49296b
TU		 312 u8 hsync_end;
313 u16 hblank_start, hblank_end, htotal;
314 bool progressive : 1, trilevel_sync : 1, component_only : 1;
315 u8 vsync_start_f1, vsync_start_f2, vsync_len;
316 bool veq_ena : 1;
317 u8 veq_start_f1, veq_start_f2, veq_len;
318 u8 vi_end_f1, vi_end_f2;
319 u16 nbr_end;
320 bool burst_ena : 1;
321 u8 hburst_start, hburst_len;
322 u8 vburst_start_f1;
323 u16 vburst_end_f1;
324 u8 vburst_start_f2;
325 u16 vburst_end_f2;
326 u8 vburst_start_f3;
327 u16 vburst_end_f3;
328 u8 vburst_start_f4;
329 u16 vburst_end_f4;
79e53945
JB		 330 /*
331 * subcarrier programming
332 */
db49296b
TU		 333 u16 dda2_size, dda3_size;
334 u8 dda1_inc;
335 u16 dda2_inc, dda3_inc;
79e53945 336 u32 sc_reset;
db49296b 337 bool pal_burst : 1;
79e53945
JB		 338 /*
339 * blank/black levels
340 */
341 const struct video_levels *composite_levels, *svideo_levels;
342 const struct color_conversion *composite_color, *svideo_color;
343 const u32 *filter_table;
79e53945
JB		 344};
345
346
347/*
348 * Sub carrier DDA
349 *
350 * I think this works as follows:
351 *
352 * subcarrier freq = pixel_clock * (dda1_inc + dda2_inc / dda2_size) / 4096
353 *
354 * Presumably, when dda3 is added in, it gets to adjust the dda2_inc value
355 *
356 * So,
357 * dda1_ideal = subcarrier/pixel * 4096
358 * dda1_inc = floor (dda1_ideal)
359 * dda2 = dda1_ideal - dda1_inc
360 *
361 * then pick a ratio for dda2 that gives the closest approximation. If
362 * you can't get close enough, you can play with dda3 as well. This
363 * seems likely to happen when dda2 is small as the jumps would be larger
364 *
365 * To invert this,
366 *
367 * pixel_clock = subcarrier * 4096 / (dda1_inc + dda2_inc / dda2_size)
368 *
369 * The constants below were all computed using a 107.520MHz clock
370 */
371
3930f18a 372/*
79e53945
JB		 373 * Register programming values for TV modes.
374 *
375 * These values account for -1s required.
376 */
005568be 377static const struct tv_mode tv_modes[] = {
79e53945
JB		 378 {
379 .name = "NTSC-M",
ba01079c 380 .clock = 108000,
23bd15ec 381 .refresh = 59940,
4f503798 382 .oversample = 8,
56f62308 383 .component_only = false,
79e53945
JB		 384 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
385
386 .hsync_end = 64, .hblank_end = 124,
387 .hblank_start = 836, .htotal = 857,
388
389 .progressive = false, .trilevel_sync = false,
390
391 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
392 .vsync_len = 6,
393
0206e353 394 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 395 .veq_start_f2 = 1, .veq_len = 18,
396
397 .vi_end_f1 = 20, .vi_end_f2 = 21,
398 .nbr_end = 240,
399
400 .burst_ena = true,
401 .hburst_start = 72, .hburst_len = 34,
402 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
403 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
404 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
405 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
406
407 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 408 .dda1_inc = 135,
409 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 410 .dda3_inc = 0, .dda3_size = 0,
411 .sc_reset = TV_SC_RESET_EVERY_4,
412 .pal_burst = false,
413
414 .composite_levels = &ntsc_m_levels_composite,
415 .composite_color = &ntsc_m_csc_composite,
416 .svideo_levels = &ntsc_m_levels_svideo,
417 .svideo_color = &ntsc_m_csc_svideo,
418
419 .filter_table = filter_table,
420 },
421 {
422 .name = "NTSC-443",
ba01079c 423 .clock = 108000,
23bd15ec 424 .refresh = 59940,
4f503798 425 .oversample = 8,
56f62308 426 .component_only = false,
79e53945
JB		 427 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 4.43MHz */
428 .hsync_end = 64, .hblank_end = 124,
429 .hblank_start = 836, .htotal = 857,
430
431 .progressive = false, .trilevel_sync = false,
432
433 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
434 .vsync_len = 6,
435
0206e353 436 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 437 .veq_start_f2 = 1, .veq_len = 18,
438
439 .vi_end_f1 = 20, .vi_end_f2 = 21,
440 .nbr_end = 240,
441
3ca87e82 442 .burst_ena = true,
79e53945
JB		 443 .hburst_start = 72, .hburst_len = 34,
444 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
445 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
446 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
447 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
448
449 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
450 .dda1_inc = 168,
ba01079c
ZW		 451 .dda2_inc = 4093, .dda2_size = 27456,
452 .dda3_inc = 310, .dda3_size = 525,
453 .sc_reset = TV_SC_RESET_NEVER,
454 .pal_burst = false,
79e53945
JB		 455
456 .composite_levels = &ntsc_m_levels_composite,
457 .composite_color = &ntsc_m_csc_composite,
458 .svideo_levels = &ntsc_m_levels_svideo,
459 .svideo_color = &ntsc_m_csc_svideo,
460
461 .filter_table = filter_table,
462 },
463 {
464 .name = "NTSC-J",
ba01079c 465 .clock = 108000,
23bd15ec 466 .refresh = 59940,
4f503798 467 .oversample = 8,
56f62308 468 .component_only = false,
79e53945
JB		 469
470 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
471 .hsync_end = 64, .hblank_end = 124,
472 .hblank_start = 836, .htotal = 857,
473
474 .progressive = false, .trilevel_sync = false,
475
476 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
477 .vsync_len = 6,
478
0206e353 479 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 480 .veq_start_f2 = 1, .veq_len = 18,
481
482 .vi_end_f1 = 20, .vi_end_f2 = 21,
483 .nbr_end = 240,
484
485 .burst_ena = true,
486 .hburst_start = 72, .hburst_len = 34,
487 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
488 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
489 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
490 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
491
492 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 493 .dda1_inc = 135,
494 .dda2_inc = 20800, .dda2_size = 27456,
79e53945
JB		 495 .dda3_inc = 0, .dda3_size = 0,
496 .sc_reset = TV_SC_RESET_EVERY_4,
497 .pal_burst = false,
498
499 .composite_levels = &ntsc_j_levels_composite,
500 .composite_color = &ntsc_j_csc_composite,
501 .svideo_levels = &ntsc_j_levels_svideo,
502 .svideo_color = &ntsc_j_csc_svideo,
503
504 .filter_table = filter_table,
505 },
506 {
507 .name = "PAL-M",
ba01079c 508 .clock = 108000,
23bd15ec 509 .refresh = 59940,
4f503798 510 .oversample = 8,
56f62308 511 .component_only = false,
79e53945
JB		 512
513 /* 525 Lines, 60 Fields, 15.734KHz line, Sub-Carrier 3.580MHz */
514 .hsync_end = 64, .hblank_end = 124,
515 .hblank_start = 836, .htotal = 857,
516
517 .progressive = false, .trilevel_sync = false,
518
519 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
520 .vsync_len = 6,
521
0206e353 522 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 523 .veq_start_f2 = 1, .veq_len = 18,
524
525 .vi_end_f1 = 20, .vi_end_f2 = 21,
526 .nbr_end = 240,
527
528 .burst_ena = true,
529 .hburst_start = 72, .hburst_len = 34,
530 .vburst_start_f1 = 9, .vburst_end_f1 = 240,
531 .vburst_start_f2 = 10, .vburst_end_f2 = 240,
532 .vburst_start_f3 = 9, .vburst_end_f3 = 240,
533 .vburst_start_f4 = 10, .vburst_end_f4 = 240,
534
535 /* desired 3.5800000 actual 3.5800000 clock 107.52 */
ba01079c
ZW		 536 .dda1_inc = 135,
537 .dda2_inc = 16704, .dda2_size = 27456,
79e53945 538 .dda3_inc = 0, .dda3_size = 0,
ba01079c
ZW		 539 .sc_reset = TV_SC_RESET_EVERY_8,
540 .pal_burst = true,
79e53945
JB		 541
542 .composite_levels = &pal_m_levels_composite,
543 .composite_color = &pal_m_csc_composite,
544 .svideo_levels = &pal_m_levels_svideo,
545 .svideo_color = &pal_m_csc_svideo,
546
547 .filter_table = filter_table,
548 },
549 {
550 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
551 .name = "PAL-N",
ba01079c 552 .clock = 108000,
23bd15ec 553 .refresh = 50000,
4f503798 554 .oversample = 8,
56f62308 555 .component_only = false,
79e53945
JB		 556
557 .hsync_end = 64, .hblank_end = 128,
558 .hblank_start = 844, .htotal = 863,
559
560 .progressive = false, .trilevel_sync = false,
561
562
563 .vsync_start_f1 = 6, .vsync_start_f2 = 7,
564 .vsync_len = 6,
565
0206e353 566 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 567 .veq_start_f2 = 1, .veq_len = 18,
568
569 .vi_end_f1 = 24, .vi_end_f2 = 25,
570 .nbr_end = 286,
571
572 .burst_ena = true,
0206e353 573 .hburst_start = 73, .hburst_len = 34,
79e53945
JB		 574 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
575 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
576 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
577 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
578
579
580 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
ba01079c
ZW		 581 .dda1_inc = 135,
582 .dda2_inc = 23578, .dda2_size = 27648,
583 .dda3_inc = 134, .dda3_size = 625,
79e53945
JB		 584 .sc_reset = TV_SC_RESET_EVERY_8,
585 .pal_burst = true,
586
587 .composite_levels = &pal_n_levels_composite,
588 .composite_color = &pal_n_csc_composite,
589 .svideo_levels = &pal_n_levels_svideo,
590 .svideo_color = &pal_n_csc_svideo,
591
592 .filter_table = filter_table,
593 },
594 {
595 /* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
596 .name = "PAL",
ba01079c 597 .clock = 108000,
23bd15ec 598 .refresh = 50000,
4f503798 599 .oversample = 8,
56f62308 600 .component_only = false,
79e53945 601
ba01079c 602 .hsync_end = 64, .hblank_end = 142,
79e53945
JB		 603 .hblank_start = 844, .htotal = 863,
604
605 .progressive = false, .trilevel_sync = false,
606
607 .vsync_start_f1 = 5, .vsync_start_f2 = 6,
608 .vsync_len = 5,
609
0206e353 610 .veq_ena = true, .veq_start_f1 = 0,
79e53945
JB		 611 .veq_start_f2 = 1, .veq_len = 15,
612
613 .vi_end_f1 = 24, .vi_end_f2 = 25,
614 .nbr_end = 286,
615
616 .burst_ena = true,
617 .hburst_start = 73, .hburst_len = 32,
618 .vburst_start_f1 = 8, .vburst_end_f1 = 285,
619 .vburst_start_f2 = 8, .vburst_end_f2 = 286,
620 .vburst_start_f3 = 9, .vburst_end_f3 = 286,
621 .vburst_start_f4 = 9, .vburst_end_f4 = 285,
622
623 /* desired 4.4336180 actual 4.4336180 clock 107.52 */
624 .dda1_inc = 168,
ba01079c
ZW		 625 .dda2_inc = 4122, .dda2_size = 27648,
626 .dda3_inc = 67, .dda3_size = 625,
79e53945
JB		 627 .sc_reset = TV_SC_RESET_EVERY_8,
628 .pal_burst = true,
629
630 .composite_levels = &pal_levels_composite,
631 .composite_color = &pal_csc_composite,
632 .svideo_levels = &pal_levels_svideo,
633 .svideo_color = &pal_csc_svideo,
634
635 .filter_table = filter_table,
636 },
9589919f
RV		 637 {
638 .name = "480p",
d5152823 639 .clock = 108000,
9589919f 640 .refresh = 59940,
4f503798 641 .oversample = 4,
56f62308 642 .component_only = true,
9589919f
RV		 643
644 .hsync_end = 64, .hblank_end = 122,
645 .hblank_start = 842, .htotal = 857,
646
647 .progressive = true, .trilevel_sync = false,
648
649 .vsync_start_f1 = 12, .vsync_start_f2 = 12,
650 .vsync_len = 12,
651
652 .veq_ena = false,
653
654 .vi_end_f1 = 44, .vi_end_f2 = 44,
655 .nbr_end = 479,
656
657 .burst_ena = false,
658
659 .filter_table = filter_table,
660 },
661 {
662 .name = "576p",
d5152823 663 .clock = 108000,
9589919f 664 .refresh = 50000,
4f503798 665 .oversample = 4,
56f62308 666 .component_only = true,
9589919f
RV		 667
668 .hsync_end = 64, .hblank_end = 139,
669 .hblank_start = 859, .htotal = 863,
670
671 .progressive = true, .trilevel_sync = false,
672
673 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
674 .vsync_len = 10,
675
676 .veq_ena = false,
677
678 .vi_end_f1 = 48, .vi_end_f2 = 48,
679 .nbr_end = 575,
680
681 .burst_ena = false,
682
683 .filter_table = filter_table,
684 },
79e53945
JB		 685 {
686 .name = "720p@60Hz",
d5152823 687 .clock = 148500,
79e53945 688 .refresh = 60000,
4f503798 689 .oversample = 2,
56f62308 690 .component_only = true,
79e53945
JB		 691
692 .hsync_end = 80, .hblank_end = 300,
693 .hblank_start = 1580, .htotal = 1649,
694
0206e353 695 .progressive = true, .trilevel_sync = true,
79e53945
JB		 696
697 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
698 .vsync_len = 10,
699
700 .veq_ena = false,
701
702 .vi_end_f1 = 29, .vi_end_f2 = 29,
703 .nbr_end = 719,
704
705 .burst_ena = false,
706
707 .filter_table = filter_table,
708 },
79e53945
JB		 709 {
710 .name = "720p@50Hz",
d5152823 711 .clock = 148500,
79e53945 712 .refresh = 50000,
4f503798 713 .oversample = 2,
56f62308 714 .component_only = true,
79e53945
JB		 715
716 .hsync_end = 80, .hblank_end = 300,
717 .hblank_start = 1580, .htotal = 1979,
718
0206e353 719 .progressive = true, .trilevel_sync = true,
79e53945
JB		 720
721 .vsync_start_f1 = 10, .vsync_start_f2 = 10,
722 .vsync_len = 10,
723
724 .veq_ena = false,
725
726 .vi_end_f1 = 29, .vi_end_f2 = 29,
727 .nbr_end = 719,
728
729 .burst_ena = false,
730
731 .filter_table = filter_table,
79e53945
JB		 732 },
733 {
734 .name = "1080i@50Hz",
d5152823 735 .clock = 148500,
23bd15ec 736 .refresh = 50000,
4f503798 737 .oversample = 2,
56f62308 738 .component_only = true,
79e53945
JB		 739
740 .hsync_end = 88, .hblank_end = 235,
741 .hblank_start = 2155, .htotal = 2639,
742
0206e353 743 .progressive = false, .trilevel_sync = true,
79e53945
JB		 744
745 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
746 .vsync_len = 10,
747
0206e353 748 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 749 .veq_start_f2 = 4, .veq_len = 10,
750
751
752 .vi_end_f1 = 21, .vi_end_f2 = 22,
753 .nbr_end = 539,
754
755 .burst_ena = false,
756
757 .filter_table = filter_table,
758 },
759 {
760 .name = "1080i@60Hz",
d5152823 761 .clock = 148500,
23bd15ec 762 .refresh = 60000,
4f503798 763 .oversample = 2,
56f62308 764 .component_only = true,
79e53945
JB		 765
766 .hsync_end = 88, .hblank_end = 235,
767 .hblank_start = 2155, .htotal = 2199,
768
0206e353 769 .progressive = false, .trilevel_sync = true,
79e53945
JB		 770
771 .vsync_start_f1 = 4, .vsync_start_f2 = 5,
772 .vsync_len = 10,
773
0206e353 774 .veq_ena = true, .veq_start_f1 = 4,
79e53945
JB		 775 .veq_start_f2 = 4, .veq_len = 10,
776
777
778 .vi_end_f1 = 21, .vi_end_f2 = 22,
779 .nbr_end = 539,
780
781 .burst_ena = false,
782
79e53945
JB		 783 .filter_table = filter_table,
784 },
a0ff6779
VS		 785
786 {
787 .name = "1080p@30Hz",
788 .clock = 148500,
789 .refresh = 30000,
790 .oversample = 2,
791 .component_only = true,
792
793 .hsync_end = 88, .hblank_end = 235,
794 .hblank_start = 2155, .htotal = 2199,
795
796 .progressive = true, .trilevel_sync = true,
797
798 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
799 .vsync_len = 10,
800
801 .veq_ena = false, .veq_start_f1 = 0,
802 .veq_start_f2 = 0, .veq_len = 0,
803
804 .vi_end_f1 = 44, .vi_end_f2 = 44,
805 .nbr_end = 1079,
806
807 .burst_ena = false,
808
809 .filter_table = filter_table,
810 },
811
812 {
813 .name = "1080p@50Hz",
814 .clock = 148500,
815 .refresh = 50000,
816 .oversample = 1,
817 .component_only = true,
818
819 .hsync_end = 88, .hblank_end = 235,
820 .hblank_start = 2155, .htotal = 2639,
821
822 .progressive = true, .trilevel_sync = true,
823
824 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
825 .vsync_len = 10,
826
827 .veq_ena = false, .veq_start_f1 = 0,
828 .veq_start_f2 = 0, .veq_len = 0,
829
830 .vi_end_f1 = 44, .vi_end_f2 = 44,
831 .nbr_end = 1079,
832
833 .burst_ena = false,
834
835 .filter_table = filter_table,
836 },
837
838 {
839 .name = "1080p@60Hz",
840 .clock = 148500,
841 .refresh = 60000,
842 .oversample = 1,
843 .component_only = true,
844
845 .hsync_end = 88, .hblank_end = 235,
846 .hblank_start = 2155, .htotal = 2199,
847
848 .progressive = true, .trilevel_sync = true,
849
850 .vsync_start_f1 = 8, .vsync_start_f2 = 8,
851 .vsync_len = 10,
852
853 .veq_ena = false, .veq_start_f1 = 0,
854 .veq_start_f2 = 0, .veq_len = 0,
855
856 .vi_end_f1 = 44, .vi_end_f2 = 44,
857 .nbr_end = 1079,
858
859 .burst_ena = false,
860
861 .filter_table = filter_table,
862 },
79e53945
JB		 863};
864
690157f0
VS		 865struct intel_tv_connector_state {
866 struct drm_connector_state base;
867
868 /*
869 * May need to override the user margins for
870 * gen3 >1024 wide source vertical centering.
871 */
872 struct {
873 u16 top, bottom;
874 } margins;
875
876 bool bypass_vfilter;
877};
878
879#define to_intel_tv_connector_state(x) container_of(x, struct intel_tv_connector_state, base)
880
881static struct drm_connector_state *
882intel_tv_connector_duplicate_state(struct drm_connector *connector)
883{
884 struct intel_tv_connector_state *state;
885
886 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
887 if (!state)
888 return NULL;
889
890 __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
891 return &state->base;
892}
893
cd91ef23 894static struct intel_tv *enc_to_tv(struct intel_encoder *encoder)
ea5b213a 895{
cd91ef23 896 return container_of(encoder, struct intel_tv, base);
ea5b213a
CW		 897}
898
df0e9248
CW		 899static struct intel_tv *intel_attached_tv(struct drm_connector *connector)
900{
cd91ef23 901 return enc_to_tv(intel_attached_encoder(connector));
df0e9248
CW		 902}
903
9a8ee983
DV		 904static bool
905intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe)
906{
4add0f6b 907 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
9a8ee983
DV		 908 u32 tmp = I915_READ(TV_CTL);
909
4add0f6b 910 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT;
9a8ee983 911
4add0f6b 912 return tmp & TV_ENC_ENABLE;
9a8ee983
DV		 913}
914
79e53945 915static void
fd6bbda9 916intel_enable_tv(struct intel_encoder *encoder,
5f88a9c6
VS		 917 const struct intel_crtc_state *pipe_config,
918 const struct drm_connector_state *conn_state)
79e53945 919{
6b5756a0 920 struct drm_device *dev = encoder->base.dev;
fac5e23e 921 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 922
7a98948f 923 /* Prevents vblank waits from timing out in intel_tv_detect_type() */
0f0f74bc 924 intel_wait_for_vblank(dev_priv,
a7f519ba 925 to_intel_crtc(pipe_config->base.crtc)->pipe);
7a98948f 926
6b5756a0
DV		 927 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE);
928}
929
930static void
fd6bbda9 931intel_disable_tv(struct intel_encoder *encoder,
5f88a9c6
VS		 932 const struct intel_crtc_state *old_crtc_state,
933 const struct drm_connector_state *old_conn_state)
6b5756a0
DV		 934{
935 struct drm_device *dev = encoder->base.dev;
fac5e23e 936 struct drm_i915_private *dev_priv = to_i915(dev);
6b5756a0
DV		 937
938 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE);
79e53945
JB		 939}
940
5f88a9c6 941static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state)
79e53945 942{
0e891b3f 943 int format = conn_state->tv.mode;
79e53945 944
0e891b3f 945 return &tv_modes[format];
79e53945
JB		 946}
947
948static enum drm_mode_status
763a4a01
CW		 949intel_tv_mode_valid(struct drm_connector *connector,
950 struct drm_display_mode *mode)
79e53945 951{
0e891b3f 952 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
54c032b3
MK		 953 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
954
e4dd27aa
VS		 955 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
956 return MODE_NO_DBLESCAN;
957
54c032b3
MK		 958 if (mode->clock > max_dotclk)
959 return MODE_CLOCK_HIGH;
79e53945
JB		 960
961 /* Ensure TV refresh is close to desired refresh */
0d0884ce
ZY		 962 if (tv_mode && abs(tv_mode->refresh - drm_mode_vrefresh(mode) * 1000)
963 < 1000)
79e53945 964 return MODE_OK;
763a4a01 965
79e53945
JB		 966 return MODE_CLOCK_RANGE;
967}
968
65ddf7f9
VS		 969static int
970intel_tv_mode_vdisplay(const struct tv_mode *tv_mode)
971{
972 if (tv_mode->progressive)
973 return tv_mode->nbr_end + 1;
974 else
975 return 2 * (tv_mode->nbr_end + 1);
976}
79e53945 977
e3bb355c
VS		 978static void
979intel_tv_mode_to_mode(struct drm_display_mode *mode,
980 const struct tv_mode *tv_mode)
981{
982 mode->clock = tv_mode->clock /
983 (tv_mode->oversample >> !tv_mode->progressive);
984
985 /*
986 * tv_mode horizontal timings:
987 *
988 * hsync_end
989 * | hblank_end
990 * | | hblank_start
991 * | | | htotal
992 * | _______ |
993 * ____/ \___
994 * \__/ \
995 */
996 mode->hdisplay =
997 tv_mode->hblank_start - tv_mode->hblank_end;
998 mode->hsync_start = mode->hdisplay +
999 tv_mode->htotal - tv_mode->hblank_start;
1000 mode->hsync_end = mode->hsync_start +
1001 tv_mode->hsync_end;
1002 mode->htotal = tv_mode->htotal + 1;
1003
1004 /*
1005 * tv_mode vertical timings:
1006 *
1007 * vsync_start
1008 * | vsync_end
1009 * | | vi_end nbr_end
1010 * | | | |
1011 * | | _______
1012 * \__ ____/ \
1013 * \__/
1014 */
1015 mode->vdisplay = intel_tv_mode_vdisplay(tv_mode);
1016 if (tv_mode->progressive) {
1017 mode->vsync_start = mode->vdisplay +
1018 tv_mode->vsync_start_f1 + 1;
1019 mode->vsync_end = mode->vsync_start +
1020 tv_mode->vsync_len;
1021 mode->vtotal = mode->vdisplay +
1022 tv_mode->vi_end_f1 + 1;
1023 } else {
1024 mode->vsync_start = mode->vdisplay +
1025 tv_mode->vsync_start_f1 + 1 +
1026 tv_mode->vsync_start_f2 + 1;
1027 mode->vsync_end = mode->vsync_start +
1028 2 * tv_mode->vsync_len;
1029 mode->vtotal = mode->vdisplay +
1030 tv_mode->vi_end_f1 + 1 +
1031 tv_mode->vi_end_f2 + 1;
1032 }
1033
1034 /* TV has it's own notion of sync and other mode flags, so clear them. */
1035 mode->flags = 0;
1036
1037 mode->vrefresh = 0;
1038 mode->vrefresh = drm_mode_vrefresh(mode);
1039
1040 snprintf(mode->name, sizeof(mode->name),
1041 "%dx%d%c (%s)",
1042 mode->hdisplay, mode->vdisplay,
1043 tv_mode->progressive ? 'p' : 'i',
1044 tv_mode->name);
1045}
1046
1047static void intel_tv_scale_mode_horiz(struct drm_display_mode *mode,
1048 int hdisplay, int left_margin,
1049 int right_margin)
1050{
1051 int hsync_start = mode->hsync_start - mode->hdisplay + right_margin;
1052 int hsync_end = mode->hsync_end - mode->hdisplay + right_margin;
1053 int new_htotal = mode->htotal * hdisplay /
1054 (mode->hdisplay - left_margin - right_margin);
1055
1056 mode->clock = mode->clock * new_htotal / mode->htotal;
1057
1058 mode->hdisplay = hdisplay;
1059 mode->hsync_start = hdisplay + hsync_start * new_htotal / mode->htotal;
1060 mode->hsync_end = hdisplay + hsync_end * new_htotal / mode->htotal;
1061 mode->htotal = new_htotal;
1062}
1063
1064static void intel_tv_scale_mode_vert(struct drm_display_mode *mode,
1065 int vdisplay, int top_margin,
1066 int bottom_margin)
1067{
1068 int vsync_start = mode->vsync_start - mode->vdisplay + bottom_margin;
1069 int vsync_end = mode->vsync_end - mode->vdisplay + bottom_margin;
1070 int new_vtotal = mode->vtotal * vdisplay /
1071 (mode->vdisplay - top_margin - bottom_margin);
1072
1073 mode->clock = mode->clock * new_vtotal / mode->vtotal;
1074
1075 mode->vdisplay = vdisplay;
1076 mode->vsync_start = vdisplay + vsync_start * new_vtotal / mode->vtotal;
1077 mode->vsync_end = vdisplay + vsync_end * new_vtotal / mode->vtotal;
1078 mode->vtotal = new_vtotal;
1079}
1080
7a495cfd
DV		 1081static void
1082intel_tv_get_config(struct intel_encoder *encoder,
5cec258b 1083 struct intel_crtc_state *pipe_config)
7a495cfd 1084{
e3bb355c
VS		 1085 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1086 struct drm_display_mode *adjusted_mode =
1087 &pipe_config->base.adjusted_mode;
1088 struct drm_display_mode mode = {};
1089 u32 tv_ctl, hctl1, hctl3, vctl1, vctl2, tmp;
1090 struct tv_mode tv_mode = {};
1091 int hdisplay = adjusted_mode->crtc_hdisplay;
1092 int vdisplay = adjusted_mode->crtc_vdisplay;
1093 int xsize, ysize, xpos, ypos;
1094
e1214b95
VS		 1095 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT);
1096
e3bb355c
VS		 1097 tv_ctl = I915_READ(TV_CTL);
1098 hctl1 = I915_READ(TV_H_CTL_1);
1099 hctl3 = I915_READ(TV_H_CTL_3);
1100 vctl1 = I915_READ(TV_V_CTL_1);
1101 vctl2 = I915_READ(TV_V_CTL_2);
1102
1103 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT;
1104 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT;
1105
1106 tv_mode.hblank_start = (hctl3 & TV_HBLANK_START_MASK) >> TV_HBLANK_START_SHIFT;
1107 tv_mode.hblank_end = (hctl3 & TV_HSYNC_END_MASK) >> TV_HBLANK_END_SHIFT;
1108
1109 tv_mode.nbr_end = (vctl1 & TV_NBR_END_MASK) >> TV_NBR_END_SHIFT;
1110 tv_mode.vi_end_f1 = (vctl1 & TV_VI_END_F1_MASK) >> TV_VI_END_F1_SHIFT;
1111 tv_mode.vi_end_f2 = (vctl1 & TV_VI_END_F2_MASK) >> TV_VI_END_F2_SHIFT;
1112
1113 tv_mode.vsync_len = (vctl2 & TV_VSYNC_LEN_MASK) >> TV_VSYNC_LEN_SHIFT;
1114 tv_mode.vsync_start_f1 = (vctl2 & TV_VSYNC_START_F1_MASK) >> TV_VSYNC_START_F1_SHIFT;
1115 tv_mode.vsync_start_f2 = (vctl2 & TV_VSYNC_START_F2_MASK) >> TV_VSYNC_START_F2_SHIFT;
1116
1117 tv_mode.clock = pipe_config->port_clock;
1118
1119 tv_mode.progressive = tv_ctl & TV_PROGRESSIVE;
1120
1121 switch (tv_ctl & TV_OVERSAMPLE_MASK) {
1122 case TV_OVERSAMPLE_8X:
1123 tv_mode.oversample = 8;
1124 break;
1125 case TV_OVERSAMPLE_4X:
1126 tv_mode.oversample = 4;
1127 break;
1128 case TV_OVERSAMPLE_2X:
1129 tv_mode.oversample = 2;
1130 break;
1131 default:
1132 tv_mode.oversample = 1;
1133 break;
1134 }
1135
1136 tmp = I915_READ(TV_WIN_POS);
1137 xpos = tmp >> 16;
1138 ypos = tmp & 0xffff;
1139
1140 tmp = I915_READ(TV_WIN_SIZE);
1141 xsize = tmp >> 16;
1142 ysize = tmp & 0xffff;
1143
1144 intel_tv_mode_to_mode(&mode, &tv_mode);
1145
1146 DRM_DEBUG_KMS("TV mode:\n");
1147 drm_mode_debug_printmodeline(&mode);
1148
1149 intel_tv_scale_mode_horiz(&mode, hdisplay,
1150 xpos, mode.hdisplay - xsize - xpos);
1151 intel_tv_scale_mode_vert(&mode, vdisplay,
1152 ypos, mode.vdisplay - ysize - ypos);
1153
1154 adjusted_mode->crtc_clock = mode.clock;
addc80f0
VS		 1155 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1156 adjusted_mode->crtc_clock /= 2;
8a920e24
VS		 1157
1158 /* pixel counter doesn't work on i965gm TV output */
1159 if (IS_I965GM(dev_priv))
1160 adjusted_mode->private_flags |=
1161 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
7a495cfd
DV		 1162}
1163
68e94f62
VS		 1164static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv,
1165 int hdisplay)
1166{
1167 return IS_GEN(dev_priv, 3) && hdisplay > 1024;
1168}
1169
1170static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode,
1171 const struct drm_connector_state *conn_state,
1172 int vdisplay)
1173{
1174 return tv_mode->crtc_vdisplay -
1175 conn_state->tv.margins.top -
1176 conn_state->tv.margins.bottom !=
1177 vdisplay;
1178}
1179
204474a6 1180static int
5d2d38dd 1181intel_tv_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1182 struct intel_crtc_state *pipe_config,
1183 struct drm_connector_state *conn_state)
79e53945 1184{
690157f0
VS		 1185 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1186 struct intel_tv_connector_state *tv_conn_state =
1187 to_intel_tv_connector_state(conn_state);
0e891b3f 1188 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
e4dd27aa
VS		 1189 struct drm_display_mode *adjusted_mode =
1190 &pipe_config->base.adjusted_mode;
e3bb355c
VS		 1191 int hdisplay = adjusted_mode->crtc_hdisplay;
1192 int vdisplay = adjusted_mode->crtc_vdisplay;
79e53945
JB		 1193
1194 if (!tv_mode)
204474a6 1195 return -EINVAL;
79e53945 1196
e4dd27aa 1197 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
204474a6 1198 return -EINVAL;
e4dd27aa 1199
d9facae6 1200 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
e3bb355c 1201
5d2d38dd
DV		 1202 DRM_DEBUG_KMS("forcing bpc to 8 for TV\n");
1203 pipe_config->pipe_bpp = 8*3;
1204
e3bb355c
VS		 1205 pipe_config->port_clock = tv_mode->clock;
1206
1207 intel_tv_mode_to_mode(adjusted_mode, tv_mode);
690157f0
VS		 1208 drm_mode_set_crtcinfo(adjusted_mode, 0);
1209
68e94f62
VS		 1210 if (intel_tv_source_too_wide(dev_priv, hdisplay) ||
1211 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) {
690157f0
VS		 1212 int extra, top, bottom;
1213
1214 extra = adjusted_mode->crtc_vdisplay - vdisplay;
1215
1216 if (extra < 0) {
1217 DRM_DEBUG_KMS("No vertical scaling for >1024 pixel wide modes\n");
6a2a9404 1218 return -EINVAL;
690157f0
VS		 1219 }
1220
1221 /* Need to turn off the vertical filter and center the image */
1222
1223 /* Attempt to maintain the relative sizes of the margins */
1224 top = conn_state->tv.margins.top;
1225 bottom = conn_state->tv.margins.bottom;
1226
1227 if (top + bottom)
1228 top = extra * top / (top + bottom);
1229 else
1230 top = extra / 2;
1231 bottom = extra - top;
1232
1233 tv_conn_state->margins.top = top;
1234 tv_conn_state->margins.bottom = bottom;
1235
1236 tv_conn_state->bypass_vfilter = true;
1237
addc80f0
VS		 1238 if (!tv_mode->progressive) {
1239 adjusted_mode->clock /= 2;
1240 adjusted_mode->crtc_clock /= 2;
690157f0 1241 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
addc80f0 1242 }
690157f0
VS		 1243 } else {
1244 tv_conn_state->margins.top = conn_state->tv.margins.top;
1245 tv_conn_state->margins.bottom = conn_state->tv.margins.bottom;
1246
1247 tv_conn_state->bypass_vfilter = false;
1248 }
e3bb355c
VS		 1249
1250 DRM_DEBUG_KMS("TV mode:\n");
1251 drm_mode_debug_printmodeline(adjusted_mode);
1062b815
DV		 1252
1253 /*
e3bb355c
VS		 1254 * The pipe scanline counter behaviour looks as follows when
1255 * using the TV encoder:
1256 *
1257 * time ->
1258 *
1259 * dsl=vtotal-1 | |
1260 * || ||
1261 * ___| | ___| |
1262 * / | / |
1263 * / | / |
1264 * dsl=0 ___/ |_____/ |
1265 * | | | | | |
1266 * ^ ^ ^ ^ ^
1267 * | | | | pipe vblank/first part of tv vblank
1268 * | | | bottom margin
1269 * | | active
1270 * | top margin
1271 * remainder of tv vblank
1272 *
1273 * When the TV encoder is used the pipe wants to run faster
1274 * than expected rate. During the active portion the TV
1275 * encoder stalls the pipe every few lines to keep it in
1276 * check. When the TV encoder reaches the bottom margin the
1277 * pipe simply stops. Once we reach the TV vblank the pipe is
1278 * no longer stalled and it runs at the max rate (apparently
1279 * oversample clock on gen3, cdclk on gen4). Once the pipe
1280 * reaches the pipe vtotal the pipe stops for the remainder
1281 * of the TV vblank/top margin. The pipe starts up again when
1282 * the TV encoder exits the top margin.
1283 *
1284 * To avoid huge hassles for vblank timestamping we scale
1285 * the pipe timings as if the pipe always runs at the average
1286 * rate it maintains during the active period. This also
1287 * gives us a reasonable guesstimate as to the pixel rate.
1288 * Due to the variation in the actual pipe speed the scanline
1289 * counter will give us slightly erroneous results during the
1290 * TV vblank/margins. But since vtotal was selected such that
1291 * it matches the average rate of the pipe during the active
1292 * portion the error shouldn't cause any serious grief to
1293 * vblank timestamps.
1294 *
1295 * For posterity here is the empirically derived formula
1296 * that gives us the maximum length of the pipe vblank
1297 * we can use without causing display corruption. Following
1298 * this would allow us to have a ticking scanline counter
1299 * everywhere except during the bottom margin (there the
1300 * pipe always stops). Ie. this would eliminate the second
1301 * flat portion of the above graph. However this would also
1302 * complicate vblank timestamping as the pipe vtotal would
1303 * no longer match the average rate the pipe runs at during
1304 * the active portion. Hence following this formula seems
1305 * more trouble that it's worth.
1306 *
1307 * if (IS_GEN(dev_priv, 4)) {
1308 * num = cdclk * (tv_mode->oversample >> !tv_mode->progressive);
1309 * den = tv_mode->clock;
1310 * } else {
1311 * num = tv_mode->oversample >> !tv_mode->progressive;
1312 * den = 1;
1313 * }
1314 * max_pipe_vblank_len ~=
1315 * (num * tv_htotal * (tv_vblank_len + top_margin)) /
1316 * (den * pipe_htotal);
1062b815 1317 */
e3bb355c
VS		 1318 intel_tv_scale_mode_horiz(adjusted_mode, hdisplay,
1319 conn_state->tv.margins.left,
1320 conn_state->tv.margins.right);
1321 intel_tv_scale_mode_vert(adjusted_mode, vdisplay,
690157f0
VS		 1322 tv_conn_state->margins.top,
1323 tv_conn_state->margins.bottom);
e3bb355c
VS		 1324 drm_mode_set_crtcinfo(adjusted_mode, 0);
1325 adjusted_mode->name[0] = '\0';
1062b815 1326
8a920e24
VS		 1327 /* pixel counter doesn't work on i965gm TV output */
1328 if (IS_I965GM(dev_priv))
1329 adjusted_mode->private_flags |=
1330 I915_MODE_FLAG_USE_SCANLINE_COUNTER;
1331
204474a6 1332 return 0;
79e53945
JB		 1333}
1334
8cb92203
DV		 1335static void
1336set_tv_mode_timings(struct drm_i915_private *dev_priv,
1337 const struct tv_mode *tv_mode,
1338 bool burst_ena)
1339{
1340 u32 hctl1, hctl2, hctl3;
1341 u32 vctl1, vctl2, vctl3, vctl4, vctl5, vctl6, vctl7;
1342
1343 hctl1 = (tv_mode->hsync_end << TV_HSYNC_END_SHIFT) |
1344 (tv_mode->htotal << TV_HTOTAL_SHIFT);
1345
1346 hctl2 = (tv_mode->hburst_start << 16) |
1347 (tv_mode->hburst_len << TV_HBURST_LEN_SHIFT);
1348
1349 if (burst_ena)
1350 hctl2 |= TV_BURST_ENA;
1351
1352 hctl3 = (tv_mode->hblank_start << TV_HBLANK_START_SHIFT) |
1353 (tv_mode->hblank_end << TV_HBLANK_END_SHIFT);
1354
1355 vctl1 = (tv_mode->nbr_end << TV_NBR_END_SHIFT) |
1356 (tv_mode->vi_end_f1 << TV_VI_END_F1_SHIFT) |
1357 (tv_mode->vi_end_f2 << TV_VI_END_F2_SHIFT);
1358
1359 vctl2 = (tv_mode->vsync_len << TV_VSYNC_LEN_SHIFT) |
1360 (tv_mode->vsync_start_f1 << TV_VSYNC_START_F1_SHIFT) |
1361 (tv_mode->vsync_start_f2 << TV_VSYNC_START_F2_SHIFT);
1362
1363 vctl3 = (tv_mode->veq_len << TV_VEQ_LEN_SHIFT) |
1364 (tv_mode->veq_start_f1 << TV_VEQ_START_F1_SHIFT) |
1365 (tv_mode->veq_start_f2 << TV_VEQ_START_F2_SHIFT);
1366
1367 if (tv_mode->veq_ena)
1368 vctl3 |= TV_EQUAL_ENA;
1369
1370 vctl4 = (tv_mode->vburst_start_f1 << TV_VBURST_START_F1_SHIFT) |
1371 (tv_mode->vburst_end_f1 << TV_VBURST_END_F1_SHIFT);
1372
1373 vctl5 = (tv_mode->vburst_start_f2 << TV_VBURST_START_F2_SHIFT) |
1374 (tv_mode->vburst_end_f2 << TV_VBURST_END_F2_SHIFT);
1375
1376 vctl6 = (tv_mode->vburst_start_f3 << TV_VBURST_START_F3_SHIFT) |
1377 (tv_mode->vburst_end_f3 << TV_VBURST_END_F3_SHIFT);
1378
1379 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) |
1380 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT);
1381
1382 I915_WRITE(TV_H_CTL_1, hctl1);
1383 I915_WRITE(TV_H_CTL_2, hctl2);
1384 I915_WRITE(TV_H_CTL_3, hctl3);
1385 I915_WRITE(TV_V_CTL_1, vctl1);
1386 I915_WRITE(TV_V_CTL_2, vctl2);
1387 I915_WRITE(TV_V_CTL_3, vctl3);
1388 I915_WRITE(TV_V_CTL_4, vctl4);
1389 I915_WRITE(TV_V_CTL_5, vctl5);
1390 I915_WRITE(TV_V_CTL_6, vctl6);
1391 I915_WRITE(TV_V_CTL_7, vctl7);
1392}
1393
b8866ef8
DV		 1394static void set_color_conversion(struct drm_i915_private *dev_priv,
1395 const struct color_conversion *color_conversion)
1396{
1397 if (!color_conversion)
1398 return;
1399
1400 I915_WRITE(TV_CSC_Y, (color_conversion->ry << 16) |
1401 color_conversion->gy);
1402 I915_WRITE(TV_CSC_Y2, (color_conversion->by << 16) |
1403 color_conversion->ay);
1404 I915_WRITE(TV_CSC_U, (color_conversion->ru << 16) |
1405 color_conversion->gu);
1406 I915_WRITE(TV_CSC_U2, (color_conversion->bu << 16) |
1407 color_conversion->au);
1408 I915_WRITE(TV_CSC_V, (color_conversion->rv << 16) |
1409 color_conversion->gv);
1410 I915_WRITE(TV_CSC_V2, (color_conversion->bv << 16) |
1411 color_conversion->av);
1412}
1413
fd6bbda9 1414static void intel_tv_pre_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 1415 const struct intel_crtc_state *pipe_config,
1416 const struct drm_connector_state *conn_state)
79e53945 1417{
66478475 1418 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
a7f519ba 1419 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
cd91ef23 1420 struct intel_tv *intel_tv = enc_to_tv(encoder);
690157f0
VS		 1421 const struct intel_tv_connector_state *tv_conn_state =
1422 to_intel_tv_connector_state(conn_state);
0e891b3f 1423 const struct tv_mode *tv_mode = intel_tv_mode_find(conn_state);
690157f0 1424 u32 tv_ctl, tv_filter_ctl;
79e53945
JB		 1425 u32 scctl1, scctl2, scctl3;
1426 int i, j;
1427 const struct video_levels *video_levels;
1428 const struct color_conversion *color_conversion;
1429 bool burst_ena;
bda5f532 1430 int xpos, ypos;
3fa2dd14 1431 unsigned int xsize, ysize;
79e53945
JB		 1432
1433 if (!tv_mode)
1434 return; /* can't happen (mode_prepare prevents this) */
1435
d2d9f232
ZW		 1436 tv_ctl = I915_READ(TV_CTL);
1437 tv_ctl &= TV_CTL_SAVE;
79e53945 1438
ea5b213a 1439 switch (intel_tv->type) {
79e53945
JB		 1440 default:
1441 case DRM_MODE_CONNECTOR_Unknown:
1442 case DRM_MODE_CONNECTOR_Composite:
1443 tv_ctl |= TV_ENC_OUTPUT_COMPOSITE;
1444 video_levels = tv_mode->composite_levels;
1445 color_conversion = tv_mode->composite_color;
1446 burst_ena = tv_mode->burst_ena;
1447 break;
1448 case DRM_MODE_CONNECTOR_Component:
1449 tv_ctl |= TV_ENC_OUTPUT_COMPONENT;
1450 video_levels = &component_levels;
1451 if (tv_mode->burst_ena)
1452 color_conversion = &sdtv_csc_yprpb;
1453 else
1454 color_conversion = &hdtv_csc_yprpb;
1455 burst_ena = false;
1456 break;
1457 case DRM_MODE_CONNECTOR_SVIDEO:
1458 tv_ctl |= TV_ENC_OUTPUT_SVIDEO;
1459 video_levels = tv_mode->svideo_levels;
1460 color_conversion = tv_mode->svideo_color;
1461 burst_ena = tv_mode->burst_ena;
1462 break;
1463 }
79e53945 1464
4add0f6b 1465 tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);
4f503798
VS		 1466
1467 switch (tv_mode->oversample) {
1468 case 8:
1469 tv_ctl |= TV_OVERSAMPLE_8X;
1470 break;
1471 case 4:
1472 tv_ctl |= TV_OVERSAMPLE_4X;
1473 break;
1474 case 2:
1475 tv_ctl |= TV_OVERSAMPLE_2X;
1476 break;
1477 default:
1478 tv_ctl |= TV_OVERSAMPLE_NONE;
1479 break;
1480 }
79e53945
JB		 1481
1482 if (tv_mode->progressive)
1483 tv_ctl |= TV_PROGRESSIVE;
1484 if (tv_mode->trilevel_sync)
1485 tv_ctl |= TV_TRILEVEL_SYNC;
1486 if (tv_mode->pal_burst)
1487 tv_ctl |= TV_PAL_BURST;
d271817b 1488
79e53945 1489 scctl1 = 0;
d271817b 1490 if (tv_mode->dda1_inc)
79e53945 1491 scctl1 |= TV_SC_DDA1_EN;
79e53945
JB		 1492 if (tv_mode->dda2_inc)
1493 scctl1 |= TV_SC_DDA2_EN;
79e53945
JB		 1494 if (tv_mode->dda3_inc)
1495 scctl1 |= TV_SC_DDA3_EN;
79e53945 1496 scctl1 |= tv_mode->sc_reset;
d271817b
CW		 1497 if (video_levels)
1498 scctl1 |= video_levels->burst << TV_BURST_LEVEL_SHIFT;
79e53945
JB		 1499 scctl1 |= tv_mode->dda1_inc << TV_SCDDA1_INC_SHIFT;
1500
1501 scctl2 = tv_mode->dda2_size << TV_SCDDA2_SIZE_SHIFT |
1502 tv_mode->dda2_inc << TV_SCDDA2_INC_SHIFT;
1503
1504 scctl3 = tv_mode->dda3_size << TV_SCDDA3_SIZE_SHIFT |
1505 tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
1506
1507 /* Enable two fixes for the chips that need them. */
50a0bc90 1508 if (IS_I915GM(dev_priv))
79e53945
JB		 1509 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
1510
8cb92203
DV		 1511 set_tv_mode_timings(dev_priv, tv_mode, burst_ena);
1512
79e53945
JB		 1513 I915_WRITE(TV_SC_CTL_1, scctl1);
1514 I915_WRITE(TV_SC_CTL_2, scctl2);
1515 I915_WRITE(TV_SC_CTL_3, scctl3);
1516
b8866ef8 1517 set_color_conversion(dev_priv, color_conversion);
79e53945 1518
66478475 1519 if (INTEL_GEN(dev_priv) >= 4)
d2d9f232
ZW		 1520 I915_WRITE(TV_CLR_KNOBS, 0x00404000);
1521 else
1522 I915_WRITE(TV_CLR_KNOBS, 0x00606000);
1523
79e53945
JB		 1524 if (video_levels)
1525 I915_WRITE(TV_CLR_LEVEL,
1526 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) |
1527 (video_levels->blank << TV_BLANK_LEVEL_SHIFT)));
3fa2dd14
DV		 1528
1529 assert_pipe_disabled(dev_priv, intel_crtc->pipe);
1530
1531 /* Filter ctl must be set before TV_WIN_SIZE */
690157f0
VS		 1532 tv_filter_ctl = TV_AUTO_SCALE;
1533 if (tv_conn_state->bypass_vfilter)
1534 tv_filter_ctl |= TV_V_FILTER_BYPASS;
1535 I915_WRITE(TV_FILTER_CTL_1, tv_filter_ctl);
1536
3fa2dd14 1537 xsize = tv_mode->hblank_start - tv_mode->hblank_end;
65ddf7f9 1538 ysize = intel_tv_mode_vdisplay(tv_mode);
3fa2dd14 1539
bda5f532 1540 xpos = conn_state->tv.margins.left;
690157f0 1541 ypos = tv_conn_state->margins.top;
0e891b3f
ML		 1542 xsize -= (conn_state->tv.margins.left +
1543 conn_state->tv.margins.right);
690157f0
VS		 1544 ysize -= (tv_conn_state->margins.top +
1545 tv_conn_state->margins.bottom);
3fa2dd14
DV		 1546 I915_WRITE(TV_WIN_POS, (xpos<<16)|ypos);
1547 I915_WRITE(TV_WIN_SIZE, (xsize<<16)|ysize);
79e53945
JB		 1548
1549 j = 0;
1550 for (i = 0; i < 60; i++)
184d7c06 1551 I915_WRITE(TV_H_LUMA(i), tv_mode->filter_table[j++]);
79e53945 1552 for (i = 0; i < 60; i++)
184d7c06 1553 I915_WRITE(TV_H_CHROMA(i), tv_mode->filter_table[j++]);
79e53945 1554 for (i = 0; i < 43; i++)
184d7c06 1555 I915_WRITE(TV_V_LUMA(i), tv_mode->filter_table[j++]);
79e53945 1556 for (i = 0; i < 43; i++)
184d7c06 1557 I915_WRITE(TV_V_CHROMA(i), tv_mode->filter_table[j++]);
b8ed2a4f 1558 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE);
79e53945
JB		 1559 I915_WRITE(TV_CTL, tv_ctl);
1560}
1561
79e53945 1562static int
0206e353 1563intel_tv_detect_type(struct intel_tv *intel_tv,
8102e126 1564 struct drm_connector *connector)
79e53945 1565{
0eadc624 1566 struct drm_crtc *crtc = connector->state->crtc;
835bff7e 1567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0eadc624 1568 struct drm_device *dev = connector->dev;
fac5e23e 1569 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 1570 u32 tv_ctl, save_tv_ctl;
1571 u32 tv_dac, save_tv_dac;
974b9331 1572 int type;
79e53945
JB		 1573
1574 /* Disable TV interrupts around load detect or we'll recurse */
8102e126 1575 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
2795aa48 1576 spin_lock_irq(&dev_priv->irq_lock);
8102e126 1577 i915_disable_pipestat(dev_priv, 0,
755e9019
ID		 1578 PIPE_HOTPLUG_INTERRUPT_STATUS |
1579 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
2795aa48 1580 spin_unlock_irq(&dev_priv->irq_lock);
8102e126 1581 }
79e53945 1582
974b9331
CW		 1583 save_tv_dac = tv_dac = I915_READ(TV_DAC);
1584 save_tv_ctl = tv_ctl = I915_READ(TV_CTL);
1585
1586 /* Poll for TV detection */
4add0f6b 1587 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK);
8ed9a5bc 1588 tv_ctl |= TV_TEST_MODE_MONITOR_DETECT;
4add0f6b 1589 tv_ctl |= TV_ENC_PIPE_SEL(intel_crtc->pipe);
974b9331
CW		 1590
1591 tv_dac &= ~(TVDAC_SENSE_MASK | DAC_A_MASK | DAC_B_MASK | DAC_C_MASK);
8ed9a5bc 1592 tv_dac |= (TVDAC_STATE_CHG_EN |
1593 TVDAC_A_SENSE_CTL |
1594 TVDAC_B_SENSE_CTL |
1595 TVDAC_C_SENSE_CTL |
1596 DAC_CTL_OVERRIDE |
1597 DAC_A_0_7_V |
1598 DAC_B_0_7_V |
1599 DAC_C_0_7_V);
974b9331 1600
d42c9e2c
DV		 1601
1602 /*
1603 * The TV sense state should be cleared to zero on cantiga platform. Otherwise
1604 * the TV is misdetected. This is hardware requirement.
1605 */
50a0bc90 1606 if (IS_GM45(dev_priv))
d42c9e2c
DV		 1607 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL |
1608 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL);
1609
8ed9a5bc 1610 I915_WRITE(TV_CTL, tv_ctl);
1611 I915_WRITE(TV_DAC, tv_dac);
4f233eff 1612 POSTING_READ(TV_DAC);
4f233eff 1613
0f0f74bc 1614 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
29e1316a 1615
974b9331 1616 type = -1;
2bf71160
KP		 1617 tv_dac = I915_READ(TV_DAC);
1618 DRM_DEBUG_KMS("TV detected: %x, %x\n", tv_ctl, tv_dac);
1619 /*
1620 * A B C
1621 * 0 1 1 Composite
1622 * 1 0 X svideo
1623 * 0 0 0 Component
1624 */
1625 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) {
1626 DRM_DEBUG_KMS("Detected Composite TV connection\n");
1627 type = DRM_MODE_CONNECTOR_Composite;
1628 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) {
1629 DRM_DEBUG_KMS("Detected S-Video TV connection\n");
1630 type = DRM_MODE_CONNECTOR_SVIDEO;
1631 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) {
1632 DRM_DEBUG_KMS("Detected Component TV connection\n");
1633 type = DRM_MODE_CONNECTOR_Component;
1634 } else {
1635 DRM_DEBUG_KMS("Unrecognised TV connection\n");
1636 type = -1;
79e53945
JB		 1637 }
1638
974b9331
CW		 1639 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1640 I915_WRITE(TV_CTL, save_tv_ctl);
bf2125e2
DV		 1641 POSTING_READ(TV_CTL);
1642
1643 /* For unknown reasons the hw barfs if we don't do this vblank wait. */
0f0f74bc 1644 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
974b9331 1645
79e53945 1646 /* Restore interrupt config */
8102e126 1647 if (connector->polled & DRM_CONNECTOR_POLL_HPD) {
2795aa48 1648 spin_lock_irq(&dev_priv->irq_lock);
8102e126 1649 i915_enable_pipestat(dev_priv, 0,
755e9019
ID		 1650 PIPE_HOTPLUG_INTERRUPT_STATUS |
1651 PIPE_HOTPLUG_TV_INTERRUPT_STATUS);
2795aa48 1652 spin_unlock_irq(&dev_priv->irq_lock);
8102e126 1653 }
79e53945
JB		 1654
1655 return type;
1656}
1657
213c2e64
ML		 1658/*
1659 * Here we set accurate tv format according to connector type
1660 * i.e Component TV should not be assigned by NTSC or PAL
1661 */
1662static void intel_tv_find_better_format(struct drm_connector *connector)
1663{
df0e9248 1664 struct intel_tv *intel_tv = intel_attached_tv(connector);
0e891b3f 1665 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
213c2e64
ML		 1666 int i;
1667
e94390aa
VS		 1668 /* Component supports everything so we can keep the current mode */
1669 if (intel_tv->type == DRM_MODE_CONNECTOR_Component)
213c2e64
ML		 1670 return;
1671
e94390aa
VS		 1672 /* If the current mode is fine don't change it */
1673 if (!tv_mode->component_only)
1674 return;
213c2e64 1675
53abb679 1676 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
e94390aa 1677 tv_mode = &tv_modes[i];
213c2e64 1678
e94390aa 1679 if (!tv_mode->component_only)
213c2e64
ML		 1680 break;
1681 }
1682
0e891b3f 1683 connector->state->tv.mode = i;
213c2e64
ML		 1684}
1685
6c5ed5ae
ML		 1686static int
1687intel_tv_detect(struct drm_connector *connector,
1688 struct drm_modeset_acquire_ctx *ctx,
1689 bool force)
79e53945 1690{
df0e9248 1691 struct intel_tv *intel_tv = intel_attached_tv(connector);
bbfb44e8 1692 enum drm_connector_status status;
ea5b213a 1693 int type;
79e53945 1694
164c8598 1695 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n",
c23cc417 1696 connector->base.id, connector->name,
164c8598
CW		 1697 force);
1698
38de45c5 1699 if (force) {
8261b191 1700 struct intel_load_detect_pipe tmp;
6c5ed5ae 1701 int ret;
ea5b213a 1702
528132a3 1703 ret = intel_get_load_detect_pipe(connector, NULL, &tmp, ctx);
6c5ed5ae
ML		 1704 if (ret < 0)
1705 return ret;
208bf9fd 1706
6c5ed5ae 1707 if (ret > 0) {
8102e126 1708 type = intel_tv_detect_type(intel_tv, connector);
6c5ed5ae 1709 intel_release_load_detect_pipe(connector, &tmp, ctx);
bbfb44e8
VS		 1710 status = type < 0 ?
1711 connector_status_disconnected :
1712 connector_status_connected;
79e53945 1713 } else
bbfb44e8 1714 status = connector_status_unknown;
bf5a269a 1715
0e891b3f
ML		 1716 if (status == connector_status_connected) {
1717 intel_tv->type = type;
1718 intel_tv_find_better_format(connector);
1719 }
d5627663 1720
0e891b3f
ML		 1721 return status;
1722 } else
1723 return connector->status;
79e53945
JB		 1724}
1725
763a4a01 1726static const struct input_res {
5023520f 1727 u16 w, h;
763a4a01 1728} input_res_table[] = {
5023520f
VS		 1729 { 640, 480 },
1730 { 800, 600 },
1731 { 1024, 768 },
1732 { 1280, 1024 },
1733 { 848, 480 },
1734 { 1280, 720 },
1735 { 1920, 1080 },
79e53945
JB		 1736};
1737
65ddf7f9
VS		 1738/* Choose preferred mode according to line number of TV format */
1739static bool
1740intel_tv_is_preferred_mode(const struct drm_display_mode *mode,
1741 const struct tv_mode *tv_mode)
1742{
1743 int vdisplay = intel_tv_mode_vdisplay(tv_mode);
1744
1745 /* prefer 480 line modes for all SD TV modes */
1746 if (vdisplay <= 576)
1747 vdisplay = 480;
1748
1749 return vdisplay == mode->vdisplay;
1750}
1751
bcae2ca8 1752static void
65ddf7f9
VS		 1753intel_tv_set_mode_type(struct drm_display_mode *mode,
1754 const struct tv_mode *tv_mode)
bcae2ca8 1755{
65ddf7f9
VS		 1756 mode->type = DRM_MODE_TYPE_DRIVER;
1757
1758 if (intel_tv_is_preferred_mode(mode, tv_mode))
1759 mode->type |= DRM_MODE_TYPE_PREFERRED;
bcae2ca8 1760}
1761
79e53945
JB		 1762static int
1763intel_tv_get_modes(struct drm_connector *connector)
1764{
0bb1ffe4 1765 struct drm_i915_private *dev_priv = to_i915(connector->dev);
0e891b3f 1766 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state);
e3bb355c 1767 int i, count = 0;
79e53945 1768
e3bb355c
VS		 1769 for (i = 0; i < ARRAY_SIZE(input_res_table); i++) {
1770 const struct input_res *input = &input_res_table[i];
1771 struct drm_display_mode *mode;
79e53945 1772
e3bb355c
VS		 1773 if (input->w > 1024 &&
1774 !tv_mode->progressive &&
1775 !tv_mode->component_only)
79e53945
JB		 1776 continue;
1777
0bb1ffe4
VS		 1778 /* no vertical scaling with wide sources on gen3 */
1779 if (IS_GEN(dev_priv, 3) && input->w > 1024 &&
1780 input->h > intel_tv_mode_vdisplay(tv_mode))
1781 continue;
1782
e3bb355c
VS		 1783 mode = drm_mode_create(connector->dev);
1784 if (!mode)
02c5dd98 1785 continue;
79e53945 1786
e3bb355c
VS		 1787 /*
1788 * We take the TV mode and scale it to look
1789 * like it had the expected h/vdisplay. This
1790 * provides the most information to userspace
1791 * about the actual timings of the mode. We
1792 * do ignore the margins though.
1793 */
1794 intel_tv_mode_to_mode(mode, tv_mode);
1795 if (count == 0) {
1796 DRM_DEBUG_KMS("TV mode:\n");
1797 drm_mode_debug_printmodeline(mode);
1798 }
1799 intel_tv_scale_mode_horiz(mode, input->w, 0, 0);
1800 intel_tv_scale_mode_vert(mode, input->h, 0, 0);
1801 intel_tv_set_mode_type(mode, tv_mode);
5023520f 1802
e3bb355c 1803 drm_mode_set_name(mode);
5023520f 1804
e3bb355c 1805 drm_mode_probed_add(connector, mode);
02c5dd98 1806 count++;
79e53945
JB		 1807 }
1808
02c5dd98 1809 return count;
79e53945
JB		 1810}
1811
79e53945 1812static const struct drm_connector_funcs intel_tv_connector_funcs = {
1ebaa0b9 1813 .late_register = intel_connector_register,
c191eca1 1814 .early_unregister = intel_connector_unregister,
d4b26e4f 1815 .destroy = intel_connector_destroy,
79e53945 1816 .fill_modes = drm_helper_probe_single_connector_modes,
c6f95f27 1817 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
690157f0 1818 .atomic_duplicate_state = intel_tv_connector_duplicate_state,
79e53945
JB		 1819};
1820
0e891b3f
ML		 1821static int intel_tv_atomic_check(struct drm_connector *connector,
1822 struct drm_connector_state *new_state)
1823{
1824 struct drm_crtc_state *new_crtc_state;
1825 struct drm_connector_state *old_state;
1826
1827 if (!new_state->crtc)
1828 return 0;
1829
1830 old_state = drm_atomic_get_old_connector_state(new_state->state, connector);
1831 new_crtc_state = drm_atomic_get_new_crtc_state(new_state->state, new_state->crtc);
1832
1833 if (old_state->tv.mode != new_state->tv.mode ||
1834 old_state->tv.margins.left != new_state->tv.margins.left ||
1835 old_state->tv.margins.right != new_state->tv.margins.right ||
1836 old_state->tv.margins.top != new_state->tv.margins.top ||
1837 old_state->tv.margins.bottom != new_state->tv.margins.bottom) {
1838 /* Force a modeset. */
1839
1840 new_crtc_state->connectors_changed = true;
1841 }
1842
1843 return 0;
1844}
1845
79e53945 1846static const struct drm_connector_helper_funcs intel_tv_connector_helper_funcs = {
6c5ed5ae 1847 .detect_ctx = intel_tv_detect,
79e53945
JB		 1848 .mode_valid = intel_tv_mode_valid,
1849 .get_modes = intel_tv_get_modes,
0e891b3f 1850 .atomic_check = intel_tv_atomic_check,
79e53945
JB		 1851};
1852
79e53945 1853static const struct drm_encoder_funcs intel_tv_enc_funcs = {
ea5b213a 1854 .destroy = intel_encoder_destroy,
79e53945
JB		 1855};
1856
79e53945 1857void
c39055b0 1858intel_tv_init(struct drm_i915_private *dev_priv)
79e53945 1859{
c39055b0 1860 struct drm_device *dev = &dev_priv->drm;
79e53945 1861 struct drm_connector *connector;
ea5b213a 1862 struct intel_tv *intel_tv;
21d40d37 1863 struct intel_encoder *intel_encoder;
0c41ee2b 1864 struct intel_connector *intel_connector;
79e53945 1865 u32 tv_dac_on, tv_dac_off, save_tv_dac;
b7c914b3 1866 const char *tv_format_names[ARRAY_SIZE(tv_modes)];
79e53945 1867 int i, initial_mode = 0;
0e891b3f 1868 struct drm_connector_state *state;
79e53945
JB		 1869
1870 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
1871 return;
1872
3bdd14d5 1873 if (!intel_bios_is_tv_present(dev_priv)) {
c3561438
ZY		 1874 DRM_DEBUG_KMS("Integrated TV is not present.\n");
1875 return;
1876 }
79e53945
JB		 1877
1878 /*
1879 * Sanity check the TV output by checking to see if the
1880 * DAC register holds a value
1881 */
1882 save_tv_dac = I915_READ(TV_DAC);
1883
1884 I915_WRITE(TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN);
1885 tv_dac_on = I915_READ(TV_DAC);
1886
1887 I915_WRITE(TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN);
1888 tv_dac_off = I915_READ(TV_DAC);
1889
1890 I915_WRITE(TV_DAC, save_tv_dac);
1891
1892 /*
1893 * If the register does not hold the state change enable
1894 * bit, (either as a 0 or a 1), assume it doesn't really
1895 * exist
1896 */
1897 if ((tv_dac_on & TVDAC_STATE_CHG_EN) == 0 ||
1898 (tv_dac_off & TVDAC_STATE_CHG_EN) != 0)
1899 return;
1900
b14c5679 1901 intel_tv = kzalloc(sizeof(*intel_tv), GFP_KERNEL);
ea5b213a 1902 if (!intel_tv) {
79e53945
JB		 1903 return;
1904 }
f8aed700 1905
08d9bc92 1906 intel_connector = intel_connector_alloc();
0c41ee2b 1907 if (!intel_connector) {
ea5b213a 1908 kfree(intel_tv);
0c41ee2b
ZW		 1909 return;
1910 }
1911
ea5b213a 1912 intel_encoder = &intel_tv->base;
0c41ee2b 1913 connector = &intel_connector->base;
0e891b3f 1914 state = connector->state;
79e53945 1915
3930f18a
CW		 1916 /*
1917 * The documentation, for the older chipsets at least, recommend
8102e126
CW		 1918 * using a polling method rather than hotplug detection for TVs.
1919 * This is because in order to perform the hotplug detection, the PLLs
1920 * for the TV must be kept alive increasing power drain and starving
1921 * bandwidth from other encoders. Notably for instance, it causes
1922 * pipe underruns on Crestline when this encoder is supposedly idle.
1923 *
1924 * More recent chipsets favour HDMI rather than integrated S-Video.
1925 */
821450c6 1926 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
8102e126 1927
79e53945
JB		 1928 drm_connector_init(dev, connector, &intel_tv_connector_funcs,
1929 DRM_MODE_CONNECTOR_SVIDEO);
1930
4ef69c7a 1931 drm_encoder_init(dev, &intel_encoder->base, &intel_tv_enc_funcs,
580d8ed5 1932 DRM_MODE_ENCODER_TVDAC, "TV");
79e53945 1933
5d2d38dd 1934 intel_encoder->compute_config = intel_tv_compute_config;
7a495cfd 1935 intel_encoder->get_config = intel_tv_get_config;
809a2a8b 1936 intel_encoder->pre_enable = intel_tv_pre_enable;
6b5756a0
DV		 1937 intel_encoder->enable = intel_enable_tv;
1938 intel_encoder->disable = intel_disable_tv;
9a8ee983
DV		 1939 intel_encoder->get_hw_state = intel_tv_get_hw_state;
1940 intel_connector->get_hw_state = intel_connector_get_hw_state;
6b5756a0 1941
df0e9248 1942 intel_connector_attach_encoder(intel_connector, intel_encoder);
03cdc1d4 1943
21d40d37 1944 intel_encoder->type = INTEL_OUTPUT_TVOUT;
79f255a0 1945 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 1946 intel_encoder->port = PORT_NONE;
21d40d37 1947 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
bc079e8b 1948 intel_encoder->cloneable = 0;
4ef69c7a 1949 intel_encoder->base.possible_crtcs = ((1 << 0) | (1 << 1));
ea5b213a 1950 intel_tv->type = DRM_MODE_CONNECTOR_Unknown;
79e53945
JB		 1951
1952 /* BIOS margin values */
0e891b3f
ML		 1953 state->tv.margins.left = 54;
1954 state->tv.margins.top = 36;
1955 state->tv.margins.right = 46;
1956 state->tv.margins.bottom = 37;
79e53945 1957
0e891b3f 1958 state->tv.mode = initial_mode;
79e53945 1959
79e53945
JB		 1960 drm_connector_helper_add(connector, &intel_tv_connector_helper_funcs);
1961 connector->interlace_allowed = false;
1962 connector->doublescan_allowed = false;
1963
1964 /* Create TV properties then attach current values */
a0ff6779
VS		 1965 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
1966 /* 1080p50/1080p60 not supported on gen3 */
1967 if (IS_GEN(dev_priv, 3) &&
1968 tv_modes[i].oversample == 1)
1969 break;
1970
b7c914b3 1971 tv_format_names[i] = tv_modes[i].name;
a0ff6779
VS		 1972 }
1973 drm_mode_create_tv_properties(dev, i, tv_format_names);
79e53945 1974
662595df 1975 drm_object_attach_property(&connector->base, dev->mode_config.tv_mode_property,
0e891b3f 1976 state->tv.mode);
662595df 1977 drm_object_attach_property(&connector->base,
79e53945 1978 dev->mode_config.tv_left_margin_property,
0e891b3f 1979 state->tv.margins.left);
662595df 1980 drm_object_attach_property(&connector->base,
79e53945 1981 dev->mode_config.tv_top_margin_property,
0e891b3f 1982 state->tv.margins.top);
662595df 1983 drm_object_attach_property(&connector->base,
79e53945 1984 dev->mode_config.tv_right_margin_property,
0e891b3f 1985 state->tv.margins.right);
662595df 1986 drm_object_attach_property(&connector->base,
79e53945 1987 dev->mode_config.tv_bottom_margin_property,
0e891b3f 1988 state->tv.margins.bottom);
79e53945 1989}
Linux 6.x block layer and io_uring tree(s)