[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_step.c

// SPDX-License-Identifier: MIT
/*
 * Copyright © 2020,2021 Intel Corporation
 */

#include "i915_drv.h"
#include "intel_step.h"

/*
 * Some platforms have unusual ways of mapping PCI revision ID to GT/display
 * steppings.  E.g., in some cases a higher PCI revision may translate to a
 * lower stepping of the GT and/or display IP.  This file provides lookup
 * tables to map the PCI revision into a standard set of stepping values that
 * can be compared numerically.
 *
 * Also note that some revisions/steppings may have been set aside as
 * placeholders but never materialized in real hardware; in those cases there
 * may be jumps in the revision IDs or stepping values in the tables below.
 */

/*
 * Some platforms always have the same stepping value for GT and display;
 * use a macro to define these to make it easier to identify the platforms
 * where the two steppings can deviate.
 */
#define COMMON_STEP(x)  .graphics_step = STEP_##x, .display_step = STEP_##x, .media_step = STEP_##x
#define COMMON_GT_MEDIA_STEP(x)  .graphics_step = STEP_##x, .media_step = STEP_##x

static const struct intel_step_info skl_revids[] = {
	[0x6] = { COMMON_STEP(G0) },
	[0x7] = { COMMON_STEP(H0) },
	[0x9] = { COMMON_STEP(J0) },
	[0xA] = { COMMON_STEP(I1) },
};

static const struct intel_step_info kbl_revids[] = {
	[1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
	[2] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 },
	[3] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_B0 },
	[4] = { COMMON_GT_MEDIA_STEP(F0), .display_step = STEP_C0 },
	[5] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B1 },
	[6] = { COMMON_GT_MEDIA_STEP(D1), .display_step = STEP_B1 },
	[7] = { COMMON_GT_MEDIA_STEP(G0), .display_step = STEP_C0 },
};

static const struct intel_step_info bxt_revids[] = {
	[0xA] = { COMMON_STEP(C0) },
	[0xB] = { COMMON_STEP(C0) },
	[0xC] = { COMMON_STEP(D0) },
	[0xD] = { COMMON_STEP(E0) },
};

static const struct intel_step_info glk_revids[] = {
	[3] = { COMMON_STEP(B0) },
};

static const struct intel_step_info icl_revids[] = {
	[7] = { COMMON_STEP(D0) },
};

static const struct intel_step_info jsl_ehl_revids[] = {
	[0] = { COMMON_STEP(A0) },
	[1] = { COMMON_STEP(B0) },
};

static const struct intel_step_info tgl_uy_revids[] = {
	[0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
	[1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 },
	[2] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
	[3] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
};

/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
static const struct intel_step_info tgl_revids[] = {
	[0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 },
	[1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_D0 },
};

static const struct intel_step_info rkl_revids[] = {
	[0] = { COMMON_STEP(A0) },
	[1] = { COMMON_STEP(B0) },
	[4] = { COMMON_STEP(C0) },
};

static const struct intel_step_info dg1_revids[] = {
	[0] = { COMMON_STEP(A0) },
	[1] = { COMMON_STEP(B0) },
};

static const struct intel_step_info adls_revids[] = {
	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
	[0x1] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A2 },
	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
	[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 },
	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
};

static const struct intel_step_info adlp_revids[] = {
	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
	[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 },
	[0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
};

static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
	[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 },
	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
	[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 },
};

static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 },
	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 },
	[0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
};

static const struct intel_step_info dg2_g12_revid_step_tbl[] = {
	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 },
	[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_C0 },
};

static const struct intel_step_info adls_rpls_revids[] = {
	[0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
};

static const struct intel_step_info adlp_rplp_revids[] = {
	[0x4] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_E0 },
};

static const struct intel_step_info adlp_n_revids[] = {
	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
};

static u8 gmd_to_intel_step(struct drm_i915_private *i915,
			    struct intel_ip_version *gmd)
{
	u8 step = gmd->step + STEP_A0;

	if (step >= STEP_FUTURE) {
		drm_dbg(&i915->drm, "Using future steppings\n");
		return STEP_FUTURE;
	}

	return step;
}

void intel_step_init(struct drm_i915_private *i915)
{
	const struct intel_step_info *revids = NULL;
	int size = 0;
	int revid = INTEL_REVID(i915);
	struct intel_step_info step = {};

	if (HAS_GMD_ID(i915)) {
		step.graphics_step = gmd_to_intel_step(i915,
						       &RUNTIME_INFO(i915)->graphics.ip);
		step.media_step = gmd_to_intel_step(i915,
						    &RUNTIME_INFO(i915)->media.ip);
		step.display_step = STEP_A0 + DISPLAY_RUNTIME_INFO(i915)->ip.step;
		if (step.display_step >= STEP_FUTURE) {
			drm_dbg(&i915->drm, "Using future display steppings\n");
			step.display_step = STEP_FUTURE;
		}

		RUNTIME_INFO(i915)->step = step;

		return;
	}

	if (IS_DG2_G10(i915)) {
		revids = dg2_g10_revid_step_tbl;
		size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
	} else if (IS_DG2_G11(i915)) {
		revids = dg2_g11_revid_step_tbl;
		size = ARRAY_SIZE(dg2_g11_revid_step_tbl);
	} else if (IS_DG2_G12(i915)) {
		revids = dg2_g12_revid_step_tbl;
		size = ARRAY_SIZE(dg2_g12_revid_step_tbl);
	} else if (IS_ALDERLAKE_P_N(i915)) {
		revids = adlp_n_revids;
		size = ARRAY_SIZE(adlp_n_revids);
	} else if (IS_RAPTORLAKE_P(i915)) {
		revids = adlp_rplp_revids;
		size = ARRAY_SIZE(adlp_rplp_revids);
	} else if (IS_ALDERLAKE_P(i915)) {
		revids = adlp_revids;
		size = ARRAY_SIZE(adlp_revids);
	} else if (IS_RAPTORLAKE_S(i915)) {
		revids = adls_rpls_revids;
		size = ARRAY_SIZE(adls_rpls_revids);
	} else if (IS_ALDERLAKE_S(i915)) {
		revids = adls_revids;
		size = ARRAY_SIZE(adls_revids);
	} else if (IS_DG1(i915)) {
		revids = dg1_revids;
		size = ARRAY_SIZE(dg1_revids);
	} else if (IS_ROCKETLAKE(i915)) {
		revids = rkl_revids;
		size = ARRAY_SIZE(rkl_revids);
	} else if (IS_TIGERLAKE_UY(i915)) {
		revids = tgl_uy_revids;
		size = ARRAY_SIZE(tgl_uy_revids);
	} else if (IS_TIGERLAKE(i915)) {
		revids = tgl_revids;
		size = ARRAY_SIZE(tgl_revids);
	} else if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) {
		revids = jsl_ehl_revids;
		size = ARRAY_SIZE(jsl_ehl_revids);
	} else if (IS_ICELAKE(i915)) {
		revids = icl_revids;
		size = ARRAY_SIZE(icl_revids);
	} else if (IS_GEMINILAKE(i915)) {
		revids = glk_revids;
		size = ARRAY_SIZE(glk_revids);
	} else if (IS_BROXTON(i915)) {
		revids = bxt_revids;
		size = ARRAY_SIZE(bxt_revids);
	} else if (IS_KABYLAKE(i915)) {
		revids = kbl_revids;
		size = ARRAY_SIZE(kbl_revids);
	} else if (IS_SKYLAKE(i915)) {
		revids = skl_revids;
		size = ARRAY_SIZE(skl_revids);
	}

	/* Not using the stepping scheme for the platform yet. */
	if (!revids)
		return;

	if (revid < size && revids[revid].graphics_step != STEP_NONE) {
		step = revids[revid];
	} else {
		drm_warn(&i915->drm, "Unknown revid 0x%02x\n", revid);

		/*
		 * If we hit a gap in the revid array, use the information for
		 * the next revid.
		 *
		 * This may be wrong in all sorts of ways, especially if the
		 * steppings in the array are not monotonically increasing, but
		 * it's better than defaulting to 0.
		 */
		while (revid < size && revids[revid].graphics_step == STEP_NONE)
			revid++;

		if (revid < size) {
			drm_dbg(&i915->drm, "Using steppings for revid 0x%02x\n",
				revid);
			step = revids[revid];
		} else {
			drm_dbg(&i915->drm, "Using future steppings\n");
			step.graphics_step = STEP_FUTURE;
			step.display_step = STEP_FUTURE;
		}
	}

	if (drm_WARN_ON(&i915->drm, step.graphics_step == STEP_NONE))
		return;

	RUNTIME_INFO(i915)->step = step;
}

#define STEP_NAME_CASE(name)	\
	case STEP_##name:	\
		return #name;

const char *intel_step_name(enum intel_step step)
{
	switch (step) {
	STEP_NAME_LIST(STEP_NAME_CASE);

	default:
		return "**";
	}
}

const char *intel_display_step_name(struct drm_i915_private *i915)
{
	return intel_step_name(RUNTIME_INFO(i915)->step.display_step);
}
Commit	Line	Data
7eb186bb JN	1	// SPDX-License-Identifier: MIT
	2	/*
	3	* Copyright © 2020,2021 Intel Corporation
	4	*/
	5
	6	#include "i915_drv.h"
	7	#include "intel_step.h"
	8
	9	/*
0f93f5da MR	10	* Some platforms have unusual ways of mapping PCI revision ID to GT/display
	11	* steppings. E.g., in some cases a higher PCI revision may translate to a
	12	* lower stepping of the GT and/or display IP. This file provides lookup
	13	* tables to map the PCI revision into a standard set of stepping values that
	14	* can be compared numerically.
	15	*
	16	* Also note that some revisions/steppings may have been set aside as
	17	* placeholders but never materialized in real hardware; in those cases there
	18	* may be jumps in the revision IDs or stepping values in the tables below.
7eb186bb JN	19	*/
7eb186bb JN	20
0f93f5da MR	21	/*
	22	* Some platforms always have the same stepping value for GT and display;
	23	* use a macro to define these to make it easier to identify the platforms
	24	* where the two steppings can deviate.
	25	*/
c1f110ee JRS	26	#define COMMON_STEP(x) .graphics_step = STEP_##x, .display_step = STEP_##x, .media_step = STEP_##x
c1f110ee JRS	27	#define COMMON_GT_MEDIA_STEP(x) .graphics_step = STEP_##x, .media_step = STEP_##x
0f93f5da MR	28
	29	static const struct intel_step_info skl_revids[] = {
	30	[0x6] = { COMMON_STEP(G0) },
	31	[0x7] = { COMMON_STEP(H0) },
	32	[0x9] = { COMMON_STEP(J0) },
	33	[0xA] = { COMMON_STEP(I1) },
	34	};
ef47b7ab	35
5644dc0a	36	static const struct intel_step_info kbl_revids[] = {
e181fa1d JRS	37	[1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
	38	[2] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 },
	39	[3] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_B0 },
	40	[4] = { COMMON_GT_MEDIA_STEP(F0), .display_step = STEP_C0 },
	41	[5] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B1 },
	42	[6] = { COMMON_GT_MEDIA_STEP(D1), .display_step = STEP_B1 },
	43	[7] = { COMMON_GT_MEDIA_STEP(G0), .display_step = STEP_C0 },
7eb186bb JN	44	};
7eb186bb JN	45
fd51fa8a MR	46	static const struct intel_step_info bxt_revids[] = {
	47	[0xA] = { COMMON_STEP(C0) },
	48	[0xB] = { COMMON_STEP(C0) },
	49	[0xC] = { COMMON_STEP(D0) },
	50	[0xD] = { COMMON_STEP(E0) },
	51	};
	52
3dd22d46 MR	53	static const struct intel_step_info glk_revids[] = {
	54	[3] = { COMMON_STEP(B0) },
	55	};
	56
cc7a3393 MR	57	static const struct intel_step_info icl_revids[] = {
	58	[7] = { COMMON_STEP(D0) },
	59	};
	60
61b2dc4b MR	61	static const struct intel_step_info jsl_ehl_revids[] = {
	62	[0] = { COMMON_STEP(A0) },
	63	[1] = { COMMON_STEP(B0) },
	64	};
	65
db47fe72	66	static const struct intel_step_info tgl_uy_revids[] = {
e181fa1d JRS	67	[0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
	68	[1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 },
	69	[2] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
	70	[3] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
7eb186bb JN	71	};
	72
	73	/* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */
db47fe72	74	static const struct intel_step_info tgl_revids[] = {
e181fa1d JRS	75	[0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 },
e181fa1d JRS	76	[1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_D0 },
7eb186bb JN	77	};
7eb186bb JN	78
97cf9b58 MR	79	static const struct intel_step_info rkl_revids[] = {
	80	[0] = { COMMON_STEP(A0) },
	81	[1] = { COMMON_STEP(B0) },
	82	[4] = { COMMON_STEP(C0) },
	83	};
	84
dae751f4 MR	85	static const struct intel_step_info dg1_revids[] = {
	86	[0] = { COMMON_STEP(A0) },
	87	[1] = { COMMON_STEP(B0) },
	88	};
	89
db47fe72	90	static const struct intel_step_info adls_revids[] = {
e181fa1d JRS	91	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
	92	[0x1] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A2 },
	93	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
	94	[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 },
	95	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
7eb186bb	96	};
ef47b7ab	97
db47fe72	98	static const struct intel_step_info adlp_revids[] = {
e181fa1d JRS	99	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
	100	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
	101	[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 },
	102	[0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 },
b2c6eaf2 JRS	103	};
b2c6eaf2 JRS	104
9e22cfc5	105	static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
e181fa1d JRS	106	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 },
	107	[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 },
	108	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 },
	109	[0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 },
9e22cfc5 MR	110	};
	111
	112	static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
e181fa1d JRS	113	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 },
	114	[0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 },
	115	[0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
9e22cfc5 MR	116	};
9e22cfc5 MR	117
86df4141 MR	118	static const struct intel_step_info dg2_g12_revid_step_tbl[] = {
86df4141 MR	119	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 },
84bd5e96	120	[0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_C0 },
86df4141 MR	121	};
86df4141 MR	122
8295524a AS	123	static const struct intel_step_info adls_rpls_revids[] = {
	124	[0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
	125	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
	126	};
	127
dc73ac63 MA	128	static const struct intel_step_info adlp_rplp_revids[] = {
	129	[0x4] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_E0 },
	130	};
	131
8d80ccee TU	132	static const struct intel_step_info adlp_n_revids[] = {
	133	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 },
	134	};
	135
944ca7d8	136	static u8 gmd_to_intel_step(struct drm_i915_private *i915,
ef7e222c	137	struct intel_ip_version *gmd)
944ca7d8 JRS	138	{
	139	u8 step = gmd->step + STEP_A0;
	140
	141	if (step >= STEP_FUTURE) {
	142	drm_dbg(&i915->drm, "Using future steppings\n");
	143	return STEP_FUTURE;
	144	}
	145
	146	return step;
	147	}
	148
ef47b7ab JN	149	void intel_step_init(struct drm_i915_private *i915)
ef47b7ab JN	150	{
5644dc0a	151	const struct intel_step_info *revids = NULL;
ef47b7ab JN	152	int size = 0;
ef47b7ab JN	153	int revid = INTEL_REVID(i915);
5644dc0a	154	struct intel_step_info step = {};
ef47b7ab	155
944ca7d8 JRS	156	if (HAS_GMD_ID(i915)) {
	157	step.graphics_step = gmd_to_intel_step(i915,
	158	&RUNTIME_INFO(i915)->graphics.ip);
	159	step.media_step = gmd_to_intel_step(i915,
	160	&RUNTIME_INFO(i915)->media.ip);
18e0deee MR	161	step.display_step = STEP_A0 + DISPLAY_RUNTIME_INFO(i915)->ip.step;
	162	if (step.display_step >= STEP_FUTURE) {
	163	drm_dbg(&i915->drm, "Using future display steppings\n");
	164	step.display_step = STEP_FUTURE;
	165	}
	166
944ca7d8 JRS	167	RUNTIME_INFO(i915)->step = step;
	168
	169	return;
	170	}
	171
326e30e4	172	if (IS_DG2_G10(i915)) {
9e22cfc5 MR	173	revids = dg2_g10_revid_step_tbl;
	174	size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
	175	} else if (IS_DG2_G11(i915)) {
	176	revids = dg2_g11_revid_step_tbl;
	177	size = ARRAY_SIZE(dg2_g11_revid_step_tbl);
86df4141 MR	178	} else if (IS_DG2_G12(i915)) {
	179	revids = dg2_g12_revid_step_tbl;
	180	size = ARRAY_SIZE(dg2_g12_revid_step_tbl);
6373b793	181	} else if (IS_ALDERLAKE_P_N(i915)) {
8d80ccee TU	182	revids = adlp_n_revids;
8d80ccee TU	183	size = ARRAY_SIZE(adlp_n_revids);
de01a919	184	} else if (IS_RAPTORLAKE_P(i915)) {
dc73ac63 MA	185	revids = adlp_rplp_revids;
dc73ac63 MA	186	size = ARRAY_SIZE(adlp_rplp_revids);
086df54e	187	} else if (IS_ALDERLAKE_P(i915)) {
db47fe72 AS	188	revids = adlp_revids;
db47fe72 AS	189	size = ARRAY_SIZE(adlp_revids);
2aa01e4d	190	} else if (IS_RAPTORLAKE_S(i915)) {
8295524a AS	191	revids = adls_rpls_revids;
8295524a AS	192	size = ARRAY_SIZE(adls_rpls_revids);
b2c6eaf2	193	} else if (IS_ALDERLAKE_S(i915)) {
db47fe72 AS	194	revids = adls_revids;
db47fe72 AS	195	size = ARRAY_SIZE(adls_revids);
dae751f4 MR	196	} else if (IS_DG1(i915)) {
	197	revids = dg1_revids;
	198	size = ARRAY_SIZE(dg1_revids);
97cf9b58 MR	199	} else if (IS_ROCKETLAKE(i915)) {
	200	revids = rkl_revids;
	201	size = ARRAY_SIZE(rkl_revids);
48077b0b	202	} else if (IS_TIGERLAKE_UY(i915)) {
db47fe72 AS	203	revids = tgl_uy_revids;
db47fe72 AS	204	size = ARRAY_SIZE(tgl_uy_revids);
34b7e27b	205	} else if (IS_TIGERLAKE(i915)) {
db47fe72 AS	206	revids = tgl_revids;
db47fe72 AS	207	size = ARRAY_SIZE(tgl_revids);
0c65dc06	208	} else if (IS_JASPERLAKE(i915) \|\| IS_ELKHARTLAKE(i915)) {
61b2dc4b MR	209	revids = jsl_ehl_revids;
61b2dc4b MR	210	size = ARRAY_SIZE(jsl_ehl_revids);
cc7a3393 MR	211	} else if (IS_ICELAKE(i915)) {
	212	revids = icl_revids;
	213	size = ARRAY_SIZE(icl_revids);
3dd22d46 MR	214	} else if (IS_GEMINILAKE(i915)) {
	215	revids = glk_revids;
	216	size = ARRAY_SIZE(glk_revids);
fd51fa8a MR	217	} else if (IS_BROXTON(i915)) {
	218	revids = bxt_revids;
	219	size = ARRAY_SIZE(bxt_revids);
34b7e27b	220	} else if (IS_KABYLAKE(i915)) {
ef47b7ab JN	221	revids = kbl_revids;
ef47b7ab JN	222	size = ARRAY_SIZE(kbl_revids);
0f93f5da MR	223	} else if (IS_SKYLAKE(i915)) {
	224	revids = skl_revids;
	225	size = ARRAY_SIZE(skl_revids);
ef47b7ab JN	226	}
	227
	228	/* Not using the stepping scheme for the platform yet. */
	229	if (!revids)
	230	return;
	231
c1f110ee	232	if (revid < size && revids[revid].graphics_step != STEP_NONE) {
ef47b7ab JN	233	step = revids[revid];
	234	} else {
	235	drm_warn(&i915->drm, "Unknown revid 0x%02x\n", revid);
	236
	237	/*
	238	* If we hit a gap in the revid array, use the information for
	239	* the next revid.
	240	*
	241	* This may be wrong in all sorts of ways, especially if the
	242	* steppings in the array are not monotonically increasing, but
	243	* it's better than defaulting to 0.
	244	*/
c1f110ee	245	while (revid < size && revids[revid].graphics_step == STEP_NONE)
ef47b7ab JN	246	revid++;
	247
	248	if (revid < size) {
	249	drm_dbg(&i915->drm, "Using steppings for revid 0x%02x\n",
	250	revid);
	251	step = revids[revid];
	252	} else {
	253	drm_dbg(&i915->drm, "Using future steppings\n");
c1f110ee	254	step.graphics_step = STEP_FUTURE;
26475ca9	255	step.display_step = STEP_FUTURE;
ef47b7ab JN	256	}
	257	}
	258
c1f110ee	259	if (drm_WARN_ON(&i915->drm, step.graphics_step == STEP_NONE))
ef47b7ab JN	260	return;
	261
	262	RUNTIME_INFO(i915)->step = step;
	263	}
e631a440 AS	264
	265	#define STEP_NAME_CASE(name) \
	266	case STEP_##name: \
	267	return #name;
	268
	269	const char *intel_step_name(enum intel_step step)
	270	{
	271	switch (step) {
	272	STEP_NAME_LIST(STEP_NAME_CASE);
	273
	274	default:
	275	return "**";
	276	}
	277	}
55ce2c37 CKB	278
	279	const char intel_display_step_name(struct drm_i915_private i915)
	280	{
	281	return intel_step_name(RUNTIME_INFO(i915)->step.display_step);
	282	}