Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
15953637 | 37 | #include <drm/drm_scdc_helper.h> |
7d57382e | 38 | #include "intel_drv.h" |
760285e7 | 39 | #include <drm/i915_drm.h> |
46d196ec | 40 | #include <drm/intel_lpe_audio.h> |
7d57382e EA |
41 | #include "i915_drv.h" |
42 | ||
30add22d PZ |
43 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
44 | { | |
da63a9f2 | 45 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
46 | } |
47 | ||
afba0188 DV |
48 | static void |
49 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
50 | { | |
30add22d | 51 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 52 | struct drm_i915_private *dev_priv = to_i915(dev); |
afba0188 DV |
53 | uint32_t enabled_bits; |
54 | ||
4f8036a2 | 55 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 56 | |
b242b7f7 | 57 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
58 | "HDMI port enabled, expecting disabled\n"); |
59 | } | |
60 | ||
f5bbfca3 | 61 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 62 | { |
da63a9f2 PZ |
63 | struct intel_digital_port *intel_dig_port = |
64 | container_of(encoder, struct intel_digital_port, base.base); | |
65 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
66 | } |
67 | ||
df0e9248 CW |
68 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
69 | { | |
da63a9f2 | 70 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
71 | } |
72 | ||
178f736a | 73 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 74 | { |
178f736a DL |
75 | switch (type) { |
76 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 77 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 78 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 79 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
80 | case HDMI_INFOFRAME_TYPE_VENDOR: |
81 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 82 | default: |
ffc85dab | 83 | MISSING_CASE(type); |
ed517fbb | 84 | return 0; |
45187ace | 85 | } |
45187ace JB |
86 | } |
87 | ||
178f736a | 88 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 89 | { |
178f736a DL |
90 | switch (type) { |
91 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 93 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 94 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
95 | case HDMI_INFOFRAME_TYPE_VENDOR: |
96 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 97 | default: |
ffc85dab | 98 | MISSING_CASE(type); |
ed517fbb | 99 | return 0; |
fa193ff7 | 100 | } |
fa193ff7 PZ |
101 | } |
102 | ||
178f736a | 103 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 104 | { |
178f736a DL |
105 | switch (type) { |
106 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 107 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 108 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 109 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
110 | case HDMI_INFOFRAME_TYPE_VENDOR: |
111 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 112 | default: |
ffc85dab | 113 | MISSING_CASE(type); |
2da8af54 PZ |
114 | return 0; |
115 | } | |
116 | } | |
117 | ||
f0f59a00 VS |
118 | static i915_reg_t |
119 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
120 | enum transcoder cpu_transcoder, | |
121 | enum hdmi_infoframe_type type, | |
122 | int i) | |
2da8af54 | 123 | { |
178f736a DL |
124 | switch (type) { |
125 | case HDMI_INFOFRAME_TYPE_AVI: | |
436c6d4a | 126 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 127 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 128 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 129 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 130 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 131 | default: |
ffc85dab | 132 | MISSING_CASE(type); |
f0f59a00 | 133 | return INVALID_MMIO_REG; |
2da8af54 PZ |
134 | } |
135 | } | |
136 | ||
a3da1df7 | 137 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 138 | const struct intel_crtc_state *crtc_state, |
178f736a | 139 | enum hdmi_infoframe_type type, |
fff63867 | 140 | const void *frame, ssize_t len) |
45187ace | 141 | { |
fff63867 | 142 | const uint32_t *data = frame; |
3c17fe4b | 143 | struct drm_device *dev = encoder->dev; |
fac5e23e | 144 | struct drm_i915_private *dev_priv = to_i915(dev); |
22509ec8 | 145 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 146 | int i; |
3c17fe4b | 147 | |
822974ae PZ |
148 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
149 | ||
1d4f85ac | 150 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 151 | val |= g4x_infoframe_index(type); |
22509ec8 | 152 | |
178f736a | 153 | val &= ~g4x_infoframe_enable(type); |
45187ace | 154 | |
22509ec8 | 155 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 156 | |
9d9740f0 | 157 | mmiowb(); |
45187ace | 158 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
159 | I915_WRITE(VIDEO_DIP_DATA, *data); |
160 | data++; | |
161 | } | |
adf00b26 PZ |
162 | /* Write every possible data byte to force correct ECC calculation. */ |
163 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
164 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 165 | mmiowb(); |
3c17fe4b | 166 | |
178f736a | 167 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 168 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 169 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 170 | |
22509ec8 | 171 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 172 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
173 | } |
174 | ||
cda0aaaf VS |
175 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder, |
176 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 177 | { |
cda0aaaf | 178 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
89a35ecd | 179 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
180 | u32 val = I915_READ(VIDEO_DIP_CTL); |
181 | ||
ec1dc603 VS |
182 | if ((val & VIDEO_DIP_ENABLE) == 0) |
183 | return false; | |
89a35ecd | 184 | |
ec1dc603 VS |
185 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
186 | return false; | |
187 | ||
188 | return val & (VIDEO_DIP_ENABLE_AVI | | |
189 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
190 | } |
191 | ||
fdf1250a | 192 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 193 | const struct intel_crtc_state *crtc_state, |
178f736a | 194 | enum hdmi_infoframe_type type, |
fff63867 | 195 | const void *frame, ssize_t len) |
fdf1250a | 196 | { |
fff63867 | 197 | const uint32_t *data = frame; |
fdf1250a | 198 | struct drm_device *dev = encoder->dev; |
fac5e23e | 199 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 201 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 202 | u32 val = I915_READ(reg); |
f0f59a00 | 203 | int i; |
fdf1250a | 204 | |
822974ae PZ |
205 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
206 | ||
fdf1250a | 207 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 208 | val |= g4x_infoframe_index(type); |
fdf1250a | 209 | |
178f736a | 210 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
211 | |
212 | I915_WRITE(reg, val); | |
213 | ||
9d9740f0 | 214 | mmiowb(); |
fdf1250a PZ |
215 | for (i = 0; i < len; i += 4) { |
216 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
217 | data++; | |
218 | } | |
adf00b26 PZ |
219 | /* Write every possible data byte to force correct ECC calculation. */ |
220 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
221 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 222 | mmiowb(); |
fdf1250a | 223 | |
178f736a | 224 | val |= g4x_infoframe_enable(type); |
fdf1250a | 225 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 226 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
227 | |
228 | I915_WRITE(reg, val); | |
9d9740f0 | 229 | POSTING_READ(reg); |
fdf1250a PZ |
230 | } |
231 | ||
cda0aaaf VS |
232 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder, |
233 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 234 | { |
cda0aaaf | 235 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
052f62f7 | 236 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
237 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
238 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
239 | u32 val = I915_READ(reg); |
240 | ||
ec1dc603 VS |
241 | if ((val & VIDEO_DIP_ENABLE) == 0) |
242 | return false; | |
243 | ||
244 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
245 | return false; | |
052f62f7 | 246 | |
ec1dc603 VS |
247 | return val & (VIDEO_DIP_ENABLE_AVI | |
248 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
249 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
250 | } |
251 | ||
fdf1250a | 252 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 253 | const struct intel_crtc_state *crtc_state, |
178f736a | 254 | enum hdmi_infoframe_type type, |
fff63867 | 255 | const void *frame, ssize_t len) |
b055c8f3 | 256 | { |
fff63867 | 257 | const uint32_t *data = frame; |
b055c8f3 | 258 | struct drm_device *dev = encoder->dev; |
fac5e23e | 259 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 260 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 261 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 262 | u32 val = I915_READ(reg); |
f0f59a00 | 263 | int i; |
b055c8f3 | 264 | |
822974ae PZ |
265 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
266 | ||
64a8fc01 | 267 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 268 | val |= g4x_infoframe_index(type); |
45187ace | 269 | |
ecb97851 PZ |
270 | /* The DIP control register spec says that we need to update the AVI |
271 | * infoframe without clearing its enable bit */ | |
178f736a DL |
272 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
273 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 274 | |
22509ec8 | 275 | I915_WRITE(reg, val); |
45187ace | 276 | |
9d9740f0 | 277 | mmiowb(); |
45187ace | 278 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
279 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
280 | data++; | |
281 | } | |
adf00b26 PZ |
282 | /* Write every possible data byte to force correct ECC calculation. */ |
283 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
284 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 285 | mmiowb(); |
b055c8f3 | 286 | |
178f736a | 287 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 288 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 289 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 290 | |
22509ec8 | 291 | I915_WRITE(reg, val); |
9d9740f0 | 292 | POSTING_READ(reg); |
45187ace | 293 | } |
90b107c8 | 294 | |
cda0aaaf VS |
295 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder, |
296 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 297 | { |
cda0aaaf VS |
298 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
299 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; | |
300 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 301 | |
ec1dc603 VS |
302 | if ((val & VIDEO_DIP_ENABLE) == 0) |
303 | return false; | |
304 | ||
305 | return val & (VIDEO_DIP_ENABLE_AVI | | |
306 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
307 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
308 | } |
309 | ||
90b107c8 | 310 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 311 | const struct intel_crtc_state *crtc_state, |
178f736a | 312 | enum hdmi_infoframe_type type, |
fff63867 | 313 | const void *frame, ssize_t len) |
90b107c8 | 314 | { |
fff63867 | 315 | const uint32_t *data = frame; |
90b107c8 | 316 | struct drm_device *dev = encoder->dev; |
fac5e23e | 317 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 318 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 319 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 320 | u32 val = I915_READ(reg); |
f0f59a00 | 321 | int i; |
90b107c8 | 322 | |
822974ae PZ |
323 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
324 | ||
90b107c8 | 325 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 326 | val |= g4x_infoframe_index(type); |
22509ec8 | 327 | |
178f736a | 328 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 329 | |
22509ec8 | 330 | I915_WRITE(reg, val); |
90b107c8 | 331 | |
9d9740f0 | 332 | mmiowb(); |
90b107c8 SK |
333 | for (i = 0; i < len; i += 4) { |
334 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
335 | data++; | |
336 | } | |
adf00b26 PZ |
337 | /* Write every possible data byte to force correct ECC calculation. */ |
338 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
339 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 340 | mmiowb(); |
90b107c8 | 341 | |
178f736a | 342 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 343 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 344 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 345 | |
22509ec8 | 346 | I915_WRITE(reg, val); |
9d9740f0 | 347 | POSTING_READ(reg); |
90b107c8 SK |
348 | } |
349 | ||
cda0aaaf VS |
350 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder, |
351 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 352 | { |
cda0aaaf | 353 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
535afa2e | 354 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
355 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
356 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 357 | |
ec1dc603 VS |
358 | if ((val & VIDEO_DIP_ENABLE) == 0) |
359 | return false; | |
360 | ||
361 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
362 | return false; | |
535afa2e | 363 | |
ec1dc603 VS |
364 | return val & (VIDEO_DIP_ENABLE_AVI | |
365 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
366 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
367 | } |
368 | ||
8c5f5f7c | 369 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 370 | const struct intel_crtc_state *crtc_state, |
178f736a | 371 | enum hdmi_infoframe_type type, |
fff63867 | 372 | const void *frame, ssize_t len) |
8c5f5f7c | 373 | { |
fff63867 | 374 | const uint32_t *data = frame; |
2da8af54 | 375 | struct drm_device *dev = encoder->dev; |
fac5e23e | 376 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 377 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 VS |
378 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
379 | i915_reg_t data_reg; | |
178f736a | 380 | int i; |
2da8af54 | 381 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 382 | |
436c6d4a | 383 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
2da8af54 | 384 | |
178f736a | 385 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
386 | I915_WRITE(ctl_reg, val); |
387 | ||
9d9740f0 | 388 | mmiowb(); |
2da8af54 | 389 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
390 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
391 | type, i >> 2), *data); | |
2da8af54 PZ |
392 | data++; |
393 | } | |
adf00b26 PZ |
394 | /* Write every possible data byte to force correct ECC calculation. */ |
395 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
436c6d4a VS |
396 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
397 | type, i >> 2), 0); | |
9d9740f0 | 398 | mmiowb(); |
8c5f5f7c | 399 | |
178f736a | 400 | val |= hsw_infoframe_enable(type); |
2da8af54 | 401 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 402 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
403 | } |
404 | ||
cda0aaaf VS |
405 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder, |
406 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 407 | { |
cda0aaaf VS |
408 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
409 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); | |
e43823ec | 410 | |
ec1dc603 VS |
411 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
412 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
413 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
414 | } |
415 | ||
5adaea79 DL |
416 | /* |
417 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
418 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
419 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
420 | * used for both technologies. | |
421 | * | |
422 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
423 | * DW1: DB3 | DB2 | DB1 | DB0 | |
424 | * DW2: DB7 | DB6 | DB5 | DB4 | |
425 | * DW3: ... | |
426 | * | |
427 | * (HB is Header Byte, DB is Data Byte) | |
428 | * | |
429 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
430 | * trick them by giving an offset into the buffer and moving back the header | |
431 | * bytes by one. | |
432 | */ | |
9198ee5b | 433 | static void intel_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 434 | const struct intel_crtc_state *crtc_state, |
9198ee5b | 435 | union hdmi_infoframe *frame) |
45187ace | 436 | { |
f99be1b3 | 437 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
5adaea79 DL |
438 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
439 | ssize_t len; | |
45187ace | 440 | |
5adaea79 DL |
441 | /* see comment above for the reason for this offset */ |
442 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
443 | if (len < 0) | |
444 | return; | |
445 | ||
446 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
447 | buffer[0] = buffer[1]; | |
448 | buffer[1] = buffer[2]; | |
449 | buffer[2] = buffer[3]; | |
450 | buffer[3] = 0; | |
451 | len++; | |
45187ace | 452 | |
f99be1b3 | 453 | intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); |
45187ace JB |
454 | } |
455 | ||
687f4d06 | 456 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
ac240288 | 457 | const struct intel_crtc_state *crtc_state) |
45187ace | 458 | { |
abedc077 | 459 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
779c4c28 VS |
460 | const struct drm_display_mode *adjusted_mode = |
461 | &crtc_state->base.adjusted_mode; | |
0c1f528c SS |
462 | struct drm_connector *connector = &intel_hdmi->attached_connector->base; |
463 | bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported; | |
5adaea79 DL |
464 | union hdmi_infoframe frame; |
465 | int ret; | |
45187ace | 466 | |
5adaea79 | 467 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
0c1f528c SS |
468 | adjusted_mode, |
469 | is_hdmi2_sink); | |
5adaea79 DL |
470 | if (ret < 0) { |
471 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
472 | return; | |
473 | } | |
c846b619 | 474 | |
2d8bd2bf SS |
475 | if (crtc_state->ycbcr420) |
476 | frame.avi.colorspace = HDMI_COLORSPACE_YUV420; | |
477 | else | |
478 | frame.avi.colorspace = HDMI_COLORSPACE_RGB; | |
479 | ||
779c4c28 | 480 | drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, |
a2ce26f8 VS |
481 | crtc_state->limited_color_range ? |
482 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
483 | HDMI_QUANTIZATION_RANGE_FULL, | |
484 | intel_hdmi->rgb_quant_range_selectable); | |
abedc077 | 485 | |
2d8bd2bf | 486 | /* TODO: handle pixel repetition for YCBCR420 outputs */ |
ac240288 | 487 | intel_write_infoframe(encoder, crtc_state, &frame); |
b055c8f3 JB |
488 | } |
489 | ||
ac240288 ML |
490 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder, |
491 | const struct intel_crtc_state *crtc_state) | |
c0864cb3 | 492 | { |
5adaea79 DL |
493 | union hdmi_infoframe frame; |
494 | int ret; | |
495 | ||
496 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
497 | if (ret < 0) { | |
498 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
499 | return; | |
500 | } | |
c0864cb3 | 501 | |
5adaea79 | 502 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 503 | |
ac240288 | 504 | intel_write_infoframe(encoder, crtc_state, &frame); |
c0864cb3 JB |
505 | } |
506 | ||
c8bb75af LD |
507 | static void |
508 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
ac240288 | 509 | const struct intel_crtc_state *crtc_state) |
c8bb75af LD |
510 | { |
511 | union hdmi_infoframe frame; | |
512 | int ret; | |
513 | ||
514 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
ac240288 | 515 | &crtc_state->base.adjusted_mode); |
c8bb75af LD |
516 | if (ret < 0) |
517 | return; | |
518 | ||
ac240288 | 519 | intel_write_infoframe(encoder, crtc_state, &frame); |
c8bb75af LD |
520 | } |
521 | ||
687f4d06 | 522 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 523 | bool enable, |
ac240288 ML |
524 | const struct intel_crtc_state *crtc_state, |
525 | const struct drm_connector_state *conn_state) | |
687f4d06 | 526 | { |
fac5e23e | 527 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
69fde0a6 VS |
528 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
529 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 530 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 531 | u32 val = I915_READ(reg); |
822cdc52 | 532 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 533 | |
afba0188 DV |
534 | assert_hdmi_port_disabled(intel_hdmi); |
535 | ||
0c14c7f9 PZ |
536 | /* If the registers were not initialized yet, they might be zeroes, |
537 | * which means we're selecting the AVI DIP and we're setting its | |
538 | * frequency to once. This seems to really confuse the HW and make | |
539 | * things stop working (the register spec says the AVI always needs to | |
540 | * be sent every VSync). So here we avoid writing to the register more | |
541 | * than we need and also explicitly select the AVI DIP and explicitly | |
542 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
543 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
544 | * either. */ | |
545 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
546 | ||
6897b4b5 | 547 | if (!enable) { |
0c14c7f9 PZ |
548 | if (!(val & VIDEO_DIP_ENABLE)) |
549 | return; | |
0be6f0c8 VS |
550 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
551 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
552 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
553 | return; | |
554 | } | |
555 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
556 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 557 | I915_WRITE(reg, val); |
9d9740f0 | 558 | POSTING_READ(reg); |
0c14c7f9 PZ |
559 | return; |
560 | } | |
561 | ||
72b78c9d PZ |
562 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
563 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
564 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
565 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
566 | return; | |
72b78c9d PZ |
567 | } |
568 | val &= ~VIDEO_DIP_PORT_MASK; | |
569 | val |= port; | |
570 | } | |
571 | ||
822974ae | 572 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
573 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
574 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 575 | |
f278d972 | 576 | I915_WRITE(reg, val); |
9d9740f0 | 577 | POSTING_READ(reg); |
f278d972 | 578 | |
ac240288 ML |
579 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
580 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
581 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
582 | } |
583 | ||
ac240288 | 584 | static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state) |
6d67415f | 585 | { |
ac240288 | 586 | struct drm_connector *connector = conn_state->connector; |
6d67415f VS |
587 | |
588 | /* | |
589 | * HDMI cloning is only supported on g4x which doesn't | |
590 | * support deep color or GCP infoframes anyway so no | |
591 | * need to worry about multiple HDMI sinks here. | |
592 | */ | |
6d67415f | 593 | |
ac240288 | 594 | return connector->display_info.bpc > 8; |
6d67415f VS |
595 | } |
596 | ||
12aa3290 VS |
597 | /* |
598 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
599 | * | |
600 | * From HDMI specification 1.4a: | |
601 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
602 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
603 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
604 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
605 | * phase of 0 | |
606 | */ | |
607 | static bool gcp_default_phase_possible(int pipe_bpp, | |
608 | const struct drm_display_mode *mode) | |
609 | { | |
610 | unsigned int pixels_per_group; | |
611 | ||
612 | switch (pipe_bpp) { | |
613 | case 30: | |
614 | /* 4 pixels in 5 clocks */ | |
615 | pixels_per_group = 4; | |
616 | break; | |
617 | case 36: | |
618 | /* 2 pixels in 3 clocks */ | |
619 | pixels_per_group = 2; | |
620 | break; | |
621 | case 48: | |
622 | /* 1 pixel in 2 clocks */ | |
623 | pixels_per_group = 1; | |
624 | break; | |
625 | default: | |
626 | /* phase information not relevant for 8bpc */ | |
627 | return false; | |
628 | } | |
629 | ||
630 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
631 | mode->crtc_htotal % pixels_per_group == 0 && | |
632 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
633 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
634 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
635 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
636 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
637 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
638 | } | |
639 | ||
ac240288 ML |
640 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder, |
641 | const struct intel_crtc_state *crtc_state, | |
642 | const struct drm_connector_state *conn_state) | |
6d67415f | 643 | { |
fac5e23e | 644 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 645 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 VS |
646 | i915_reg_t reg; |
647 | u32 val = 0; | |
6d67415f VS |
648 | |
649 | if (HAS_DDI(dev_priv)) | |
ac240288 | 650 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 651 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 652 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 653 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
654 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
655 | else | |
656 | return false; | |
657 | ||
658 | /* Indicate color depth whenever the sink supports deep color */ | |
ac240288 | 659 | if (hdmi_sink_is_deep_color(conn_state)) |
6d67415f VS |
660 | val |= GCP_COLOR_INDICATION; |
661 | ||
12aa3290 | 662 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
663 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
664 | &crtc_state->base.adjusted_mode)) | |
12aa3290 VS |
665 | val |= GCP_DEFAULT_PHASE_ENABLE; |
666 | ||
6d67415f VS |
667 | I915_WRITE(reg, val); |
668 | ||
669 | return val != 0; | |
670 | } | |
671 | ||
687f4d06 | 672 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 673 | bool enable, |
ac240288 ML |
674 | const struct intel_crtc_state *crtc_state, |
675 | const struct drm_connector_state *conn_state) | |
687f4d06 | 676 | { |
fac5e23e | 677 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
69fde0a6 VS |
679 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
680 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 681 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 682 | u32 val = I915_READ(reg); |
822cdc52 | 683 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 684 | |
afba0188 DV |
685 | assert_hdmi_port_disabled(intel_hdmi); |
686 | ||
0c14c7f9 PZ |
687 | /* See the big comment in g4x_set_infoframes() */ |
688 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
689 | ||
6897b4b5 | 690 | if (!enable) { |
0c14c7f9 PZ |
691 | if (!(val & VIDEO_DIP_ENABLE)) |
692 | return; | |
0be6f0c8 VS |
693 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
694 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
695 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 696 | I915_WRITE(reg, val); |
9d9740f0 | 697 | POSTING_READ(reg); |
0c14c7f9 PZ |
698 | return; |
699 | } | |
700 | ||
72b78c9d | 701 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
702 | WARN(val & VIDEO_DIP_ENABLE, |
703 | "DIP already enabled on port %c\n", | |
704 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
705 | val &= ~VIDEO_DIP_PORT_MASK; |
706 | val |= port; | |
707 | } | |
708 | ||
822974ae | 709 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
710 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
711 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
712 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 713 | |
ac240288 | 714 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
715 | val |= VIDEO_DIP_ENABLE_GCP; |
716 | ||
f278d972 | 717 | I915_WRITE(reg, val); |
9d9740f0 | 718 | POSTING_READ(reg); |
f278d972 | 719 | |
ac240288 ML |
720 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
721 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
722 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
723 | } |
724 | ||
725 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 726 | bool enable, |
ac240288 ML |
727 | const struct intel_crtc_state *crtc_state, |
728 | const struct drm_connector_state *conn_state) | |
687f4d06 | 729 | { |
fac5e23e | 730 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 731 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 732 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 733 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
734 | u32 val = I915_READ(reg); |
735 | ||
afba0188 DV |
736 | assert_hdmi_port_disabled(intel_hdmi); |
737 | ||
0c14c7f9 PZ |
738 | /* See the big comment in g4x_set_infoframes() */ |
739 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
740 | ||
6897b4b5 | 741 | if (!enable) { |
0c14c7f9 PZ |
742 | if (!(val & VIDEO_DIP_ENABLE)) |
743 | return; | |
0be6f0c8 VS |
744 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
745 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
746 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 747 | I915_WRITE(reg, val); |
9d9740f0 | 748 | POSTING_READ(reg); |
0c14c7f9 PZ |
749 | return; |
750 | } | |
751 | ||
822974ae PZ |
752 | /* Set both together, unset both together: see the spec. */ |
753 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 754 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 755 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 756 | |
ac240288 | 757 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
758 | val |= VIDEO_DIP_ENABLE_GCP; |
759 | ||
822974ae | 760 | I915_WRITE(reg, val); |
9d9740f0 | 761 | POSTING_READ(reg); |
822974ae | 762 | |
ac240288 ML |
763 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
764 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
765 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
766 | } |
767 | ||
768 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 769 | bool enable, |
ac240288 ML |
770 | const struct intel_crtc_state *crtc_state, |
771 | const struct drm_connector_state *conn_state) | |
687f4d06 | 772 | { |
fac5e23e | 773 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
6a2b8021 | 774 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
ac240288 | 775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 776 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 777 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 778 | u32 val = I915_READ(reg); |
6a2b8021 | 779 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 780 | |
afba0188 DV |
781 | assert_hdmi_port_disabled(intel_hdmi); |
782 | ||
0c14c7f9 PZ |
783 | /* See the big comment in g4x_set_infoframes() */ |
784 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
785 | ||
6897b4b5 | 786 | if (!enable) { |
0c14c7f9 PZ |
787 | if (!(val & VIDEO_DIP_ENABLE)) |
788 | return; | |
0be6f0c8 VS |
789 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
790 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
791 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 792 | I915_WRITE(reg, val); |
9d9740f0 | 793 | POSTING_READ(reg); |
0c14c7f9 PZ |
794 | return; |
795 | } | |
796 | ||
6a2b8021 | 797 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
798 | WARN(val & VIDEO_DIP_ENABLE, |
799 | "DIP already enabled on port %c\n", | |
800 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
801 | val &= ~VIDEO_DIP_PORT_MASK; |
802 | val |= port; | |
803 | } | |
804 | ||
822974ae | 805 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
806 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
807 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
808 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 809 | |
ac240288 | 810 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
811 | val |= VIDEO_DIP_ENABLE_GCP; |
812 | ||
822974ae | 813 | I915_WRITE(reg, val); |
9d9740f0 | 814 | POSTING_READ(reg); |
822974ae | 815 | |
ac240288 ML |
816 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
817 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
818 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
819 | } |
820 | ||
821 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 822 | bool enable, |
ac240288 ML |
823 | const struct intel_crtc_state *crtc_state, |
824 | const struct drm_connector_state *conn_state) | |
687f4d06 | 825 | { |
fac5e23e | 826 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
0c14c7f9 | 827 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
ac240288 | 828 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 829 | u32 val = I915_READ(reg); |
0c14c7f9 | 830 | |
afba0188 DV |
831 | assert_hdmi_port_disabled(intel_hdmi); |
832 | ||
0be6f0c8 VS |
833 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
834 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
835 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
836 | ||
6897b4b5 | 837 | if (!enable) { |
0be6f0c8 | 838 | I915_WRITE(reg, val); |
9d9740f0 | 839 | POSTING_READ(reg); |
0c14c7f9 PZ |
840 | return; |
841 | } | |
842 | ||
ac240288 | 843 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
844 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
845 | ||
0dd87d20 | 846 | I915_WRITE(reg, val); |
9d9740f0 | 847 | POSTING_READ(reg); |
0dd87d20 | 848 | |
ac240288 ML |
849 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
850 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
851 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state); | |
687f4d06 PZ |
852 | } |
853 | ||
b2ccb822 VS |
854 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
855 | { | |
856 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
857 | struct i2c_adapter *adapter = | |
858 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
859 | ||
860 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
861 | return; | |
862 | ||
863 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
864 | enable ? "Enabling" : "Disabling"); | |
865 | ||
866 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
867 | adapter, enable); | |
868 | } | |
869 | ||
ac240288 ML |
870 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
871 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 872 | { |
c59423a3 | 873 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 874 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 875 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 876 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 877 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 878 | u32 hdmi_val; |
7d57382e | 879 | |
b2ccb822 VS |
880 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
881 | ||
b242b7f7 | 882 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 883 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 884 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 885 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 886 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 887 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 888 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 889 | |
ac240288 | 890 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 891 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 892 | else |
4f3a8bc7 | 893 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 894 | |
ac240288 | 895 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 896 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 897 | |
6e266956 | 898 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 899 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 900 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 901 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 902 | else |
c59423a3 | 903 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 904 | |
b242b7f7 PZ |
905 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
906 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
907 | } |
908 | ||
85234cdc DV |
909 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
910 | enum pipe *pipe) | |
7d57382e | 911 | { |
85234cdc | 912 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 913 | struct drm_i915_private *dev_priv = to_i915(dev); |
85234cdc DV |
914 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
915 | u32 tmp; | |
5b092174 | 916 | bool ret; |
85234cdc | 917 | |
79f255a0 ACO |
918 | if (!intel_display_power_get_if_enabled(dev_priv, |
919 | encoder->power_domain)) | |
6d129bea ID |
920 | return false; |
921 | ||
5b092174 ID |
922 | ret = false; |
923 | ||
b242b7f7 | 924 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
925 | |
926 | if (!(tmp & SDVO_ENABLE)) | |
5b092174 | 927 | goto out; |
85234cdc | 928 | |
6e266956 | 929 | if (HAS_PCH_CPT(dev_priv)) |
85234cdc | 930 | *pipe = PORT_TO_PIPE_CPT(tmp); |
920a14b2 | 931 | else if (IS_CHERRYVIEW(dev_priv)) |
71485e0a | 932 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
85234cdc DV |
933 | else |
934 | *pipe = PORT_TO_PIPE(tmp); | |
935 | ||
5b092174 ID |
936 | ret = true; |
937 | ||
938 | out: | |
79f255a0 | 939 | intel_display_power_put(dev_priv, encoder->power_domain); |
5b092174 ID |
940 | |
941 | return ret; | |
85234cdc DV |
942 | } |
943 | ||
045ac3b5 | 944 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 945 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
946 | { |
947 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
f99be1b3 | 948 | struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi); |
8c875fca | 949 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 950 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 951 | u32 tmp, flags = 0; |
18442d08 | 952 | int dotclock; |
045ac3b5 JB |
953 | |
954 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
955 | ||
956 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
957 | flags |= DRM_MODE_FLAG_PHSYNC; | |
958 | else | |
959 | flags |= DRM_MODE_FLAG_NHSYNC; | |
960 | ||
961 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
962 | flags |= DRM_MODE_FLAG_PVSYNC; | |
963 | else | |
964 | flags |= DRM_MODE_FLAG_NVSYNC; | |
965 | ||
6897b4b5 DV |
966 | if (tmp & HDMI_MODE_SELECT_HDMI) |
967 | pipe_config->has_hdmi_sink = true; | |
968 | ||
f99be1b3 | 969 | if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) |
e43823ec JB |
970 | pipe_config->has_infoframe = true; |
971 | ||
c84db770 | 972 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
973 | pipe_config->has_audio = true; |
974 | ||
6e266956 | 975 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
976 | tmp & HDMI_COLOR_RANGE_16_235) |
977 | pipe_config->limited_color_range = true; | |
978 | ||
2d112de7 | 979 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
980 | |
981 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
982 | dotclock = pipe_config->port_clock * 2 / 3; | |
983 | else | |
984 | dotclock = pipe_config->port_clock; | |
985 | ||
be69a133 VS |
986 | if (pipe_config->pixel_multiplier) |
987 | dotclock /= pipe_config->pixel_multiplier; | |
988 | ||
2d112de7 | 989 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
990 | |
991 | pipe_config->lane_count = 4; | |
045ac3b5 JB |
992 | } |
993 | ||
df18e721 ML |
994 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
995 | struct intel_crtc_state *pipe_config, | |
996 | struct drm_connector_state *conn_state) | |
d1b1589c | 997 | { |
ac240288 | 998 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 999 | |
ac240288 | 1000 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
1001 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
1002 | pipe_name(crtc->pipe)); | |
bbf35e9d | 1003 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
1004 | } |
1005 | ||
fd6bbda9 ML |
1006 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
1007 | struct intel_crtc_state *pipe_config, | |
1008 | struct drm_connector_state *conn_state) | |
7d57382e | 1009 | { |
5ab432ef | 1010 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1011 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1012 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1013 | u32 temp; |
1014 | ||
b242b7f7 | 1015 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1016 | |
bf868c7d | 1017 | temp |= SDVO_ENABLE; |
df18e721 | 1018 | if (pipe_config->has_audio) |
bf868c7d | 1019 | temp |= SDVO_AUDIO_ENABLE; |
7a87c289 | 1020 | |
bf868c7d VS |
1021 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1022 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1023 | ||
df18e721 ML |
1024 | if (pipe_config->has_audio) |
1025 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1026 | } |
1027 | ||
fd6bbda9 ML |
1028 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
1029 | struct intel_crtc_state *pipe_config, | |
1030 | struct drm_connector_state *conn_state) | |
bf868c7d VS |
1031 | { |
1032 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1033 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1034 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1035 | u32 temp; | |
1036 | ||
1037 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1038 | |
bf868c7d | 1039 | temp |= SDVO_ENABLE; |
ac240288 | 1040 | if (pipe_config->has_audio) |
bf868c7d | 1041 | temp |= SDVO_AUDIO_ENABLE; |
5ab432ef | 1042 | |
bf868c7d VS |
1043 | /* |
1044 | * HW workaround, need to write this twice for issue | |
1045 | * that may result in first write getting masked. | |
1046 | */ | |
1047 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1048 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1049 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1050 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1051 | |
bf868c7d VS |
1052 | /* |
1053 | * HW workaround, need to toggle enable bit off and on | |
1054 | * for 12bpc with pixel repeat. | |
1055 | * | |
1056 | * FIXME: BSpec says this should be done at the end of | |
1057 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1058 | */ |
df18e721 ML |
1059 | if (pipe_config->pipe_bpp > 24 && |
1060 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1061 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1062 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1063 | ||
1064 | /* | |
1065 | * HW workaround, need to write this twice for issue | |
1066 | * that may result in first write getting masked. | |
1067 | */ | |
1068 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1069 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1070 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1071 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1072 | } |
c1dec79a | 1073 | |
df18e721 ML |
1074 | if (pipe_config->has_audio) |
1075 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1076 | } |
1077 | ||
fd6bbda9 ML |
1078 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
1079 | struct intel_crtc_state *pipe_config, | |
1080 | struct drm_connector_state *conn_state) | |
d1b1589c VS |
1081 | { |
1082 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1083 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1084 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1085 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1086 | enum pipe pipe = crtc->pipe; | |
1087 | u32 temp; | |
1088 | ||
1089 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1090 | ||
1091 | temp |= SDVO_ENABLE; | |
df18e721 | 1092 | if (pipe_config->has_audio) |
d1b1589c VS |
1093 | temp |= SDVO_AUDIO_ENABLE; |
1094 | ||
1095 | /* | |
1096 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1097 | * | |
1098 | * The procedure for 12bpc is as follows: | |
1099 | * 1. disable HDMI clock gating | |
1100 | * 2. enable HDMI with 8bpc | |
1101 | * 3. enable HDMI with 12bpc | |
1102 | * 4. enable HDMI clock gating | |
1103 | */ | |
1104 | ||
df18e721 | 1105 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1106 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1107 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1108 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1109 | ||
1110 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1111 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1112 | } |
d1b1589c VS |
1113 | |
1114 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1115 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1116 | ||
df18e721 | 1117 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1118 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1119 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1120 | ||
1121 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1122 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1123 | ||
1124 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1125 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1126 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1127 | } | |
1128 | ||
df18e721 ML |
1129 | if (pipe_config->has_audio) |
1130 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1131 | } |
89b667f8 | 1132 | |
fd6bbda9 ML |
1133 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
1134 | struct intel_crtc_state *pipe_config, | |
1135 | struct drm_connector_state *conn_state) | |
b76cf76b | 1136 | { |
5ab432ef DV |
1137 | } |
1138 | ||
fd6bbda9 ML |
1139 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
1140 | struct intel_crtc_state *old_crtc_state, | |
1141 | struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
1142 | { |
1143 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1144 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1145 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f99be1b3 VS |
1146 | struct intel_digital_port *intel_dig_port = |
1147 | hdmi_to_dig_port(intel_hdmi); | |
ac240288 | 1148 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 1149 | u32 temp; |
5ab432ef | 1150 | |
b242b7f7 | 1151 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1152 | |
1612c8bd | 1153 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1154 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1155 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1156 | |
1157 | /* | |
1158 | * HW workaround for IBX, we need to move the port | |
1159 | * to transcoder A after disabling it to allow the | |
1160 | * matching DP port to be enabled on transcoder A. | |
1161 | */ | |
6e266956 | 1162 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
1163 | /* |
1164 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1165 | * doing the workaround. Sweep them under the rug. | |
1166 | */ | |
1167 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1168 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1169 | ||
1612c8bd VS |
1170 | temp &= ~SDVO_PIPE_B_SELECT; |
1171 | temp |= SDVO_ENABLE; | |
1172 | /* | |
1173 | * HW workaround, need to write this twice for issue | |
1174 | * that may result in first write getting masked. | |
1175 | */ | |
1176 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1177 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1178 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1179 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1180 | ||
1181 | temp &= ~SDVO_ENABLE; | |
1182 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1183 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 1184 | |
0f0f74bc | 1185 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
1186 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
1187 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 1188 | } |
6d67415f | 1189 | |
f99be1b3 VS |
1190 | intel_dig_port->set_infoframes(&encoder->base, false, |
1191 | old_crtc_state, old_conn_state); | |
b2ccb822 VS |
1192 | |
1193 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
1194 | } |
1195 | ||
fd6bbda9 ML |
1196 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
1197 | struct intel_crtc_state *old_crtc_state, | |
1198 | struct drm_connector_state *old_conn_state) | |
a4790cec | 1199 | { |
df18e721 | 1200 | if (old_crtc_state->has_audio) |
a4790cec VS |
1201 | intel_audio_codec_disable(encoder); |
1202 | ||
fd6bbda9 | 1203 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1204 | } |
1205 | ||
fd6bbda9 ML |
1206 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
1207 | struct intel_crtc_state *old_crtc_state, | |
1208 | struct drm_connector_state *old_conn_state) | |
a4790cec | 1209 | { |
df18e721 | 1210 | if (old_crtc_state->has_audio) |
a4790cec VS |
1211 | intel_audio_codec_disable(encoder); |
1212 | } | |
1213 | ||
fd6bbda9 ML |
1214 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
1215 | struct intel_crtc_state *old_crtc_state, | |
1216 | struct drm_connector_state *old_conn_state) | |
a4790cec | 1217 | { |
fd6bbda9 | 1218 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1219 | } |
1220 | ||
b1ba124d | 1221 | static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) |
7d148ef5 | 1222 | { |
b1ba124d | 1223 | if (IS_G4X(dev_priv)) |
7d148ef5 | 1224 | return 165000; |
14292b7f SS |
1225 | else if (IS_GEMINILAKE(dev_priv)) |
1226 | return 594000; | |
b1ba124d | 1227 | else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) |
7d148ef5 DV |
1228 | return 300000; |
1229 | else | |
1230 | return 225000; | |
1231 | } | |
1232 | ||
b1ba124d | 1233 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f ML |
1234 | bool respect_downstream_limits, |
1235 | bool force_dvi) | |
b1ba124d VS |
1236 | { |
1237 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1238 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); | |
1239 | ||
1240 | if (respect_downstream_limits) { | |
8cadab0a VS |
1241 | struct intel_connector *connector = hdmi->attached_connector; |
1242 | const struct drm_display_info *info = &connector->base.display_info; | |
1243 | ||
b1ba124d VS |
1244 | if (hdmi->dp_dual_mode.max_tmds_clock) |
1245 | max_tmds_clock = min(max_tmds_clock, | |
1246 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
1247 | |
1248 | if (info->max_tmds_clock) | |
1249 | max_tmds_clock = min(max_tmds_clock, | |
1250 | info->max_tmds_clock); | |
7a5ca19f | 1251 | else if (!hdmi->has_hdmi_sink || force_dvi) |
b1ba124d VS |
1252 | max_tmds_clock = min(max_tmds_clock, 165000); |
1253 | } | |
1254 | ||
1255 | return max_tmds_clock; | |
1256 | } | |
1257 | ||
e64e739e VS |
1258 | static enum drm_mode_status |
1259 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f ML |
1260 | int clock, bool respect_downstream_limits, |
1261 | bool force_dvi) | |
e64e739e | 1262 | { |
e2d214ae | 1263 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
1264 | |
1265 | if (clock < 25000) | |
1266 | return MODE_CLOCK_LOW; | |
7a5ca19f | 1267 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) |
e64e739e VS |
1268 | return MODE_CLOCK_HIGH; |
1269 | ||
5e6ccc0b | 1270 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 1271 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
1272 | return MODE_CLOCK_RANGE; |
1273 | ||
1274 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 1275 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
1276 | return MODE_CLOCK_RANGE; |
1277 | ||
1278 | return MODE_OK; | |
1279 | } | |
1280 | ||
c19de8eb DL |
1281 | static enum drm_mode_status |
1282 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1283 | struct drm_display_mode *mode) | |
7d57382e | 1284 | { |
e64e739e VS |
1285 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1286 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 1287 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
1288 | enum drm_mode_status status; |
1289 | int clock; | |
587bf496 | 1290 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
7a5ca19f ML |
1291 | bool force_dvi = |
1292 | READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; | |
e64e739e VS |
1293 | |
1294 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1295 | return MODE_NO_DBLESCAN; | |
697c4078 | 1296 | |
e64e739e | 1297 | clock = mode->clock; |
587bf496 MK |
1298 | |
1299 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
1300 | clock *= 2; | |
1301 | ||
1302 | if (clock > max_dotclk) | |
1303 | return MODE_CLOCK_HIGH; | |
1304 | ||
697c4078 CT |
1305 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1306 | clock *= 2; | |
1307 | ||
b22ca995 SS |
1308 | if (drm_mode_is_420_only(&connector->display_info, mode)) |
1309 | clock /= 2; | |
1310 | ||
e64e739e | 1311 | /* check if we can do 8bpc */ |
7a5ca19f | 1312 | status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); |
7d57382e | 1313 | |
e64e739e | 1314 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
7a5ca19f ML |
1315 | if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi) |
1316 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi); | |
7d57382e | 1317 | |
e64e739e | 1318 | return status; |
7d57382e EA |
1319 | } |
1320 | ||
77f06c86 | 1321 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 1322 | { |
c750bdd3 VS |
1323 | struct drm_i915_private *dev_priv = |
1324 | to_i915(crtc_state->base.crtc->dev); | |
1325 | struct drm_atomic_state *state = crtc_state->base.state; | |
1326 | struct drm_connector_state *connector_state; | |
1327 | struct drm_connector *connector; | |
1328 | int i; | |
71800632 | 1329 | |
c750bdd3 | 1330 | if (HAS_GMCH_DISPLAY(dev_priv)) |
71800632 VS |
1331 | return false; |
1332 | ||
71800632 VS |
1333 | /* |
1334 | * HDMI 12bpc affects the clocks, so it's only possible | |
1335 | * when not cloning with other encoder types. | |
1336 | */ | |
c750bdd3 VS |
1337 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
1338 | return false; | |
1339 | ||
fe5f6b1f | 1340 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
c750bdd3 VS |
1341 | const struct drm_display_info *info = &connector->display_info; |
1342 | ||
1343 | if (connector_state->crtc != crtc_state->base.crtc) | |
1344 | continue; | |
1345 | ||
60436fd4 SS |
1346 | if (crtc_state->ycbcr420) { |
1347 | const struct drm_hdmi_info *hdmi = &info->hdmi; | |
1348 | ||
1349 | if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) | |
1350 | return false; | |
1351 | } else { | |
1352 | if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36)) | |
1353 | return false; | |
1354 | } | |
c750bdd3 VS |
1355 | } |
1356 | ||
46649d8b ACO |
1357 | /* Display Wa #1139 */ |
1358 | if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && | |
1359 | crtc_state->base.adjusted_mode.htotal > 5460) | |
1360 | return false; | |
1361 | ||
c750bdd3 | 1362 | return true; |
71800632 VS |
1363 | } |
1364 | ||
60436fd4 SS |
1365 | static bool |
1366 | intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |
1367 | struct intel_crtc_state *config, | |
1368 | int *clock_12bpc, int *clock_8bpc) | |
1369 | { | |
e5c05931 SS |
1370 | struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); |
1371 | ||
60436fd4 SS |
1372 | if (!connector->ycbcr_420_allowed) { |
1373 | DRM_ERROR("Platform doesn't support YCBCR420 output\n"); | |
1374 | return false; | |
1375 | } | |
1376 | ||
1377 | /* YCBCR420 TMDS rate requirement is half the pixel clock */ | |
1378 | config->port_clock /= 2; | |
1379 | *clock_12bpc /= 2; | |
1380 | *clock_8bpc /= 2; | |
1381 | config->ycbcr420 = true; | |
e5c05931 SS |
1382 | |
1383 | /* YCBCR 420 output conversion needs a scaler */ | |
1384 | if (skl_update_scaler_crtc(config)) { | |
1385 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
1386 | return false; | |
1387 | } | |
1388 | ||
1389 | intel_pch_panel_fitting(intel_crtc, config, | |
1390 | DRM_MODE_SCALE_FULLSCREEN); | |
1391 | ||
60436fd4 SS |
1392 | return true; |
1393 | } | |
1394 | ||
5bfe2ac0 | 1395 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1396 | struct intel_crtc_state *pipe_config, |
1397 | struct drm_connector_state *conn_state) | |
7d57382e | 1398 | { |
5bfe2ac0 | 1399 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 1400 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1401 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
60436fd4 SS |
1402 | struct drm_connector *connector = conn_state->connector; |
1403 | struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; | |
7a5ca19f ML |
1404 | struct intel_digital_connector_state *intel_conn_state = |
1405 | to_intel_digital_connector_state(conn_state); | |
e64e739e VS |
1406 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1407 | int clock_12bpc = clock_8bpc * 3 / 2; | |
e29c22c0 | 1408 | int desired_bpp; |
7a5ca19f | 1409 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
3685a8f3 | 1410 | |
7a5ca19f | 1411 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
6897b4b5 | 1412 | |
e43823ec JB |
1413 | if (pipe_config->has_hdmi_sink) |
1414 | pipe_config->has_infoframe = true; | |
1415 | ||
7a5ca19f | 1416 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db | 1417 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
0f2a2a75 VS |
1418 | pipe_config->limited_color_range = |
1419 | pipe_config->has_hdmi_sink && | |
c8127cf0 VS |
1420 | drm_default_rgb_quant_range(adjusted_mode) == |
1421 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1422 | } else { |
1423 | pipe_config->limited_color_range = | |
7a5ca19f | 1424 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
1425 | } |
1426 | ||
697c4078 CT |
1427 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1428 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1429 | clock_8bpc *= 2; |
3320e37f | 1430 | clock_12bpc *= 2; |
697c4078 CT |
1431 | } |
1432 | ||
60436fd4 SS |
1433 | if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { |
1434 | if (!intel_hdmi_ycbcr420_config(connector, pipe_config, | |
1435 | &clock_12bpc, &clock_8bpc)) { | |
1436 | DRM_ERROR("Can't support YCBCR420 output\n"); | |
1437 | return false; | |
1438 | } | |
1439 | } | |
1440 | ||
4f8036a2 | 1441 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
1442 | pipe_config->has_pch_encoder = true; |
1443 | ||
7a5ca19f ML |
1444 | if (pipe_config->has_hdmi_sink) { |
1445 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
1446 | pipe_config->has_audio = intel_hdmi->has_audio; | |
1447 | else | |
1448 | pipe_config->has_audio = | |
1449 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
1450 | } | |
9ed109a7 | 1451 | |
4e53c2e0 DV |
1452 | /* |
1453 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1454 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1455 | * outputs. We also need to check that the higher clock still fits |
1456 | * within limits. | |
4e53c2e0 | 1457 | */ |
7a5ca19f ML |
1458 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi && |
1459 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK && | |
7a0baa62 | 1460 | hdmi_12bpc_possible(pipe_config)) { |
e29c22c0 DV |
1461 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1462 | desired_bpp = 12*3; | |
325b9d04 DV |
1463 | |
1464 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1465 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1466 | } else { |
e29c22c0 DV |
1467 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1468 | desired_bpp = 8*3; | |
e64e739e VS |
1469 | |
1470 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1471 | } |
1472 | ||
1473 | if (!pipe_config->bw_constrained) { | |
b64b7a60 | 1474 | DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp); |
e29c22c0 | 1475 | pipe_config->pipe_bpp = desired_bpp; |
4e53c2e0 DV |
1476 | } |
1477 | ||
e64e739e | 1478 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
7a5ca19f | 1479 | false, force_dvi) != MODE_OK) { |
e64e739e | 1480 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
325b9d04 DV |
1481 | return false; |
1482 | } | |
1483 | ||
28b468a0 | 1484 | /* Set user selected PAR to incoming mode's member */ |
0e9f25d0 | 1485 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
28b468a0 | 1486 | |
d4d6279a ACO |
1487 | pipe_config->lane_count = 4; |
1488 | ||
15953637 SS |
1489 | if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) { |
1490 | if (scdc->scrambling.low_rates) | |
1491 | pipe_config->hdmi_scrambling = true; | |
1492 | ||
1493 | if (pipe_config->port_clock > 340000) { | |
1494 | pipe_config->hdmi_scrambling = true; | |
1495 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
1496 | } | |
1497 | } | |
1498 | ||
7d57382e EA |
1499 | return true; |
1500 | } | |
1501 | ||
953ece69 CW |
1502 | static void |
1503 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1504 | { |
df0e9248 | 1505 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1506 | |
953ece69 CW |
1507 | intel_hdmi->has_hdmi_sink = false; |
1508 | intel_hdmi->has_audio = false; | |
1509 | intel_hdmi->rgb_quant_range_selectable = false; | |
1510 | ||
b1ba124d VS |
1511 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
1512 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
1513 | ||
953ece69 CW |
1514 | kfree(to_intel_connector(connector)->detect_edid); |
1515 | to_intel_connector(connector)->detect_edid = NULL; | |
1516 | } | |
1517 | ||
b1ba124d | 1518 | static void |
d6199256 | 1519 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
1520 | { |
1521 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1522 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
d6199256 | 1523 | enum port port = hdmi_to_dig_port(hdmi)->port; |
b1ba124d VS |
1524 | struct i2c_adapter *adapter = |
1525 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1526 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
1527 | ||
d6199256 VS |
1528 | /* |
1529 | * Type 1 DVI adaptors are not required to implement any | |
1530 | * registers, so we can't always detect their presence. | |
1531 | * Ideally we should be able to check the state of the | |
1532 | * CONFIG1 pin, but no such luck on our hardware. | |
1533 | * | |
1534 | * The only method left to us is to check the VBT to see | |
1535 | * if the port is a dual mode capable DP port. But let's | |
1536 | * only do that when we sucesfully read the EDID, to avoid | |
1537 | * confusing log messages about DP dual mode adaptors when | |
1538 | * there's nothing connected to the port. | |
1539 | */ | |
1540 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
1541 | if (has_edid && | |
1542 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { | |
1543 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
1544 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
1545 | } else { | |
1546 | type = DRM_DP_DUAL_MODE_NONE; | |
1547 | } | |
1548 | } | |
1549 | ||
1550 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
1551 | return; |
1552 | ||
1553 | hdmi->dp_dual_mode.type = type; | |
1554 | hdmi->dp_dual_mode.max_tmds_clock = | |
1555 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
1556 | ||
1557 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
1558 | drm_dp_get_dual_mode_type_name(type), | |
1559 | hdmi->dp_dual_mode.max_tmds_clock); | |
1560 | } | |
1561 | ||
953ece69 | 1562 | static bool |
23f889bd | 1563 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
1564 | { |
1565 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1566 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
23f889bd | 1567 | struct edid *edid; |
953ece69 | 1568 | bool connected = false; |
164c8598 | 1569 | |
23f889bd | 1570 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 1571 | |
23f889bd DW |
1572 | edid = drm_get_edid(connector, |
1573 | intel_gmbus_get_adapter(dev_priv, | |
1574 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1575 | |
23f889bd | 1576 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 1577 | |
23f889bd | 1578 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
30ad48b7 | 1579 | |
953ece69 CW |
1580 | to_intel_connector(connector)->detect_edid = edid; |
1581 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1582 | intel_hdmi->rgb_quant_range_selectable = | |
1583 | drm_rgb_quant_range_selectable(edid); | |
1584 | ||
1585 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
7a5ca19f | 1586 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
1587 | |
1588 | connected = true; | |
55b7d6e8 CW |
1589 | } |
1590 | ||
953ece69 CW |
1591 | return connected; |
1592 | } | |
1593 | ||
8166fcea DV |
1594 | static enum drm_connector_status |
1595 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 1596 | { |
8166fcea | 1597 | enum drm_connector_status status; |
8166fcea | 1598 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
953ece69 | 1599 | |
8166fcea DV |
1600 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1601 | connector->base.id, connector->name); | |
1602 | ||
29bb94bb ID |
1603 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1604 | ||
8166fcea | 1605 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 1606 | |
23f889bd | 1607 | if (intel_hdmi_set_edid(connector)) { |
953ece69 CW |
1608 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1609 | ||
1610 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1611 | status = connector_status_connected; | |
8166fcea | 1612 | } else |
953ece69 | 1613 | status = connector_status_disconnected; |
671dedd2 | 1614 | |
29bb94bb ID |
1615 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1616 | ||
2ded9e27 | 1617 | return status; |
7d57382e EA |
1618 | } |
1619 | ||
953ece69 CW |
1620 | static void |
1621 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1622 | { |
953ece69 | 1623 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1624 | |
953ece69 CW |
1625 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1626 | connector->base.id, connector->name); | |
7d57382e | 1627 | |
953ece69 | 1628 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1629 | |
953ece69 CW |
1630 | if (connector->status != connector_status_connected) |
1631 | return; | |
671dedd2 | 1632 | |
23f889bd | 1633 | intel_hdmi_set_edid(connector); |
953ece69 CW |
1634 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1635 | } | |
671dedd2 | 1636 | |
953ece69 CW |
1637 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1638 | { | |
1639 | struct edid *edid; | |
1640 | ||
1641 | edid = to_intel_connector(connector)->detect_edid; | |
1642 | if (edid == NULL) | |
1643 | return 0; | |
671dedd2 | 1644 | |
953ece69 | 1645 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1646 | } |
1647 | ||
fd6bbda9 ML |
1648 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
1649 | struct intel_crtc_state *pipe_config, | |
1650 | struct drm_connector_state *conn_state) | |
13732ba7 | 1651 | { |
f99be1b3 VS |
1652 | struct intel_digital_port *intel_dig_port = |
1653 | enc_to_dig_port(&encoder->base); | |
13732ba7 | 1654 | |
ac240288 | 1655 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1656 | |
f99be1b3 VS |
1657 | intel_dig_port->set_infoframes(&encoder->base, |
1658 | pipe_config->has_infoframe, | |
1659 | pipe_config, conn_state); | |
13732ba7 JB |
1660 | } |
1661 | ||
fd6bbda9 ML |
1662 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
1663 | struct intel_crtc_state *pipe_config, | |
1664 | struct drm_connector_state *conn_state) | |
89b667f8 JB |
1665 | { |
1666 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1667 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1668 | struct drm_i915_private *dev_priv = to_i915(dev); |
5f68c275 ACO |
1669 | |
1670 | vlv_phy_pre_encoder_enable(encoder); | |
b76cf76b | 1671 | |
53d98725 ACO |
1672 | /* HDMI 1.0V-2dB */ |
1673 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
1674 | 0x2b247878); | |
1675 | ||
f99be1b3 VS |
1676 | dport->set_infoframes(&encoder->base, |
1677 | pipe_config->has_infoframe, | |
1678 | pipe_config, conn_state); | |
13732ba7 | 1679 | |
fd6bbda9 | 1680 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 1681 | |
9b6de0a1 | 1682 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1683 | } |
1684 | ||
fd6bbda9 ML |
1685 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
1686 | struct intel_crtc_state *pipe_config, | |
1687 | struct drm_connector_state *conn_state) | |
89b667f8 | 1688 | { |
ac240288 | 1689 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1690 | |
6da2e616 | 1691 | vlv_phy_pre_pll_enable(encoder); |
89b667f8 JB |
1692 | } |
1693 | ||
fd6bbda9 ML |
1694 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
1695 | struct intel_crtc_state *pipe_config, | |
1696 | struct drm_connector_state *conn_state) | |
9197c88b | 1697 | { |
ac240288 | 1698 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 1699 | |
419b1b7a | 1700 | chv_phy_pre_pll_enable(encoder); |
9197c88b VS |
1701 | } |
1702 | ||
fd6bbda9 ML |
1703 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
1704 | struct intel_crtc_state *old_crtc_state, | |
1705 | struct drm_connector_state *old_conn_state) | |
d6db995f | 1706 | { |
204970b5 | 1707 | chv_phy_post_pll_disable(encoder); |
d6db995f VS |
1708 | } |
1709 | ||
fd6bbda9 ML |
1710 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
1711 | struct intel_crtc_state *old_crtc_state, | |
1712 | struct drm_connector_state *old_conn_state) | |
89b667f8 | 1713 | { |
89b667f8 | 1714 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
0f572ebe | 1715 | vlv_phy_reset_lanes(encoder); |
89b667f8 JB |
1716 | } |
1717 | ||
fd6bbda9 ML |
1718 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
1719 | struct intel_crtc_state *old_crtc_state, | |
1720 | struct drm_connector_state *old_conn_state) | |
580d3811 | 1721 | { |
580d3811 | 1722 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1723 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 1724 | |
a580516d | 1725 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 1726 | |
a8f327fb VS |
1727 | /* Assert data lane reset */ |
1728 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 1729 | |
a580516d | 1730 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1731 | } |
1732 | ||
fd6bbda9 ML |
1733 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
1734 | struct intel_crtc_state *pipe_config, | |
1735 | struct drm_connector_state *conn_state) | |
e4a1d846 CML |
1736 | { |
1737 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1738 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1739 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 1740 | |
e7d2a717 | 1741 | chv_phy_pre_encoder_enable(encoder); |
a02ef3c7 | 1742 | |
e4a1d846 CML |
1743 | /* FIXME: Program the support xxx V-dB */ |
1744 | /* Use 800mV-0dB */ | |
b7fa22d8 | 1745 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 1746 | |
f99be1b3 VS |
1747 | dport->set_infoframes(&encoder->base, |
1748 | pipe_config->has_infoframe, | |
1749 | pipe_config, conn_state); | |
b4eb1564 | 1750 | |
fd6bbda9 | 1751 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 1752 | |
9b6de0a1 | 1753 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
1754 | |
1755 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 1756 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
1757 | } |
1758 | ||
7d57382e EA |
1759 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1760 | { | |
10e972d3 | 1761 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1762 | drm_connector_cleanup(connector); |
674e2d08 | 1763 | kfree(connector); |
7d57382e EA |
1764 | } |
1765 | ||
7d57382e | 1766 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
7d57382e | 1767 | .detect = intel_hdmi_detect, |
953ece69 | 1768 | .force = intel_hdmi_force, |
7d57382e | 1769 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
1770 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
1771 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
1ebaa0b9 | 1772 | .late_register = intel_connector_register, |
c191eca1 | 1773 | .early_unregister = intel_connector_unregister, |
7d57382e | 1774 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 1775 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 1776 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
1777 | }; |
1778 | ||
1779 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1780 | .get_modes = intel_hdmi_get_modes, | |
1781 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 1782 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
1783 | }; |
1784 | ||
7d57382e | 1785 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1786 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1787 | }; |
1788 | ||
55b7d6e8 CW |
1789 | static void |
1790 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1791 | { | |
3f43c48d | 1792 | intel_attach_force_audio_property(connector); |
e953fd7b | 1793 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 1794 | intel_attach_aspect_ratio_property(connector); |
0e9f25d0 | 1795 | connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
55b7d6e8 CW |
1796 | } |
1797 | ||
15953637 SS |
1798 | /* |
1799 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
1800 | * @encoder: intel_encoder | |
1801 | * @connector: drm_connector | |
1802 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
1803 | * or reset the high tmds clock ratio for scrambling | |
1804 | * @scrambling: bool to Indicate if the function needs to set or reset | |
1805 | * sink scrambling | |
1806 | * | |
1807 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
1808 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
1809 | * it enables scrambling. This should be called before enabling the HDMI | |
1810 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
1811 | * detect a scrambled clock within 100 ms. | |
1812 | */ | |
1813 | void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, | |
1814 | struct drm_connector *connector, | |
1815 | bool high_tmds_clock_ratio, | |
1816 | bool scrambling) | |
1817 | { | |
1818 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1819 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
1820 | struct drm_scrambling *sink_scrambling = | |
1821 | &connector->display_info.hdmi.scdc.scrambling; | |
1822 | struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv, | |
1823 | intel_hdmi->ddc_bus); | |
1824 | bool ret; | |
1825 | ||
1826 | if (!sink_scrambling->supported) | |
1827 | return; | |
1828 | ||
1829 | DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n", | |
1830 | encoder->base.name, connector->name); | |
1831 | ||
1832 | /* Set TMDS bit clock ratio to 1/40 or 1/10 */ | |
1833 | ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio); | |
1834 | if (!ret) { | |
1835 | DRM_ERROR("Set TMDS ratio failed\n"); | |
1836 | return; | |
1837 | } | |
1838 | ||
1839 | /* Enable/disable sink scrambling */ | |
1840 | ret = drm_scdc_set_scrambling(adptr, scrambling); | |
1841 | if (!ret) { | |
1842 | DRM_ERROR("Set sink scrambling failed\n"); | |
1843 | return; | |
1844 | } | |
1845 | ||
1846 | DRM_DEBUG_KMS("sink scrambling handled\n"); | |
1847 | } | |
1848 | ||
cec3bb01 | 1849 | static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
e4ab73a1 | 1850 | { |
e4ab73a1 VS |
1851 | u8 ddc_pin; |
1852 | ||
cec3bb01 AS |
1853 | switch (port) { |
1854 | case PORT_B: | |
1855 | ddc_pin = GMBUS_PIN_DPB; | |
1856 | break; | |
1857 | case PORT_C: | |
1858 | ddc_pin = GMBUS_PIN_DPC; | |
1859 | break; | |
1860 | case PORT_D: | |
1861 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
1862 | break; | |
1863 | default: | |
1864 | MISSING_CASE(port); | |
1865 | ddc_pin = GMBUS_PIN_DPB; | |
1866 | break; | |
e4ab73a1 | 1867 | } |
cec3bb01 AS |
1868 | return ddc_pin; |
1869 | } | |
1870 | ||
1871 | static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) | |
1872 | { | |
1873 | u8 ddc_pin; | |
e4ab73a1 VS |
1874 | |
1875 | switch (port) { | |
1876 | case PORT_B: | |
cec3bb01 | 1877 | ddc_pin = GMBUS_PIN_1_BXT; |
e4ab73a1 VS |
1878 | break; |
1879 | case PORT_C: | |
cec3bb01 AS |
1880 | ddc_pin = GMBUS_PIN_2_BXT; |
1881 | break; | |
1882 | default: | |
1883 | MISSING_CASE(port); | |
1884 | ddc_pin = GMBUS_PIN_1_BXT; | |
1885 | break; | |
1886 | } | |
1887 | return ddc_pin; | |
1888 | } | |
1889 | ||
1890 | static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
1891 | enum port port) | |
1892 | { | |
1893 | u8 ddc_pin; | |
1894 | ||
1895 | switch (port) { | |
1896 | case PORT_B: | |
1897 | ddc_pin = GMBUS_PIN_1_BXT; | |
1898 | break; | |
1899 | case PORT_C: | |
1900 | ddc_pin = GMBUS_PIN_2_BXT; | |
e4ab73a1 VS |
1901 | break; |
1902 | case PORT_D: | |
cec3bb01 AS |
1903 | ddc_pin = GMBUS_PIN_4_CNP; |
1904 | break; | |
1905 | default: | |
1906 | MISSING_CASE(port); | |
1907 | ddc_pin = GMBUS_PIN_1_BXT; | |
1908 | break; | |
1909 | } | |
1910 | return ddc_pin; | |
1911 | } | |
1912 | ||
1913 | static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
1914 | enum port port) | |
1915 | { | |
1916 | u8 ddc_pin; | |
1917 | ||
1918 | switch (port) { | |
1919 | case PORT_B: | |
1920 | ddc_pin = GMBUS_PIN_DPB; | |
1921 | break; | |
1922 | case PORT_C: | |
1923 | ddc_pin = GMBUS_PIN_DPC; | |
1924 | break; | |
1925 | case PORT_D: | |
1926 | ddc_pin = GMBUS_PIN_DPD; | |
e4ab73a1 VS |
1927 | break; |
1928 | default: | |
1929 | MISSING_CASE(port); | |
1930 | ddc_pin = GMBUS_PIN_DPB; | |
1931 | break; | |
1932 | } | |
cec3bb01 AS |
1933 | return ddc_pin; |
1934 | } | |
1935 | ||
1936 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, | |
1937 | enum port port) | |
1938 | { | |
1939 | const struct ddi_vbt_port_info *info = | |
1940 | &dev_priv->vbt.ddi_port_info[port]; | |
1941 | u8 ddc_pin; | |
1942 | ||
1943 | if (info->alternate_ddc_pin) { | |
1944 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
1945 | info->alternate_ddc_pin, port_name(port)); | |
1946 | return info->alternate_ddc_pin; | |
1947 | } | |
1948 | ||
1949 | if (IS_CHERRYVIEW(dev_priv)) | |
1950 | ddc_pin = chv_port_to_ddc_pin(dev_priv, port); | |
1951 | else if (IS_GEN9_LP(dev_priv)) | |
1952 | ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); | |
1953 | else if (HAS_PCH_CNP(dev_priv)) | |
1954 | ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); | |
1955 | else | |
1956 | ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); | |
e4ab73a1 VS |
1957 | |
1958 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
1959 | ddc_pin, port_name(port)); | |
1960 | ||
1961 | return ddc_pin; | |
1962 | } | |
1963 | ||
00c09d70 PZ |
1964 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1965 | struct intel_connector *intel_connector) | |
7d57382e | 1966 | { |
b9cb234c PZ |
1967 | struct drm_connector *connector = &intel_connector->base; |
1968 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1969 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1970 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 1971 | struct drm_i915_private *dev_priv = to_i915(dev); |
174edf1f | 1972 | enum port port = intel_dig_port->port; |
373a3cf7 | 1973 | |
22f35042 VS |
1974 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
1975 | port_name(port)); | |
1976 | ||
ccb1a831 VS |
1977 | if (WARN(intel_dig_port->max_lanes < 4, |
1978 | "Not enough lanes (%d) for HDMI on port %c\n", | |
1979 | intel_dig_port->max_lanes, port_name(port))) | |
1980 | return; | |
1981 | ||
7d57382e | 1982 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1983 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1984 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1985 | ||
c3febcc4 | 1986 | connector->interlace_allowed = 1; |
7d57382e | 1987 | connector->doublescan_allowed = 0; |
573e74ad | 1988 | connector->stereo_allowed = 1; |
66a9278e | 1989 | |
eadc2e51 SS |
1990 | if (IS_GEMINILAKE(dev_priv)) |
1991 | connector->ycbcr_420_allowed = true; | |
1992 | ||
e4ab73a1 VS |
1993 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
1994 | ||
f761bef2 | 1995 | if (WARN_ON(port == PORT_A)) |
e4ab73a1 | 1996 | return; |
f761bef2 | 1997 | intel_encoder->hpd_pin = intel_hpd_pin(port); |
7d57382e | 1998 | |
920a14b2 | 1999 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
f99be1b3 VS |
2000 | intel_dig_port->write_infoframe = vlv_write_infoframe; |
2001 | intel_dig_port->set_infoframes = vlv_set_infoframes; | |
2002 | intel_dig_port->infoframe_enabled = vlv_infoframe_enabled; | |
9beb5fea | 2003 | } else if (IS_G4X(dev_priv)) { |
f99be1b3 VS |
2004 | intel_dig_port->write_infoframe = g4x_write_infoframe; |
2005 | intel_dig_port->set_infoframes = g4x_set_infoframes; | |
2006 | intel_dig_port->infoframe_enabled = g4x_infoframe_enabled; | |
4f8036a2 | 2007 | } else if (HAS_DDI(dev_priv)) { |
f99be1b3 VS |
2008 | intel_dig_port->write_infoframe = hsw_write_infoframe; |
2009 | intel_dig_port->set_infoframes = hsw_set_infoframes; | |
2010 | intel_dig_port->infoframe_enabled = hsw_infoframe_enabled; | |
6e266956 | 2011 | } else if (HAS_PCH_IBX(dev_priv)) { |
f99be1b3 VS |
2012 | intel_dig_port->write_infoframe = ibx_write_infoframe; |
2013 | intel_dig_port->set_infoframes = ibx_set_infoframes; | |
2014 | intel_dig_port->infoframe_enabled = ibx_infoframe_enabled; | |
fdf1250a | 2015 | } else { |
f99be1b3 VS |
2016 | intel_dig_port->write_infoframe = cpt_write_infoframe; |
2017 | intel_dig_port->set_infoframes = cpt_set_infoframes; | |
2018 | intel_dig_port->infoframe_enabled = cpt_infoframe_enabled; | |
64a8fc01 | 2019 | } |
45187ace | 2020 | |
4f8036a2 | 2021 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
2022 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2023 | else | |
2024 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
2025 | |
2026 | intel_hdmi_add_properties(intel_hdmi, connector); | |
2027 | ||
2028 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
d8b4c43a | 2029 | intel_hdmi->attached_connector = intel_connector; |
b9cb234c PZ |
2030 | |
2031 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
2032 | * 0xd. Failure to do so will result in spurious interrupts being | |
2033 | * generated on the port when a cable is not attached. | |
2034 | */ | |
50a0bc90 | 2035 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
b9cb234c PZ |
2036 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2037 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2038 | } | |
2039 | } | |
2040 | ||
c39055b0 | 2041 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 2042 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
2043 | { |
2044 | struct intel_digital_port *intel_dig_port; | |
2045 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
2046 | struct intel_connector *intel_connector; |
2047 | ||
b14c5679 | 2048 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
2049 | if (!intel_dig_port) |
2050 | return; | |
2051 | ||
08d9bc92 | 2052 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
2053 | if (!intel_connector) { |
2054 | kfree(intel_dig_port); | |
2055 | return; | |
2056 | } | |
2057 | ||
2058 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 2059 | |
c39055b0 ACO |
2060 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
2061 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
2062 | "HDMI %c", port_name(port)); | |
00c09d70 | 2063 | |
5bfe2ac0 | 2064 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 2065 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
2066 | intel_encoder->disable = pch_disable_hdmi; |
2067 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
2068 | } else { | |
2069 | intel_encoder->disable = g4x_disable_hdmi; | |
2070 | } | |
00c09d70 | 2071 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 2072 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 2073 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 2074 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
2075 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2076 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 2077 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 2078 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 2079 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
2080 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2081 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 2082 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 2083 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 2084 | } else { |
13732ba7 | 2085 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 2086 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 2087 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 2088 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 2089 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 2090 | else |
bf868c7d | 2091 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 2092 | } |
5ab432ef | 2093 | |
b9cb234c | 2094 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 2095 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 2096 | intel_encoder->port = port; |
920a14b2 | 2097 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
2098 | if (port == PORT_D) |
2099 | intel_encoder->crtc_mask = 1 << 2; | |
2100 | else | |
2101 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
2102 | } else { | |
2103 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
2104 | } | |
301ea74a | 2105 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
2106 | /* |
2107 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
2108 | * to work on real hardware. And since g4x can send infoframes to | |
2109 | * only one port anyway, nothing is lost by allowing it. | |
2110 | */ | |
9beb5fea | 2111 | if (IS_G4X(dev_priv)) |
c6f1495d | 2112 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 2113 | |
174edf1f | 2114 | intel_dig_port->port = port; |
b242b7f7 | 2115 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 2116 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 2117 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 2118 | |
b9cb234c | 2119 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2120 | } |