Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
f5bbfca3 | 40 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 41 | { |
4ef69c7a | 42 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
43 | } |
44 | ||
df0e9248 CW |
45 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
46 | { | |
47 | return container_of(intel_attached_encoder(connector), | |
48 | struct intel_hdmi, base); | |
49 | } | |
50 | ||
45187ace | 51 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 52 | { |
45187ace | 53 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
54 | uint8_t sum = 0; |
55 | unsigned i; | |
56 | ||
45187ace JB |
57 | frame->checksum = 0; |
58 | frame->ecc = 0; | |
3c17fe4b | 59 | |
64a8fc01 | 60 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
61 | sum += data[i]; |
62 | ||
45187ace | 63 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
64 | } |
65 | ||
bc2481f3 | 66 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 67 | { |
45187ace JB |
68 | switch (frame->type) { |
69 | case DIP_TYPE_AVI: | |
ed517fbb | 70 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 71 | case DIP_TYPE_SPD: |
ed517fbb | 72 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
73 | default: |
74 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 75 | return 0; |
45187ace | 76 | } |
45187ace JB |
77 | } |
78 | ||
bc2481f3 | 79 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 80 | { |
45187ace JB |
81 | switch (frame->type) { |
82 | case DIP_TYPE_AVI: | |
ed517fbb | 83 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 84 | case DIP_TYPE_SPD: |
ed517fbb | 85 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
86 | default: |
87 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 88 | return 0; |
fa193ff7 | 89 | } |
fa193ff7 PZ |
90 | } |
91 | ||
a3da1df7 DV |
92 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
93 | struct dip_infoframe *frame) | |
45187ace JB |
94 | { |
95 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
96 | struct drm_device *dev = encoder->dev; |
97 | struct drm_i915_private *dev_priv = dev->dev_private; | |
98 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
22509ec8 | 99 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 100 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 101 | |
3e6e6395 | 102 | val &= ~VIDEO_DIP_PORT_MASK; |
3c17fe4b | 103 | if (intel_hdmi->sdvox_reg == SDVOB) |
22509ec8 | 104 | val |= VIDEO_DIP_PORT_B; |
3c17fe4b | 105 | else if (intel_hdmi->sdvox_reg == SDVOC) |
22509ec8 | 106 | val |= VIDEO_DIP_PORT_C; |
3c17fe4b DH |
107 | else |
108 | return; | |
109 | ||
1d4f85ac | 110 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 111 | val |= g4x_infoframe_index(frame); |
22509ec8 | 112 | |
bc2481f3 | 113 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 114 | val |= VIDEO_DIP_ENABLE; |
45187ace | 115 | |
22509ec8 | 116 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 117 | |
45187ace | 118 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
119 | I915_WRITE(VIDEO_DIP_DATA, *data); |
120 | data++; | |
121 | } | |
122 | ||
bc2481f3 | 123 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 124 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 125 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 126 | |
22509ec8 | 127 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b DH |
128 | } |
129 | ||
fdf1250a PZ |
130 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
131 | struct dip_infoframe *frame) | |
132 | { | |
133 | uint32_t *data = (uint32_t *)frame; | |
134 | struct drm_device *dev = encoder->dev; | |
135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 136 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
4e89ee17 | 137 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
fdf1250a PZ |
138 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
139 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
140 | u32 val = I915_READ(reg); | |
141 | ||
4e89ee17 PZ |
142 | val &= ~VIDEO_DIP_PORT_MASK; |
143 | switch (intel_hdmi->sdvox_reg) { | |
144 | case HDMIB: | |
145 | val |= VIDEO_DIP_PORT_B; | |
146 | break; | |
147 | case HDMIC: | |
148 | val |= VIDEO_DIP_PORT_C; | |
149 | break; | |
150 | case HDMID: | |
151 | val |= VIDEO_DIP_PORT_D; | |
152 | break; | |
153 | default: | |
154 | return; | |
155 | } | |
156 | ||
fdf1250a PZ |
157 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
158 | ||
159 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
bc2481f3 | 160 | val |= g4x_infoframe_index(frame); |
fdf1250a | 161 | |
bc2481f3 | 162 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
163 | val |= VIDEO_DIP_ENABLE; |
164 | ||
165 | I915_WRITE(reg, val); | |
166 | ||
167 | for (i = 0; i < len; i += 4) { | |
168 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
169 | data++; | |
170 | } | |
171 | ||
bc2481f3 | 172 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 173 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 174 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
175 | |
176 | I915_WRITE(reg, val); | |
177 | } | |
178 | ||
179 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
180 | struct dip_infoframe *frame) | |
b055c8f3 | 181 | { |
45187ace | 182 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
183 | struct drm_device *dev = encoder->dev; |
184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 185 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 186 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 187 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 188 | u32 val = I915_READ(reg); |
b055c8f3 JB |
189 | |
190 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
191 | ||
64a8fc01 | 192 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 193 | val |= g4x_infoframe_index(frame); |
45187ace | 194 | |
ecb97851 PZ |
195 | /* The DIP control register spec says that we need to update the AVI |
196 | * infoframe without clearing its enable bit */ | |
197 | if (frame->type == DIP_TYPE_AVI) | |
198 | val |= VIDEO_DIP_ENABLE_AVI; | |
199 | else | |
bc2481f3 | 200 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 201 | |
22509ec8 PZ |
202 | val |= VIDEO_DIP_ENABLE; |
203 | ||
204 | I915_WRITE(reg, val); | |
45187ace JB |
205 | |
206 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
207 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
208 | data++; | |
209 | } | |
210 | ||
bc2481f3 | 211 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 212 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 213 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 214 | |
22509ec8 | 215 | I915_WRITE(reg, val); |
45187ace | 216 | } |
90b107c8 SK |
217 | |
218 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
219 | struct dip_infoframe *frame) | |
220 | { | |
221 | uint32_t *data = (uint32_t *)frame; | |
222 | struct drm_device *dev = encoder->dev; | |
223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 224 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
225 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
226 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 227 | u32 val = I915_READ(reg); |
90b107c8 SK |
228 | |
229 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
230 | ||
90b107c8 | 231 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 232 | val |= g4x_infoframe_index(frame); |
22509ec8 | 233 | |
bc2481f3 | 234 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 235 | val |= VIDEO_DIP_ENABLE; |
90b107c8 | 236 | |
22509ec8 | 237 | I915_WRITE(reg, val); |
90b107c8 SK |
238 | |
239 | for (i = 0; i < len; i += 4) { | |
240 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
241 | data++; | |
242 | } | |
243 | ||
bc2481f3 | 244 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 245 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 246 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 247 | |
22509ec8 | 248 | I915_WRITE(reg, val); |
90b107c8 SK |
249 | } |
250 | ||
8c5f5f7c | 251 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 252 | struct dip_infoframe *frame) |
8c5f5f7c ED |
253 | { |
254 | /* Not implemented yet, so avoid doing anything at all. | |
255 | * This is the placeholder for Paulo Zanoni's infoframe writing patch | |
256 | */ | |
257 | DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n"); | |
258 | ||
259 | return; | |
260 | ||
261 | } | |
262 | ||
45187ace JB |
263 | static void intel_set_infoframe(struct drm_encoder *encoder, |
264 | struct dip_infoframe *frame) | |
265 | { | |
266 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
267 | ||
268 | if (!intel_hdmi->has_hdmi_sink) | |
269 | return; | |
270 | ||
271 | intel_dip_infoframe_csum(frame); | |
272 | intel_hdmi->write_infoframe(encoder, frame); | |
273 | } | |
274 | ||
f5bbfca3 | 275 | void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 276 | struct drm_display_mode *adjusted_mode) |
45187ace JB |
277 | { |
278 | struct dip_infoframe avi_if = { | |
279 | .type = DIP_TYPE_AVI, | |
280 | .ver = DIP_VERSION_AVI, | |
281 | .len = DIP_LEN_AVI, | |
282 | }; | |
283 | ||
c846b619 PZ |
284 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
285 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
286 | ||
45187ace | 287 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
288 | } |
289 | ||
f5bbfca3 | 290 | void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
291 | { |
292 | struct dip_infoframe spd_if; | |
293 | ||
294 | memset(&spd_if, 0, sizeof(spd_if)); | |
295 | spd_if.type = DIP_TYPE_SPD; | |
296 | spd_if.ver = DIP_VERSION_SPD; | |
297 | spd_if.len = DIP_LEN_SPD; | |
298 | strcpy(spd_if.body.spd.vn, "Intel"); | |
299 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
300 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
301 | ||
302 | intel_set_infoframe(encoder, &spd_if); | |
303 | } | |
304 | ||
7d57382e EA |
305 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
306 | struct drm_display_mode *mode, | |
307 | struct drm_display_mode *adjusted_mode) | |
308 | { | |
309 | struct drm_device *dev = encoder->dev; | |
310 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 311 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 312 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
313 | u32 sdvox; |
314 | ||
b599c0bc | 315 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
316 | if (!HAS_PCH_SPLIT(dev)) |
317 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
318 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
319 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
320 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
321 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 322 | |
020f6704 JB |
323 | if (intel_crtc->bpp > 24) |
324 | sdvox |= COLOR_FORMAT_12bpc; | |
325 | else | |
326 | sdvox |= COLOR_FORMAT_8bpc; | |
327 | ||
2e3d6006 ZW |
328 | /* Required on CPT */ |
329 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
330 | sdvox |= HDMI_MODE_SELECT; | |
331 | ||
3c17fe4b | 332 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
333 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
334 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 335 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 336 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 337 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 338 | } |
7d57382e | 339 | |
75770564 JB |
340 | if (HAS_PCH_CPT(dev)) |
341 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
342 | else if (intel_crtc->pipe == 1) | |
343 | sdvox |= SDVO_PIPE_B_SELECT; | |
7d57382e | 344 | |
ea5b213a CW |
345 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
346 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 347 | |
c846b619 | 348 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
c0864cb3 | 349 | intel_hdmi_set_spd_infoframe(encoder); |
7d57382e EA |
350 | } |
351 | ||
352 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
353 | { | |
354 | struct drm_device *dev = encoder->dev; | |
355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 356 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 357 | u32 temp; |
2deed761 WF |
358 | u32 enable_bits = SDVO_ENABLE; |
359 | ||
360 | if (intel_hdmi->has_audio) | |
361 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 362 | |
ea5b213a | 363 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
364 | |
365 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
366 | * we do this anyway which shows more stable in testing. | |
367 | */ | |
c619eed4 | 368 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
369 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
370 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
371 | } |
372 | ||
373 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 374 | temp &= ~enable_bits; |
7d57382e | 375 | } else { |
2deed761 | 376 | temp |= enable_bits; |
7d57382e | 377 | } |
d8a2d0e0 | 378 | |
ea5b213a CW |
379 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
380 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
381 | |
382 | /* HW workaround, need to write this twice for issue that may result | |
383 | * in first write getting masked. | |
384 | */ | |
c619eed4 | 385 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
386 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
387 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 388 | } |
7d57382e EA |
389 | } |
390 | ||
7d57382e EA |
391 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
392 | struct drm_display_mode *mode) | |
393 | { | |
394 | if (mode->clock > 165000) | |
395 | return MODE_CLOCK_HIGH; | |
396 | if (mode->clock < 20000) | |
5cbba41d | 397 | return MODE_CLOCK_LOW; |
7d57382e EA |
398 | |
399 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
400 | return MODE_NO_DBLESCAN; | |
401 | ||
402 | return MODE_OK; | |
403 | } | |
404 | ||
405 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
406 | struct drm_display_mode *mode, | |
407 | struct drm_display_mode *adjusted_mode) | |
408 | { | |
409 | return true; | |
410 | } | |
411 | ||
aa93d632 | 412 | static enum drm_connector_status |
930a9e28 | 413 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 414 | { |
df0e9248 | 415 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
416 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
417 | struct edid *edid; | |
aa93d632 | 418 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 419 | |
ea5b213a | 420 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 421 | intel_hdmi->has_audio = false; |
f899fc64 | 422 | edid = drm_get_edid(connector, |
3bd7d909 DK |
423 | intel_gmbus_get_adapter(dev_priv, |
424 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 425 | |
aa93d632 | 426 | if (edid) { |
be9f1c4f | 427 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 428 | status = connector_status_connected; |
b1d7e4b4 WF |
429 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
430 | intel_hdmi->has_hdmi_sink = | |
431 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 432 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 433 | } |
674e2d08 | 434 | connector->display_info.raw_edid = NULL; |
aa93d632 | 435 | kfree(edid); |
9dff6af8 | 436 | } |
30ad48b7 | 437 | |
55b7d6e8 | 438 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
439 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
440 | intel_hdmi->has_audio = | |
441 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
442 | } |
443 | ||
2ded9e27 | 444 | return status; |
7d57382e EA |
445 | } |
446 | ||
447 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
448 | { | |
df0e9248 | 449 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 450 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
451 | |
452 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
453 | * we can send audio to it. | |
454 | */ | |
455 | ||
f899fc64 | 456 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
457 | intel_gmbus_get_adapter(dev_priv, |
458 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
459 | } |
460 | ||
1aad7ac0 CW |
461 | static bool |
462 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
463 | { | |
464 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
465 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
466 | struct edid *edid; | |
467 | bool has_audio = false; | |
468 | ||
469 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
470 | intel_gmbus_get_adapter(dev_priv, |
471 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
472 | if (edid) { |
473 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
474 | has_audio = drm_detect_monitor_audio(edid); | |
475 | ||
476 | connector->display_info.raw_edid = NULL; | |
477 | kfree(edid); | |
478 | } | |
479 | ||
480 | return has_audio; | |
481 | } | |
482 | ||
55b7d6e8 CW |
483 | static int |
484 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
485 | struct drm_property *property, |
486 | uint64_t val) | |
55b7d6e8 CW |
487 | { |
488 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 489 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
490 | int ret; |
491 | ||
492 | ret = drm_connector_property_set_value(connector, property, val); | |
493 | if (ret) | |
494 | return ret; | |
495 | ||
3f43c48d | 496 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 497 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
498 | bool has_audio; |
499 | ||
500 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
501 | return 0; |
502 | ||
1aad7ac0 | 503 | intel_hdmi->force_audio = i; |
55b7d6e8 | 504 | |
b1d7e4b4 | 505 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
506 | has_audio = intel_hdmi_detect_audio(connector); |
507 | else | |
b1d7e4b4 | 508 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 509 | |
b1d7e4b4 WF |
510 | if (i == HDMI_AUDIO_OFF_DVI) |
511 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 512 | |
1aad7ac0 | 513 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
514 | goto done; |
515 | } | |
516 | ||
e953fd7b CW |
517 | if (property == dev_priv->broadcast_rgb_property) { |
518 | if (val == !!intel_hdmi->color_range) | |
519 | return 0; | |
520 | ||
521 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
522 | goto done; | |
523 | } | |
524 | ||
55b7d6e8 CW |
525 | return -EINVAL; |
526 | ||
527 | done: | |
528 | if (intel_hdmi->base.base.crtc) { | |
529 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
530 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
531 | crtc->x, crtc->y, | |
532 | crtc->fb); | |
533 | } | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
7d57382e EA |
538 | static void intel_hdmi_destroy(struct drm_connector *connector) |
539 | { | |
7d57382e EA |
540 | drm_sysfs_connector_remove(connector); |
541 | drm_connector_cleanup(connector); | |
674e2d08 | 542 | kfree(connector); |
7d57382e EA |
543 | } |
544 | ||
72662e10 ED |
545 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs_hsw = { |
546 | .dpms = intel_ddi_dpms, | |
547 | .mode_fixup = intel_hdmi_mode_fixup, | |
548 | .prepare = intel_encoder_prepare, | |
549 | .mode_set = intel_ddi_mode_set, | |
550 | .commit = intel_encoder_commit, | |
551 | }; | |
552 | ||
7d57382e EA |
553 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { |
554 | .dpms = intel_hdmi_dpms, | |
555 | .mode_fixup = intel_hdmi_mode_fixup, | |
556 | .prepare = intel_encoder_prepare, | |
557 | .mode_set = intel_hdmi_mode_set, | |
558 | .commit = intel_encoder_commit, | |
559 | }; | |
560 | ||
561 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 562 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
563 | .detect = intel_hdmi_detect, |
564 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 565 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
566 | .destroy = intel_hdmi_destroy, |
567 | }; | |
568 | ||
569 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
570 | .get_modes = intel_hdmi_get_modes, | |
571 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 572 | .best_encoder = intel_best_encoder, |
7d57382e EA |
573 | }; |
574 | ||
7d57382e | 575 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 576 | .destroy = intel_encoder_destroy, |
7d57382e EA |
577 | }; |
578 | ||
55b7d6e8 CW |
579 | static void |
580 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
581 | { | |
3f43c48d | 582 | intel_attach_force_audio_property(connector); |
e953fd7b | 583 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
584 | } |
585 | ||
7d57382e EA |
586 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
587 | { | |
588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
589 | struct drm_connector *connector; | |
21d40d37 | 590 | struct intel_encoder *intel_encoder; |
674e2d08 | 591 | struct intel_connector *intel_connector; |
ea5b213a | 592 | struct intel_hdmi *intel_hdmi; |
64a8fc01 | 593 | int i; |
7d57382e | 594 | |
ea5b213a CW |
595 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
596 | if (!intel_hdmi) | |
7d57382e | 597 | return; |
674e2d08 ZW |
598 | |
599 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
600 | if (!intel_connector) { | |
ea5b213a | 601 | kfree(intel_hdmi); |
674e2d08 ZW |
602 | return; |
603 | } | |
604 | ||
ea5b213a | 605 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
606 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
607 | DRM_MODE_ENCODER_TMDS); | |
608 | ||
674e2d08 | 609 | connector = &intel_connector->base; |
7d57382e | 610 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 611 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
612 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
613 | ||
21d40d37 | 614 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 615 | |
eb1f8e4f | 616 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 617 | connector->interlace_allowed = 1; |
7d57382e | 618 | connector->doublescan_allowed = 0; |
27f8227b | 619 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
620 | |
621 | /* Set up the DDC bus. */ | |
f8aed700 | 622 | if (sdvox_reg == SDVOB) { |
21d40d37 | 623 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 624 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 625 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 626 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 627 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 628 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 629 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 630 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 631 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 632 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 633 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 634 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 635 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 636 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 637 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 638 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 639 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 640 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 641 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
7ceae0a5 ED |
642 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) { |
643 | DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n"); | |
644 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); | |
645 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; | |
646 | intel_hdmi->ddi_port = PORT_B; | |
647 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; | |
648 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) { | |
649 | DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n"); | |
650 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); | |
651 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; | |
652 | intel_hdmi->ddi_port = PORT_C; | |
653 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; | |
654 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) { | |
655 | DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n"); | |
656 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); | |
657 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
658 | intel_hdmi->ddi_port = PORT_D; | |
659 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; | |
6e4c1677 ED |
660 | } else { |
661 | /* If we got an unknown sdvox_reg, things are pretty much broken | |
662 | * in a way that we should let the kernel know about it */ | |
663 | BUG(); | |
f8aed700 | 664 | } |
7d57382e | 665 | |
ea5b213a | 666 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 667 | |
64a8fc01 | 668 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 669 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
64a8fc01 | 670 | I915_WRITE(VIDEO_DIP_CTL, 0); |
90b107c8 SK |
671 | } else if (IS_VALLEYVIEW(dev)) { |
672 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
673 | for_each_pipe(i) | |
674 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); | |
8c5f5f7c ED |
675 | } else if (IS_HASWELL(dev)) { |
676 | /* FIXME: Haswell has a new set of DIP frame registers, but we are | |
677 | * just doing the minimal required for HDMI to work at this stage. | |
678 | */ | |
679 | intel_hdmi->write_infoframe = hsw_write_infoframe; | |
680 | for_each_pipe(i) | |
681 | I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0); | |
fdf1250a PZ |
682 | } else if (HAS_PCH_IBX(dev)) { |
683 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
684 | for_each_pipe(i) | |
685 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
686 | } else { | |
687 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
64a8fc01 JB |
688 | for_each_pipe(i) |
689 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
690 | } | |
45187ace | 691 | |
72662e10 ED |
692 | if (IS_HASWELL(dev)) |
693 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs_hsw); | |
694 | else | |
695 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); | |
7d57382e | 696 | |
55b7d6e8 CW |
697 | intel_hdmi_add_properties(intel_hdmi, connector); |
698 | ||
df0e9248 | 699 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
700 | drm_sysfs_connector_add(connector); |
701 | ||
702 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
703 | * 0xd. Failure to do so will result in spurious interrupts being | |
704 | * generated on the port when a cable is not attached. | |
705 | */ | |
706 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
707 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
708 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
709 | } | |
7d57382e | 710 | } |