Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
ea5b213a CW |
40 | struct intel_hdmi { |
41 | struct intel_encoder base; | |
7d57382e | 42 | u32 sdvox_reg; |
f899fc64 | 43 | int ddc_bus; |
e953fd7b | 44 | uint32_t color_range; |
9dff6af8 | 45 | bool has_hdmi_sink; |
2e3d6006 | 46 | bool has_audio; |
b1d7e4b4 | 47 | enum hdmi_force_audio force_audio; |
45187ace JB |
48 | void (*write_infoframe)(struct drm_encoder *encoder, |
49 | struct dip_infoframe *frame); | |
7d57382e EA |
50 | }; |
51 | ||
ea5b213a CW |
52 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
53 | { | |
4ef69c7a | 54 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
55 | } |
56 | ||
df0e9248 CW |
57 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
58 | { | |
59 | return container_of(intel_attached_encoder(connector), | |
60 | struct intel_hdmi, base); | |
61 | } | |
62 | ||
45187ace | 63 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 64 | { |
45187ace | 65 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
66 | uint8_t sum = 0; |
67 | unsigned i; | |
68 | ||
45187ace JB |
69 | frame->checksum = 0; |
70 | frame->ecc = 0; | |
3c17fe4b | 71 | |
64a8fc01 | 72 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
73 | sum += data[i]; |
74 | ||
45187ace | 75 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
76 | } |
77 | ||
45187ace | 78 | static u32 intel_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 79 | { |
45187ace JB |
80 | u32 flags = 0; |
81 | ||
82 | switch (frame->type) { | |
83 | case DIP_TYPE_AVI: | |
84 | flags |= VIDEO_DIP_SELECT_AVI; | |
85 | break; | |
86 | case DIP_TYPE_SPD: | |
87 | flags |= VIDEO_DIP_SELECT_SPD; | |
88 | break; | |
89 | default: | |
90 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
91 | break; | |
92 | } | |
93 | ||
94 | return flags; | |
95 | } | |
96 | ||
fa193ff7 | 97 | static u32 intel_infoframe_enable(struct dip_infoframe *frame) |
45187ace JB |
98 | { |
99 | u32 flags = 0; | |
100 | ||
101 | switch (frame->type) { | |
102 | case DIP_TYPE_AVI: | |
fa193ff7 | 103 | flags |= VIDEO_DIP_ENABLE_AVI; |
45187ace JB |
104 | break; |
105 | case DIP_TYPE_SPD: | |
fa193ff7 PZ |
106 | flags |= VIDEO_DIP_ENABLE_SPD; |
107 | break; | |
108 | default: | |
109 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
110 | break; | |
111 | } | |
112 | ||
113 | return flags; | |
114 | } | |
115 | ||
116 | static u32 intel_infoframe_frequency(struct dip_infoframe *frame) | |
117 | { | |
118 | u32 flags = 0; | |
119 | ||
120 | switch (frame->type) { | |
121 | case DIP_TYPE_AVI: | |
122 | case DIP_TYPE_SPD: | |
123 | flags |= VIDEO_DIP_FREQ_VSYNC; | |
45187ace JB |
124 | break; |
125 | default: | |
126 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
127 | break; | |
128 | } | |
129 | ||
130 | return flags; | |
131 | } | |
132 | ||
133 | static void i9xx_write_infoframe(struct drm_encoder *encoder, | |
134 | struct dip_infoframe *frame) | |
135 | { | |
136 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
137 | struct drm_device *dev = encoder->dev; |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
139 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
22509ec8 | 140 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 141 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 142 | |
3c17fe4b DH |
143 | |
144 | /* XXX first guess at handling video port, is this corrent? */ | |
3e6e6395 | 145 | val &= ~VIDEO_DIP_PORT_MASK; |
3c17fe4b | 146 | if (intel_hdmi->sdvox_reg == SDVOB) |
22509ec8 | 147 | val |= VIDEO_DIP_PORT_B; |
3c17fe4b | 148 | else if (intel_hdmi->sdvox_reg == SDVOC) |
22509ec8 | 149 | val |= VIDEO_DIP_PORT_C; |
3c17fe4b DH |
150 | else |
151 | return; | |
152 | ||
1d4f85ac | 153 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
22509ec8 PZ |
154 | val |= intel_infoframe_index(frame); |
155 | ||
ecb97851 | 156 | val &= ~intel_infoframe_enable(frame); |
22509ec8 | 157 | val |= VIDEO_DIP_ENABLE; |
45187ace | 158 | |
22509ec8 | 159 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 160 | |
45187ace | 161 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
162 | I915_WRITE(VIDEO_DIP_DATA, *data); |
163 | data++; | |
164 | } | |
165 | ||
fa193ff7 PZ |
166 | val |= intel_infoframe_enable(frame); |
167 | val |= intel_infoframe_frequency(frame); | |
45187ace | 168 | |
22509ec8 | 169 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b DH |
170 | } |
171 | ||
45187ace JB |
172 | static void ironlake_write_infoframe(struct drm_encoder *encoder, |
173 | struct dip_infoframe *frame) | |
b055c8f3 | 174 | { |
45187ace | 175 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
176 | struct drm_device *dev = encoder->dev; |
177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b055c8f3 JB |
178 | struct drm_crtc *crtc = encoder->crtc; |
179 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
180 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
45187ace | 181 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 182 | u32 val = I915_READ(reg); |
b055c8f3 JB |
183 | |
184 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
185 | ||
64a8fc01 | 186 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
22509ec8 | 187 | val |= intel_infoframe_index(frame); |
45187ace | 188 | |
ecb97851 PZ |
189 | /* The DIP control register spec says that we need to update the AVI |
190 | * infoframe without clearing its enable bit */ | |
191 | if (frame->type == DIP_TYPE_AVI) | |
192 | val |= VIDEO_DIP_ENABLE_AVI; | |
193 | else | |
194 | val &= ~intel_infoframe_enable(frame); | |
195 | ||
22509ec8 PZ |
196 | val |= VIDEO_DIP_ENABLE; |
197 | ||
198 | I915_WRITE(reg, val); | |
45187ace JB |
199 | |
200 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
201 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
202 | data++; | |
203 | } | |
204 | ||
fa193ff7 PZ |
205 | val |= intel_infoframe_enable(frame); |
206 | val |= intel_infoframe_frequency(frame); | |
45187ace | 207 | |
22509ec8 | 208 | I915_WRITE(reg, val); |
45187ace | 209 | } |
90b107c8 SK |
210 | |
211 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
212 | struct dip_infoframe *frame) | |
213 | { | |
214 | uint32_t *data = (uint32_t *)frame; | |
215 | struct drm_device *dev = encoder->dev; | |
216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
217 | struct drm_crtc *crtc = encoder->crtc; | |
218 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
219 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
220 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 221 | u32 val = I915_READ(reg); |
90b107c8 SK |
222 | |
223 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
224 | ||
90b107c8 | 225 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
22509ec8 PZ |
226 | val |= intel_infoframe_index(frame); |
227 | ||
ecb97851 | 228 | val &= ~intel_infoframe_enable(frame); |
22509ec8 | 229 | val |= VIDEO_DIP_ENABLE; |
90b107c8 | 230 | |
22509ec8 | 231 | I915_WRITE(reg, val); |
90b107c8 SK |
232 | |
233 | for (i = 0; i < len; i += 4) { | |
234 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
235 | data++; | |
236 | } | |
237 | ||
fa193ff7 PZ |
238 | val |= intel_infoframe_enable(frame); |
239 | val |= intel_infoframe_frequency(frame); | |
90b107c8 | 240 | |
22509ec8 | 241 | I915_WRITE(reg, val); |
90b107c8 SK |
242 | } |
243 | ||
45187ace JB |
244 | static void intel_set_infoframe(struct drm_encoder *encoder, |
245 | struct dip_infoframe *frame) | |
246 | { | |
247 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
248 | ||
249 | if (!intel_hdmi->has_hdmi_sink) | |
250 | return; | |
251 | ||
252 | intel_dip_infoframe_csum(frame); | |
253 | intel_hdmi->write_infoframe(encoder, frame); | |
254 | } | |
255 | ||
c846b619 PZ |
256 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
257 | struct drm_display_mode *adjusted_mode) | |
45187ace JB |
258 | { |
259 | struct dip_infoframe avi_if = { | |
260 | .type = DIP_TYPE_AVI, | |
261 | .ver = DIP_VERSION_AVI, | |
262 | .len = DIP_LEN_AVI, | |
263 | }; | |
264 | ||
c846b619 PZ |
265 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
266 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
267 | ||
45187ace | 268 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
269 | } |
270 | ||
c0864cb3 JB |
271 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
272 | { | |
273 | struct dip_infoframe spd_if; | |
274 | ||
275 | memset(&spd_if, 0, sizeof(spd_if)); | |
276 | spd_if.type = DIP_TYPE_SPD; | |
277 | spd_if.ver = DIP_VERSION_SPD; | |
278 | spd_if.len = DIP_LEN_SPD; | |
279 | strcpy(spd_if.body.spd.vn, "Intel"); | |
280 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
281 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
282 | ||
283 | intel_set_infoframe(encoder, &spd_if); | |
284 | } | |
285 | ||
7d57382e EA |
286 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
287 | struct drm_display_mode *mode, | |
288 | struct drm_display_mode *adjusted_mode) | |
289 | { | |
290 | struct drm_device *dev = encoder->dev; | |
291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
292 | struct drm_crtc *crtc = encoder->crtc; | |
293 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea5b213a | 294 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
295 | u32 sdvox; |
296 | ||
b599c0bc | 297 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
298 | if (!HAS_PCH_SPLIT(dev)) |
299 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
300 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
301 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
302 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
303 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 304 | |
020f6704 JB |
305 | if (intel_crtc->bpp > 24) |
306 | sdvox |= COLOR_FORMAT_12bpc; | |
307 | else | |
308 | sdvox |= COLOR_FORMAT_8bpc; | |
309 | ||
2e3d6006 ZW |
310 | /* Required on CPT */ |
311 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
312 | sdvox |= HDMI_MODE_SELECT; | |
313 | ||
3c17fe4b | 314 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
315 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
316 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 317 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 318 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 319 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 320 | } |
7d57382e | 321 | |
75770564 JB |
322 | if (HAS_PCH_CPT(dev)) |
323 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
324 | else if (intel_crtc->pipe == 1) | |
325 | sdvox |= SDVO_PIPE_B_SELECT; | |
7d57382e | 326 | |
ea5b213a CW |
327 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
328 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 329 | |
c846b619 | 330 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
c0864cb3 | 331 | intel_hdmi_set_spd_infoframe(encoder); |
7d57382e EA |
332 | } |
333 | ||
334 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
335 | { | |
336 | struct drm_device *dev = encoder->dev; | |
337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 338 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 339 | u32 temp; |
2deed761 WF |
340 | u32 enable_bits = SDVO_ENABLE; |
341 | ||
342 | if (intel_hdmi->has_audio) | |
343 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 344 | |
ea5b213a | 345 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
346 | |
347 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
348 | * we do this anyway which shows more stable in testing. | |
349 | */ | |
c619eed4 | 350 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
351 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
352 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
353 | } |
354 | ||
355 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 356 | temp &= ~enable_bits; |
7d57382e | 357 | } else { |
2deed761 | 358 | temp |= enable_bits; |
7d57382e | 359 | } |
d8a2d0e0 | 360 | |
ea5b213a CW |
361 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
362 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
363 | |
364 | /* HW workaround, need to write this twice for issue that may result | |
365 | * in first write getting masked. | |
366 | */ | |
c619eed4 | 367 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
368 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
369 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 370 | } |
7d57382e EA |
371 | } |
372 | ||
7d57382e EA |
373 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
374 | struct drm_display_mode *mode) | |
375 | { | |
376 | if (mode->clock > 165000) | |
377 | return MODE_CLOCK_HIGH; | |
378 | if (mode->clock < 20000) | |
5cbba41d | 379 | return MODE_CLOCK_LOW; |
7d57382e EA |
380 | |
381 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
382 | return MODE_NO_DBLESCAN; | |
383 | ||
384 | return MODE_OK; | |
385 | } | |
386 | ||
387 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
388 | struct drm_display_mode *mode, | |
389 | struct drm_display_mode *adjusted_mode) | |
390 | { | |
391 | return true; | |
392 | } | |
393 | ||
aa93d632 | 394 | static enum drm_connector_status |
930a9e28 | 395 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 396 | { |
df0e9248 | 397 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
398 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
399 | struct edid *edid; | |
aa93d632 | 400 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 401 | |
ea5b213a | 402 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 403 | intel_hdmi->has_audio = false; |
f899fc64 | 404 | edid = drm_get_edid(connector, |
3bd7d909 DK |
405 | intel_gmbus_get_adapter(dev_priv, |
406 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 407 | |
aa93d632 | 408 | if (edid) { |
be9f1c4f | 409 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 410 | status = connector_status_connected; |
b1d7e4b4 WF |
411 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
412 | intel_hdmi->has_hdmi_sink = | |
413 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 414 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 415 | } |
674e2d08 | 416 | connector->display_info.raw_edid = NULL; |
aa93d632 | 417 | kfree(edid); |
9dff6af8 | 418 | } |
30ad48b7 | 419 | |
55b7d6e8 | 420 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
421 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
422 | intel_hdmi->has_audio = | |
423 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
424 | } |
425 | ||
2ded9e27 | 426 | return status; |
7d57382e EA |
427 | } |
428 | ||
429 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
430 | { | |
df0e9248 | 431 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 432 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
433 | |
434 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
435 | * we can send audio to it. | |
436 | */ | |
437 | ||
f899fc64 | 438 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
439 | intel_gmbus_get_adapter(dev_priv, |
440 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
441 | } |
442 | ||
1aad7ac0 CW |
443 | static bool |
444 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
445 | { | |
446 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
447 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
448 | struct edid *edid; | |
449 | bool has_audio = false; | |
450 | ||
451 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
452 | intel_gmbus_get_adapter(dev_priv, |
453 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
454 | if (edid) { |
455 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
456 | has_audio = drm_detect_monitor_audio(edid); | |
457 | ||
458 | connector->display_info.raw_edid = NULL; | |
459 | kfree(edid); | |
460 | } | |
461 | ||
462 | return has_audio; | |
463 | } | |
464 | ||
55b7d6e8 CW |
465 | static int |
466 | intel_hdmi_set_property(struct drm_connector *connector, | |
467 | struct drm_property *property, | |
468 | uint64_t val) | |
469 | { | |
470 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 471 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
472 | int ret; |
473 | ||
474 | ret = drm_connector_property_set_value(connector, property, val); | |
475 | if (ret) | |
476 | return ret; | |
477 | ||
3f43c48d | 478 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 479 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
480 | bool has_audio; |
481 | ||
482 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
483 | return 0; |
484 | ||
1aad7ac0 | 485 | intel_hdmi->force_audio = i; |
55b7d6e8 | 486 | |
b1d7e4b4 | 487 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
488 | has_audio = intel_hdmi_detect_audio(connector); |
489 | else | |
b1d7e4b4 | 490 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 491 | |
b1d7e4b4 WF |
492 | if (i == HDMI_AUDIO_OFF_DVI) |
493 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 494 | |
1aad7ac0 | 495 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
496 | goto done; |
497 | } | |
498 | ||
e953fd7b CW |
499 | if (property == dev_priv->broadcast_rgb_property) { |
500 | if (val == !!intel_hdmi->color_range) | |
501 | return 0; | |
502 | ||
503 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
504 | goto done; | |
505 | } | |
506 | ||
55b7d6e8 CW |
507 | return -EINVAL; |
508 | ||
509 | done: | |
510 | if (intel_hdmi->base.base.crtc) { | |
511 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
512 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
513 | crtc->x, crtc->y, | |
514 | crtc->fb); | |
515 | } | |
516 | ||
517 | return 0; | |
518 | } | |
519 | ||
7d57382e EA |
520 | static void intel_hdmi_destroy(struct drm_connector *connector) |
521 | { | |
7d57382e EA |
522 | drm_sysfs_connector_remove(connector); |
523 | drm_connector_cleanup(connector); | |
674e2d08 | 524 | kfree(connector); |
7d57382e EA |
525 | } |
526 | ||
527 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
528 | .dpms = intel_hdmi_dpms, | |
529 | .mode_fixup = intel_hdmi_mode_fixup, | |
530 | .prepare = intel_encoder_prepare, | |
531 | .mode_set = intel_hdmi_mode_set, | |
532 | .commit = intel_encoder_commit, | |
533 | }; | |
534 | ||
535 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 536 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
537 | .detect = intel_hdmi_detect, |
538 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 539 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
540 | .destroy = intel_hdmi_destroy, |
541 | }; | |
542 | ||
543 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
544 | .get_modes = intel_hdmi_get_modes, | |
545 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 546 | .best_encoder = intel_best_encoder, |
7d57382e EA |
547 | }; |
548 | ||
7d57382e | 549 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 550 | .destroy = intel_encoder_destroy, |
7d57382e EA |
551 | }; |
552 | ||
55b7d6e8 CW |
553 | static void |
554 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
555 | { | |
3f43c48d | 556 | intel_attach_force_audio_property(connector); |
e953fd7b | 557 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
558 | } |
559 | ||
7d57382e EA |
560 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
561 | { | |
562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
563 | struct drm_connector *connector; | |
21d40d37 | 564 | struct intel_encoder *intel_encoder; |
674e2d08 | 565 | struct intel_connector *intel_connector; |
ea5b213a | 566 | struct intel_hdmi *intel_hdmi; |
64a8fc01 | 567 | int i; |
7d57382e | 568 | |
ea5b213a CW |
569 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
570 | if (!intel_hdmi) | |
7d57382e | 571 | return; |
674e2d08 ZW |
572 | |
573 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
574 | if (!intel_connector) { | |
ea5b213a | 575 | kfree(intel_hdmi); |
674e2d08 ZW |
576 | return; |
577 | } | |
578 | ||
ea5b213a | 579 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
580 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
581 | DRM_MODE_ENCODER_TMDS); | |
582 | ||
674e2d08 | 583 | connector = &intel_connector->base; |
7d57382e | 584 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 585 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
586 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
587 | ||
21d40d37 | 588 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 589 | |
eb1f8e4f | 590 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 591 | connector->interlace_allowed = 1; |
7d57382e | 592 | connector->doublescan_allowed = 0; |
27f8227b | 593 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
594 | |
595 | /* Set up the DDC bus. */ | |
f8aed700 | 596 | if (sdvox_reg == SDVOB) { |
21d40d37 | 597 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 598 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 599 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 600 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 601 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 602 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 603 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 604 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 605 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 606 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 607 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 608 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 609 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 610 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 611 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 612 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 613 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 614 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 615 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
f8aed700 | 616 | } |
7d57382e | 617 | |
ea5b213a | 618 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 619 | |
64a8fc01 | 620 | if (!HAS_PCH_SPLIT(dev)) { |
45187ace | 621 | intel_hdmi->write_infoframe = i9xx_write_infoframe; |
64a8fc01 | 622 | I915_WRITE(VIDEO_DIP_CTL, 0); |
90b107c8 SK |
623 | } else if (IS_VALLEYVIEW(dev)) { |
624 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
625 | for_each_pipe(i) | |
626 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); | |
627 | } else { | |
45187ace | 628 | intel_hdmi->write_infoframe = ironlake_write_infoframe; |
64a8fc01 JB |
629 | for_each_pipe(i) |
630 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
631 | } | |
45187ace | 632 | |
4ef69c7a | 633 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
7d57382e | 634 | |
55b7d6e8 CW |
635 | intel_hdmi_add_properties(intel_hdmi, connector); |
636 | ||
df0e9248 | 637 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
638 | drm_sysfs_connector_add(connector); |
639 | ||
640 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
641 | * 0xd. Failure to do so will result in spurious interrupts being | |
642 | * generated on the port when a cable is not attached. | |
643 | */ | |
644 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
645 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
646 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
647 | } | |
7d57382e | 648 | } |