[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_hdmi.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_edid.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

struct intel_hdmi {
	struct intel_encoder base;
	u32 sdvox_reg;
	int ddc_bus;
	uint32_t color_range;
	bool has_hdmi_sink;
	bool has_audio;
	int force_audio;
	void (*write_infoframe)(struct drm_encoder *encoder,
				struct dip_infoframe *frame);
};

static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_hdmi, base.base);
}

static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_hdmi, base);
}

void intel_dip_infoframe_csum(struct dip_infoframe *frame)
{
	uint8_t *data = (uint8_t *)frame;
	uint8_t sum = 0;
	unsigned i;

	frame->checksum = 0;
	frame->ecc = 0;

	/* Header isn't part of the checksum */
	for (i = 5; i < frame->len; i++)
		sum += data[i];

	frame->checksum = 0x100 - sum;
}

static u32 intel_infoframe_index(struct dip_infoframe *frame)
{
	u32 flags = 0;

	switch (frame->type) {
	case DIP_TYPE_AVI:
		flags |= VIDEO_DIP_SELECT_AVI;
		break;
	case DIP_TYPE_SPD:
		flags |= VIDEO_DIP_SELECT_SPD;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		break;
	}

	return flags;
}

static u32 intel_infoframe_flags(struct dip_infoframe *frame)
{
	u32 flags = 0;

	switch (frame->type) {
	case DIP_TYPE_AVI:
		flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
		break;
	case DIP_TYPE_SPD:
		flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_2VSYNC;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		break;
	}

	return flags;
}

static void i9xx_write_infoframe(struct drm_encoder *encoder,
				 struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;


	/* XXX first guess at handling video port, is this corrent? */
	if (intel_hdmi->sdvox_reg == SDVOB)
		port = VIDEO_DIP_PORT_B;
	else if (intel_hdmi->sdvox_reg == SDVOC)
		port = VIDEO_DIP_PORT_C;
	else
		return;

	flags = intel_infoframe_index(frame);

	val &= ~VIDEO_DIP_SELECT_MASK;

	I915_WRITE(VIDEO_DIP_CTL, val | port | flags);

	for (i = 0; i < len; i += 4) {
		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}

	flags |= intel_infoframe_flags(frame);

	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
}

static void ironlake_write_infoframe(struct drm_encoder *encoder,
				     struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
	u32 flags, val = I915_READ(reg);

	intel_wait_for_vblank(dev, intel_crtc->pipe);

	flags = intel_infoframe_index(frame);

	val &= ~VIDEO_DIP_SELECT_MASK;

	I915_WRITE(reg, val | flags);

	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}

	flags |= intel_infoframe_flags(frame);

	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
}
static void intel_set_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	if (!intel_hdmi->has_hdmi_sink)
		return;

	intel_dip_infoframe_csum(frame);
	intel_hdmi->write_infoframe(encoder, frame);
}

static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
{
	struct dip_infoframe avi_if = {
		.type = DIP_TYPE_AVI,
		.ver = DIP_VERSION_AVI,
		.len = DIP_LEN_AVI,
	};

	intel_set_infoframe(encoder, &avi_if);
}

static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
{
	struct dip_infoframe spd_if;

	memset(&spd_if, 0, sizeof(spd_if));
	spd_if.type = DIP_TYPE_SPD;
	spd_if.ver = DIP_VERSION_SPD;
	spd_if.len = DIP_LEN_SPD;
	strcpy(spd_if.body.spd.vn, "Intel");
	strcpy(spd_if.body.spd.pd, "Integrated gfx");
	spd_if.body.spd.sdi = DIP_SPD_PC;

	intel_set_infoframe(encoder, &spd_if);
}

static void intel_hdmi_mode_set(struct drm_encoder *encoder,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 sdvox;

	sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
	if (!HAS_PCH_SPLIT(dev))
		sdvox |= intel_hdmi->color_range;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		sdvox |= SDVO_HSYNC_ACTIVE_HIGH;

	if (intel_crtc->bpp > 24)
		sdvox |= COLOR_FORMAT_12bpc;
	else
		sdvox |= COLOR_FORMAT_8bpc;

	/* Required on CPT */
	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
		sdvox |= HDMI_MODE_SELECT;

	if (intel_hdmi->has_audio) {
		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
		sdvox |= SDVO_AUDIO_ENABLE;
		sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
		intel_write_eld(encoder, adjusted_mode);
	}

	if (intel_crtc->pipe == 1) {
		if (HAS_PCH_CPT(dev))
			sdvox |= PORT_TRANS_B_SEL_CPT;
		else
			sdvox |= SDVO_PIPE_B_SELECT;
	}

	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
	POSTING_READ(intel_hdmi->sdvox_reg);

	intel_hdmi_set_avi_infoframe(encoder);
	intel_hdmi_set_spd_infoframe(encoder);
}

static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 temp;

	temp = I915_READ(intel_hdmi->sdvox_reg);

	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}

	if (mode != DRM_MODE_DPMS_ON) {
		temp &= ~SDVO_ENABLE;
	} else {
		temp |= SDVO_ENABLE;
	}

	I915_WRITE(intel_hdmi->sdvox_reg, temp);
	POSTING_READ(intel_hdmi->sdvox_reg);

	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}
}

static int intel_hdmi_mode_valid(struct drm_connector *connector,
				 struct drm_display_mode *mode)
{
	if (mode->clock > 165000)
		return MODE_CLOCK_HIGH;
	if (mode->clock < 20000)
		return MODE_CLOCK_LOW;

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	return MODE_OK;
}

static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
				  struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	return true;
}

static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	enum drm_connector_status status = connector_status_disconnected;

	intel_hdmi->has_hdmi_sink = false;
	intel_hdmi->has_audio = false;
	edid = drm_get_edid(connector,
			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);

	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
			status = connector_status_connected;
			intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
		}
		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	if (status == connector_status_connected) {
		if (intel_hdmi->force_audio)
			intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
	}

	return status;
}

static int intel_hdmi_get_modes(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	/* We should parse the EDID data and find out if it's an HDMI sink so
	 * we can send audio to it.
	 */

	return intel_ddc_get_modes(connector,
				   &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
}

static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	bool has_audio = false;

	edid = drm_get_edid(connector,
			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL)
			has_audio = drm_detect_monitor_audio(edid);

		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	return has_audio;
}

static int
intel_hdmi_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	int ret;

	ret = drm_connector_property_set_value(connector, property, val);
	if (ret)
		return ret;

	if (property == dev_priv->force_audio_property) {
		int i = val;
		bool has_audio;

		if (i == intel_hdmi->force_audio)
			return 0;

		intel_hdmi->force_audio = i;

		if (i == 0)
			has_audio = intel_hdmi_detect_audio(connector);
		else
			has_audio = i > 0;

		if (has_audio == intel_hdmi->has_audio)
			return 0;

		intel_hdmi->has_audio = has_audio;
		goto done;
	}

	if (property == dev_priv->broadcast_rgb_property) {
		if (val == !!intel_hdmi->color_range)
			return 0;

		intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
		goto done;
	}

	return -EINVAL;

done:
	if (intel_hdmi->base.base.crtc) {
		struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
		drm_crtc_helper_set_mode(crtc, &crtc->mode,
					 crtc->x, crtc->y,
					 crtc->fb);
	}

	return 0;
}

static void intel_hdmi_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	.dpms = intel_hdmi_dpms,
	.mode_fixup = intel_hdmi_mode_fixup,
	.prepare = intel_encoder_prepare,
	.mode_set = intel_hdmi_mode_set,
	.commit = intel_encoder_commit,
};

static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = intel_hdmi_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.set_property = intel_hdmi_set_property,
	.destroy = intel_hdmi_destroy,
};

static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
	.best_encoder = intel_best_encoder,
};

static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
	.destroy = intel_encoder_destroy,
};

static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
	intel_attach_force_audio_property(connector);
	intel_attach_broadcast_rgb_property(connector);
}

void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
	struct intel_encoder *intel_encoder;
	struct intel_connector *intel_connector;
	struct intel_hdmi *intel_hdmi;

	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
	if (!intel_hdmi)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_hdmi);
		return;
	}

	intel_encoder = &intel_hdmi->base;
	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

	connector = &intel_connector->base;
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
			   DRM_MODE_CONNECTOR_HDMIA);
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

	intel_encoder->type = INTEL_OUTPUT_HDMI;

	connector->polled = DRM_CONNECTOR_POLL_HPD;
	connector->interlace_allowed = 0;
	connector->doublescan_allowed = 0;
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);

	/* Set up the DDC bus. */
	if (sdvox_reg == SDVOB) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == SDVOC) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMIB) {
		intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMIC) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMID) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
	}

	intel_hdmi->sdvox_reg = sdvox_reg;

	if (!HAS_PCH_SPLIT(dev))
		intel_hdmi->write_infoframe = i9xx_write_infoframe;
	else
		intel_hdmi->write_infoframe = ironlake_write_infoframe;

	drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);

	intel_hdmi_add_properties(intel_hdmi, connector);

	intel_connector_attach_encoder(intel_connector, intel_encoder);
	drm_sysfs_connector_add(connector);

	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}
Commit	Line	Data
7d57382e EA	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2009 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	* Jesse Barnes <jesse.barnes@intel.com>
	27	*/
	28
	29	#include <linux/i2c.h>
5a0e3ad6	30	#include <linux/slab.h>
7d57382e EA	31	#include <linux/delay.h>
	32	#include "drmP.h"
	33	#include "drm.h"
	34	#include "drm_crtc.h"
aa93d632	35	#include "drm_edid.h"
7d57382e EA	36	#include "intel_drv.h"
	37	#include "i915_drm.h"
	38	#include "i915_drv.h"
	39
ea5b213a CW	40	struct intel_hdmi {
ea5b213a CW	41	struct intel_encoder base;
7d57382e	42	u32 sdvox_reg;
f899fc64	43	int ddc_bus;
e953fd7b	44	uint32_t color_range;
9dff6af8	45	bool has_hdmi_sink;
2e3d6006	46	bool has_audio;
55b7d6e8	47	int force_audio;
45187ace JB	48	void (write_infoframe)(struct drm_encoder encoder,
45187ace JB	49	struct dip_infoframe *frame);
7d57382e EA	50	};
7d57382e EA	51
ea5b213a CW	52	static struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)
ea5b213a CW	53	{
4ef69c7a	54	return container_of(encoder, struct intel_hdmi, base.base);
ea5b213a CW	55	}
ea5b213a CW	56
df0e9248 CW	57	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)
	58	{
	59	return container_of(intel_attached_encoder(connector),
	60	struct intel_hdmi, base);
	61	}
	62
45187ace	63	void intel_dip_infoframe_csum(struct dip_infoframe *frame)
3c17fe4b	64	{
45187ace	65	uint8_t data = (uint8_t )frame;
3c17fe4b DH	66	uint8_t sum = 0;
	67	unsigned i;
	68
45187ace JB	69	frame->checksum = 0;
45187ace JB	70	frame->ecc = 0;
3c17fe4b	71
45187ace JB	72	/* Header isn't part of the checksum */
45187ace JB	73	for (i = 5; i < frame->len; i++)
3c17fe4b DH	74	sum += data[i];
3c17fe4b DH	75
45187ace	76	frame->checksum = 0x100 - sum;
3c17fe4b DH	77	}
3c17fe4b DH	78
45187ace	79	static u32 intel_infoframe_index(struct dip_infoframe *frame)
3c17fe4b	80	{
45187ace JB	81	u32 flags = 0;
	82
	83	switch (frame->type) {
	84	case DIP_TYPE_AVI:
	85	flags \|= VIDEO_DIP_SELECT_AVI;
	86	break;
	87	case DIP_TYPE_SPD:
	88	flags \|= VIDEO_DIP_SELECT_SPD;
	89	break;
	90	default:
	91	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
	92	break;
	93	}
	94
	95	return flags;
	96	}
	97
	98	static u32 intel_infoframe_flags(struct dip_infoframe *frame)
	99	{
	100	u32 flags = 0;
	101
	102	switch (frame->type) {
	103	case DIP_TYPE_AVI:
	104	flags \|= VIDEO_DIP_ENABLE_AVI \| VIDEO_DIP_FREQ_VSYNC;
	105	break;
	106	case DIP_TYPE_SPD:
	107	flags \|= VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_FREQ_2VSYNC;
	108	break;
	109	default:
	110	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
	111	break;
	112	}
	113
	114	return flags;
	115	}
	116
	117	static void i9xx_write_infoframe(struct drm_encoder *encoder,
	118	struct dip_infoframe *frame)
	119	{
	120	uint32_t data = (uint32_t )frame;
3c17fe4b DH	121	struct drm_device *dev = encoder->dev;
	122	struct drm_i915_private *dev_priv = dev->dev_private;
	123	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
45187ace JB	124	u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
45187ace JB	125	unsigned i, len = DIP_HEADER_SIZE + frame->len;
3c17fe4b	126
3c17fe4b DH	127
	128	/* XXX first guess at handling video port, is this corrent? */
	129	if (intel_hdmi->sdvox_reg == SDVOB)
	130	port = VIDEO_DIP_PORT_B;
	131	else if (intel_hdmi->sdvox_reg == SDVOC)
	132	port = VIDEO_DIP_PORT_C;
	133	else
	134	return;
	135
45187ace JB	136	flags = intel_infoframe_index(frame);
	137
	138	val &= ~VIDEO_DIP_SELECT_MASK;
	139
	140	I915_WRITE(VIDEO_DIP_CTL, val \| port \| flags);
3c17fe4b	141
45187ace	142	for (i = 0; i < len; i += 4) {
3c17fe4b DH	143	I915_WRITE(VIDEO_DIP_DATA, *data);
	144	data++;
	145	}
	146
45187ace JB	147	flags \|= intel_infoframe_flags(frame);
	148
	149	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE \| val \| port \| flags);
3c17fe4b DH	150	}
3c17fe4b DH	151
45187ace JB	152	static void ironlake_write_infoframe(struct drm_encoder *encoder,
45187ace JB	153	struct dip_infoframe *frame)
b055c8f3	154	{
45187ace	155	uint32_t data = (uint32_t )frame;
b055c8f3 JB	156	struct drm_device *dev = encoder->dev;
b055c8f3 JB	157	struct drm_i915_private *dev_priv = dev->dev_private;
b055c8f3 JB	158	struct drm_crtc *crtc = encoder->crtc;
	159	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	160	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
45187ace JB	161	unsigned i, len = DIP_HEADER_SIZE + frame->len;
45187ace JB	162	u32 flags, val = I915_READ(reg);
b055c8f3 JB	163
	164	intel_wait_for_vblank(dev, intel_crtc->pipe);
	165
45187ace	166	flags = intel_infoframe_index(frame);
b055c8f3	167
45187ace JB	168	val &= ~VIDEO_DIP_SELECT_MASK;
	169
	170	I915_WRITE(reg, val \| flags);
	171
	172	for (i = 0; i < len; i += 4) {
b055c8f3 JB	173	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
	174	data++;
	175	}
	176
45187ace JB	177	flags \|= intel_infoframe_flags(frame);
	178
	179	I915_WRITE(reg, VIDEO_DIP_ENABLE \| val \| flags);
	180	}
	181	static void intel_set_infoframe(struct drm_encoder *encoder,
	182	struct dip_infoframe *frame)
	183	{
	184	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	185
	186	if (!intel_hdmi->has_hdmi_sink)
	187	return;
	188
	189	intel_dip_infoframe_csum(frame);
	190	intel_hdmi->write_infoframe(encoder, frame);
	191	}
	192
	193	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
	194	{
	195	struct dip_infoframe avi_if = {
	196	.type = DIP_TYPE_AVI,
	197	.ver = DIP_VERSION_AVI,
	198	.len = DIP_LEN_AVI,
	199	};
	200
	201	intel_set_infoframe(encoder, &avi_if);
b055c8f3 JB	202	}
b055c8f3 JB	203
c0864cb3 JB	204	static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
	205	{
	206	struct dip_infoframe spd_if;
	207
	208	memset(&spd_if, 0, sizeof(spd_if));
	209	spd_if.type = DIP_TYPE_SPD;
	210	spd_if.ver = DIP_VERSION_SPD;
	211	spd_if.len = DIP_LEN_SPD;
	212	strcpy(spd_if.body.spd.vn, "Intel");
	213	strcpy(spd_if.body.spd.pd, "Integrated gfx");
	214	spd_if.body.spd.sdi = DIP_SPD_PC;
	215
	216	intel_set_infoframe(encoder, &spd_if);
	217	}
	218
7d57382e EA	219	static void intel_hdmi_mode_set(struct drm_encoder *encoder,
	220	struct drm_display_mode *mode,
	221	struct drm_display_mode *adjusted_mode)
	222	{
	223	struct drm_device *dev = encoder->dev;
	224	struct drm_i915_private *dev_priv = dev->dev_private;
	225	struct drm_crtc *crtc = encoder->crtc;
	226	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a	227	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
7d57382e EA	228	u32 sdvox;
7d57382e EA	229
b599c0bc	230	sdvox = SDVO_ENCODING_HDMI \| SDVO_BORDER_ENABLE;
5d4fac97 JB	231	if (!HAS_PCH_SPLIT(dev))
5d4fac97 JB	232	sdvox \|= intel_hdmi->color_range;
b599c0bc AJ	233	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	234	sdvox \|= SDVO_VSYNC_ACTIVE_HIGH;
	235	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	236	sdvox \|= SDVO_HSYNC_ACTIVE_HIGH;
7d57382e	237
020f6704 JB	238	if (intel_crtc->bpp > 24)
	239	sdvox \|= COLOR_FORMAT_12bpc;
	240	else
	241	sdvox \|= COLOR_FORMAT_8bpc;
	242
2e3d6006 ZW	243	/* Required on CPT */
	244	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
	245	sdvox \|= HDMI_MODE_SELECT;
	246
3c17fe4b	247	if (intel_hdmi->has_audio) {
e0dac65e WF	248	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
e0dac65e WF	249	pipe_name(intel_crtc->pipe));
7d57382e	250	sdvox \|= SDVO_AUDIO_ENABLE;
3c17fe4b	251	sdvox \|= SDVO_NULL_PACKETS_DURING_VSYNC;
e0dac65e	252	intel_write_eld(encoder, adjusted_mode);
3c17fe4b	253	}
7d57382e	254
0f229062 ZW	255	if (intel_crtc->pipe == 1) {
	256	if (HAS_PCH_CPT(dev))
	257	sdvox \|= PORT_TRANS_B_SEL_CPT;
	258	else
	259	sdvox \|= SDVO_PIPE_B_SELECT;
	260	}
7d57382e	261
ea5b213a CW	262	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
ea5b213a CW	263	POSTING_READ(intel_hdmi->sdvox_reg);
3c17fe4b	264
45187ace	265	intel_hdmi_set_avi_infoframe(encoder);
c0864cb3	266	intel_hdmi_set_spd_infoframe(encoder);
7d57382e EA	267	}
	268
	269	static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
	270	{
	271	struct drm_device *dev = encoder->dev;
	272	struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a	273	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
7d57382e EA	274	u32 temp;
7d57382e EA	275
ea5b213a	276	temp = I915_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	277
	278	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	279	* we do this anyway which shows more stable in testing.
	280	*/
c619eed4	281	if (HAS_PCH_SPLIT(dev)) {
ea5b213a CW	282	I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
ea5b213a CW	283	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	284	}
	285
	286	if (mode != DRM_MODE_DPMS_ON) {
	287	temp &= ~SDVO_ENABLE;
7d57382e	288	} else {
d8a2d0e0	289	temp \|= SDVO_ENABLE;
7d57382e	290	}
d8a2d0e0	291
ea5b213a CW	292	I915_WRITE(intel_hdmi->sdvox_reg, temp);
ea5b213a CW	293	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	294
	295	/* HW workaround, need to write this twice for issue that may result
	296	* in first write getting masked.
	297	*/
c619eed4	298	if (HAS_PCH_SPLIT(dev)) {
ea5b213a CW	299	I915_WRITE(intel_hdmi->sdvox_reg, temp);
ea5b213a CW	300	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0	301	}
7d57382e EA	302	}
7d57382e EA	303
7d57382e EA	304	static int intel_hdmi_mode_valid(struct drm_connector *connector,
	305	struct drm_display_mode *mode)
	306	{
	307	if (mode->clock > 165000)
	308	return MODE_CLOCK_HIGH;
	309	if (mode->clock < 20000)
5cbba41d	310	return MODE_CLOCK_LOW;
7d57382e EA	311
	312	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	313	return MODE_NO_DBLESCAN;
	314
	315	return MODE_OK;
	316	}
	317
	318	static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
	319	struct drm_display_mode *mode,
	320	struct drm_display_mode *adjusted_mode)
	321	{
	322	return true;
	323	}
	324
aa93d632	325	static enum drm_connector_status
930a9e28	326	intel_hdmi_detect(struct drm_connector *connector, bool force)
9dff6af8	327	{
df0e9248	328	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
f899fc64 CW	329	struct drm_i915_private *dev_priv = connector->dev->dev_private;
f899fc64 CW	330	struct edid *edid;
aa93d632	331	enum drm_connector_status status = connector_status_disconnected;
9dff6af8	332
ea5b213a	333	intel_hdmi->has_hdmi_sink = false;
2e3d6006	334	intel_hdmi->has_audio = false;
f899fc64 CW	335	edid = drm_get_edid(connector,
f899fc64 CW	336	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
2ded9e27	337
aa93d632	338	if (edid) {
be9f1c4f	339	if (edid->input & DRM_EDID_INPUT_DIGITAL) {
aa93d632	340	status = connector_status_connected;
ea5b213a	341	intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2e3d6006	342	intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
aa93d632	343	}
674e2d08	344	connector->display_info.raw_edid = NULL;
aa93d632	345	kfree(edid);
9dff6af8	346	}
30ad48b7	347
55b7d6e8 CW	348	if (status == connector_status_connected) {
	349	if (intel_hdmi->force_audio)
	350	intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
	351	}
	352
2ded9e27	353	return status;
7d57382e EA	354	}
	355
	356	static int intel_hdmi_get_modes(struct drm_connector *connector)
	357	{
df0e9248	358	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
f899fc64	359	struct drm_i915_private *dev_priv = connector->dev->dev_private;
7d57382e EA	360
	361	/* We should parse the EDID data and find out if it's an HDMI sink so
	362	* we can send audio to it.
	363	*/
	364
f899fc64 CW	365	return intel_ddc_get_modes(connector,
f899fc64 CW	366	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
7d57382e EA	367	}
7d57382e EA	368
1aad7ac0 CW	369	static bool
	370	intel_hdmi_detect_audio(struct drm_connector *connector)
	371	{
	372	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	373	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	374	struct edid *edid;
	375	bool has_audio = false;
	376
	377	edid = drm_get_edid(connector,
	378	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
	379	if (edid) {
	380	if (edid->input & DRM_EDID_INPUT_DIGITAL)
	381	has_audio = drm_detect_monitor_audio(edid);
	382
	383	connector->display_info.raw_edid = NULL;
	384	kfree(edid);
	385	}
	386
	387	return has_audio;
	388	}
	389
55b7d6e8 CW	390	static int
	391	intel_hdmi_set_property(struct drm_connector *connector,
	392	struct drm_property *property,
	393	uint64_t val)
	394	{
	395	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
e953fd7b	396	struct drm_i915_private *dev_priv = connector->dev->dev_private;
55b7d6e8 CW	397	int ret;
	398
	399	ret = drm_connector_property_set_value(connector, property, val);
	400	if (ret)
	401	return ret;
	402
3f43c48d	403	if (property == dev_priv->force_audio_property) {
1aad7ac0 CW	404	int i = val;
	405	bool has_audio;
	406
	407	if (i == intel_hdmi->force_audio)
55b7d6e8 CW	408	return 0;
55b7d6e8 CW	409
1aad7ac0	410	intel_hdmi->force_audio = i;
55b7d6e8	411
1aad7ac0 CW	412	if (i == 0)
	413	has_audio = intel_hdmi_detect_audio(connector);
	414	else
	415	has_audio = i > 0;
	416
	417	if (has_audio == intel_hdmi->has_audio)
55b7d6e8 CW	418	return 0;
55b7d6e8 CW	419
1aad7ac0	420	intel_hdmi->has_audio = has_audio;
55b7d6e8 CW	421	goto done;
	422	}
	423
e953fd7b CW	424	if (property == dev_priv->broadcast_rgb_property) {
	425	if (val == !!intel_hdmi->color_range)
	426	return 0;
	427
	428	intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
	429	goto done;
	430	}
	431
55b7d6e8 CW	432	return -EINVAL;
	433
	434	done:
	435	if (intel_hdmi->base.base.crtc) {
	436	struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
	437	drm_crtc_helper_set_mode(crtc, &crtc->mode,
	438	crtc->x, crtc->y,
	439	crtc->fb);
	440	}
	441
	442	return 0;
	443	}
	444
7d57382e EA	445	static void intel_hdmi_destroy(struct drm_connector *connector)
7d57382e EA	446	{
7d57382e EA	447	drm_sysfs_connector_remove(connector);
7d57382e EA	448	drm_connector_cleanup(connector);
674e2d08	449	kfree(connector);
7d57382e EA	450	}
	451
	452	static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	453	.dpms = intel_hdmi_dpms,
	454	.mode_fixup = intel_hdmi_mode_fixup,
	455	.prepare = intel_encoder_prepare,
	456	.mode_set = intel_hdmi_mode_set,
	457	.commit = intel_encoder_commit,
	458	};
	459
	460	static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
c9fb15f6	461	.dpms = drm_helper_connector_dpms,
7d57382e EA	462	.detect = intel_hdmi_detect,
7d57382e EA	463	.fill_modes = drm_helper_probe_single_connector_modes,
55b7d6e8	464	.set_property = intel_hdmi_set_property,
7d57382e EA	465	.destroy = intel_hdmi_destroy,
	466	};
	467
	468	static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	469	.get_modes = intel_hdmi_get_modes,
	470	.mode_valid = intel_hdmi_mode_valid,
df0e9248	471	.best_encoder = intel_best_encoder,
7d57382e EA	472	};
7d57382e EA	473
7d57382e	474	static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
ea5b213a	475	.destroy = intel_encoder_destroy,
7d57382e EA	476	};
7d57382e EA	477
55b7d6e8 CW	478	static void
	479	intel_hdmi_add_properties(struct intel_hdmi intel_hdmi, struct drm_connector connector)
	480	{
3f43c48d	481	intel_attach_force_audio_property(connector);
e953fd7b	482	intel_attach_broadcast_rgb_property(connector);
55b7d6e8 CW	483	}
55b7d6e8 CW	484
7d57382e EA	485	void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
	486	{
	487	struct drm_i915_private *dev_priv = dev->dev_private;
	488	struct drm_connector *connector;
21d40d37	489	struct intel_encoder *intel_encoder;
674e2d08	490	struct intel_connector *intel_connector;
ea5b213a	491	struct intel_hdmi *intel_hdmi;
7d57382e	492
ea5b213a CW	493	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
ea5b213a CW	494	if (!intel_hdmi)
7d57382e	495	return;
674e2d08 ZW	496
	497	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	498	if (!intel_connector) {
ea5b213a	499	kfree(intel_hdmi);
674e2d08 ZW	500	return;
	501	}
	502
ea5b213a	503	intel_encoder = &intel_hdmi->base;
373a3cf7 CW	504	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
	505	DRM_MODE_ENCODER_TMDS);
	506
674e2d08	507	connector = &intel_connector->base;
7d57382e	508	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
8d91104a	509	DRM_MODE_CONNECTOR_HDMIA);
7d57382e EA	510	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
7d57382e EA	511
21d40d37	512	intel_encoder->type = INTEL_OUTPUT_HDMI;
7d57382e	513
eb1f8e4f	514	connector->polled = DRM_CONNECTOR_POLL_HPD;
7d57382e EA	515	connector->interlace_allowed = 0;
7d57382e EA	516	connector->doublescan_allowed = 0;
27f8227b	517	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
7d57382e EA	518
7d57382e EA	519	/* Set up the DDC bus. */
f8aed700	520	if (sdvox_reg == SDVOB) {
21d40d37	521	intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
f899fc64	522	intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
b01f2c3a	523	dev_priv->hotplug_supported_mask \|= HDMIB_HOTPLUG_INT_STATUS;
f8aed700	524	} else if (sdvox_reg == SDVOC) {
21d40d37	525	intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
f899fc64	526	intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
b01f2c3a	527	dev_priv->hotplug_supported_mask \|= HDMIC_HOTPLUG_INT_STATUS;
f8aed700	528	} else if (sdvox_reg == HDMIB) {
21d40d37	529	intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
f899fc64	530	intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
b01f2c3a	531	dev_priv->hotplug_supported_mask \|= HDMIB_HOTPLUG_INT_STATUS;
f8aed700	532	} else if (sdvox_reg == HDMIC) {
21d40d37	533	intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
f899fc64	534	intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
b01f2c3a	535	dev_priv->hotplug_supported_mask \|= HDMIC_HOTPLUG_INT_STATUS;
f8aed700	536	} else if (sdvox_reg == HDMID) {
21d40d37	537	intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
f899fc64	538	intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
b01f2c3a	539	dev_priv->hotplug_supported_mask \|= HDMID_HOTPLUG_INT_STATUS;
f8aed700	540	}
7d57382e	541
ea5b213a	542	intel_hdmi->sdvox_reg = sdvox_reg;
7d57382e	543
45187ace JB	544	if (!HAS_PCH_SPLIT(dev))
	545	intel_hdmi->write_infoframe = i9xx_write_infoframe;
	546	else
	547	intel_hdmi->write_infoframe = ironlake_write_infoframe;
	548
4ef69c7a	549	drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
7d57382e	550
55b7d6e8 CW	551	intel_hdmi_add_properties(intel_hdmi, connector);
55b7d6e8 CW	552
df0e9248	553	intel_connector_attach_encoder(intel_connector, intel_encoder);
7d57382e EA	554	drm_sysfs_connector_add(connector);
	555
	556	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	557	* 0xd. Failure to do so will result in spurious interrupts being
	558	* generated on the port when a cable is not attached.
	559	*/
	560	if (IS_G4X(dev) && !IS_GM45(dev)) {
	561	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
	562	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
	563	}
7d57382e	564	}