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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
40 | struct intel_hdmi_priv { | |
41 | u32 sdvox_reg; | |
9dff6af8 | 42 | bool has_hdmi_sink; |
7d57382e EA |
43 | }; |
44 | ||
45 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, | |
46 | struct drm_display_mode *mode, | |
47 | struct drm_display_mode *adjusted_mode) | |
48 | { | |
49 | struct drm_device *dev = encoder->dev; | |
50 | struct drm_i915_private *dev_priv = dev->dev_private; | |
51 | struct drm_crtc *crtc = encoder->crtc; | |
52 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
21d40d37 EA |
53 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
54 | struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; | |
7d57382e EA |
55 | u32 sdvox; |
56 | ||
57 | sdvox = SDVO_ENCODING_HDMI | | |
58 | SDVO_BORDER_ENABLE | | |
59 | SDVO_VSYNC_ACTIVE_HIGH | | |
56d21b07 | 60 | SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 61 | |
467b200d | 62 | if (hdmi_priv->has_hdmi_sink) { |
7d57382e | 63 | sdvox |= SDVO_AUDIO_ENABLE; |
467b200d ZW |
64 | if (HAS_PCH_CPT(dev)) |
65 | sdvox |= HDMI_MODE_SELECT; | |
66 | } | |
7d57382e | 67 | |
0f229062 ZW |
68 | if (intel_crtc->pipe == 1) { |
69 | if (HAS_PCH_CPT(dev)) | |
70 | sdvox |= PORT_TRANS_B_SEL_CPT; | |
71 | else | |
72 | sdvox |= SDVO_PIPE_B_SELECT; | |
73 | } | |
7d57382e EA |
74 | |
75 | I915_WRITE(hdmi_priv->sdvox_reg, sdvox); | |
76 | POSTING_READ(hdmi_priv->sdvox_reg); | |
77 | } | |
78 | ||
79 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
80 | { | |
81 | struct drm_device *dev = encoder->dev; | |
82 | struct drm_i915_private *dev_priv = dev->dev_private; | |
21d40d37 EA |
83 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
84 | struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; | |
7d57382e EA |
85 | u32 temp; |
86 | ||
d8a2d0e0 ZW |
87 | temp = I915_READ(hdmi_priv->sdvox_reg); |
88 | ||
89 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
90 | * we do this anyway which shows more stable in testing. | |
91 | */ | |
c619eed4 | 92 | if (HAS_PCH_SPLIT(dev)) { |
7d57382e | 93 | I915_WRITE(hdmi_priv->sdvox_reg, temp & ~SDVO_ENABLE); |
d8a2d0e0 ZW |
94 | POSTING_READ(hdmi_priv->sdvox_reg); |
95 | } | |
96 | ||
97 | if (mode != DRM_MODE_DPMS_ON) { | |
98 | temp &= ~SDVO_ENABLE; | |
7d57382e | 99 | } else { |
d8a2d0e0 | 100 | temp |= SDVO_ENABLE; |
7d57382e | 101 | } |
d8a2d0e0 ZW |
102 | |
103 | I915_WRITE(hdmi_priv->sdvox_reg, temp); | |
7d57382e | 104 | POSTING_READ(hdmi_priv->sdvox_reg); |
d8a2d0e0 ZW |
105 | |
106 | /* HW workaround, need to write this twice for issue that may result | |
107 | * in first write getting masked. | |
108 | */ | |
c619eed4 | 109 | if (HAS_PCH_SPLIT(dev)) { |
d8a2d0e0 ZW |
110 | I915_WRITE(hdmi_priv->sdvox_reg, temp); |
111 | POSTING_READ(hdmi_priv->sdvox_reg); | |
112 | } | |
7d57382e EA |
113 | } |
114 | ||
7d57382e EA |
115 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
116 | struct drm_display_mode *mode) | |
117 | { | |
118 | if (mode->clock > 165000) | |
119 | return MODE_CLOCK_HIGH; | |
120 | if (mode->clock < 20000) | |
121 | return MODE_CLOCK_HIGH; | |
122 | ||
123 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
124 | return MODE_NO_DBLESCAN; | |
125 | ||
126 | return MODE_OK; | |
127 | } | |
128 | ||
129 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
130 | struct drm_display_mode *mode, | |
131 | struct drm_display_mode *adjusted_mode) | |
132 | { | |
133 | return true; | |
134 | } | |
135 | ||
aa93d632 | 136 | static enum drm_connector_status |
2ded9e27 | 137 | intel_hdmi_detect(struct drm_connector *connector) |
9dff6af8 | 138 | { |
674e2d08 ZW |
139 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
140 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
21d40d37 | 141 | struct intel_hdmi_priv *hdmi_priv = intel_encoder->dev_priv; |
9dff6af8 | 142 | struct edid *edid = NULL; |
aa93d632 | 143 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 144 | |
2ded9e27 | 145 | hdmi_priv->has_hdmi_sink = false; |
674e2d08 | 146 | edid = drm_get_edid(connector, |
21d40d37 | 147 | intel_encoder->ddc_bus); |
2ded9e27 | 148 | |
aa93d632 | 149 | if (edid) { |
be9f1c4f | 150 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 KP |
151 | status = connector_status_connected; |
152 | hdmi_priv->has_hdmi_sink = drm_detect_hdmi_monitor(edid); | |
153 | } | |
674e2d08 | 154 | connector->display_info.raw_edid = NULL; |
aa93d632 | 155 | kfree(edid); |
9dff6af8 | 156 | } |
30ad48b7 | 157 | |
2ded9e27 | 158 | return status; |
7d57382e EA |
159 | } |
160 | ||
161 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
162 | { | |
674e2d08 ZW |
163 | struct drm_encoder *encoder = intel_attached_encoder(connector); |
164 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
7d57382e EA |
165 | |
166 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
167 | * we can send audio to it. | |
168 | */ | |
169 | ||
335af9a2 | 170 | return intel_ddc_get_modes(connector, intel_encoder->ddc_bus); |
7d57382e EA |
171 | } |
172 | ||
173 | static void intel_hdmi_destroy(struct drm_connector *connector) | |
174 | { | |
7d57382e EA |
175 | drm_sysfs_connector_remove(connector); |
176 | drm_connector_cleanup(connector); | |
674e2d08 | 177 | kfree(connector); |
7d57382e EA |
178 | } |
179 | ||
180 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
181 | .dpms = intel_hdmi_dpms, | |
182 | .mode_fixup = intel_hdmi_mode_fixup, | |
183 | .prepare = intel_encoder_prepare, | |
184 | .mode_set = intel_hdmi_mode_set, | |
185 | .commit = intel_encoder_commit, | |
186 | }; | |
187 | ||
188 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 189 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
190 | .detect = intel_hdmi_detect, |
191 | .fill_modes = drm_helper_probe_single_connector_modes, | |
192 | .destroy = intel_hdmi_destroy, | |
193 | }; | |
194 | ||
195 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
196 | .get_modes = intel_hdmi_get_modes, | |
197 | .mode_valid = intel_hdmi_mode_valid, | |
674e2d08 | 198 | .best_encoder = intel_attached_encoder, |
7d57382e EA |
199 | }; |
200 | ||
201 | static void intel_hdmi_enc_destroy(struct drm_encoder *encoder) | |
202 | { | |
674e2d08 ZW |
203 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); |
204 | ||
205 | if (intel_encoder->i2c_bus) | |
206 | intel_i2c_destroy(intel_encoder->i2c_bus); | |
7d57382e | 207 | drm_encoder_cleanup(encoder); |
674e2d08 | 208 | kfree(intel_encoder); |
7d57382e EA |
209 | } |
210 | ||
211 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { | |
212 | .destroy = intel_hdmi_enc_destroy, | |
213 | }; | |
214 | ||
7d57382e EA |
215 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
216 | { | |
217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
218 | struct drm_connector *connector; | |
21d40d37 | 219 | struct intel_encoder *intel_encoder; |
674e2d08 | 220 | struct intel_connector *intel_connector; |
7d57382e EA |
221 | struct intel_hdmi_priv *hdmi_priv; |
222 | ||
21d40d37 | 223 | intel_encoder = kcalloc(sizeof(struct intel_encoder) + |
7d57382e | 224 | sizeof(struct intel_hdmi_priv), 1, GFP_KERNEL); |
21d40d37 | 225 | if (!intel_encoder) |
7d57382e | 226 | return; |
674e2d08 ZW |
227 | |
228 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
229 | if (!intel_connector) { | |
230 | kfree(intel_encoder); | |
231 | return; | |
232 | } | |
233 | ||
21d40d37 | 234 | hdmi_priv = (struct intel_hdmi_priv *)(intel_encoder + 1); |
7d57382e | 235 | |
674e2d08 | 236 | connector = &intel_connector->base; |
7d57382e | 237 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 238 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
239 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
240 | ||
21d40d37 | 241 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 242 | |
eb1f8e4f | 243 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
7d57382e EA |
244 | connector->interlace_allowed = 0; |
245 | connector->doublescan_allowed = 0; | |
21d40d37 | 246 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
7d57382e EA |
247 | |
248 | /* Set up the DDC bus. */ | |
f8aed700 | 249 | if (sdvox_reg == SDVOB) { |
21d40d37 EA |
250 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
251 | intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOE, "HDMIB"); | |
b01f2c3a | 252 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 253 | } else if (sdvox_reg == SDVOC) { |
21d40d37 EA |
254 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
255 | intel_encoder->ddc_bus = intel_i2c_create(dev, GPIOD, "HDMIC"); | |
b01f2c3a | 256 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 257 | } else if (sdvox_reg == HDMIB) { |
21d40d37 EA |
258 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
259 | intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOE, | |
30ad48b7 | 260 | "HDMIB"); |
b01f2c3a | 261 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 262 | } else if (sdvox_reg == HDMIC) { |
21d40d37 EA |
263 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
264 | intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOD, | |
30ad48b7 | 265 | "HDMIC"); |
b01f2c3a | 266 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 267 | } else if (sdvox_reg == HDMID) { |
21d40d37 EA |
268 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
269 | intel_encoder->ddc_bus = intel_i2c_create(dev, PCH_GPIOF, | |
30ad48b7 | 270 | "HDMID"); |
b01f2c3a | 271 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
f8aed700 | 272 | } |
21d40d37 | 273 | if (!intel_encoder->ddc_bus) |
7d57382e EA |
274 | goto err_connector; |
275 | ||
276 | hdmi_priv->sdvox_reg = sdvox_reg; | |
21d40d37 | 277 | intel_encoder->dev_priv = hdmi_priv; |
7d57382e | 278 | |
21d40d37 | 279 | drm_encoder_init(dev, &intel_encoder->enc, &intel_hdmi_enc_funcs, |
7d57382e | 280 | DRM_MODE_ENCODER_TMDS); |
21d40d37 | 281 | drm_encoder_helper_add(&intel_encoder->enc, &intel_hdmi_helper_funcs); |
7d57382e | 282 | |
674e2d08 | 283 | drm_mode_connector_attach_encoder(&intel_connector->base, |
21d40d37 | 284 | &intel_encoder->enc); |
7d57382e EA |
285 | drm_sysfs_connector_add(connector); |
286 | ||
287 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
288 | * 0xd. Failure to do so will result in spurious interrupts being | |
289 | * generated on the port when a cable is not attached. | |
290 | */ | |
291 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
292 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
293 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
294 | } | |
295 | ||
296 | return; | |
297 | ||
298 | err_connector: | |
299 | drm_connector_cleanup(connector); | |
21d40d37 | 300 | kfree(intel_encoder); |
674e2d08 | 301 | kfree(intel_connector); |
7d57382e EA |
302 | |
303 | return; | |
304 | } |