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drm/i915: Fix comments about GMBUSFREQ register
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_hdmi.c
CommitLineData
7d57382e
EA		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/i2c.h>
5a0e3ad6 30#include <linux/slab.h>
7d57382e 31#include <linux/delay.h>
178f736a 32#include <linux/hdmi.h>
760285e7 33#include <drm/drmP.h>
c6f95f27 34#include <drm/drm_atomic_helper.h>
760285e7
DH		 35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
7d57382e 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
7d57382e
EA		 39#include "i915_drv.h"
40
30add22d
PZ		 41static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
42{
da63a9f2 43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
30add22d
PZ		 44}
45
afba0188
DV		 46static void
47assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
48{
30add22d 49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
afba0188
DV		 50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
52
affa9354 53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
afba0188 54
b242b7f7 55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
afba0188
DV		 56 "HDMI port enabled, expecting disabled\n");
57}
58
f5bbfca3 59struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
ea5b213a 60{
da63a9f2
PZ		 61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
ea5b213a
CW		 64}
65
df0e9248
CW		 66static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
67{
da63a9f2 68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
df0e9248
CW		 69}
70
178f736a 71static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
3c17fe4b 72{
178f736a
DL		 73 switch (type) {
74 case HDMI_INFOFRAME_TYPE_AVI:
ed517fbb 75 return VIDEO_DIP_SELECT_AVI;
178f736a 76 case HDMI_INFOFRAME_TYPE_SPD:
ed517fbb 77 return VIDEO_DIP_SELECT_SPD;
c8bb75af
LD		 78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
45187ace 80 default:
ffc85dab 81 MISSING_CASE(type);
ed517fbb 82 return 0;
45187ace 83 }
45187ace
JB		 84}
85
178f736a 86static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
45187ace 87{
178f736a
DL		 88 switch (type) {
89 case HDMI_INFOFRAME_TYPE_AVI:
ed517fbb 90 return VIDEO_DIP_ENABLE_AVI;
178f736a 91 case HDMI_INFOFRAME_TYPE_SPD:
ed517fbb 92 return VIDEO_DIP_ENABLE_SPD;
c8bb75af
LD		 93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
fa193ff7 95 default:
ffc85dab 96 MISSING_CASE(type);
ed517fbb 97 return 0;
fa193ff7 98 }
fa193ff7
PZ		 99}
100
178f736a 101static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
2da8af54 102{
178f736a
DL		 103 switch (type) {
104 case HDMI_INFOFRAME_TYPE_AVI:
2da8af54 105 return VIDEO_DIP_ENABLE_AVI_HSW;
178f736a 106 case HDMI_INFOFRAME_TYPE_SPD:
2da8af54 107 return VIDEO_DIP_ENABLE_SPD_HSW;
c8bb75af
LD		 108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
2da8af54 110 default:
ffc85dab 111 MISSING_CASE(type);
2da8af54
PZ		 112 return 0;
113 }
114}
115
f0f59a00
VS		 116static i915_reg_t
117hsw_dip_data_reg(struct drm_i915_private *dev_priv,
118 enum transcoder cpu_transcoder,
119 enum hdmi_infoframe_type type,
120 int i)
2da8af54 121{
178f736a
DL		 122 switch (type) {
123 case HDMI_INFOFRAME_TYPE_AVI:
436c6d4a 124 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
178f736a 125 case HDMI_INFOFRAME_TYPE_SPD:
436c6d4a 126 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
c8bb75af 127 case HDMI_INFOFRAME_TYPE_VENDOR:
436c6d4a 128 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
2da8af54 129 default:
ffc85dab 130 MISSING_CASE(type);
f0f59a00 131 return INVALID_MMIO_REG;
2da8af54
PZ		 132 }
133}
134
a3da1df7 135static void g4x_write_infoframe(struct drm_encoder *encoder,
178f736a 136 enum hdmi_infoframe_type type,
fff63867 137 const void *frame, ssize_t len)
45187ace 138{
fff63867 139 const uint32_t *data = frame;
3c17fe4b
DH		 140 struct drm_device *dev = encoder->dev;
141 struct drm_i915_private *dev_priv = dev->dev_private;
22509ec8 142 u32 val = I915_READ(VIDEO_DIP_CTL);
178f736a 143 int i;
3c17fe4b 144
822974ae
PZ		 145 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
146
1d4f85ac 147 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 148 val |= g4x_infoframe_index(type);
22509ec8 149
178f736a 150 val &= ~g4x_infoframe_enable(type);
45187ace 151
22509ec8 152 I915_WRITE(VIDEO_DIP_CTL, val);
3c17fe4b 153
9d9740f0 154 mmiowb();
45187ace 155 for (i = 0; i < len; i += 4) {
3c17fe4b
DH		 156 I915_WRITE(VIDEO_DIP_DATA, *data);
157 data++;
158 }
adf00b26
PZ		 159 /* Write every possible data byte to force correct ECC calculation. */
160 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
161 I915_WRITE(VIDEO_DIP_DATA, 0);
9d9740f0 162 mmiowb();
3c17fe4b 163
178f736a 164 val |= g4x_infoframe_enable(type);
60c5ea2d 165 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 166 val |= VIDEO_DIP_FREQ_VSYNC;
45187ace 167
22509ec8 168 I915_WRITE(VIDEO_DIP_CTL, val);
9d9740f0 169 POSTING_READ(VIDEO_DIP_CTL);
3c17fe4b
DH		 170}
171
cda0aaaf
VS		 172static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
173 const struct intel_crtc_state *pipe_config)
e43823ec 174{
cda0aaaf 175 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
89a35ecd 176 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
e43823ec
JB		 177 u32 val = I915_READ(VIDEO_DIP_CTL);
178
ec1dc603
VS		 179 if ((val & VIDEO_DIP_ENABLE) == 0)
180 return false;
89a35ecd 181
ec1dc603
VS		 182 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
183 return false;
184
185 return val & (VIDEO_DIP_ENABLE_AVI |
186 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
e43823ec
JB		 187}
188
fdf1250a 189static void ibx_write_infoframe(struct drm_encoder *encoder,
178f736a 190 enum hdmi_infoframe_type type,
fff63867 191 const void *frame, ssize_t len)
fdf1250a 192{
fff63867 193 const uint32_t *data = frame;
fdf1250a
PZ		 194 struct drm_device *dev = encoder->dev;
195 struct drm_i915_private *dev_priv = dev->dev_private;
ed517fbb 196 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
f0f59a00 197 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
fdf1250a 198 u32 val = I915_READ(reg);
f0f59a00 199 int i;
fdf1250a 200
822974ae
PZ		 201 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
202
fdf1250a 203 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 204 val |= g4x_infoframe_index(type);
fdf1250a 205
178f736a 206 val &= ~g4x_infoframe_enable(type);
fdf1250a
PZ		 207
208 I915_WRITE(reg, val);
209
9d9740f0 210 mmiowb();
fdf1250a
PZ		 211 for (i = 0; i < len; i += 4) {
212 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
213 data++;
214 }
adf00b26
PZ		 215 /* Write every possible data byte to force correct ECC calculation. */
216 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
217 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
9d9740f0 218 mmiowb();
fdf1250a 219
178f736a 220 val |= g4x_infoframe_enable(type);
fdf1250a 221 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 222 val |= VIDEO_DIP_FREQ_VSYNC;
fdf1250a
PZ		 223
224 I915_WRITE(reg, val);
9d9740f0 225 POSTING_READ(reg);
fdf1250a
PZ		 226}
227
cda0aaaf
VS		 228static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
229 const struct intel_crtc_state *pipe_config)
e43823ec 230{
cda0aaaf 231 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
052f62f7 232 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
cda0aaaf
VS		 233 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
234 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
e43823ec
JB		 235 u32 val = I915_READ(reg);
236
ec1dc603
VS		 237 if ((val & VIDEO_DIP_ENABLE) == 0)
238 return false;
239
240 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
241 return false;
052f62f7 242
ec1dc603
VS		 243 return val & (VIDEO_DIP_ENABLE_AVI |
244 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
245 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
e43823ec
JB		 246}
247
fdf1250a 248static void cpt_write_infoframe(struct drm_encoder *encoder,
178f736a 249 enum hdmi_infoframe_type type,
fff63867 250 const void *frame, ssize_t len)
b055c8f3 251{
fff63867 252 const uint32_t *data = frame;
b055c8f3
JB		 253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
ed517fbb 255 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
f0f59a00 256 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
22509ec8 257 u32 val = I915_READ(reg);
f0f59a00 258 int i;
b055c8f3 259
822974ae
PZ		 260 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
261
64a8fc01 262 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 263 val |= g4x_infoframe_index(type);
45187ace 264
ecb97851
PZ		 265 /* The DIP control register spec says that we need to update the AVI
266 * infoframe without clearing its enable bit */
178f736a
DL		 267 if (type != HDMI_INFOFRAME_TYPE_AVI)
268 val &= ~g4x_infoframe_enable(type);
ecb97851 269
22509ec8 270 I915_WRITE(reg, val);
45187ace 271
9d9740f0 272 mmiowb();
45187ace 273 for (i = 0; i < len; i += 4) {
b055c8f3
JB		 274 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
275 data++;
276 }
adf00b26
PZ		 277 /* Write every possible data byte to force correct ECC calculation. */
278 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
279 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
9d9740f0 280 mmiowb();
b055c8f3 281
178f736a 282 val |= g4x_infoframe_enable(type);
60c5ea2d 283 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 284 val |= VIDEO_DIP_FREQ_VSYNC;
45187ace 285
22509ec8 286 I915_WRITE(reg, val);
9d9740f0 287 POSTING_READ(reg);
45187ace 288}
90b107c8 289
cda0aaaf
VS		 290static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
291 const struct intel_crtc_state *pipe_config)
e43823ec 292{
cda0aaaf
VS		 293 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
294 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
295 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
e43823ec 296
ec1dc603
VS		 297 if ((val & VIDEO_DIP_ENABLE) == 0)
298 return false;
299
300 return val & (VIDEO_DIP_ENABLE_AVI |
301 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
302 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
e43823ec
JB		 303}
304
90b107c8 305static void vlv_write_infoframe(struct drm_encoder *encoder,
178f736a 306 enum hdmi_infoframe_type type,
fff63867 307 const void *frame, ssize_t len)
90b107c8 308{
fff63867 309 const uint32_t *data = frame;
90b107c8
SK		 310 struct drm_device *dev = encoder->dev;
311 struct drm_i915_private *dev_priv = dev->dev_private;
ed517fbb 312 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
f0f59a00 313 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
22509ec8 314 u32 val = I915_READ(reg);
f0f59a00 315 int i;
90b107c8 316
822974ae
PZ		 317 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
318
90b107c8 319 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 320 val |= g4x_infoframe_index(type);
22509ec8 321
178f736a 322 val &= ~g4x_infoframe_enable(type);
90b107c8 323
22509ec8 324 I915_WRITE(reg, val);
90b107c8 325
9d9740f0 326 mmiowb();
90b107c8
SK		 327 for (i = 0; i < len; i += 4) {
328 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
329 data++;
330 }
adf00b26
PZ		 331 /* Write every possible data byte to force correct ECC calculation. */
332 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
333 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
9d9740f0 334 mmiowb();
90b107c8 335
178f736a 336 val |= g4x_infoframe_enable(type);
60c5ea2d 337 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 338 val |= VIDEO_DIP_FREQ_VSYNC;
90b107c8 339
22509ec8 340 I915_WRITE(reg, val);
9d9740f0 341 POSTING_READ(reg);
90b107c8
SK		 342}
343
cda0aaaf
VS		 344static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
345 const struct intel_crtc_state *pipe_config)
e43823ec 346{
cda0aaaf 347 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
535afa2e 348 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
cda0aaaf
VS		 349 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
350 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
e43823ec 351
ec1dc603
VS		 352 if ((val & VIDEO_DIP_ENABLE) == 0)
353 return false;
354
355 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
356 return false;
535afa2e 357
ec1dc603
VS		 358 return val & (VIDEO_DIP_ENABLE_AVI |
359 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
360 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
e43823ec
JB		 361}
362
8c5f5f7c 363static void hsw_write_infoframe(struct drm_encoder *encoder,
178f736a 364 enum hdmi_infoframe_type type,
fff63867 365 const void *frame, ssize_t len)
8c5f5f7c 366{
fff63867 367 const uint32_t *data = frame;
2da8af54
PZ		 368 struct drm_device *dev = encoder->dev;
369 struct drm_i915_private *dev_priv = dev->dev_private;
370 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
436c6d4a 371 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
f0f59a00
VS		 372 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
373 i915_reg_t data_reg;
178f736a 374 int i;
2da8af54 375 u32 val = I915_READ(ctl_reg);
8c5f5f7c 376
436c6d4a 377 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
2da8af54 378
178f736a 379 val &= ~hsw_infoframe_enable(type);
2da8af54
PZ		 380 I915_WRITE(ctl_reg, val);
381
9d9740f0 382 mmiowb();
2da8af54 383 for (i = 0; i < len; i += 4) {
436c6d4a
VS		 384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
385 type, i >> 2), *data);
2da8af54
PZ		 386 data++;
387 }
adf00b26
PZ		 388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
436c6d4a
VS		 390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
391 type, i >> 2), 0);
9d9740f0 392 mmiowb();
8c5f5f7c 393
178f736a 394 val |= hsw_infoframe_enable(type);
2da8af54 395 I915_WRITE(ctl_reg, val);
9d9740f0 396 POSTING_READ(ctl_reg);
8c5f5f7c
ED		 397}
398
cda0aaaf
VS		 399static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
400 const struct intel_crtc_state *pipe_config)
e43823ec 401{
cda0aaaf
VS		 402 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
403 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
e43823ec 404
ec1dc603
VS		 405 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
406 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
407 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
e43823ec
JB		 408}
409
5adaea79
DL		 410/*
411 * The data we write to the DIP data buffer registers is 1 byte bigger than the
412 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
413 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
414 * used for both technologies.
415 *
416 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
417 * DW1: DB3 | DB2 | DB1 | DB0
418 * DW2: DB7 | DB6 | DB5 | DB4
419 * DW3: ...
420 *
421 * (HB is Header Byte, DB is Data Byte)
422 *
423 * The hdmi pack() functions don't know about that hardware specific hole so we
424 * trick them by giving an offset into the buffer and moving back the header
425 * bytes by one.
426 */
9198ee5b
DL		 427static void intel_write_infoframe(struct drm_encoder *encoder,
428 union hdmi_infoframe *frame)
45187ace
JB		 429{
430 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
5adaea79
DL		 431 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
432 ssize_t len;
45187ace 433
5adaea79
DL		 434 /* see comment above for the reason for this offset */
435 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
436 if (len < 0)
437 return;
438
439 /* Insert the 'hole' (see big comment above) at position 3 */
440 buffer[0] = buffer[1];
441 buffer[1] = buffer[2];
442 buffer[2] = buffer[3];
443 buffer[3] = 0;
444 len++;
45187ace 445
5adaea79 446 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
45187ace
JB		 447}
448
687f4d06 449static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
7c5f93b0 450 const struct drm_display_mode *adjusted_mode)
45187ace 451{
abedc077 452 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
50f3b016 453 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
5adaea79
DL		 454 union hdmi_infoframe frame;
455 int ret;
45187ace 456
5adaea79
DL		 457 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
458 adjusted_mode);
459 if (ret < 0) {
460 DRM_ERROR("couldn't fill AVI infoframe\n");
461 return;
462 }
c846b619 463
abedc077 464 if (intel_hdmi->rgb_quant_range_selectable) {
6e3c9717 465 if (intel_crtc->config->limited_color_range)
5adaea79
DL		 466 frame.avi.quantization_range =
467 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 468 else
5adaea79
DL		 469 frame.avi.quantization_range =
470 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 471 }
472
9198ee5b 473 intel_write_infoframe(encoder, &frame);
b055c8f3
JB		 474}
475
687f4d06 476static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
c0864cb3 477{
5adaea79
DL		 478 union hdmi_infoframe frame;
479 int ret;
480
481 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
482 if (ret < 0) {
483 DRM_ERROR("couldn't fill SPD infoframe\n");
484 return;
485 }
c0864cb3 486
5adaea79 487 frame.spd.sdi = HDMI_SPD_SDI_PC;
c0864cb3 488
9198ee5b 489 intel_write_infoframe(encoder, &frame);
c0864cb3
JB		 490}
491
c8bb75af
LD		 492static void
493intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
7c5f93b0 494 const struct drm_display_mode *adjusted_mode)
c8bb75af
LD		 495{
496 union hdmi_infoframe frame;
497 int ret;
498
499 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
500 adjusted_mode);
501 if (ret < 0)
502 return;
503
504 intel_write_infoframe(encoder, &frame);
505}
506
687f4d06 507static void g4x_set_infoframes(struct drm_encoder *encoder,
6897b4b5 508 bool enable,
7c5f93b0 509 const struct drm_display_mode *adjusted_mode)
687f4d06 510{
0c14c7f9 511 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
69fde0a6
VS		 512 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
513 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
f0f59a00 514 i915_reg_t reg = VIDEO_DIP_CTL;
0c14c7f9 515 u32 val = I915_READ(reg);
822cdc52 516 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
0c14c7f9 517
afba0188
DV		 518 assert_hdmi_port_disabled(intel_hdmi);
519
0c14c7f9
PZ		 520 /* If the registers were not initialized yet, they might be zeroes,
521 * which means we're selecting the AVI DIP and we're setting its
522 * frequency to once. This seems to really confuse the HW and make
523 * things stop working (the register spec says the AVI always needs to
524 * be sent every VSync). So here we avoid writing to the register more
525 * than we need and also explicitly select the AVI DIP and explicitly
526 * set its frequency to every VSync. Avoiding to write it twice seems to
527 * be enough to solve the problem, but being defensive shouldn't hurt us
528 * either. */
529 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
530
6897b4b5 531 if (!enable) {
0c14c7f9
PZ		 532 if (!(val & VIDEO_DIP_ENABLE))
533 return;
0be6f0c8
VS		 534 if (port != (val & VIDEO_DIP_PORT_MASK)) {
535 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
536 (val & VIDEO_DIP_PORT_MASK) >> 29);
537 return;
538 }
539 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
540 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
0c14c7f9 541 I915_WRITE(reg, val);
9d9740f0 542 POSTING_READ(reg);
0c14c7f9
PZ		 543 return;
544 }
545
72b78c9d
PZ		 546 if (port != (val & VIDEO_DIP_PORT_MASK)) {
547 if (val & VIDEO_DIP_ENABLE) {
0be6f0c8
VS		 548 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
549 (val & VIDEO_DIP_PORT_MASK) >> 29);
550 return;
72b78c9d
PZ		 551 }
552 val &= ~VIDEO_DIP_PORT_MASK;
553 val |= port;
554 }
555
822974ae 556 val |= VIDEO_DIP_ENABLE;
0be6f0c8
VS		 557 val &= ~(VIDEO_DIP_ENABLE_AVI |
558 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
822974ae 559
f278d972 560 I915_WRITE(reg, val);
9d9740f0 561 POSTING_READ(reg);
f278d972 562
687f4d06
PZ		 563 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
564 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 565 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 566}
567
6d67415f
VS		 568static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
569{
570 struct drm_device *dev = encoder->dev;
571 struct drm_connector *connector;
572
573 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
574
575 /*
576 * HDMI cloning is only supported on g4x which doesn't
577 * support deep color or GCP infoframes anyway so no
578 * need to worry about multiple HDMI sinks here.
579 */
580 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
581 if (connector->encoder == encoder)
582 return connector->display_info.bpc > 8;
583
584 return false;
585}
586
12aa3290
VS		 587/*
588 * Determine if default_phase=1 can be indicated in the GCP infoframe.
589 *
590 * From HDMI specification 1.4a:
591 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
592 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
593 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
594 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
595 * phase of 0
596 */
597static bool gcp_default_phase_possible(int pipe_bpp,
598 const struct drm_display_mode *mode)
599{
600 unsigned int pixels_per_group;
601
602 switch (pipe_bpp) {
603 case 30:
604 /* 4 pixels in 5 clocks */
605 pixels_per_group = 4;
606 break;
607 case 36:
608 /* 2 pixels in 3 clocks */
609 pixels_per_group = 2;
610 break;
611 case 48:
612 /* 1 pixel in 2 clocks */
613 pixels_per_group = 1;
614 break;
615 default:
616 /* phase information not relevant for 8bpc */
617 return false;
618 }
619
620 return mode->crtc_hdisplay % pixels_per_group == 0 &&
621 mode->crtc_htotal % pixels_per_group == 0 &&
622 mode->crtc_hblank_start % pixels_per_group == 0 &&
623 mode->crtc_hblank_end % pixels_per_group == 0 &&
624 mode->crtc_hsync_start % pixels_per_group == 0 &&
625 mode->crtc_hsync_end % pixels_per_group == 0 &&
626 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
627 mode->crtc_htotal/2 % pixels_per_group == 0);
628}
629
6d67415f
VS		 630static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
631{
632 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
633 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
f0f59a00
VS		 634 i915_reg_t reg;
635 u32 val = 0;
6d67415f
VS		 636
637 if (HAS_DDI(dev_priv))
638 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
666a4537 639 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6d67415f 640 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
2d1fe073 641 else if (HAS_PCH_SPLIT(dev_priv))
6d67415f
VS		 642 reg = TVIDEO_DIP_GCP(crtc->pipe);
643 else
644 return false;
645
646 /* Indicate color depth whenever the sink supports deep color */
647 if (hdmi_sink_is_deep_color(encoder))
648 val |= GCP_COLOR_INDICATION;
649
12aa3290
VS		 650 /* Enable default_phase whenever the display mode is suitably aligned */
651 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
652 &crtc->config->base.adjusted_mode))
653 val |= GCP_DEFAULT_PHASE_ENABLE;
654
6d67415f
VS		 655 I915_WRITE(reg, val);
656
657 return val != 0;
658}
659
687f4d06 660static void ibx_set_infoframes(struct drm_encoder *encoder,
6897b4b5 661 bool enable,
7c5f93b0 662 const struct drm_display_mode *adjusted_mode)
687f4d06 663{
0c14c7f9
PZ		 664 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
665 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
69fde0a6
VS		 666 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
667 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
f0f59a00 668 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
0c14c7f9 669 u32 val = I915_READ(reg);
822cdc52 670 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
0c14c7f9 671
afba0188
DV		 672 assert_hdmi_port_disabled(intel_hdmi);
673
0c14c7f9
PZ		 674 /* See the big comment in g4x_set_infoframes() */
675 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
676
6897b4b5 677 if (!enable) {
0c14c7f9
PZ		 678 if (!(val & VIDEO_DIP_ENABLE))
679 return;
0be6f0c8
VS		 680 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
681 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
682 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
0c14c7f9 683 I915_WRITE(reg, val);
9d9740f0 684 POSTING_READ(reg);
0c14c7f9
PZ		 685 return;
686 }
687
72b78c9d 688 if (port != (val & VIDEO_DIP_PORT_MASK)) {
0be6f0c8
VS		 689 WARN(val & VIDEO_DIP_ENABLE,
690 "DIP already enabled on port %c\n",
691 (val & VIDEO_DIP_PORT_MASK) >> 29);
72b78c9d
PZ		 692 val &= ~VIDEO_DIP_PORT_MASK;
693 val |= port;
694 }
695
822974ae 696 val |= VIDEO_DIP_ENABLE;
0be6f0c8
VS		 697 val &= ~(VIDEO_DIP_ENABLE_AVI |
698 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
699 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
822974ae 700
6d67415f
VS		 701 if (intel_hdmi_set_gcp_infoframe(encoder))
702 val |= VIDEO_DIP_ENABLE_GCP;
703
f278d972 704 I915_WRITE(reg, val);
9d9740f0 705 POSTING_READ(reg);
f278d972 706
687f4d06
PZ		 707 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
708 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 709 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 710}
711
712static void cpt_set_infoframes(struct drm_encoder *encoder,
6897b4b5 713 bool enable,
7c5f93b0 714 const struct drm_display_mode *adjusted_mode)
687f4d06 715{
0c14c7f9
PZ		 716 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
717 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
718 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
f0f59a00 719 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
0c14c7f9
PZ		 720 u32 val = I915_READ(reg);
721
afba0188
DV		 722 assert_hdmi_port_disabled(intel_hdmi);
723
0c14c7f9
PZ		 724 /* See the big comment in g4x_set_infoframes() */
725 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
726
6897b4b5 727 if (!enable) {
0c14c7f9
PZ		 728 if (!(val & VIDEO_DIP_ENABLE))
729 return;
0be6f0c8
VS		 730 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
731 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
732 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
0c14c7f9 733 I915_WRITE(reg, val);
9d9740f0 734 POSTING_READ(reg);
0c14c7f9
PZ		 735 return;
736 }
737
822974ae
PZ		 738 /* Set both together, unset both together: see the spec. */
739 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
0dd87d20 740 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
0be6f0c8 741 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
822974ae 742
6d67415f
VS		 743 if (intel_hdmi_set_gcp_infoframe(encoder))
744 val |= VIDEO_DIP_ENABLE_GCP;
745
822974ae 746 I915_WRITE(reg, val);
9d9740f0 747 POSTING_READ(reg);
822974ae 748
687f4d06
PZ		 749 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
750 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 751 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 752}
753
754static void vlv_set_infoframes(struct drm_encoder *encoder,
6897b4b5 755 bool enable,
7c5f93b0 756 const struct drm_display_mode *adjusted_mode)
687f4d06 757{
0c14c7f9 758 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
6a2b8021 759 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
0c14c7f9
PZ		 760 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
761 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
f0f59a00 762 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
0c14c7f9 763 u32 val = I915_READ(reg);
6a2b8021 764 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
0c14c7f9 765
afba0188
DV		 766 assert_hdmi_port_disabled(intel_hdmi);
767
0c14c7f9
PZ		 768 /* See the big comment in g4x_set_infoframes() */
769 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
770
6897b4b5 771 if (!enable) {
0c14c7f9
PZ		 772 if (!(val & VIDEO_DIP_ENABLE))
773 return;
0be6f0c8
VS		 774 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
775 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
776 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
0c14c7f9 777 I915_WRITE(reg, val);
9d9740f0 778 POSTING_READ(reg);
0c14c7f9
PZ		 779 return;
780 }
781
6a2b8021 782 if (port != (val & VIDEO_DIP_PORT_MASK)) {
0be6f0c8
VS		 783 WARN(val & VIDEO_DIP_ENABLE,
784 "DIP already enabled on port %c\n",
785 (val & VIDEO_DIP_PORT_MASK) >> 29);
6a2b8021
JB		 786 val &= ~VIDEO_DIP_PORT_MASK;
787 val |= port;
788 }
789
822974ae 790 val |= VIDEO_DIP_ENABLE;
0be6f0c8
VS		 791 val &= ~(VIDEO_DIP_ENABLE_AVI |
792 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
793 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
822974ae 794
6d67415f
VS		 795 if (intel_hdmi_set_gcp_infoframe(encoder))
796 val |= VIDEO_DIP_ENABLE_GCP;
797
822974ae 798 I915_WRITE(reg, val);
9d9740f0 799 POSTING_READ(reg);
822974ae 800
687f4d06
PZ		 801 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
802 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 803 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 804}
805
806static void hsw_set_infoframes(struct drm_encoder *encoder,
6897b4b5 807 bool enable,
7c5f93b0 808 const struct drm_display_mode *adjusted_mode)
687f4d06 809{
0c14c7f9
PZ		 810 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
811 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
812 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
f0f59a00 813 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
0dd87d20 814 u32 val = I915_READ(reg);
0c14c7f9 815
afba0188
DV		 816 assert_hdmi_port_disabled(intel_hdmi);
817
0be6f0c8
VS		 818 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
819 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
820 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
821
6897b4b5 822 if (!enable) {
0be6f0c8 823 I915_WRITE(reg, val);
9d9740f0 824 POSTING_READ(reg);
0c14c7f9
PZ		 825 return;
826 }
827
6d67415f
VS		 828 if (intel_hdmi_set_gcp_infoframe(encoder))
829 val |= VIDEO_DIP_ENABLE_GCP_HSW;
830
0dd87d20 831 I915_WRITE(reg, val);
9d9740f0 832 POSTING_READ(reg);
0dd87d20 833
687f4d06
PZ		 834 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
835 intel_hdmi_set_spd_infoframe(encoder);
c8bb75af 836 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
687f4d06
PZ		 837}
838
4cde8a21 839static void intel_hdmi_prepare(struct intel_encoder *encoder)
7d57382e 840{
c59423a3 841 struct drm_device *dev = encoder->base.dev;
7d57382e 842 struct drm_i915_private *dev_priv = dev->dev_private;
c59423a3
DV		 843 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
844 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
7c5f93b0 845 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
b242b7f7 846 u32 hdmi_val;
7d57382e 847
b242b7f7 848 hdmi_val = SDVO_ENCODING_HDMI;
0f2a2a75
VS		 849 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
850 hdmi_val |= HDMI_COLOR_RANGE_16_235;
b599c0bc 851 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
b242b7f7 852 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
b599c0bc 853 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
b242b7f7 854 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
7d57382e 855
6e3c9717 856 if (crtc->config->pipe_bpp > 24)
4f3a8bc7 857 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
020f6704 858 else
4f3a8bc7 859 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
020f6704 860
6e3c9717 861 if (crtc->config->has_hdmi_sink)
dc0fa718 862 hdmi_val |= HDMI_MODE_SELECT_HDMI;
2e3d6006 863
75770564 864 if (HAS_PCH_CPT(dev))
c59423a3 865 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
44f37d1f
CML		 866 else if (IS_CHERRYVIEW(dev))
867 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
dc0fa718 868 else
c59423a3 869 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
7d57382e 870
b242b7f7
PZ		 871 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
872 POSTING_READ(intel_hdmi->hdmi_reg);
7d57382e
EA		 873}
874
85234cdc
DV		 875static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
876 enum pipe *pipe)
7d57382e 877{
85234cdc 878 struct drm_device *dev = encoder->base.dev;
7d57382e 879 struct drm_i915_private *dev_priv = dev->dev_private;
85234cdc 880 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
6d129bea 881 enum intel_display_power_domain power_domain;
85234cdc 882 u32 tmp;
5b092174 883 bool ret;
85234cdc 884
6d129bea 885 power_domain = intel_display_port_power_domain(encoder);
5b092174 886 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 887 return false;
888
5b092174
ID		 889 ret = false;
890
b242b7f7 891 tmp = I915_READ(intel_hdmi->hdmi_reg);
85234cdc
DV		 892
893 if (!(tmp & SDVO_ENABLE))
5b092174 894 goto out;
85234cdc
DV		 895
896 if (HAS_PCH_CPT(dev))
897 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 898 else if (IS_CHERRYVIEW(dev))
899 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
85234cdc
DV		 900 else
901 *pipe = PORT_TO_PIPE(tmp);
902
5b092174
ID		 903 ret = true;
904
905out:
906 intel_display_power_put(dev_priv, power_domain);
907
908 return ret;
85234cdc
DV		 909}
910
045ac3b5 911static void intel_hdmi_get_config(struct intel_encoder *encoder,
5cec258b 912 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 913{
914 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
8c875fca
VS		 915 struct drm_device *dev = encoder->base.dev;
916 struct drm_i915_private *dev_priv = dev->dev_private;
045ac3b5 917 u32 tmp, flags = 0;
18442d08 918 int dotclock;
045ac3b5
JB		 919
920 tmp = I915_READ(intel_hdmi->hdmi_reg);
921
922 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
923 flags |= DRM_MODE_FLAG_PHSYNC;
924 else
925 flags |= DRM_MODE_FLAG_NHSYNC;
926
927 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
928 flags |= DRM_MODE_FLAG_PVSYNC;
929 else
930 flags |= DRM_MODE_FLAG_NVSYNC;
931
6897b4b5
DV		 932 if (tmp & HDMI_MODE_SELECT_HDMI)
933 pipe_config->has_hdmi_sink = true;
934
cda0aaaf 935 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
e43823ec
JB		 936 pipe_config->has_infoframe = true;
937
c84db770 938 if (tmp & SDVO_AUDIO_ENABLE)
9ed109a7
DV		 939 pipe_config->has_audio = true;
940
8c875fca
VS		 941 if (!HAS_PCH_SPLIT(dev) &&
942 tmp & HDMI_COLOR_RANGE_16_235)
943 pipe_config->limited_color_range = true;
944
2d112de7 945 pipe_config->base.adjusted_mode.flags |= flags;
18442d08
VS		 946
947 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
948 dotclock = pipe_config->port_clock * 2 / 3;
949 else
950 dotclock = pipe_config->port_clock;
951
be69a133
VS		 952 if (pipe_config->pixel_multiplier)
953 dotclock /= pipe_config->pixel_multiplier;
954
2d112de7 955 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
045ac3b5
JB		 956}
957
d1b1589c
VS		 958static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
959{
960 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
961
962 WARN_ON(!crtc->config->has_hdmi_sink);
963 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
964 pipe_name(crtc->pipe));
965 intel_audio_codec_enable(encoder);
966}
967
bf868c7d 968static void g4x_enable_hdmi(struct intel_encoder *encoder)
7d57382e 969{
5ab432ef 970 struct drm_device *dev = encoder->base.dev;
7d57382e 971 struct drm_i915_private *dev_priv = dev->dev_private;
bf868c7d 972 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
5ab432ef 973 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
7d57382e
EA		 974 u32 temp;
975
b242b7f7 976 temp = I915_READ(intel_hdmi->hdmi_reg);
d8a2d0e0 977
bf868c7d
VS		 978 temp |= SDVO_ENABLE;
979 if (crtc->config->has_audio)
980 temp |= SDVO_AUDIO_ENABLE;
7a87c289 981
bf868c7d
VS		 982 I915_WRITE(intel_hdmi->hdmi_reg, temp);
983 POSTING_READ(intel_hdmi->hdmi_reg);
984
985 if (crtc->config->has_audio)
986 intel_enable_hdmi_audio(encoder);
987}
988
989static void ibx_enable_hdmi(struct intel_encoder *encoder)
990{
991 struct drm_device *dev = encoder->base.dev;
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
994 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
995 u32 temp;
996
997 temp = I915_READ(intel_hdmi->hdmi_reg);
d8a2d0e0 998
bf868c7d
VS		 999 temp |= SDVO_ENABLE;
1000 if (crtc->config->has_audio)
1001 temp |= SDVO_AUDIO_ENABLE;
5ab432ef 1002
bf868c7d
VS		 1003 /*
1004 * HW workaround, need to write this twice for issue
1005 * that may result in first write getting masked.
1006 */
1007 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1008 POSTING_READ(intel_hdmi->hdmi_reg);
b242b7f7
PZ		 1009 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1010 POSTING_READ(intel_hdmi->hdmi_reg);
5ab432ef 1011
bf868c7d
VS		 1012 /*
1013 * HW workaround, need to toggle enable bit off and on
1014 * for 12bpc with pixel repeat.
1015 *
1016 * FIXME: BSpec says this should be done at the end of
1017 * of the modeset sequence, so not sure if this isn't too soon.
5ab432ef 1018 */
bf868c7d
VS		 1019 if (crtc->config->pipe_bpp > 24 &&
1020 crtc->config->pixel_multiplier > 1) {
1021 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1022 POSTING_READ(intel_hdmi->hdmi_reg);
1023
1024 /*
1025 * HW workaround, need to write this twice for issue
1026 * that may result in first write getting masked.
1027 */
1028 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1029 POSTING_READ(intel_hdmi->hdmi_reg);
b242b7f7
PZ		 1030 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1031 POSTING_READ(intel_hdmi->hdmi_reg);
7d57382e 1032 }
c1dec79a 1033
bf868c7d 1034 if (crtc->config->has_audio)
d1b1589c
VS		 1035 intel_enable_hdmi_audio(encoder);
1036}
1037
1038static void cpt_enable_hdmi(struct intel_encoder *encoder)
1039{
1040 struct drm_device *dev = encoder->base.dev;
1041 struct drm_i915_private *dev_priv = dev->dev_private;
1042 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1043 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1044 enum pipe pipe = crtc->pipe;
1045 u32 temp;
1046
1047 temp = I915_READ(intel_hdmi->hdmi_reg);
1048
1049 temp |= SDVO_ENABLE;
1050 if (crtc->config->has_audio)
1051 temp |= SDVO_AUDIO_ENABLE;
1052
1053 /*
1054 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1055 *
1056 * The procedure for 12bpc is as follows:
1057 * 1. disable HDMI clock gating
1058 * 2. enable HDMI with 8bpc
1059 * 3. enable HDMI with 12bpc
1060 * 4. enable HDMI clock gating
1061 */
1062
1063 if (crtc->config->pipe_bpp > 24) {
1064 I915_WRITE(TRANS_CHICKEN1(pipe),
1065 I915_READ(TRANS_CHICKEN1(pipe)) |
1066 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1067
1068 temp &= ~SDVO_COLOR_FORMAT_MASK;
1069 temp |= SDVO_COLOR_FORMAT_8bpc;
c1dec79a 1070 }
d1b1589c
VS		 1071
1072 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1073 POSTING_READ(intel_hdmi->hdmi_reg);
1074
1075 if (crtc->config->pipe_bpp > 24) {
1076 temp &= ~SDVO_COLOR_FORMAT_MASK;
1077 temp |= HDMI_COLOR_FORMAT_12bpc;
1078
1079 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1080 POSTING_READ(intel_hdmi->hdmi_reg);
1081
1082 I915_WRITE(TRANS_CHICKEN1(pipe),
1083 I915_READ(TRANS_CHICKEN1(pipe)) &
1084 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1085 }
1086
1087 if (crtc->config->has_audio)
1088 intel_enable_hdmi_audio(encoder);
b76cf76b 1089}
89b667f8 1090
b76cf76b
JN		 1091static void vlv_enable_hdmi(struct intel_encoder *encoder)
1092{
5ab432ef
DV		 1093}
1094
1095static void intel_disable_hdmi(struct intel_encoder *encoder)
1096{
1097 struct drm_device *dev = encoder->base.dev;
1098 struct drm_i915_private *dev_priv = dev->dev_private;
1099 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
495a5bb8 1100 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
5ab432ef 1101 u32 temp;
5ab432ef 1102
b242b7f7 1103 temp = I915_READ(intel_hdmi->hdmi_reg);
5ab432ef 1104
1612c8bd 1105 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
b242b7f7
PZ		 1106 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1107 POSTING_READ(intel_hdmi->hdmi_reg);
1612c8bd
VS		 1108
1109 /*
1110 * HW workaround for IBX, we need to move the port
1111 * to transcoder A after disabling it to allow the
1112 * matching DP port to be enabled on transcoder A.
1113 */
1114 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1115 /*
1116 * We get CPU/PCH FIFO underruns on the other pipe when
1117 * doing the workaround. Sweep them under the rug.
1118 */
1119 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1120 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1121
1612c8bd
VS		 1122 temp &= ~SDVO_PIPE_B_SELECT;
1123 temp |= SDVO_ENABLE;
1124 /*
1125 * HW workaround, need to write this twice for issue
1126 * that may result in first write getting masked.
1127 */
1128 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1129 POSTING_READ(intel_hdmi->hdmi_reg);
1130 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1131 POSTING_READ(intel_hdmi->hdmi_reg);
1132
1133 temp &= ~SDVO_ENABLE;
1134 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1135 POSTING_READ(intel_hdmi->hdmi_reg);
0c241d5b
VS		 1136
1137 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
1138 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1139 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1612c8bd 1140 }
6d67415f 1141
0be6f0c8 1142 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
7d57382e
EA		 1143}
1144
a4790cec
VS		 1145static void g4x_disable_hdmi(struct intel_encoder *encoder)
1146{
1147 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1148
1149 if (crtc->config->has_audio)
1150 intel_audio_codec_disable(encoder);
1151
1152 intel_disable_hdmi(encoder);
1153}
1154
1155static void pch_disable_hdmi(struct intel_encoder *encoder)
1156{
1157 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1158
1159 if (crtc->config->has_audio)
1160 intel_audio_codec_disable(encoder);
1161}
1162
1163static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1164{
1165 intel_disable_hdmi(encoder);
1166}
1167
e64e739e 1168static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
7d148ef5
DV		 1169{
1170 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1171
40478455 1172 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
7d148ef5 1173 return 165000;
e3c33578 1174 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
7d148ef5
DV		 1175 return 300000;
1176 else
1177 return 225000;
1178}
1179
e64e739e
VS		 1180static enum drm_mode_status
1181hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1182 int clock, bool respect_dvi_limit)
1183{
1184 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1185
1186 if (clock < 25000)
1187 return MODE_CLOCK_LOW;
1188 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1189 return MODE_CLOCK_HIGH;
1190
5e6ccc0b
VS		 1191 /* BXT DPLL can't generate 223-240 MHz */
1192 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1193 return MODE_CLOCK_RANGE;
1194
1195 /* CHV DPLL can't generate 216-240 MHz */
1196 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
e64e739e
VS		 1197 return MODE_CLOCK_RANGE;
1198
1199 return MODE_OK;
1200}
1201
c19de8eb
DL		 1202static enum drm_mode_status
1203intel_hdmi_mode_valid(struct drm_connector *connector,
1204 struct drm_display_mode *mode)
7d57382e 1205{
e64e739e
VS		 1206 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1207 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1208 enum drm_mode_status status;
1209 int clock;
587bf496 1210 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
e64e739e
VS		 1211
1212 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1213 return MODE_NO_DBLESCAN;
697c4078 1214
e64e739e 1215 clock = mode->clock;
587bf496
MK		 1216
1217 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1218 clock *= 2;
1219
1220 if (clock > max_dotclk)
1221 return MODE_CLOCK_HIGH;
1222
697c4078
CT		 1223 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1224 clock *= 2;
1225
e64e739e
VS		 1226 /* check if we can do 8bpc */
1227 status = hdmi_port_clock_valid(hdmi, clock, true);
7d57382e 1228
e64e739e
VS		 1229 /* if we can't do 8bpc we may still be able to do 12bpc */
1230 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1231 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
7d57382e 1232
e64e739e 1233 return status;
7d57382e
EA		 1234}
1235
77f06c86 1236static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
71800632 1237{
77f06c86
ACO		 1238 struct drm_device *dev = crtc_state->base.crtc->dev;
1239 struct drm_atomic_state *state;
71800632 1240 struct intel_encoder *encoder;
da3ced29 1241 struct drm_connector *connector;
77f06c86 1242 struct drm_connector_state *connector_state;
71800632 1243 int count = 0, count_hdmi = 0;
77f06c86 1244 int i;
71800632 1245
f227ae9e 1246 if (HAS_GMCH_DISPLAY(dev))
71800632
VS		 1247 return false;
1248
77f06c86
ACO		 1249 state = crtc_state->base.state;
1250
da3ced29 1251 for_each_connector_in_state(state, connector, connector_state, i) {
77f06c86
ACO		 1252 if (connector_state->crtc != crtc_state->base.crtc)
1253 continue;
1254
1255 encoder = to_intel_encoder(connector_state->best_encoder);
1256
71800632
VS		 1257 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1258 count++;
1259 }
1260
1261 /*
1262 * HDMI 12bpc affects the clocks, so it's only possible
1263 * when not cloning with other encoder types.
1264 */
1265 return count_hdmi > 0 && count_hdmi == count;
1266}
1267
5bfe2ac0 1268bool intel_hdmi_compute_config(struct intel_encoder *encoder,
5cec258b 1269 struct intel_crtc_state *pipe_config)
7d57382e 1270{
5bfe2ac0
DV		 1271 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1272 struct drm_device *dev = encoder->base.dev;
2d112de7 1273 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
e64e739e
VS		 1274 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1275 int clock_12bpc = clock_8bpc * 3 / 2;
e29c22c0 1276 int desired_bpp;
3685a8f3 1277
6897b4b5
DV		 1278 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1279
e43823ec
JB		 1280 if (pipe_config->has_hdmi_sink)
1281 pipe_config->has_infoframe = true;
1282
55bc60db
VS		 1283 if (intel_hdmi->color_range_auto) {
1284 /* See CEA-861-E - 5.1 Default Encoding Parameters */
0f2a2a75
VS		 1285 pipe_config->limited_color_range =
1286 pipe_config->has_hdmi_sink &&
1287 drm_match_cea_mode(adjusted_mode) > 1;
1288 } else {
1289 pipe_config->limited_color_range =
1290 intel_hdmi->limited_color_range;
55bc60db
VS		 1291 }
1292
697c4078
CT		 1293 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1294 pipe_config->pixel_multiplier = 2;
e64e739e 1295 clock_8bpc *= 2;
3320e37f 1296 clock_12bpc *= 2;
697c4078
CT		 1297 }
1298
5bfe2ac0
DV		 1299 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1300 pipe_config->has_pch_encoder = true;
1301
9ed109a7
DV		 1302 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1303 pipe_config->has_audio = true;
1304
4e53c2e0
DV		 1305 /*
1306 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1307 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
325b9d04
DV		 1308 * outputs. We also need to check that the higher clock still fits
1309 * within limits.
4e53c2e0 1310 */
6897b4b5 1311 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
e64e739e 1312 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
7a0baa62 1313 hdmi_12bpc_possible(pipe_config)) {
e29c22c0
DV		 1314 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1315 desired_bpp = 12*3;
325b9d04
DV		 1316
1317 /* Need to adjust the port link by 1.5x for 12bpc. */
ff9a6750 1318 pipe_config->port_clock = clock_12bpc;
4e53c2e0 1319 } else {
e29c22c0
DV		 1320 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1321 desired_bpp = 8*3;
e64e739e
VS		 1322
1323 pipe_config->port_clock = clock_8bpc;
e29c22c0
DV		 1324 }
1325
1326 if (!pipe_config->bw_constrained) {
1327 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1328 pipe_config->pipe_bpp = desired_bpp;
4e53c2e0
DV		 1329 }
1330
e64e739e
VS		 1331 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1332 false) != MODE_OK) {
1333 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
325b9d04
DV		 1334 return false;
1335 }
1336
28b468a0
VS		 1337 /* Set user selected PAR to incoming mode's member */
1338 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1339
7d57382e
EA		 1340 return true;
1341}
1342
953ece69
CW		 1343static void
1344intel_hdmi_unset_edid(struct drm_connector *connector)
9dff6af8 1345{
df0e9248 1346 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
9dff6af8 1347
953ece69
CW		 1348 intel_hdmi->has_hdmi_sink = false;
1349 intel_hdmi->has_audio = false;
1350 intel_hdmi->rgb_quant_range_selectable = false;
1351
1352 kfree(to_intel_connector(connector)->detect_edid);
1353 to_intel_connector(connector)->detect_edid = NULL;
1354}
1355
1356static bool
237ed86c 1357intel_hdmi_set_edid(struct drm_connector *connector, bool force)
953ece69
CW		 1358{
1359 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1360 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
237ed86c 1361 struct edid *edid = NULL;
953ece69 1362 bool connected = false;
164c8598 1363
69172f21
ID		 1364 if (force) {
1365 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
671dedd2 1366
237ed86c
SJ		 1367 edid = drm_get_edid(connector,
1368 intel_gmbus_get_adapter(dev_priv,
1369 intel_hdmi->ddc_bus));
2ded9e27 1370
69172f21
ID		 1371 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1372 }
30ad48b7 1373
953ece69
CW		 1374 to_intel_connector(connector)->detect_edid = edid;
1375 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1376 intel_hdmi->rgb_quant_range_selectable =
1377 drm_rgb_quant_range_selectable(edid);
1378
1379 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
b1d7e4b4
WF		 1380 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1381 intel_hdmi->has_audio =
953ece69
CW		 1382 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1383
1384 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1385 intel_hdmi->has_hdmi_sink =
1386 drm_detect_hdmi_monitor(edid);
1387
1388 connected = true;
55b7d6e8
CW		 1389 }
1390
953ece69
CW		 1391 return connected;
1392}
1393
8166fcea
DV		 1394static enum drm_connector_status
1395intel_hdmi_detect(struct drm_connector *connector, bool force)
953ece69 1396{
8166fcea
DV		 1397 enum drm_connector_status status;
1398 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1399 struct drm_i915_private *dev_priv = to_i915(connector->dev);
237ed86c 1400 bool live_status = false;
61fb3980 1401 unsigned int try;
953ece69 1402
8166fcea
DV		 1403 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1404 connector->base.id, connector->name);
1405
29bb94bb
ID		 1406 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1407
f8d03ea0 1408 for (try = 0; !live_status && try < 9; try++) {
61fb3980
GW		 1409 if (try)
1410 msleep(10);
237ed86c
SJ		 1411 live_status = intel_digital_port_connected(dev_priv,
1412 hdmi_to_dig_port(intel_hdmi));
237ed86c
SJ		 1413 }
1414
4f4a8185
SS		 1415 if (!live_status) {
1416 DRM_DEBUG_KMS("HDMI live status down\n");
1417 /*
1418 * Live status register is not reliable on all intel platforms.
1419 * So consider live_status only for certain platforms, for
1420 * others, read EDID to determine presence of sink.
1421 */
1422 if (INTEL_INFO(dev_priv)->gen < 7 || IS_IVYBRIDGE(dev_priv))
1423 live_status = true;
1424 }
237ed86c 1425
8166fcea 1426 intel_hdmi_unset_edid(connector);
0b5e88dc 1427
8166fcea 1428 if (intel_hdmi_set_edid(connector, live_status)) {
953ece69
CW		 1429 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1430
1431 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1432 status = connector_status_connected;
8166fcea 1433 } else
953ece69 1434 status = connector_status_disconnected;
671dedd2 1435
29bb94bb
ID		 1436 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1437
2ded9e27 1438 return status;
7d57382e
EA		 1439}
1440
953ece69
CW		 1441static void
1442intel_hdmi_force(struct drm_connector *connector)
7d57382e 1443{
953ece69 1444 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
7d57382e 1445
953ece69
CW		 1446 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1447 connector->base.id, connector->name);
7d57382e 1448
953ece69 1449 intel_hdmi_unset_edid(connector);
671dedd2 1450
953ece69
CW		 1451 if (connector->status != connector_status_connected)
1452 return;
671dedd2 1453
237ed86c 1454 intel_hdmi_set_edid(connector, true);
953ece69
CW		 1455 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1456}
671dedd2 1457
953ece69
CW		 1458static int intel_hdmi_get_modes(struct drm_connector *connector)
1459{
1460 struct edid *edid;
1461
1462 edid = to_intel_connector(connector)->detect_edid;
1463 if (edid == NULL)
1464 return 0;
671dedd2 1465
953ece69 1466 return intel_connector_update_modes(connector, edid);
7d57382e
EA		 1467}
1468
1aad7ac0
CW		 1469static bool
1470intel_hdmi_detect_audio(struct drm_connector *connector)
1471{
1aad7ac0 1472 bool has_audio = false;
953ece69 1473 struct edid *edid;
1aad7ac0 1474
953ece69
CW		 1475 edid = to_intel_connector(connector)->detect_edid;
1476 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1477 has_audio = drm_detect_monitor_audio(edid);
671dedd2 1478
1aad7ac0
CW		 1479 return has_audio;
1480}
1481
55b7d6e8
CW		 1482static int
1483intel_hdmi_set_property(struct drm_connector *connector,
ed517fbb
PZ		 1484 struct drm_property *property,
1485 uint64_t val)
55b7d6e8
CW		 1486{
1487 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
da63a9f2
PZ		 1488 struct intel_digital_port *intel_dig_port =
1489 hdmi_to_dig_port(intel_hdmi);
e953fd7b 1490 struct drm_i915_private *dev_priv = connector->dev->dev_private;
55b7d6e8
CW		 1491 int ret;
1492
662595df 1493 ret = drm_object_property_set_value(&connector->base, property, val);
55b7d6e8
CW		 1494 if (ret)
1495 return ret;
1496
3f43c48d 1497 if (property == dev_priv->force_audio_property) {
b1d7e4b4 1498 enum hdmi_force_audio i = val;
1aad7ac0
CW		 1499 bool has_audio;
1500
1501 if (i == intel_hdmi->force_audio)
55b7d6e8
CW		 1502 return 0;
1503
1aad7ac0 1504 intel_hdmi->force_audio = i;
55b7d6e8 1505
b1d7e4b4 1506 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1507 has_audio = intel_hdmi_detect_audio(connector);
1508 else
b1d7e4b4 1509 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0 1510
b1d7e4b4
WF		 1511 if (i == HDMI_AUDIO_OFF_DVI)
1512 intel_hdmi->has_hdmi_sink = 0;
55b7d6e8 1513
1aad7ac0 1514 intel_hdmi->has_audio = has_audio;
55b7d6e8
CW		 1515 goto done;
1516 }
1517
e953fd7b 1518 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80 1519 bool old_auto = intel_hdmi->color_range_auto;
0f2a2a75 1520 bool old_range = intel_hdmi->limited_color_range;
ae4edb80 1521
55bc60db
VS		 1522 switch (val) {
1523 case INTEL_BROADCAST_RGB_AUTO:
1524 intel_hdmi->color_range_auto = true;
1525 break;
1526 case INTEL_BROADCAST_RGB_FULL:
1527 intel_hdmi->color_range_auto = false;
0f2a2a75 1528 intel_hdmi->limited_color_range = false;
55bc60db
VS		 1529 break;
1530 case INTEL_BROADCAST_RGB_LIMITED:
1531 intel_hdmi->color_range_auto = false;
0f2a2a75 1532 intel_hdmi->limited_color_range = true;
55bc60db
VS		 1533 break;
1534 default:
1535 return -EINVAL;
1536 }
ae4edb80
DV		 1537
1538 if (old_auto == intel_hdmi->color_range_auto &&
0f2a2a75 1539 old_range == intel_hdmi->limited_color_range)
ae4edb80
DV		 1540 return 0;
1541
e953fd7b
CW		 1542 goto done;
1543 }
1544
94a11ddc
VK		 1545 if (property == connector->dev->mode_config.aspect_ratio_property) {
1546 switch (val) {
1547 case DRM_MODE_PICTURE_ASPECT_NONE:
1548 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1549 break;
1550 case DRM_MODE_PICTURE_ASPECT_4_3:
1551 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1552 break;
1553 case DRM_MODE_PICTURE_ASPECT_16_9:
1554 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1555 break;
1556 default:
1557 return -EINVAL;
1558 }
1559 goto done;
1560 }
1561
55b7d6e8
CW		 1562 return -EINVAL;
1563
1564done:
c0c36b94
CW		 1565 if (intel_dig_port->base.base.crtc)
1566 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
55b7d6e8
CW		 1567
1568 return 0;
1569}
1570
13732ba7
JB		 1571static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1572{
1573 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1574 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
7c5f93b0 1575 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
13732ba7 1576
4cde8a21
DV		 1577 intel_hdmi_prepare(encoder);
1578
6897b4b5 1579 intel_hdmi->set_infoframes(&encoder->base,
6e3c9717 1580 intel_crtc->config->has_hdmi_sink,
6897b4b5 1581 adjusted_mode);
13732ba7
JB		 1582}
1583
9514ac6e 1584static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
89b667f8
JB		 1585{
1586 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
13732ba7 1587 struct intel_hdmi *intel_hdmi = &dport->hdmi;
89b667f8
JB		 1588 struct drm_device *dev = encoder->base.dev;
1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 struct intel_crtc *intel_crtc =
1591 to_intel_crtc(encoder->base.crtc);
7c5f93b0 1592 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
e4607fcf 1593 enum dpio_channel port = vlv_dport_to_channel(dport);
89b667f8
JB		 1594 int pipe = intel_crtc->pipe;
1595 u32 val;
1596
89b667f8 1597 /* Enable clock channels for this port */
a580516d 1598 mutex_lock(&dev_priv->sb_lock);
ab3c759a 1599 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
89b667f8
JB		 1600 val = 0;
1601 if (pipe)
1602 val |= (1<<21);
1603 else
1604 val &= ~(1<<21);
1605 val |= 0x001000c4;
ab3c759a 1606 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
89b667f8
JB		 1607
1608 /* HDMI 1.0V-2dB */
ab3c759a
CML		 1609 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1610 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1611 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1612 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1613 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1614 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1615 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1616 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
89b667f8
JB		 1617
1618 /* Program lane clock */
ab3c759a
CML		 1619 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1620 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
a580516d 1621 mutex_unlock(&dev_priv->sb_lock);
b76cf76b 1622
6897b4b5 1623 intel_hdmi->set_infoframes(&encoder->base,
6e3c9717 1624 intel_crtc->config->has_hdmi_sink,
6897b4b5 1625 adjusted_mode);
13732ba7 1626
bf868c7d 1627 g4x_enable_hdmi(encoder);
b76cf76b 1628
9b6de0a1 1629 vlv_wait_port_ready(dev_priv, dport, 0x0);
89b667f8
JB		 1630}
1631
9514ac6e 1632static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 1633{
1634 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1635 struct drm_device *dev = encoder->base.dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 1637 struct intel_crtc *intel_crtc =
1638 to_intel_crtc(encoder->base.crtc);
e4607fcf 1639 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1640 int pipe = intel_crtc->pipe;
89b667f8 1641
4cde8a21
DV		 1642 intel_hdmi_prepare(encoder);
1643
89b667f8 1644 /* Program Tx lane resets to default */
a580516d 1645 mutex_lock(&dev_priv->sb_lock);
ab3c759a 1646 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 1647 DPIO_PCS_TX_LANE2_RESET |
1648 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 1649 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 1650 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1651 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1652 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1653 DPIO_PCS_CLK_SOFT_RESET);
1654
1655 /* Fix up inter-pair skew failure */
ab3c759a
CML		 1656 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1657 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1658 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1659
1660 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1661 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
a580516d 1662 mutex_unlock(&dev_priv->sb_lock);
89b667f8
JB		 1663}
1664
a8f327fb
VS		 1665static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1666 bool reset)
1667{
1668 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1669 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1670 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1671 enum pipe pipe = crtc->pipe;
1672 uint32_t val;
1673
1674 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1675 if (reset)
1676 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1677 else
1678 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1679 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1680
1681 if (crtc->config->lane_count > 2) {
1682 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1683 if (reset)
1684 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1685 else
1686 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1687 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1688 }
1689
1690 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1691 val |= CHV_PCS_REQ_SOFTRESET_EN;
1692 if (reset)
1693 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1694 else
1695 val |= DPIO_PCS_CLK_SOFT_RESET;
1696 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1697
1698 if (crtc->config->lane_count > 2) {
1699 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1700 val |= CHV_PCS_REQ_SOFTRESET_EN;
1701 if (reset)
1702 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1703 else
1704 val |= DPIO_PCS_CLK_SOFT_RESET;
1705 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1706 }
1707}
1708
9197c88b
VS		 1709static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1710{
1711 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1712 struct drm_device *dev = encoder->base.dev;
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1714 struct intel_crtc *intel_crtc =
1715 to_intel_crtc(encoder->base.crtc);
1716 enum dpio_channel ch = vlv_dport_to_channel(dport);
1717 enum pipe pipe = intel_crtc->pipe;
1718 u32 val;
1719
625695f8
VS		 1720 intel_hdmi_prepare(encoder);
1721
b0b33846
VS		 1722 /*
1723 * Must trick the second common lane into life.
1724 * Otherwise we can't even access the PLL.
1725 */
1726 if (ch == DPIO_CH0 && pipe == PIPE_B)
1727 dport->release_cl2_override =
1728 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1729
e0fce78f
VS		 1730 chv_phy_powergate_lanes(encoder, true, 0x0);
1731
a580516d 1732 mutex_lock(&dev_priv->sb_lock);
9197c88b 1733
a8f327fb
VS		 1734 /* Assert data lane reset */
1735 chv_data_lane_soft_reset(encoder, true);
1736
b9e5ac3c
VS		 1737 /* program left/right clock distribution */
1738 if (pipe != PIPE_B) {
1739 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1740 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1741 if (ch == DPIO_CH0)
1742 val |= CHV_BUFLEFTENA1_FORCE;
1743 if (ch == DPIO_CH1)
1744 val |= CHV_BUFRIGHTENA1_FORCE;
1745 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1746 } else {
1747 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1748 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1749 if (ch == DPIO_CH0)
1750 val |= CHV_BUFLEFTENA2_FORCE;
1751 if (ch == DPIO_CH1)
1752 val |= CHV_BUFRIGHTENA2_FORCE;
1753 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1754 }
1755
9197c88b
VS		 1756 /* program clock channel usage */
1757 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1758 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1759 if (pipe != PIPE_B)
1760 val &= ~CHV_PCS_USEDCLKCHANNEL;
1761 else
1762 val |= CHV_PCS_USEDCLKCHANNEL;
1763 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1764
1765 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1766 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1767 if (pipe != PIPE_B)
1768 val &= ~CHV_PCS_USEDCLKCHANNEL;
1769 else
1770 val |= CHV_PCS_USEDCLKCHANNEL;
1771 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1772
1773 /*
1774 * This a a bit weird since generally CL
1775 * matches the pipe, but here we need to
1776 * pick the CL based on the port.
1777 */
1778 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1779 if (pipe != PIPE_B)
1780 val &= ~CHV_CMN_USEDCLKCHANNEL;
1781 else
1782 val |= CHV_CMN_USEDCLKCHANNEL;
1783 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1784
a580516d 1785 mutex_unlock(&dev_priv->sb_lock);
9197c88b
VS		 1786}
1787
d6db995f
VS		 1788static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1789{
1790 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1791 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1792 u32 val;
1793
1794 mutex_lock(&dev_priv->sb_lock);
1795
1796 /* disable left/right clock distribution */
1797 if (pipe != PIPE_B) {
1798 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1799 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1800 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1801 } else {
1802 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1803 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1804 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1805 }
1806
1807 mutex_unlock(&dev_priv->sb_lock);
e0fce78f 1808
b0b33846
VS		 1809 /*
1810 * Leave the power down bit cleared for at least one
1811 * lane so that chv_powergate_phy_ch() will power
1812 * on something when the channel is otherwise unused.
1813 * When the port is off and the override is removed
1814 * the lanes power down anyway, so otherwise it doesn't
1815 * really matter what the state of power down bits is
1816 * after this.
1817 */
e0fce78f 1818 chv_phy_powergate_lanes(encoder, false, 0x0);
d6db995f
VS		 1819}
1820
9514ac6e 1821static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
89b667f8
JB		 1822{
1823 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1824 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
5e69f97f
CML		 1825 struct intel_crtc *intel_crtc =
1826 to_intel_crtc(encoder->base.crtc);
e4607fcf 1827 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 1828 int pipe = intel_crtc->pipe;
89b667f8
JB		 1829
1830 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
a580516d 1831 mutex_lock(&dev_priv->sb_lock);
ab3c759a
CML		 1832 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1833 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
a580516d 1834 mutex_unlock(&dev_priv->sb_lock);
89b667f8
JB		 1835}
1836
580d3811
VS		 1837static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1838{
580d3811
VS		 1839 struct drm_device *dev = encoder->base.dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
580d3811 1841
a580516d 1842 mutex_lock(&dev_priv->sb_lock);
580d3811 1843
a8f327fb
VS		 1844 /* Assert data lane reset */
1845 chv_data_lane_soft_reset(encoder, true);
580d3811 1846
a580516d 1847 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 1848}
1849
e4a1d846
CML		 1850static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1851{
1852 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
b4eb1564 1853 struct intel_hdmi *intel_hdmi = &dport->hdmi;
e4a1d846
CML		 1854 struct drm_device *dev = encoder->base.dev;
1855 struct drm_i915_private *dev_priv = dev->dev_private;
1856 struct intel_crtc *intel_crtc =
1857 to_intel_crtc(encoder->base.crtc);
7c5f93b0 1858 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
e4a1d846
CML		 1859 enum dpio_channel ch = vlv_dport_to_channel(dport);
1860 int pipe = intel_crtc->pipe;
2e523e98 1861 int data, i, stagger;
e4a1d846
CML		 1862 u32 val;
1863
a580516d 1864 mutex_lock(&dev_priv->sb_lock);
949c1d43 1865
570e2a74
VS		 1866 /* allow hardware to manage TX FIFO reset source */
1867 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1868 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1869 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1870
1871 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1872 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1873 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1874
949c1d43 1875 /* Program Tx latency optimal setting */
e4a1d846 1876 for (i = 0; i < 4; i++) {
e4a1d846
CML		 1877 /* Set the upar bit */
1878 data = (i == 1) ? 0x0 : 0x1;
1879 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1880 data << DPIO_UPAR_SHIFT);
1881 }
1882
1883 /* Data lane stagger programming */
2e523e98
VS		 1884 if (intel_crtc->config->port_clock > 270000)
1885 stagger = 0x18;
1886 else if (intel_crtc->config->port_clock > 135000)
1887 stagger = 0xd;
1888 else if (intel_crtc->config->port_clock > 67500)
1889 stagger = 0x7;
1890 else if (intel_crtc->config->port_clock > 33750)
1891 stagger = 0x4;
1892 else
1893 stagger = 0x2;
1894
1895 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1896 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1897 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1898
1899 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1900 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1901 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1902
1903 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1904 DPIO_LANESTAGGER_STRAP(stagger) |
1905 DPIO_LANESTAGGER_STRAP_OVRD |
1906 DPIO_TX1_STAGGER_MASK(0x1f) |
1907 DPIO_TX1_STAGGER_MULT(6) |
1908 DPIO_TX2_STAGGER_MULT(0));
1909
1910 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1911 DPIO_LANESTAGGER_STRAP(stagger) |
1912 DPIO_LANESTAGGER_STRAP_OVRD |
1913 DPIO_TX1_STAGGER_MASK(0x1f) |
1914 DPIO_TX1_STAGGER_MULT(7) |
1915 DPIO_TX2_STAGGER_MULT(5));
e4a1d846 1916
a8f327fb
VS		 1917 /* Deassert data lane reset */
1918 chv_data_lane_soft_reset(encoder, false);
1919
e4a1d846 1920 /* Clear calc init */
1966e59e
VS		 1921 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1922 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 1923 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1924 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e
VS		 1925 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1926
1927 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1928 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
a02ef3c7
VS		 1929 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1930 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1966e59e 1931 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 1932
a02ef3c7
VS		 1933 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1934 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1935 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1936 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1937
1938 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1939 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1940 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1941 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1942
e4a1d846
CML		 1943 /* FIXME: Program the support xxx V-dB */
1944 /* Use 800mV-0dB */
f72df8db
VS		 1945 for (i = 0; i < 4; i++) {
1946 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1947 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1948 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1949 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1950 }
e4a1d846 1951
f72df8db
VS		 1952 for (i = 0; i < 4; i++) {
1953 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
67fa24b4 1954
1fb44505
VS		 1955 val &= ~DPIO_SWING_MARGIN000_MASK;
1956 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
67fa24b4
VS		 1957
1958 /*
1959 * Supposedly this value shouldn't matter when unique transition
1960 * scale is disabled, but in fact it does matter. Let's just
1961 * always program the same value and hope it's OK.
1962 */
1963 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1964 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1965
f72df8db
VS		 1966 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1967 }
e4a1d846 1968
67fa24b4
VS		 1969 /*
1970 * The document said it needs to set bit 27 for ch0 and bit 26
1971 * for ch1. Might be a typo in the doc.
1972 * For now, for this unique transition scale selection, set bit
1973 * 27 for ch0 and ch1.
1974 */
f72df8db
VS		 1975 for (i = 0; i < 4; i++) {
1976 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1977 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1978 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1979 }
e4a1d846 1980
e4a1d846 1981 /* Start swing calculation */
1966e59e
VS		 1982 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1983 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1984 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1985
1986 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1987 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1988 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846 1989
a580516d 1990 mutex_unlock(&dev_priv->sb_lock);
e4a1d846 1991
b4eb1564 1992 intel_hdmi->set_infoframes(&encoder->base,
6e3c9717 1993 intel_crtc->config->has_hdmi_sink,
b4eb1564
CT		 1994 adjusted_mode);
1995
bf868c7d 1996 g4x_enable_hdmi(encoder);
e4a1d846 1997
9b6de0a1 1998 vlv_wait_port_ready(dev_priv, dport, 0x0);
b0b33846
VS		 1999
2000 /* Second common lane will stay alive on its own now */
2001 if (dport->release_cl2_override) {
2002 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
2003 dport->release_cl2_override = false;
2004 }
e4a1d846
CML		 2005}
2006
7d57382e
EA		 2007static void intel_hdmi_destroy(struct drm_connector *connector)
2008{
10e972d3 2009 kfree(to_intel_connector(connector)->detect_edid);
7d57382e 2010 drm_connector_cleanup(connector);
674e2d08 2011 kfree(connector);
7d57382e
EA		 2012}
2013
7d57382e 2014static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
4d688a2a 2015 .dpms = drm_atomic_helper_connector_dpms,
7d57382e 2016 .detect = intel_hdmi_detect,
953ece69 2017 .force = intel_hdmi_force,
7d57382e 2018 .fill_modes = drm_helper_probe_single_connector_modes,
55b7d6e8 2019 .set_property = intel_hdmi_set_property,
2545e4a6 2020 .atomic_get_property = intel_connector_atomic_get_property,
7d57382e 2021 .destroy = intel_hdmi_destroy,
c6f95f27 2022 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 2023 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
7d57382e
EA		 2024};
2025
2026static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2027 .get_modes = intel_hdmi_get_modes,
2028 .mode_valid = intel_hdmi_mode_valid,
df0e9248 2029 .best_encoder = intel_best_encoder,
7d57382e
EA		 2030};
2031
7d57382e 2032static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
ea5b213a 2033 .destroy = intel_encoder_destroy,
7d57382e
EA		 2034};
2035
55b7d6e8
CW		 2036static void
2037intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2038{
3f43c48d 2039 intel_attach_force_audio_property(connector);
e953fd7b 2040 intel_attach_broadcast_rgb_property(connector);
55bc60db 2041 intel_hdmi->color_range_auto = true;
94a11ddc
VK		 2042 intel_attach_aspect_ratio_property(connector);
2043 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
55b7d6e8
CW		 2044}
2045
00c09d70
PZ		 2046void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2047 struct intel_connector *intel_connector)
7d57382e 2048{
b9cb234c
PZ		 2049 struct drm_connector *connector = &intel_connector->base;
2050 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2051 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2052 struct drm_device *dev = intel_encoder->base.dev;
7d57382e 2053 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2054 enum port port = intel_dig_port->port;
11c1b657 2055 uint8_t alternate_ddc_pin;
373a3cf7 2056
ccb1a831
VS		 2057 if (WARN(intel_dig_port->max_lanes < 4,
2058 "Not enough lanes (%d) for HDMI on port %c\n",
2059 intel_dig_port->max_lanes, port_name(port)))
2060 return;
2061
7d57382e 2062 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
8d91104a 2063 DRM_MODE_CONNECTOR_HDMIA);
7d57382e
EA		 2064 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2065
c3febcc4 2066 connector->interlace_allowed = 1;
7d57382e 2067 connector->doublescan_allowed = 0;
573e74ad 2068 connector->stereo_allowed = 1;
66a9278e 2069
08d644ad
DV		 2070 switch (port) {
2071 case PORT_B:
4c272834
JN		 2072 if (IS_BROXTON(dev_priv))
2073 intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT;
2074 else
2075 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
cf1d5883
SJ		 2076 /*
2077 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2078 * interrupts to check the external panel connection.
2079 */
e87a005d 2080 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
cf1d5883
SJ		 2081 intel_encoder->hpd_pin = HPD_PORT_A;
2082 else
2083 intel_encoder->hpd_pin = HPD_PORT_B;
08d644ad
DV		 2084 break;
2085 case PORT_C:
4c272834
JN		 2086 if (IS_BROXTON(dev_priv))
2087 intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT;
2088 else
2089 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
1d843f9d 2090 intel_encoder->hpd_pin = HPD_PORT_C;
08d644ad
DV		 2091 break;
2092 case PORT_D:
4c272834
JN		 2093 if (WARN_ON(IS_BROXTON(dev_priv)))
2094 intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED;
2095 else if (IS_CHERRYVIEW(dev_priv))
988c7015 2096 intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV;
c0c35329 2097 else
988c7015 2098 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
1d843f9d 2099 intel_encoder->hpd_pin = HPD_PORT_D;
08d644ad 2100 break;
11c1b657
XZ		 2101 case PORT_E:
2102 /* On SKL PORT E doesn't have seperate GMBUS pin
2103 * We rely on VBT to set a proper alternate GMBUS pin. */
2104 alternate_ddc_pin =
2105 dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin;
2106 switch (alternate_ddc_pin) {
2107 case DDC_PIN_B:
2108 intel_hdmi->ddc_bus = GMBUS_PIN_DPB;
2109 break;
2110 case DDC_PIN_C:
2111 intel_hdmi->ddc_bus = GMBUS_PIN_DPC;
2112 break;
2113 case DDC_PIN_D:
2114 intel_hdmi->ddc_bus = GMBUS_PIN_DPD;
2115 break;
2116 default:
2117 MISSING_CASE(alternate_ddc_pin);
2118 }
2119 intel_encoder->hpd_pin = HPD_PORT_E;
2120 break;
08d644ad 2121 case PORT_A:
1d843f9d 2122 intel_encoder->hpd_pin = HPD_PORT_A;
08d644ad
DV		 2123 /* Internal port only for eDP. */
2124 default:
6e4c1677 2125 BUG();
f8aed700 2126 }
7d57382e 2127
666a4537 2128 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
90b107c8 2129 intel_hdmi->write_infoframe = vlv_write_infoframe;
687f4d06 2130 intel_hdmi->set_infoframes = vlv_set_infoframes;
e43823ec 2131 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
b98856a8 2132 } else if (IS_G4X(dev)) {
7637bfdb
JB		 2133 intel_hdmi->write_infoframe = g4x_write_infoframe;
2134 intel_hdmi->set_infoframes = g4x_set_infoframes;
e43823ec 2135 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
22b8bf17 2136 } else if (HAS_DDI(dev)) {
8c5f5f7c 2137 intel_hdmi->write_infoframe = hsw_write_infoframe;
687f4d06 2138 intel_hdmi->set_infoframes = hsw_set_infoframes;
e43823ec 2139 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
fdf1250a
PZ		 2140 } else if (HAS_PCH_IBX(dev)) {
2141 intel_hdmi->write_infoframe = ibx_write_infoframe;
687f4d06 2142 intel_hdmi->set_infoframes = ibx_set_infoframes;
e43823ec 2143 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
fdf1250a
PZ		 2144 } else {
2145 intel_hdmi->write_infoframe = cpt_write_infoframe;
687f4d06 2146 intel_hdmi->set_infoframes = cpt_set_infoframes;
e43823ec 2147 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
64a8fc01 2148 }
45187ace 2149
affa9354 2150 if (HAS_DDI(dev))
bcbc889b
PZ		 2151 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2152 else
2153 intel_connector->get_hw_state = intel_connector_get_hw_state;
4932e2c3 2154 intel_connector->unregister = intel_connector_unregister;
b9cb234c
PZ		 2155
2156 intel_hdmi_add_properties(intel_hdmi, connector);
2157
2158 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 2159 drm_connector_register(connector);
d8b4c43a 2160 intel_hdmi->attached_connector = intel_connector;
b9cb234c
PZ		 2161
2162 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2163 * 0xd. Failure to do so will result in spurious interrupts being
2164 * generated on the port when a cable is not attached.
2165 */
2166 if (IS_G4X(dev) && !IS_GM45(dev)) {
2167 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2168 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2169 }
2170}
2171
f0f59a00
VS		 2172void intel_hdmi_init(struct drm_device *dev,
2173 i915_reg_t hdmi_reg, enum port port)
b9cb234c
PZ		 2174{
2175 struct intel_digital_port *intel_dig_port;
2176 struct intel_encoder *intel_encoder;
b9cb234c
PZ		 2177 struct intel_connector *intel_connector;
2178
b14c5679 2179 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
b9cb234c
PZ		 2180 if (!intel_dig_port)
2181 return;
2182
08d9bc92 2183 intel_connector = intel_connector_alloc();
b9cb234c
PZ		 2184 if (!intel_connector) {
2185 kfree(intel_dig_port);
2186 return;
2187 }
2188
2189 intel_encoder = &intel_dig_port->base;
b9cb234c
PZ		 2190
2191 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
13a3d91f 2192 DRM_MODE_ENCODER_TMDS, NULL);
00c09d70 2193
5bfe2ac0 2194 intel_encoder->compute_config = intel_hdmi_compute_config;
a4790cec
VS		 2195 if (HAS_PCH_SPLIT(dev)) {
2196 intel_encoder->disable = pch_disable_hdmi;
2197 intel_encoder->post_disable = pch_post_disable_hdmi;
2198 } else {
2199 intel_encoder->disable = g4x_disable_hdmi;
2200 }
00c09d70 2201 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
045ac3b5 2202 intel_encoder->get_config = intel_hdmi_get_config;
e4a1d846 2203 if (IS_CHERRYVIEW(dev)) {
9197c88b 2204 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
e4a1d846
CML		 2205 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2206 intel_encoder->enable = vlv_enable_hdmi;
580d3811 2207 intel_encoder->post_disable = chv_hdmi_post_disable;
d6db995f 2208 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
e4a1d846 2209 } else if (IS_VALLEYVIEW(dev)) {
9514ac6e
CML		 2210 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2211 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
b76cf76b 2212 intel_encoder->enable = vlv_enable_hdmi;
9514ac6e 2213 intel_encoder->post_disable = vlv_hdmi_post_disable;
b76cf76b 2214 } else {
13732ba7 2215 intel_encoder->pre_enable = intel_hdmi_pre_enable;
d1b1589c
VS		 2216 if (HAS_PCH_CPT(dev))
2217 intel_encoder->enable = cpt_enable_hdmi;
bf868c7d
VS		 2218 else if (HAS_PCH_IBX(dev))
2219 intel_encoder->enable = ibx_enable_hdmi;
d1b1589c 2220 else
bf868c7d 2221 intel_encoder->enable = g4x_enable_hdmi;
89b667f8 2222 }
5ab432ef 2223
b9cb234c 2224 intel_encoder->type = INTEL_OUTPUT_HDMI;
882ec384
VS		 2225 if (IS_CHERRYVIEW(dev)) {
2226 if (port == PORT_D)
2227 intel_encoder->crtc_mask = 1 << 2;
2228 else
2229 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2230 } else {
2231 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2232 }
301ea74a 2233 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
c6f1495d
VS		 2234 /*
2235 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2236 * to work on real hardware. And since g4x can send infoframes to
2237 * only one port anyway, nothing is lost by allowing it.
2238 */
2239 if (IS_G4X(dev))
2240 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
7d57382e 2241
174edf1f 2242 intel_dig_port->port = port;
b242b7f7 2243 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
f0f59a00 2244 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
ccb1a831 2245 intel_dig_port->max_lanes = 4;
55b7d6e8 2246
b9cb234c 2247 intel_hdmi_init_connector(intel_dig_port, intel_connector);
7d57382e 2248}
Linux 6.x block layer and io_uring tree(s)