Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
7d57382e | 29 | #include <linux/delay.h> |
178f736a | 30 | #include <linux/hdmi.h> |
331c201a JN |
31 | #include <linux/i2c.h> |
32 | #include <linux/slab.h> | |
33 | ||
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
2320175f | 37 | #include <drm/drm_hdcp.h> |
15953637 | 38 | #include <drm/drm_scdc_helper.h> |
760285e7 | 39 | #include <drm/i915_drm.h> |
46d196ec | 40 | #include <drm/intel_lpe_audio.h> |
331c201a | 41 | |
2126d3e9 | 42 | #include "i915_debugfs.h" |
7d57382e | 43 | #include "i915_drv.h" |
12392a74 | 44 | #include "intel_atomic.h" |
331c201a | 45 | #include "intel_audio.h" |
ec7f29ff | 46 | #include "intel_connector.h" |
fdc24cf3 | 47 | #include "intel_ddi.h" |
27fec1f9 | 48 | #include "intel_dp.h" |
b1ad4c39 | 49 | #include "intel_dpio_phy.h" |
331c201a | 50 | #include "intel_drv.h" |
8834e365 | 51 | #include "intel_fifo_underrun.h" |
408bd917 | 52 | #include "intel_hdcp.h" |
0550691d | 53 | #include "intel_hdmi.h" |
dbeb38d9 | 54 | #include "intel_hotplug.h" |
f3e18947 | 55 | #include "intel_lspcon.h" |
596fee14 | 56 | #include "intel_sdvo.h" |
44c1220a | 57 | #include "intel_panel.h" |
56c5098f | 58 | #include "intel_sideband.h" |
7d57382e | 59 | |
30add22d PZ |
60 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
61 | { | |
da63a9f2 | 62 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
63 | } |
64 | ||
afba0188 DV |
65 | static void |
66 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
67 | { | |
30add22d | 68 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 69 | struct drm_i915_private *dev_priv = to_i915(dev); |
faa087c4 | 70 | u32 enabled_bits; |
afba0188 | 71 | |
4f8036a2 | 72 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 73 | |
b242b7f7 | 74 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
75 | "HDMI port enabled, expecting disabled\n"); |
76 | } | |
77 | ||
8fc0aa6e ID |
78 | static void |
79 | assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, | |
80 | enum transcoder cpu_transcoder) | |
81 | { | |
82 | WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & | |
83 | TRANS_DDI_FUNC_ENABLE, | |
84 | "HDMI transcoder function enabled, expecting disabled\n"); | |
85 | } | |
86 | ||
f5bbfca3 | 87 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 88 | { |
da63a9f2 PZ |
89 | struct intel_digital_port *intel_dig_port = |
90 | container_of(encoder, struct intel_digital_port, base.base); | |
91 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
92 | } |
93 | ||
df0e9248 CW |
94 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
95 | { | |
da63a9f2 | 96 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
97 | } |
98 | ||
1d776538 | 99 | static u32 g4x_infoframe_index(unsigned int type) |
3c17fe4b | 100 | { |
178f736a | 101 | switch (type) { |
5cb3c1a1 VS |
102 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
103 | return VIDEO_DIP_SELECT_GAMUT; | |
178f736a | 104 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 105 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 106 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 107 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 110 | default: |
ffc85dab | 111 | MISSING_CASE(type); |
ed517fbb | 112 | return 0; |
45187ace | 113 | } |
45187ace JB |
114 | } |
115 | ||
1d776538 | 116 | static u32 g4x_infoframe_enable(unsigned int type) |
45187ace | 117 | { |
178f736a | 118 | switch (type) { |
5cb3c1a1 VS |
119 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
120 | return VIDEO_DIP_ENABLE_GCP; | |
121 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
122 | return VIDEO_DIP_ENABLE_GAMUT; | |
509efa2b VS |
123 | case DP_SDP_VSC: |
124 | return 0; | |
178f736a | 125 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 126 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 127 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 128 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
129 | case HDMI_INFOFRAME_TYPE_VENDOR: |
130 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 131 | default: |
ffc85dab | 132 | MISSING_CASE(type); |
ed517fbb | 133 | return 0; |
fa193ff7 | 134 | } |
fa193ff7 PZ |
135 | } |
136 | ||
1d776538 | 137 | static u32 hsw_infoframe_enable(unsigned int type) |
2da8af54 | 138 | { |
178f736a | 139 | switch (type) { |
5cb3c1a1 VS |
140 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
141 | return VIDEO_DIP_ENABLE_GCP_HSW; | |
142 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
143 | return VIDEO_DIP_ENABLE_GMP_HSW; | |
1d776538 VS |
144 | case DP_SDP_VSC: |
145 | return VIDEO_DIP_ENABLE_VSC_HSW; | |
4c614831 MN |
146 | case DP_SDP_PPS: |
147 | return VDIP_ENABLE_PPS; | |
178f736a | 148 | case HDMI_INFOFRAME_TYPE_AVI: |
2da8af54 | 149 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 150 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 151 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
152 | case HDMI_INFOFRAME_TYPE_VENDOR: |
153 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 154 | default: |
ffc85dab | 155 | MISSING_CASE(type); |
2da8af54 PZ |
156 | return 0; |
157 | } | |
158 | } | |
159 | ||
f0f59a00 VS |
160 | static i915_reg_t |
161 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
162 | enum transcoder cpu_transcoder, | |
1d776538 | 163 | unsigned int type, |
f0f59a00 | 164 | int i) |
2da8af54 | 165 | { |
178f736a | 166 | switch (type) { |
5cb3c1a1 VS |
167 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
168 | return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); | |
1d776538 VS |
169 | case DP_SDP_VSC: |
170 | return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); | |
4c614831 MN |
171 | case DP_SDP_PPS: |
172 | return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); | |
178f736a | 173 | case HDMI_INFOFRAME_TYPE_AVI: |
436c6d4a | 174 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 175 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 176 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 177 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 178 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 179 | default: |
ffc85dab | 180 | MISSING_CASE(type); |
f0f59a00 | 181 | return INVALID_MMIO_REG; |
2da8af54 PZ |
182 | } |
183 | } | |
184 | ||
4c614831 MN |
185 | static int hsw_dip_data_size(unsigned int type) |
186 | { | |
187 | switch (type) { | |
188 | case DP_SDP_VSC: | |
189 | return VIDEO_DIP_VSC_DATA_SIZE; | |
190 | case DP_SDP_PPS: | |
191 | return VIDEO_DIP_PPS_DATA_SIZE; | |
192 | default: | |
193 | return VIDEO_DIP_DATA_SIZE; | |
194 | } | |
195 | } | |
196 | ||
790ea70c | 197 | static void g4x_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 198 | const struct intel_crtc_state *crtc_state, |
1d776538 | 199 | unsigned int type, |
fff63867 | 200 | const void *frame, ssize_t len) |
45187ace | 201 | { |
faa087c4 | 202 | const u32 *data = frame; |
790ea70c | 203 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
22509ec8 | 204 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 205 | int i; |
3c17fe4b | 206 | |
822974ae PZ |
207 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
208 | ||
1d4f85ac | 209 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 210 | val |= g4x_infoframe_index(type); |
22509ec8 | 211 | |
178f736a | 212 | val &= ~g4x_infoframe_enable(type); |
45187ace | 213 | |
22509ec8 | 214 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 215 | |
9d9740f0 | 216 | mmiowb(); |
45187ace | 217 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
218 | I915_WRITE(VIDEO_DIP_DATA, *data); |
219 | data++; | |
220 | } | |
adf00b26 PZ |
221 | /* Write every possible data byte to force correct ECC calculation. */ |
222 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
223 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 224 | mmiowb(); |
3c17fe4b | 225 | |
178f736a | 226 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 227 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 228 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 229 | |
22509ec8 | 230 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 231 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
232 | } |
233 | ||
f2a10d61 VS |
234 | static void g4x_read_infoframe(struct intel_encoder *encoder, |
235 | const struct intel_crtc_state *crtc_state, | |
236 | unsigned int type, | |
237 | void *frame, ssize_t len) | |
238 | { | |
239 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
240 | u32 val, *data = frame; | |
241 | int i; | |
242 | ||
243 | val = I915_READ(VIDEO_DIP_CTL); | |
244 | ||
245 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
246 | val |= g4x_infoframe_index(type); | |
247 | ||
248 | I915_WRITE(VIDEO_DIP_CTL, val); | |
249 | ||
250 | for (i = 0; i < len; i += 4) | |
251 | *data++ = I915_READ(VIDEO_DIP_DATA); | |
252 | } | |
253 | ||
509efa2b | 254 | static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 255 | const struct intel_crtc_state *pipe_config) |
e43823ec | 256 | { |
790ea70c | 257 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e43823ec JB |
258 | u32 val = I915_READ(VIDEO_DIP_CTL); |
259 | ||
ec1dc603 | 260 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 261 | return 0; |
89a35ecd | 262 | |
790ea70c | 263 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 264 | return 0; |
ec1dc603 VS |
265 | |
266 | return val & (VIDEO_DIP_ENABLE_AVI | | |
267 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
268 | } |
269 | ||
790ea70c | 270 | static void ibx_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 271 | const struct intel_crtc_state *crtc_state, |
1d776538 | 272 | unsigned int type, |
fff63867 | 273 | const void *frame, ssize_t len) |
fdf1250a | 274 | { |
faa087c4 | 275 | const u32 *data = frame; |
790ea70c | 276 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 277 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 278 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 279 | u32 val = I915_READ(reg); |
f0f59a00 | 280 | int i; |
fdf1250a | 281 | |
822974ae PZ |
282 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
283 | ||
fdf1250a | 284 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 285 | val |= g4x_infoframe_index(type); |
fdf1250a | 286 | |
178f736a | 287 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
288 | |
289 | I915_WRITE(reg, val); | |
290 | ||
9d9740f0 | 291 | mmiowb(); |
fdf1250a PZ |
292 | for (i = 0; i < len; i += 4) { |
293 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
294 | data++; | |
295 | } | |
adf00b26 PZ |
296 | /* Write every possible data byte to force correct ECC calculation. */ |
297 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
298 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 299 | mmiowb(); |
fdf1250a | 300 | |
178f736a | 301 | val |= g4x_infoframe_enable(type); |
fdf1250a | 302 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 303 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
304 | |
305 | I915_WRITE(reg, val); | |
9d9740f0 | 306 | POSTING_READ(reg); |
fdf1250a PZ |
307 | } |
308 | ||
f2a10d61 VS |
309 | static void ibx_read_infoframe(struct intel_encoder *encoder, |
310 | const struct intel_crtc_state *crtc_state, | |
311 | unsigned int type, | |
312 | void *frame, ssize_t len) | |
313 | { | |
314 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
315 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
316 | u32 val, *data = frame; | |
317 | int i; | |
318 | ||
319 | val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); | |
320 | ||
321 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
322 | val |= g4x_infoframe_index(type); | |
323 | ||
324 | I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); | |
325 | ||
326 | for (i = 0; i < len; i += 4) | |
327 | *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); | |
328 | } | |
329 | ||
509efa2b | 330 | static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 331 | const struct intel_crtc_state *pipe_config) |
e43823ec | 332 | { |
790ea70c | 333 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
334 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
335 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
336 | u32 val = I915_READ(reg); |
337 | ||
ec1dc603 | 338 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 339 | return 0; |
ec1dc603 | 340 | |
790ea70c | 341 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 342 | return 0; |
052f62f7 | 343 | |
ec1dc603 VS |
344 | return val & (VIDEO_DIP_ENABLE_AVI | |
345 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
346 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
347 | } |
348 | ||
790ea70c | 349 | static void cpt_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 350 | const struct intel_crtc_state *crtc_state, |
1d776538 | 351 | unsigned int type, |
fff63867 | 352 | const void *frame, ssize_t len) |
b055c8f3 | 353 | { |
faa087c4 | 354 | const u32 *data = frame; |
790ea70c | 355 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 357 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 358 | u32 val = I915_READ(reg); |
f0f59a00 | 359 | int i; |
b055c8f3 | 360 | |
822974ae PZ |
361 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
362 | ||
64a8fc01 | 363 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 364 | val |= g4x_infoframe_index(type); |
45187ace | 365 | |
ecb97851 PZ |
366 | /* The DIP control register spec says that we need to update the AVI |
367 | * infoframe without clearing its enable bit */ | |
178f736a DL |
368 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
369 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 370 | |
22509ec8 | 371 | I915_WRITE(reg, val); |
45187ace | 372 | |
9d9740f0 | 373 | mmiowb(); |
45187ace | 374 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
375 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
376 | data++; | |
377 | } | |
adf00b26 PZ |
378 | /* Write every possible data byte to force correct ECC calculation. */ |
379 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
380 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 381 | mmiowb(); |
b055c8f3 | 382 | |
178f736a | 383 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 384 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 385 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 386 | |
22509ec8 | 387 | I915_WRITE(reg, val); |
9d9740f0 | 388 | POSTING_READ(reg); |
45187ace | 389 | } |
90b107c8 | 390 | |
f2a10d61 VS |
391 | static void cpt_read_infoframe(struct intel_encoder *encoder, |
392 | const struct intel_crtc_state *crtc_state, | |
393 | unsigned int type, | |
394 | void *frame, ssize_t len) | |
395 | { | |
396 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
397 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
398 | u32 val, *data = frame; | |
399 | int i; | |
400 | ||
401 | val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); | |
402 | ||
403 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
404 | val |= g4x_infoframe_index(type); | |
405 | ||
406 | I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); | |
407 | ||
408 | for (i = 0; i < len; i += 4) | |
409 | *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); | |
410 | } | |
411 | ||
509efa2b | 412 | static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 413 | const struct intel_crtc_state *pipe_config) |
e43823ec | 414 | { |
790ea70c | 415 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
416 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
417 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 418 | |
ec1dc603 | 419 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 420 | return 0; |
ec1dc603 VS |
421 | |
422 | return val & (VIDEO_DIP_ENABLE_AVI | | |
423 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
424 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
425 | } |
426 | ||
790ea70c | 427 | static void vlv_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 428 | const struct intel_crtc_state *crtc_state, |
1d776538 | 429 | unsigned int type, |
fff63867 | 430 | const void *frame, ssize_t len) |
90b107c8 | 431 | { |
faa087c4 | 432 | const u32 *data = frame; |
790ea70c | 433 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 434 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 435 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 436 | u32 val = I915_READ(reg); |
f0f59a00 | 437 | int i; |
90b107c8 | 438 | |
822974ae PZ |
439 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
440 | ||
90b107c8 | 441 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 442 | val |= g4x_infoframe_index(type); |
22509ec8 | 443 | |
178f736a | 444 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 445 | |
22509ec8 | 446 | I915_WRITE(reg, val); |
90b107c8 | 447 | |
9d9740f0 | 448 | mmiowb(); |
90b107c8 SK |
449 | for (i = 0; i < len; i += 4) { |
450 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
451 | data++; | |
452 | } | |
adf00b26 PZ |
453 | /* Write every possible data byte to force correct ECC calculation. */ |
454 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
455 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 456 | mmiowb(); |
90b107c8 | 457 | |
178f736a | 458 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 459 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 460 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 461 | |
22509ec8 | 462 | I915_WRITE(reg, val); |
9d9740f0 | 463 | POSTING_READ(reg); |
90b107c8 SK |
464 | } |
465 | ||
f2a10d61 VS |
466 | static void vlv_read_infoframe(struct intel_encoder *encoder, |
467 | const struct intel_crtc_state *crtc_state, | |
468 | unsigned int type, | |
469 | void *frame, ssize_t len) | |
470 | { | |
471 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
472 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
473 | u32 val, *data = frame; | |
474 | int i; | |
475 | ||
476 | val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); | |
477 | ||
478 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
479 | val |= g4x_infoframe_index(type); | |
480 | ||
481 | I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val); | |
482 | ||
483 | for (i = 0; i < len; i += 4) | |
484 | *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe)); | |
485 | } | |
486 | ||
509efa2b | 487 | static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 488 | const struct intel_crtc_state *pipe_config) |
e43823ec | 489 | { |
790ea70c | 490 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
491 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
492 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 493 | |
ec1dc603 | 494 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 495 | return 0; |
ec1dc603 | 496 | |
790ea70c | 497 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 498 | return 0; |
535afa2e | 499 | |
ec1dc603 VS |
500 | return val & (VIDEO_DIP_ENABLE_AVI | |
501 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
502 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
503 | } |
504 | ||
790ea70c | 505 | static void hsw_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 506 | const struct intel_crtc_state *crtc_state, |
1d776538 | 507 | unsigned int type, |
fff63867 | 508 | const void *frame, ssize_t len) |
8c5f5f7c | 509 | { |
faa087c4 | 510 | const u32 *data = frame; |
790ea70c | 511 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 512 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 | 513 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
4c614831 | 514 | int data_size; |
178f736a | 515 | int i; |
2da8af54 | 516 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 517 | |
4c614831 MN |
518 | data_size = hsw_dip_data_size(type); |
519 | ||
178f736a | 520 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
521 | I915_WRITE(ctl_reg, val); |
522 | ||
9d9740f0 | 523 | mmiowb(); |
2da8af54 | 524 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
525 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
526 | type, i >> 2), *data); | |
2da8af54 PZ |
527 | data++; |
528 | } | |
adf00b26 | 529 | /* Write every possible data byte to force correct ECC calculation. */ |
1d776538 | 530 | for (; i < data_size; i += 4) |
436c6d4a VS |
531 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
532 | type, i >> 2), 0); | |
9d9740f0 | 533 | mmiowb(); |
8c5f5f7c | 534 | |
178f736a | 535 | val |= hsw_infoframe_enable(type); |
2da8af54 | 536 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 537 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
538 | } |
539 | ||
f2a10d61 VS |
540 | static void hsw_read_infoframe(struct intel_encoder *encoder, |
541 | const struct intel_crtc_state *crtc_state, | |
542 | unsigned int type, | |
543 | void *frame, ssize_t len) | |
544 | { | |
545 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
546 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
547 | u32 val, *data = frame; | |
548 | int i; | |
549 | ||
550 | val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); | |
551 | ||
552 | for (i = 0; i < len; i += 4) | |
553 | *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, | |
554 | type, i >> 2)); | |
555 | } | |
556 | ||
509efa2b | 557 | static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 558 | const struct intel_crtc_state *pipe_config) |
e43823ec | 559 | { |
790ea70c | 560 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf | 561 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); |
e43823ec | 562 | |
ec1dc603 VS |
563 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
564 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
565 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
566 | } |
567 | ||
509efa2b VS |
568 | static const u8 infoframe_type_to_idx[] = { |
569 | HDMI_PACKET_TYPE_GENERAL_CONTROL, | |
570 | HDMI_PACKET_TYPE_GAMUT_METADATA, | |
571 | DP_SDP_VSC, | |
572 | HDMI_INFOFRAME_TYPE_AVI, | |
573 | HDMI_INFOFRAME_TYPE_SPD, | |
574 | HDMI_INFOFRAME_TYPE_VENDOR, | |
575 | }; | |
576 | ||
fbf08556 VS |
577 | u32 intel_hdmi_infoframe_enable(unsigned int type) |
578 | { | |
579 | int i; | |
580 | ||
581 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
582 | if (infoframe_type_to_idx[i] == type) | |
583 | return BIT(i); | |
584 | } | |
585 | ||
586 | return 0; | |
587 | } | |
588 | ||
509efa2b VS |
589 | u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, |
590 | const struct intel_crtc_state *crtc_state) | |
591 | { | |
592 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
593 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
594 | u32 val, ret = 0; | |
595 | int i; | |
596 | ||
597 | val = dig_port->infoframes_enabled(encoder, crtc_state); | |
598 | ||
599 | /* map from hardware bits to dip idx */ | |
600 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
601 | unsigned int type = infoframe_type_to_idx[i]; | |
602 | ||
603 | if (HAS_DDI(dev_priv)) { | |
604 | if (val & hsw_infoframe_enable(type)) | |
605 | ret |= BIT(i); | |
606 | } else { | |
607 | if (val & g4x_infoframe_enable(type)) | |
608 | ret |= BIT(i); | |
609 | } | |
610 | } | |
611 | ||
612 | return ret; | |
613 | } | |
614 | ||
5adaea79 DL |
615 | /* |
616 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
617 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
618 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
619 | * used for both technologies. | |
620 | * | |
621 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
622 | * DW1: DB3 | DB2 | DB1 | DB0 | |
623 | * DW2: DB7 | DB6 | DB5 | DB4 | |
624 | * DW3: ... | |
625 | * | |
626 | * (HB is Header Byte, DB is Data Byte) | |
627 | * | |
628 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
629 | * trick them by giving an offset into the buffer and moving back the header | |
630 | * bytes by one. | |
631 | */ | |
790ea70c | 632 | static void intel_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 633 | const struct intel_crtc_state *crtc_state, |
fbf08556 VS |
634 | enum hdmi_infoframe_type type, |
635 | const union hdmi_infoframe *frame) | |
45187ace | 636 | { |
790ea70c | 637 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
faa087c4 | 638 | u8 buffer[VIDEO_DIP_DATA_SIZE]; |
5adaea79 | 639 | ssize_t len; |
45187ace | 640 | |
fbf08556 VS |
641 | if ((crtc_state->infoframes.enable & |
642 | intel_hdmi_infoframe_enable(type)) == 0) | |
643 | return; | |
644 | ||
645 | if (WARN_ON(frame->any.type != type)) | |
646 | return; | |
647 | ||
5adaea79 | 648 | /* see comment above for the reason for this offset */ |
fbf08556 VS |
649 | len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); |
650 | if (WARN_ON(len < 0)) | |
5adaea79 DL |
651 | return; |
652 | ||
653 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
121f0ff5 | 654 | memmove(&buffer[0], &buffer[1], 3); |
5adaea79 DL |
655 | buffer[3] = 0; |
656 | len++; | |
45187ace | 657 | |
fbf08556 | 658 | intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); |
45187ace JB |
659 | } |
660 | ||
f2a10d61 VS |
661 | void intel_read_infoframe(struct intel_encoder *encoder, |
662 | const struct intel_crtc_state *crtc_state, | |
663 | enum hdmi_infoframe_type type, | |
664 | union hdmi_infoframe *frame) | |
665 | { | |
666 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
667 | u8 buffer[VIDEO_DIP_DATA_SIZE]; | |
668 | int ret; | |
669 | ||
670 | if ((crtc_state->infoframes.enable & | |
671 | intel_hdmi_infoframe_enable(type)) == 0) | |
672 | return; | |
673 | ||
674 | intel_dig_port->read_infoframe(encoder, crtc_state, | |
675 | type, buffer, sizeof(buffer)); | |
676 | ||
677 | /* Fill the 'hole' (see big comment above) at position 3 */ | |
678 | memmove(&buffer[1], &buffer[0], 3); | |
679 | ||
680 | /* see comment above for the reason for this offset */ | |
681 | ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); | |
682 | if (ret) { | |
683 | DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); | |
684 | return; | |
685 | } | |
686 | ||
687 | if (frame->any.type != type) | |
688 | DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", | |
689 | frame->any.type, type); | |
690 | } | |
691 | ||
fbf08556 VS |
692 | static bool |
693 | intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, | |
694 | struct intel_crtc_state *crtc_state, | |
695 | struct drm_connector_state *conn_state) | |
45187ace | 696 | { |
fbf08556 | 697 | struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; |
779c4c28 VS |
698 | const struct drm_display_mode *adjusted_mode = |
699 | &crtc_state->base.adjusted_mode; | |
fbf08556 | 700 | struct drm_connector *connector = conn_state->connector; |
5adaea79 | 701 | int ret; |
45187ace | 702 | |
fbf08556 VS |
703 | if (!crtc_state->has_infoframe) |
704 | return true; | |
705 | ||
706 | crtc_state->infoframes.enable |= | |
707 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); | |
708 | ||
709 | ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, | |
13d0add3 | 710 | adjusted_mode); |
fbf08556 VS |
711 | if (ret) |
712 | return false; | |
c846b619 | 713 | |
33b7f3ee | 714 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
fbf08556 | 715 | frame->colorspace = HDMI_COLORSPACE_YUV420; |
8c79f844 | 716 | else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) |
fbf08556 | 717 | frame->colorspace = HDMI_COLORSPACE_YUV444; |
2d8bd2bf | 718 | else |
fbf08556 | 719 | frame->colorspace = HDMI_COLORSPACE_RGB; |
2d8bd2bf | 720 | |
0e2f54f8 | 721 | drm_hdmi_avi_infoframe_colorspace(frame, conn_state); |
2f146b78 | 722 | |
fbf08556 | 723 | drm_hdmi_avi_infoframe_quant_range(frame, connector, |
13d0add3 | 724 | adjusted_mode, |
a2ce26f8 VS |
725 | crtc_state->limited_color_range ? |
726 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
1581b2df | 727 | HDMI_QUANTIZATION_RANGE_FULL); |
abedc077 | 728 | |
fbf08556 | 729 | drm_hdmi_avi_infoframe_content_type(frame, conn_state); |
6553b123 | 730 | |
2d8bd2bf | 731 | /* TODO: handle pixel repetition for YCBCR420 outputs */ |
fbf08556 VS |
732 | |
733 | ret = hdmi_avi_infoframe_check(frame); | |
734 | if (WARN_ON(ret)) | |
735 | return false; | |
736 | ||
737 | return true; | |
b055c8f3 JB |
738 | } |
739 | ||
fbf08556 VS |
740 | static bool |
741 | intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, | |
742 | struct intel_crtc_state *crtc_state, | |
743 | struct drm_connector_state *conn_state) | |
c0864cb3 | 744 | { |
fbf08556 | 745 | struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; |
5adaea79 DL |
746 | int ret; |
747 | ||
fbf08556 VS |
748 | if (!crtc_state->has_infoframe) |
749 | return true; | |
c0864cb3 | 750 | |
fbf08556 VS |
751 | crtc_state->infoframes.enable |= |
752 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); | |
c0864cb3 | 753 | |
fbf08556 VS |
754 | ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); |
755 | if (WARN_ON(ret)) | |
756 | return false; | |
757 | ||
758 | frame->sdi = HDMI_SPD_SDI_PC; | |
759 | ||
760 | ret = hdmi_spd_infoframe_check(frame); | |
761 | if (WARN_ON(ret)) | |
762 | return false; | |
763 | ||
764 | return true; | |
c0864cb3 JB |
765 | } |
766 | ||
fbf08556 VS |
767 | static bool |
768 | intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, | |
769 | struct intel_crtc_state *crtc_state, | |
770 | struct drm_connector_state *conn_state) | |
771 | { | |
772 | struct hdmi_vendor_infoframe *frame = | |
773 | &crtc_state->infoframes.hdmi.vendor.hdmi; | |
774 | const struct drm_display_info *info = | |
775 | &conn_state->connector->display_info; | |
c8bb75af LD |
776 | int ret; |
777 | ||
fbf08556 VS |
778 | if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) |
779 | return true; | |
780 | ||
781 | crtc_state->infoframes.enable |= | |
782 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); | |
783 | ||
784 | ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, | |
f1781e9b | 785 | conn_state->connector, |
ac240288 | 786 | &crtc_state->base.adjusted_mode); |
fbf08556 VS |
787 | if (WARN_ON(ret)) |
788 | return false; | |
c8bb75af | 789 | |
fbf08556 VS |
790 | ret = hdmi_vendor_infoframe_check(frame); |
791 | if (WARN_ON(ret)) | |
792 | return false; | |
793 | ||
794 | return true; | |
c8bb75af LD |
795 | } |
796 | ||
790ea70c | 797 | static void g4x_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 798 | bool enable, |
ac240288 ML |
799 | const struct intel_crtc_state *crtc_state, |
800 | const struct drm_connector_state *conn_state) | |
687f4d06 | 801 | { |
790ea70c VS |
802 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
803 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
69fde0a6 | 804 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 805 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 806 | u32 val = I915_READ(reg); |
790ea70c | 807 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 808 | |
afba0188 DV |
809 | assert_hdmi_port_disabled(intel_hdmi); |
810 | ||
0c14c7f9 PZ |
811 | /* If the registers were not initialized yet, they might be zeroes, |
812 | * which means we're selecting the AVI DIP and we're setting its | |
813 | * frequency to once. This seems to really confuse the HW and make | |
814 | * things stop working (the register spec says the AVI always needs to | |
815 | * be sent every VSync). So here we avoid writing to the register more | |
816 | * than we need and also explicitly select the AVI DIP and explicitly | |
817 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
818 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
819 | * either. */ | |
820 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
821 | ||
6897b4b5 | 822 | if (!enable) { |
0c14c7f9 PZ |
823 | if (!(val & VIDEO_DIP_ENABLE)) |
824 | return; | |
0be6f0c8 VS |
825 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
826 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
827 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
828 | return; | |
829 | } | |
830 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
831 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 832 | I915_WRITE(reg, val); |
9d9740f0 | 833 | POSTING_READ(reg); |
0c14c7f9 PZ |
834 | return; |
835 | } | |
836 | ||
72b78c9d PZ |
837 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
838 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
839 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
840 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
841 | return; | |
72b78c9d PZ |
842 | } |
843 | val &= ~VIDEO_DIP_PORT_MASK; | |
844 | val |= port; | |
845 | } | |
846 | ||
822974ae | 847 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
848 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
849 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 850 | |
f278d972 | 851 | I915_WRITE(reg, val); |
9d9740f0 | 852 | POSTING_READ(reg); |
f278d972 | 853 | |
fbf08556 VS |
854 | intel_write_infoframe(encoder, crtc_state, |
855 | HDMI_INFOFRAME_TYPE_AVI, | |
856 | &crtc_state->infoframes.avi); | |
857 | intel_write_infoframe(encoder, crtc_state, | |
858 | HDMI_INFOFRAME_TYPE_SPD, | |
859 | &crtc_state->infoframes.spd); | |
860 | intel_write_infoframe(encoder, crtc_state, | |
861 | HDMI_INFOFRAME_TYPE_VENDOR, | |
862 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
863 | } |
864 | ||
ac240288 | 865 | static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state) |
6d67415f | 866 | { |
ac240288 | 867 | struct drm_connector *connector = conn_state->connector; |
6d67415f VS |
868 | |
869 | /* | |
870 | * HDMI cloning is only supported on g4x which doesn't | |
871 | * support deep color or GCP infoframes anyway so no | |
872 | * need to worry about multiple HDMI sinks here. | |
873 | */ | |
6d67415f | 874 | |
ac240288 | 875 | return connector->display_info.bpc > 8; |
6d67415f VS |
876 | } |
877 | ||
12aa3290 VS |
878 | /* |
879 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
880 | * | |
881 | * From HDMI specification 1.4a: | |
882 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
883 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
884 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
885 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
886 | * phase of 0 | |
887 | */ | |
888 | static bool gcp_default_phase_possible(int pipe_bpp, | |
889 | const struct drm_display_mode *mode) | |
890 | { | |
891 | unsigned int pixels_per_group; | |
892 | ||
893 | switch (pipe_bpp) { | |
894 | case 30: | |
895 | /* 4 pixels in 5 clocks */ | |
896 | pixels_per_group = 4; | |
897 | break; | |
898 | case 36: | |
899 | /* 2 pixels in 3 clocks */ | |
900 | pixels_per_group = 2; | |
901 | break; | |
902 | case 48: | |
903 | /* 1 pixel in 2 clocks */ | |
904 | pixels_per_group = 1; | |
905 | break; | |
906 | default: | |
907 | /* phase information not relevant for 8bpc */ | |
908 | return false; | |
909 | } | |
910 | ||
911 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
912 | mode->crtc_htotal % pixels_per_group == 0 && | |
913 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
914 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
915 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
916 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
917 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
918 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
919 | } | |
920 | ||
790ea70c | 921 | static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, |
ac240288 ML |
922 | const struct intel_crtc_state *crtc_state, |
923 | const struct drm_connector_state *conn_state) | |
6d67415f | 924 | { |
790ea70c | 925 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 926 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 927 | i915_reg_t reg; |
fbf08556 VS |
928 | |
929 | if ((crtc_state->infoframes.enable & | |
930 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
931 | return false; | |
6d67415f VS |
932 | |
933 | if (HAS_DDI(dev_priv)) | |
ac240288 | 934 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 935 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 936 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 937 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
938 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
939 | else | |
940 | return false; | |
941 | ||
fbf08556 VS |
942 | I915_WRITE(reg, crtc_state->infoframes.gcp); |
943 | ||
944 | return true; | |
945 | } | |
946 | ||
f2a10d61 VS |
947 | void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, |
948 | struct intel_crtc_state *crtc_state) | |
949 | { | |
950 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
951 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
952 | i915_reg_t reg; | |
953 | ||
954 | if ((crtc_state->infoframes.enable & | |
955 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
956 | return; | |
957 | ||
958 | if (HAS_DDI(dev_priv)) | |
959 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); | |
960 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
961 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); | |
962 | else if (HAS_PCH_SPLIT(dev_priv)) | |
963 | reg = TVIDEO_DIP_GCP(crtc->pipe); | |
964 | else | |
965 | return; | |
966 | ||
967 | crtc_state->infoframes.gcp = I915_READ(reg); | |
968 | } | |
969 | ||
fbf08556 VS |
970 | static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, |
971 | struct intel_crtc_state *crtc_state, | |
972 | struct drm_connector_state *conn_state) | |
973 | { | |
974 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
975 | ||
976 | if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) | |
977 | return; | |
978 | ||
979 | crtc_state->infoframes.enable |= | |
980 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); | |
981 | ||
6d67415f | 982 | /* Indicate color depth whenever the sink supports deep color */ |
ac240288 | 983 | if (hdmi_sink_is_deep_color(conn_state)) |
fbf08556 | 984 | crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; |
6d67415f | 985 | |
12aa3290 | 986 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
987 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
988 | &crtc_state->base.adjusted_mode)) | |
fbf08556 | 989 | crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; |
6d67415f VS |
990 | } |
991 | ||
790ea70c | 992 | static void ibx_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 993 | bool enable, |
ac240288 ML |
994 | const struct intel_crtc_state *crtc_state, |
995 | const struct drm_connector_state *conn_state) | |
687f4d06 | 996 | { |
790ea70c | 997 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 998 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 999 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
69fde0a6 | 1000 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 1001 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 1002 | u32 val = I915_READ(reg); |
790ea70c | 1003 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 1004 | |
afba0188 DV |
1005 | assert_hdmi_port_disabled(intel_hdmi); |
1006 | ||
0c14c7f9 PZ |
1007 | /* See the big comment in g4x_set_infoframes() */ |
1008 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1009 | ||
6897b4b5 | 1010 | if (!enable) { |
0c14c7f9 PZ |
1011 | if (!(val & VIDEO_DIP_ENABLE)) |
1012 | return; | |
0be6f0c8 VS |
1013 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1014 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1015 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1016 | I915_WRITE(reg, val); |
9d9740f0 | 1017 | POSTING_READ(reg); |
0c14c7f9 PZ |
1018 | return; |
1019 | } | |
1020 | ||
72b78c9d | 1021 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
1022 | WARN(val & VIDEO_DIP_ENABLE, |
1023 | "DIP already enabled on port %c\n", | |
1024 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
1025 | val &= ~VIDEO_DIP_PORT_MASK; |
1026 | val |= port; | |
1027 | } | |
1028 | ||
822974ae | 1029 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1030 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1031 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1032 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1033 | |
ac240288 | 1034 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1035 | val |= VIDEO_DIP_ENABLE_GCP; |
1036 | ||
f278d972 | 1037 | I915_WRITE(reg, val); |
9d9740f0 | 1038 | POSTING_READ(reg); |
f278d972 | 1039 | |
fbf08556 VS |
1040 | intel_write_infoframe(encoder, crtc_state, |
1041 | HDMI_INFOFRAME_TYPE_AVI, | |
1042 | &crtc_state->infoframes.avi); | |
1043 | intel_write_infoframe(encoder, crtc_state, | |
1044 | HDMI_INFOFRAME_TYPE_SPD, | |
1045 | &crtc_state->infoframes.spd); | |
1046 | intel_write_infoframe(encoder, crtc_state, | |
1047 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1048 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1049 | } |
1050 | ||
790ea70c | 1051 | static void cpt_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1052 | bool enable, |
ac240288 ML |
1053 | const struct intel_crtc_state *crtc_state, |
1054 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1055 | { |
790ea70c | 1056 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1057 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1058 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 1059 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
1060 | u32 val = I915_READ(reg); |
1061 | ||
afba0188 DV |
1062 | assert_hdmi_port_disabled(intel_hdmi); |
1063 | ||
0c14c7f9 PZ |
1064 | /* See the big comment in g4x_set_infoframes() */ |
1065 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1066 | ||
6897b4b5 | 1067 | if (!enable) { |
0c14c7f9 PZ |
1068 | if (!(val & VIDEO_DIP_ENABLE)) |
1069 | return; | |
0be6f0c8 VS |
1070 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1071 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1072 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1073 | I915_WRITE(reg, val); |
9d9740f0 | 1074 | POSTING_READ(reg); |
0c14c7f9 PZ |
1075 | return; |
1076 | } | |
1077 | ||
822974ae PZ |
1078 | /* Set both together, unset both together: see the spec. */ |
1079 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 1080 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 1081 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 1082 | |
ac240288 | 1083 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1084 | val |= VIDEO_DIP_ENABLE_GCP; |
1085 | ||
822974ae | 1086 | I915_WRITE(reg, val); |
9d9740f0 | 1087 | POSTING_READ(reg); |
822974ae | 1088 | |
fbf08556 VS |
1089 | intel_write_infoframe(encoder, crtc_state, |
1090 | HDMI_INFOFRAME_TYPE_AVI, | |
1091 | &crtc_state->infoframes.avi); | |
1092 | intel_write_infoframe(encoder, crtc_state, | |
1093 | HDMI_INFOFRAME_TYPE_SPD, | |
1094 | &crtc_state->infoframes.spd); | |
1095 | intel_write_infoframe(encoder, crtc_state, | |
1096 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1097 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1098 | } |
1099 | ||
790ea70c | 1100 | static void vlv_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1101 | bool enable, |
ac240288 ML |
1102 | const struct intel_crtc_state *crtc_state, |
1103 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1104 | { |
790ea70c | 1105 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1107 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 1108 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 1109 | u32 val = I915_READ(reg); |
790ea70c | 1110 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 1111 | |
afba0188 DV |
1112 | assert_hdmi_port_disabled(intel_hdmi); |
1113 | ||
0c14c7f9 PZ |
1114 | /* See the big comment in g4x_set_infoframes() */ |
1115 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1116 | ||
6897b4b5 | 1117 | if (!enable) { |
0c14c7f9 PZ |
1118 | if (!(val & VIDEO_DIP_ENABLE)) |
1119 | return; | |
0be6f0c8 VS |
1120 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1121 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1122 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1123 | I915_WRITE(reg, val); |
9d9740f0 | 1124 | POSTING_READ(reg); |
0c14c7f9 PZ |
1125 | return; |
1126 | } | |
1127 | ||
6a2b8021 | 1128 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
1129 | WARN(val & VIDEO_DIP_ENABLE, |
1130 | "DIP already enabled on port %c\n", | |
1131 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
1132 | val &= ~VIDEO_DIP_PORT_MASK; |
1133 | val |= port; | |
1134 | } | |
1135 | ||
822974ae | 1136 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1137 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1138 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1139 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1140 | |
ac240288 | 1141 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1142 | val |= VIDEO_DIP_ENABLE_GCP; |
1143 | ||
822974ae | 1144 | I915_WRITE(reg, val); |
9d9740f0 | 1145 | POSTING_READ(reg); |
822974ae | 1146 | |
fbf08556 VS |
1147 | intel_write_infoframe(encoder, crtc_state, |
1148 | HDMI_INFOFRAME_TYPE_AVI, | |
1149 | &crtc_state->infoframes.avi); | |
1150 | intel_write_infoframe(encoder, crtc_state, | |
1151 | HDMI_INFOFRAME_TYPE_SPD, | |
1152 | &crtc_state->infoframes.spd); | |
1153 | intel_write_infoframe(encoder, crtc_state, | |
1154 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1155 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1156 | } |
1157 | ||
790ea70c | 1158 | static void hsw_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1159 | bool enable, |
ac240288 ML |
1160 | const struct intel_crtc_state *crtc_state, |
1161 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1162 | { |
790ea70c | 1163 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1164 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 1165 | u32 val = I915_READ(reg); |
0c14c7f9 | 1166 | |
8fc0aa6e ID |
1167 | assert_hdmi_transcoder_func_disabled(dev_priv, |
1168 | crtc_state->cpu_transcoder); | |
afba0188 | 1169 | |
0be6f0c8 VS |
1170 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
1171 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
1172 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
1173 | ||
6897b4b5 | 1174 | if (!enable) { |
0be6f0c8 | 1175 | I915_WRITE(reg, val); |
9d9740f0 | 1176 | POSTING_READ(reg); |
0c14c7f9 PZ |
1177 | return; |
1178 | } | |
1179 | ||
ac240288 | 1180 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1181 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
1182 | ||
0dd87d20 | 1183 | I915_WRITE(reg, val); |
9d9740f0 | 1184 | POSTING_READ(reg); |
0dd87d20 | 1185 | |
fbf08556 VS |
1186 | intel_write_infoframe(encoder, crtc_state, |
1187 | HDMI_INFOFRAME_TYPE_AVI, | |
1188 | &crtc_state->infoframes.avi); | |
1189 | intel_write_infoframe(encoder, crtc_state, | |
1190 | HDMI_INFOFRAME_TYPE_SPD, | |
1191 | &crtc_state->infoframes.spd); | |
1192 | intel_write_infoframe(encoder, crtc_state, | |
1193 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1194 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1195 | } |
1196 | ||
b2ccb822 VS |
1197 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
1198 | { | |
1199 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
1200 | struct i2c_adapter *adapter = | |
1201 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1202 | ||
1203 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
1204 | return; | |
1205 | ||
1206 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
1207 | enable ? "Enabling" : "Disabling"); | |
1208 | ||
1209 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
1210 | adapter, enable); | |
1211 | } | |
1212 | ||
2320175f SP |
1213 | static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, |
1214 | unsigned int offset, void *buffer, size_t size) | |
1215 | { | |
1216 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1217 | struct drm_i915_private *dev_priv = | |
1218 | intel_dig_port->base.base.dev->dev_private; | |
1219 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1220 | hdmi->ddc_bus); | |
1221 | int ret; | |
1222 | u8 start = offset & 0xff; | |
1223 | struct i2c_msg msgs[] = { | |
1224 | { | |
1225 | .addr = DRM_HDCP_DDC_ADDR, | |
1226 | .flags = 0, | |
1227 | .len = 1, | |
1228 | .buf = &start, | |
1229 | }, | |
1230 | { | |
1231 | .addr = DRM_HDCP_DDC_ADDR, | |
1232 | .flags = I2C_M_RD, | |
1233 | .len = size, | |
1234 | .buf = buffer | |
1235 | } | |
1236 | }; | |
1237 | ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); | |
1238 | if (ret == ARRAY_SIZE(msgs)) | |
1239 | return 0; | |
1240 | return ret >= 0 ? -EIO : ret; | |
1241 | } | |
1242 | ||
1243 | static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, | |
1244 | unsigned int offset, void *buffer, size_t size) | |
1245 | { | |
1246 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1247 | struct drm_i915_private *dev_priv = | |
1248 | intel_dig_port->base.base.dev->dev_private; | |
1249 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1250 | hdmi->ddc_bus); | |
1251 | int ret; | |
1252 | u8 *write_buf; | |
1253 | struct i2c_msg msg; | |
1254 | ||
1255 | write_buf = kzalloc(size + 1, GFP_KERNEL); | |
1256 | if (!write_buf) | |
1257 | return -ENOMEM; | |
1258 | ||
1259 | write_buf[0] = offset & 0xff; | |
1260 | memcpy(&write_buf[1], buffer, size); | |
1261 | ||
1262 | msg.addr = DRM_HDCP_DDC_ADDR; | |
1263 | msg.flags = 0, | |
1264 | msg.len = size + 1, | |
1265 | msg.buf = write_buf; | |
1266 | ||
1267 | ret = i2c_transfer(adapter, &msg, 1); | |
1268 | if (ret == 1) | |
1b1b1162 RV |
1269 | ret = 0; |
1270 | else if (ret >= 0) | |
1271 | ret = -EIO; | |
1272 | ||
1273 | kfree(write_buf); | |
1274 | return ret; | |
2320175f SP |
1275 | } |
1276 | ||
1277 | static | |
1278 | int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
1279 | u8 *an) | |
1280 | { | |
1281 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1282 | struct drm_i915_private *dev_priv = | |
1283 | intel_dig_port->base.base.dev->dev_private; | |
1284 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1285 | hdmi->ddc_bus); | |
1286 | int ret; | |
1287 | ||
1288 | ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, | |
1289 | DRM_HDCP_AN_LEN); | |
1290 | if (ret) { | |
3aae21fc | 1291 | DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); |
2320175f SP |
1292 | return ret; |
1293 | } | |
1294 | ||
1295 | ret = intel_gmbus_output_aksv(adapter); | |
1296 | if (ret < 0) { | |
3aae21fc | 1297 | DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); |
2320175f SP |
1298 | return ret; |
1299 | } | |
1300 | return 0; | |
1301 | } | |
1302 | ||
1303 | static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
1304 | u8 *bksv) | |
1305 | { | |
1306 | int ret; | |
1307 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, | |
1308 | DRM_HDCP_KSV_LEN); | |
1309 | if (ret) | |
3aae21fc | 1310 | DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); |
2320175f SP |
1311 | return ret; |
1312 | } | |
1313 | ||
1314 | static | |
1315 | int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
1316 | u8 *bstatus) | |
1317 | { | |
1318 | int ret; | |
1319 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, | |
1320 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
1321 | if (ret) | |
3aae21fc | 1322 | DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); |
2320175f SP |
1323 | return ret; |
1324 | } | |
1325 | ||
1326 | static | |
1327 | int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
1328 | bool *repeater_present) | |
1329 | { | |
1330 | int ret; | |
1331 | u8 val; | |
1332 | ||
1333 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1334 | if (ret) { | |
3aae21fc | 1335 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1336 | return ret; |
1337 | } | |
1338 | *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; | |
1339 | return 0; | |
1340 | } | |
1341 | ||
1342 | static | |
1343 | int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
1344 | u8 *ri_prime) | |
1345 | { | |
1346 | int ret; | |
1347 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, | |
1348 | ri_prime, DRM_HDCP_RI_LEN); | |
1349 | if (ret) | |
3aae21fc | 1350 | DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); |
2320175f SP |
1351 | return ret; |
1352 | } | |
1353 | ||
1354 | static | |
1355 | int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
1356 | bool *ksv_ready) | |
1357 | { | |
1358 | int ret; | |
1359 | u8 val; | |
1360 | ||
1361 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1362 | if (ret) { | |
3aae21fc | 1363 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1364 | return ret; |
1365 | } | |
1366 | *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; | |
1367 | return 0; | |
1368 | } | |
1369 | ||
1370 | static | |
1371 | int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
1372 | int num_downstream, u8 *ksv_fifo) | |
1373 | { | |
1374 | int ret; | |
1375 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, | |
1376 | ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); | |
1377 | if (ret) { | |
3aae21fc | 1378 | DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); |
2320175f SP |
1379 | return ret; |
1380 | } | |
1381 | return 0; | |
1382 | } | |
1383 | ||
1384 | static | |
1385 | int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
1386 | int i, u32 *part) | |
1387 | { | |
1388 | int ret; | |
1389 | ||
1390 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
1391 | return -EINVAL; | |
1392 | ||
1393 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), | |
1394 | part, DRM_HDCP_V_PRIME_PART_LEN); | |
1395 | if (ret) | |
3aae21fc | 1396 | DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); |
2320175f SP |
1397 | return ret; |
1398 | } | |
1399 | ||
7412826c R |
1400 | static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) |
1401 | { | |
1402 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
1403 | struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); | |
1404 | struct drm_crtc *crtc = connector->base.state->crtc; | |
1405 | struct intel_crtc *intel_crtc = container_of(crtc, | |
1406 | struct intel_crtc, base); | |
1407 | u32 scanline; | |
1408 | int ret; | |
1409 | ||
1410 | for (;;) { | |
1411 | scanline = I915_READ(PIPEDSL(intel_crtc->pipe)); | |
1412 | if (scanline > 100 && scanline < 200) | |
1413 | break; | |
1414 | usleep_range(25, 50); | |
1415 | } | |
1416 | ||
1417 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); | |
1418 | if (ret) { | |
1419 | DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret); | |
1420 | return ret; | |
1421 | } | |
1422 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); | |
1423 | if (ret) { | |
1424 | DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret); | |
1425 | return ret; | |
1426 | } | |
1427 | ||
1428 | return 0; | |
1429 | } | |
1430 | ||
2320175f SP |
1431 | static |
1432 | int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
1433 | bool enable) | |
1434 | { | |
7412826c R |
1435 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; |
1436 | struct intel_connector *connector = hdmi->attached_connector; | |
1437 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
2320175f SP |
1438 | int ret; |
1439 | ||
1440 | if (!enable) | |
1441 | usleep_range(6, 60); /* Bspec says >= 6us */ | |
1442 | ||
1443 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); | |
1444 | if (ret) { | |
1445 | DRM_ERROR("%s HDCP signalling failed (%d)\n", | |
1446 | enable ? "Enable" : "Disable", ret); | |
1447 | return ret; | |
1448 | } | |
7412826c R |
1449 | |
1450 | /* | |
1451 | * WA: To fix incorrect positioning of the window of | |
1452 | * opportunity and enc_en signalling in KABYLAKE. | |
1453 | */ | |
1454 | if (IS_KABYLAKE(dev_priv) && enable) | |
1455 | return kbl_repositioning_enc_en_signal(connector); | |
1456 | ||
2320175f SP |
1457 | return 0; |
1458 | } | |
1459 | ||
1460 | static | |
1461 | bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
1462 | { | |
1463 | struct drm_i915_private *dev_priv = | |
1464 | intel_dig_port->base.base.dev->dev_private; | |
1465 | enum port port = intel_dig_port->base.port; | |
1466 | int ret; | |
1467 | union { | |
1468 | u32 reg; | |
1469 | u8 shim[DRM_HDCP_RI_LEN]; | |
1470 | } ri; | |
1471 | ||
1472 | ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); | |
1473 | if (ret) | |
1474 | return false; | |
1475 | ||
1476 | I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); | |
1477 | ||
1478 | /* Wait for Ri prime match */ | |
1479 | if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & | |
1480 | (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { | |
1481 | DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", | |
1482 | I915_READ(PORT_HDCP_STATUS(port))); | |
1483 | return false; | |
1484 | } | |
1485 | return true; | |
1486 | } | |
1487 | ||
2d4254e5 R |
1488 | static struct hdcp2_hdmi_msg_data { |
1489 | u8 msg_id; | |
1490 | u32 timeout; | |
1491 | u32 timeout2; | |
1492 | } hdcp2_msg_data[] = { | |
1493 | {HDCP_2_2_AKE_INIT, 0, 0}, | |
1494 | {HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0}, | |
1495 | {HDCP_2_2_AKE_NO_STORED_KM, 0, 0}, | |
1496 | {HDCP_2_2_AKE_STORED_KM, 0, 0}, | |
1497 | {HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, | |
1498 | HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS}, | |
1499 | {HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, | |
1500 | 0}, | |
1501 | {HDCP_2_2_LC_INIT, 0, 0}, | |
1502 | {HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0}, | |
1503 | {HDCP_2_2_SKE_SEND_EKS, 0, 0}, | |
1504 | {HDCP_2_2_REP_SEND_RECVID_LIST, | |
1505 | HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0}, | |
1506 | {HDCP_2_2_REP_SEND_ACK, 0, 0}, | |
1507 | {HDCP_2_2_REP_STREAM_MANAGE, 0, 0}, | |
1508 | {HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, | |
1509 | 0}, | |
1510 | }; | |
1511 | ||
1512 | static | |
1513 | int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, | |
126d0a94 | 1514 | u8 *rx_status) |
2d4254e5 R |
1515 | { |
1516 | return intel_hdmi_hdcp_read(intel_dig_port, | |
1517 | HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, | |
1518 | rx_status, | |
1519 | HDCP_2_2_HDMI_RXSTATUS_LEN); | |
1520 | } | |
1521 | ||
1522 | static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) | |
1523 | { | |
1524 | int i; | |
1525 | ||
1526 | for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++) | |
1527 | if (hdcp2_msg_data[i].msg_id == msg_id && | |
1528 | (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired)) | |
1529 | return hdcp2_msg_data[i].timeout; | |
1530 | else if (hdcp2_msg_data[i].msg_id == msg_id) | |
1531 | return hdcp2_msg_data[i].timeout2; | |
1532 | ||
1533 | return -EINVAL; | |
1534 | } | |
1535 | ||
1536 | static inline | |
1537 | int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port, | |
1538 | u8 msg_id, bool *msg_ready, | |
1539 | ssize_t *msg_sz) | |
1540 | { | |
1541 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1542 | int ret; | |
1543 | ||
1544 | ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status); | |
1545 | if (ret < 0) { | |
1546 | DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret); | |
1547 | return ret; | |
1548 | } | |
1549 | ||
1550 | *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | | |
1551 | rx_status[0]); | |
1552 | ||
1553 | if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) | |
1554 | *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && | |
1555 | *msg_sz); | |
1556 | else | |
1557 | *msg_ready = *msg_sz; | |
1558 | ||
1559 | return 0; | |
1560 | } | |
1561 | ||
1562 | static ssize_t | |
1563 | intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, | |
1564 | u8 msg_id, bool paired) | |
1565 | { | |
1566 | bool msg_ready = false; | |
1567 | int timeout, ret; | |
1568 | ssize_t msg_sz = 0; | |
1569 | ||
1570 | timeout = get_hdcp2_msg_timeout(msg_id, paired); | |
1571 | if (timeout < 0) | |
1572 | return timeout; | |
1573 | ||
1574 | ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, | |
1575 | msg_id, &msg_ready, | |
1576 | &msg_sz), | |
1577 | !ret && msg_ready && msg_sz, timeout * 1000, | |
1578 | 1000, 5 * 1000); | |
1579 | if (ret) | |
1580 | DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n", | |
1581 | msg_id, ret, timeout); | |
1582 | ||
1583 | return ret ? ret : msg_sz; | |
1584 | } | |
1585 | ||
1586 | static | |
1587 | int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, | |
1588 | void *buf, size_t size) | |
1589 | { | |
1590 | unsigned int offset; | |
1591 | ||
1592 | offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; | |
1593 | return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); | |
1594 | } | |
1595 | ||
1596 | static | |
1597 | int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, | |
1598 | u8 msg_id, void *buf, size_t size) | |
1599 | { | |
1600 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1601 | struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; | |
1602 | unsigned int offset; | |
1603 | ssize_t ret; | |
1604 | ||
1605 | ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, | |
1606 | hdcp->is_paired); | |
1607 | if (ret < 0) | |
1608 | return ret; | |
1609 | ||
1610 | /* | |
1611 | * Available msg size should be equal to or lesser than the | |
1612 | * available buffer. | |
1613 | */ | |
1614 | if (ret > size) { | |
1615 | DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n", | |
1616 | ret, size); | |
1617 | return -1; | |
1618 | } | |
1619 | ||
1620 | offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; | |
1621 | ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); | |
1622 | if (ret) | |
1623 | DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret); | |
1624 | ||
1625 | return ret; | |
1626 | } | |
1627 | ||
1628 | static | |
1629 | int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) | |
1630 | { | |
1631 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1632 | int ret; | |
1633 | ||
1634 | ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); | |
1635 | if (ret) | |
1636 | return ret; | |
1637 | ||
1638 | /* | |
1639 | * Re-auth request and Link Integrity Failures are represented by | |
1640 | * same bit. i.e reauth_req. | |
1641 | */ | |
1642 | if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) | |
1643 | ret = HDCP_REAUTH_REQUEST; | |
1644 | else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) | |
1645 | ret = HDCP_TOPOLOGY_CHANGE; | |
1646 | ||
1647 | return ret; | |
1648 | } | |
1649 | ||
1650 | static | |
1651 | int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, | |
1652 | bool *capable) | |
1653 | { | |
1654 | u8 hdcp2_version; | |
1655 | int ret; | |
1656 | ||
1657 | *capable = false; | |
1658 | ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, | |
1659 | &hdcp2_version, sizeof(hdcp2_version)); | |
1660 | if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) | |
1661 | *capable = true; | |
1662 | ||
1663 | return ret; | |
1664 | } | |
1665 | ||
1666 | static inline | |
1667 | enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void) | |
1668 | { | |
1669 | return HDCP_PROTOCOL_HDMI; | |
1670 | } | |
1671 | ||
2320175f SP |
1672 | static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { |
1673 | .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, | |
1674 | .read_bksv = intel_hdmi_hdcp_read_bksv, | |
1675 | .read_bstatus = intel_hdmi_hdcp_read_bstatus, | |
1676 | .repeater_present = intel_hdmi_hdcp_repeater_present, | |
1677 | .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, | |
1678 | .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, | |
1679 | .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, | |
1680 | .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, | |
1681 | .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, | |
1682 | .check_link = intel_hdmi_hdcp_check_link, | |
2d4254e5 R |
1683 | .write_2_2_msg = intel_hdmi_hdcp2_write_msg, |
1684 | .read_2_2_msg = intel_hdmi_hdcp2_read_msg, | |
1685 | .check_2_2_link = intel_hdmi_hdcp2_check_link, | |
1686 | .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, | |
1687 | .protocol = HDCP_PROTOCOL_HDMI, | |
2320175f SP |
1688 | }; |
1689 | ||
ac240288 ML |
1690 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
1691 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 1692 | { |
c59423a3 | 1693 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1694 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1695 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 1696 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 1697 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 1698 | u32 hdmi_val; |
7d57382e | 1699 | |
b2ccb822 VS |
1700 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
1701 | ||
b242b7f7 | 1702 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 1703 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 1704 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 1705 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 1706 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 1707 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 1708 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 1709 | |
ac240288 | 1710 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 1711 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 1712 | else |
4f3a8bc7 | 1713 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 1714 | |
ac240288 | 1715 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 1716 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 1717 | |
6e266956 | 1718 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 1719 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 1720 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1721 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 1722 | else |
c59423a3 | 1723 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 1724 | |
b242b7f7 PZ |
1725 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
1726 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
1727 | } |
1728 | ||
85234cdc DV |
1729 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
1730 | enum pipe *pipe) | |
7d57382e | 1731 | { |
76203467 | 1732 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
85234cdc | 1733 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
0e6e0be4 | 1734 | intel_wakeref_t wakeref; |
5b092174 | 1735 | bool ret; |
85234cdc | 1736 | |
0e6e0be4 CW |
1737 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
1738 | encoder->power_domain); | |
1739 | if (!wakeref) | |
6d129bea ID |
1740 | return false; |
1741 | ||
76203467 | 1742 | ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); |
5b092174 | 1743 | |
0e6e0be4 | 1744 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
5b092174 ID |
1745 | |
1746 | return ret; | |
85234cdc DV |
1747 | } |
1748 | ||
045ac3b5 | 1749 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 1750 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
1751 | { |
1752 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca | 1753 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1754 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 1755 | u32 tmp, flags = 0; |
18442d08 | 1756 | int dotclock; |
045ac3b5 | 1757 | |
e1214b95 VS |
1758 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); |
1759 | ||
045ac3b5 JB |
1760 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
1761 | ||
1762 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
1763 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1764 | else | |
1765 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1766 | ||
1767 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
1768 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1769 | else | |
1770 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1771 | ||
6897b4b5 DV |
1772 | if (tmp & HDMI_MODE_SELECT_HDMI) |
1773 | pipe_config->has_hdmi_sink = true; | |
1774 | ||
e5e70d4a VS |
1775 | pipe_config->infoframes.enable |= |
1776 | intel_hdmi_infoframes_enabled(encoder, pipe_config); | |
1777 | ||
1778 | if (pipe_config->infoframes.enable) | |
e43823ec JB |
1779 | pipe_config->has_infoframe = true; |
1780 | ||
c84db770 | 1781 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
1782 | pipe_config->has_audio = true; |
1783 | ||
6e266956 | 1784 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
1785 | tmp & HDMI_COLOR_RANGE_16_235) |
1786 | pipe_config->limited_color_range = true; | |
1787 | ||
2d112de7 | 1788 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
1789 | |
1790 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
1791 | dotclock = pipe_config->port_clock * 2 / 3; | |
1792 | else | |
1793 | dotclock = pipe_config->port_clock; | |
1794 | ||
be69a133 VS |
1795 | if (pipe_config->pixel_multiplier) |
1796 | dotclock /= pipe_config->pixel_multiplier; | |
1797 | ||
2d112de7 | 1798 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
1799 | |
1800 | pipe_config->lane_count = 4; | |
f2a10d61 VS |
1801 | |
1802 | intel_hdmi_read_gcp_infoframe(encoder, pipe_config); | |
1803 | ||
1804 | intel_read_infoframe(encoder, pipe_config, | |
1805 | HDMI_INFOFRAME_TYPE_AVI, | |
1806 | &pipe_config->infoframes.avi); | |
1807 | intel_read_infoframe(encoder, pipe_config, | |
1808 | HDMI_INFOFRAME_TYPE_SPD, | |
1809 | &pipe_config->infoframes.spd); | |
1810 | intel_read_infoframe(encoder, pipe_config, | |
1811 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1812 | &pipe_config->infoframes.hdmi); | |
045ac3b5 JB |
1813 | } |
1814 | ||
df18e721 | 1815 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
5f88a9c6 VS |
1816 | const struct intel_crtc_state *pipe_config, |
1817 | const struct drm_connector_state *conn_state) | |
d1b1589c | 1818 | { |
ac240288 | 1819 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 1820 | |
ac240288 | 1821 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
1822 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
1823 | pipe_name(crtc->pipe)); | |
bbf35e9d | 1824 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
1825 | } |
1826 | ||
fd6bbda9 | 1827 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1828 | const struct intel_crtc_state *pipe_config, |
1829 | const struct drm_connector_state *conn_state) | |
7d57382e | 1830 | { |
5ab432ef | 1831 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1832 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1833 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1834 | u32 temp; |
1835 | ||
b242b7f7 | 1836 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1837 | |
bf868c7d | 1838 | temp |= SDVO_ENABLE; |
df18e721 | 1839 | if (pipe_config->has_audio) |
bf868c7d | 1840 | temp |= SDVO_AUDIO_ENABLE; |
7a87c289 | 1841 | |
bf868c7d VS |
1842 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1843 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1844 | ||
df18e721 ML |
1845 | if (pipe_config->has_audio) |
1846 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1847 | } |
1848 | ||
fd6bbda9 | 1849 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1850 | const struct intel_crtc_state *pipe_config, |
1851 | const struct drm_connector_state *conn_state) | |
bf868c7d VS |
1852 | { |
1853 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1854 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1855 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1856 | u32 temp; | |
1857 | ||
1858 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1859 | |
bf868c7d | 1860 | temp |= SDVO_ENABLE; |
ac240288 | 1861 | if (pipe_config->has_audio) |
bf868c7d | 1862 | temp |= SDVO_AUDIO_ENABLE; |
5ab432ef | 1863 | |
bf868c7d VS |
1864 | /* |
1865 | * HW workaround, need to write this twice for issue | |
1866 | * that may result in first write getting masked. | |
1867 | */ | |
1868 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1869 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1870 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1871 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1872 | |
bf868c7d VS |
1873 | /* |
1874 | * HW workaround, need to toggle enable bit off and on | |
1875 | * for 12bpc with pixel repeat. | |
1876 | * | |
1877 | * FIXME: BSpec says this should be done at the end of | |
1878 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1879 | */ |
df18e721 ML |
1880 | if (pipe_config->pipe_bpp > 24 && |
1881 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1882 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1883 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1884 | ||
1885 | /* | |
1886 | * HW workaround, need to write this twice for issue | |
1887 | * that may result in first write getting masked. | |
1888 | */ | |
1889 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1890 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1891 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1892 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1893 | } |
c1dec79a | 1894 | |
df18e721 ML |
1895 | if (pipe_config->has_audio) |
1896 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1897 | } |
1898 | ||
fd6bbda9 | 1899 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1900 | const struct intel_crtc_state *pipe_config, |
1901 | const struct drm_connector_state *conn_state) | |
d1b1589c VS |
1902 | { |
1903 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1904 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1905 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1906 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1907 | enum pipe pipe = crtc->pipe; | |
1908 | u32 temp; | |
1909 | ||
1910 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1911 | ||
1912 | temp |= SDVO_ENABLE; | |
df18e721 | 1913 | if (pipe_config->has_audio) |
d1b1589c VS |
1914 | temp |= SDVO_AUDIO_ENABLE; |
1915 | ||
1916 | /* | |
1917 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1918 | * | |
1919 | * The procedure for 12bpc is as follows: | |
1920 | * 1. disable HDMI clock gating | |
1921 | * 2. enable HDMI with 8bpc | |
1922 | * 3. enable HDMI with 12bpc | |
1923 | * 4. enable HDMI clock gating | |
1924 | */ | |
1925 | ||
df18e721 | 1926 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1927 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1928 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1929 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1930 | ||
1931 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1932 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1933 | } |
d1b1589c VS |
1934 | |
1935 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1936 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1937 | ||
df18e721 | 1938 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1939 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1940 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1941 | ||
1942 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1943 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1944 | ||
1945 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1946 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1947 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1948 | } | |
1949 | ||
df18e721 ML |
1950 | if (pipe_config->has_audio) |
1951 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1952 | } |
89b667f8 | 1953 | |
fd6bbda9 | 1954 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1955 | const struct intel_crtc_state *pipe_config, |
1956 | const struct drm_connector_state *conn_state) | |
b76cf76b | 1957 | { |
5ab432ef DV |
1958 | } |
1959 | ||
fd6bbda9 | 1960 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1961 | const struct intel_crtc_state *old_crtc_state, |
1962 | const struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
1963 | { |
1964 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1965 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1966 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f99be1b3 VS |
1967 | struct intel_digital_port *intel_dig_port = |
1968 | hdmi_to_dig_port(intel_hdmi); | |
ac240288 | 1969 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 1970 | u32 temp; |
5ab432ef | 1971 | |
b242b7f7 | 1972 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1973 | |
1612c8bd | 1974 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1975 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1976 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1977 | |
1978 | /* | |
1979 | * HW workaround for IBX, we need to move the port | |
1980 | * to transcoder A after disabling it to allow the | |
1981 | * matching DP port to be enabled on transcoder A. | |
1982 | */ | |
6e266956 | 1983 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
1984 | /* |
1985 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1986 | * doing the workaround. Sweep them under the rug. | |
1987 | */ | |
1988 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1989 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1990 | ||
76203467 VS |
1991 | temp &= ~SDVO_PIPE_SEL_MASK; |
1992 | temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); | |
1612c8bd VS |
1993 | /* |
1994 | * HW workaround, need to write this twice for issue | |
1995 | * that may result in first write getting masked. | |
1996 | */ | |
1997 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1998 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1999 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
2000 | POSTING_READ(intel_hdmi->hdmi_reg); | |
2001 | ||
2002 | temp &= ~SDVO_ENABLE; | |
2003 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
2004 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 2005 | |
0f0f74bc | 2006 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
2007 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
2008 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 2009 | } |
6d67415f | 2010 | |
790ea70c VS |
2011 | intel_dig_port->set_infoframes(encoder, |
2012 | false, | |
f99be1b3 | 2013 | old_crtc_state, old_conn_state); |
b2ccb822 VS |
2014 | |
2015 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
2016 | } |
2017 | ||
fd6bbda9 | 2018 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2019 | const struct intel_crtc_state *old_crtc_state, |
2020 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2021 | { |
df18e721 | 2022 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2023 | intel_audio_codec_disable(encoder, |
2024 | old_crtc_state, old_conn_state); | |
a4790cec | 2025 | |
fd6bbda9 | 2026 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2027 | } |
2028 | ||
fd6bbda9 | 2029 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2030 | const struct intel_crtc_state *old_crtc_state, |
2031 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2032 | { |
df18e721 | 2033 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2034 | intel_audio_codec_disable(encoder, |
2035 | old_crtc_state, old_conn_state); | |
a4790cec VS |
2036 | } |
2037 | ||
fd6bbda9 | 2038 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2039 | const struct intel_crtc_state *old_crtc_state, |
2040 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2041 | { |
fd6bbda9 | 2042 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2043 | } |
2044 | ||
d6038611 | 2045 | static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) |
7d148ef5 | 2046 | { |
d6038611 VS |
2047 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2048 | const struct ddi_vbt_port_info *info = | |
2049 | &dev_priv->vbt.ddi_port_info[encoder->port]; | |
2050 | int max_tmds_clock; | |
2051 | ||
9672a69c | 2052 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
d6038611 VS |
2053 | max_tmds_clock = 594000; |
2054 | else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) | |
2055 | max_tmds_clock = 300000; | |
2056 | else if (INTEL_GEN(dev_priv) >= 5) | |
2057 | max_tmds_clock = 225000; | |
7d148ef5 | 2058 | else |
d6038611 VS |
2059 | max_tmds_clock = 165000; |
2060 | ||
2061 | if (info->max_tmds_clock) | |
2062 | max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); | |
2063 | ||
2064 | return max_tmds_clock; | |
7d148ef5 DV |
2065 | } |
2066 | ||
b1ba124d | 2067 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f ML |
2068 | bool respect_downstream_limits, |
2069 | bool force_dvi) | |
b1ba124d | 2070 | { |
d6038611 VS |
2071 | struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; |
2072 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); | |
b1ba124d VS |
2073 | |
2074 | if (respect_downstream_limits) { | |
8cadab0a VS |
2075 | struct intel_connector *connector = hdmi->attached_connector; |
2076 | const struct drm_display_info *info = &connector->base.display_info; | |
2077 | ||
b1ba124d VS |
2078 | if (hdmi->dp_dual_mode.max_tmds_clock) |
2079 | max_tmds_clock = min(max_tmds_clock, | |
2080 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
2081 | |
2082 | if (info->max_tmds_clock) | |
2083 | max_tmds_clock = min(max_tmds_clock, | |
2084 | info->max_tmds_clock); | |
7a5ca19f | 2085 | else if (!hdmi->has_hdmi_sink || force_dvi) |
b1ba124d VS |
2086 | max_tmds_clock = min(max_tmds_clock, 165000); |
2087 | } | |
2088 | ||
2089 | return max_tmds_clock; | |
2090 | } | |
2091 | ||
e64e739e VS |
2092 | static enum drm_mode_status |
2093 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f ML |
2094 | int clock, bool respect_downstream_limits, |
2095 | bool force_dvi) | |
e64e739e | 2096 | { |
e2d214ae | 2097 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
2098 | |
2099 | if (clock < 25000) | |
2100 | return MODE_CLOCK_LOW; | |
7a5ca19f | 2101 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) |
e64e739e VS |
2102 | return MODE_CLOCK_HIGH; |
2103 | ||
5e6ccc0b | 2104 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 2105 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
2106 | return MODE_CLOCK_RANGE; |
2107 | ||
2108 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 2109 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
2110 | return MODE_CLOCK_RANGE; |
2111 | ||
2112 | return MODE_OK; | |
2113 | } | |
2114 | ||
c19de8eb DL |
2115 | static enum drm_mode_status |
2116 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
2117 | struct drm_display_mode *mode) | |
7d57382e | 2118 | { |
e64e739e VS |
2119 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
2120 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 2121 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
2122 | enum drm_mode_status status; |
2123 | int clock; | |
587bf496 | 2124 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
7a5ca19f ML |
2125 | bool force_dvi = |
2126 | READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; | |
e64e739e | 2127 | |
e4dd27aa VS |
2128 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
2129 | return MODE_NO_DBLESCAN; | |
2130 | ||
e64e739e | 2131 | clock = mode->clock; |
587bf496 MK |
2132 | |
2133 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
2134 | clock *= 2; | |
2135 | ||
2136 | if (clock > max_dotclk) | |
2137 | return MODE_CLOCK_HIGH; | |
2138 | ||
697c4078 CT |
2139 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
2140 | clock *= 2; | |
2141 | ||
b22ca995 SS |
2142 | if (drm_mode_is_420_only(&connector->display_info, mode)) |
2143 | clock /= 2; | |
2144 | ||
e64e739e | 2145 | /* check if we can do 8bpc */ |
7a5ca19f | 2146 | status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); |
7d57382e | 2147 | |
cd9e11a8 RS |
2148 | if (hdmi->has_hdmi_sink && !force_dvi) { |
2149 | /* if we can't do 8bpc we may still be able to do 12bpc */ | |
b2ae318a | 2150 | if (status != MODE_OK && !HAS_GMCH(dev_priv)) |
cd9e11a8 RS |
2151 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, |
2152 | true, force_dvi); | |
2153 | ||
2154 | /* if we can't do 8,12bpc we may still be able to do 10bpc */ | |
2155 | if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) | |
2156 | status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, | |
2157 | true, force_dvi); | |
2158 | } | |
7d57382e | 2159 | |
e64e739e | 2160 | return status; |
7d57382e EA |
2161 | } |
2162 | ||
cd9e11a8 RS |
2163 | static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, |
2164 | int bpc) | |
71800632 | 2165 | { |
c750bdd3 VS |
2166 | struct drm_i915_private *dev_priv = |
2167 | to_i915(crtc_state->base.crtc->dev); | |
2168 | struct drm_atomic_state *state = crtc_state->base.state; | |
2169 | struct drm_connector_state *connector_state; | |
2170 | struct drm_connector *connector; | |
22dae8a0 RS |
2171 | const struct drm_display_mode *adjusted_mode = |
2172 | &crtc_state->base.adjusted_mode; | |
c750bdd3 | 2173 | int i; |
71800632 | 2174 | |
b2ae318a | 2175 | if (HAS_GMCH(dev_priv)) |
71800632 VS |
2176 | return false; |
2177 | ||
cd9e11a8 RS |
2178 | if (bpc == 10 && INTEL_GEN(dev_priv) < 11) |
2179 | return false; | |
2180 | ||
be33be5d VS |
2181 | if (crtc_state->pipe_bpp <= 8*3) |
2182 | return false; | |
2183 | ||
2184 | if (!crtc_state->has_hdmi_sink) | |
2185 | return false; | |
2186 | ||
71800632 | 2187 | /* |
cd9e11a8 | 2188 | * HDMI deep color affects the clocks, so it's only possible |
71800632 VS |
2189 | * when not cloning with other encoder types. |
2190 | */ | |
c750bdd3 VS |
2191 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
2192 | return false; | |
2193 | ||
fe5f6b1f | 2194 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
c750bdd3 VS |
2195 | const struct drm_display_info *info = &connector->display_info; |
2196 | ||
2197 | if (connector_state->crtc != crtc_state->base.crtc) | |
2198 | continue; | |
2199 | ||
33b7f3ee | 2200 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { |
60436fd4 SS |
2201 | const struct drm_hdmi_info *hdmi = &info->hdmi; |
2202 | ||
cd9e11a8 RS |
2203 | if (bpc == 12 && !(hdmi->y420_dc_modes & |
2204 | DRM_EDID_YCBCR420_DC_36)) | |
2205 | return false; | |
2206 | else if (bpc == 10 && !(hdmi->y420_dc_modes & | |
2207 | DRM_EDID_YCBCR420_DC_30)) | |
60436fd4 SS |
2208 | return false; |
2209 | } else { | |
cd9e11a8 RS |
2210 | if (bpc == 12 && !(info->edid_hdmi_dc_modes & |
2211 | DRM_EDID_HDMI_DC_36)) | |
2212 | return false; | |
2213 | else if (bpc == 10 && !(info->edid_hdmi_dc_modes & | |
2214 | DRM_EDID_HDMI_DC_30)) | |
60436fd4 SS |
2215 | return false; |
2216 | } | |
c750bdd3 VS |
2217 | } |
2218 | ||
2abf3c0d | 2219 | /* Display WA #1139: glk */ |
cd9e11a8 | 2220 | if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && |
22dae8a0 RS |
2221 | adjusted_mode->htotal > 5460) |
2222 | return false; | |
2223 | ||
2224 | /* Display Wa_1405510057:icl */ | |
2225 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && | |
2dd24a9c | 2226 | bpc == 10 && INTEL_GEN(dev_priv) >= 11 && |
22dae8a0 RS |
2227 | (adjusted_mode->crtc_hblank_end - |
2228 | adjusted_mode->crtc_hblank_start) % 8 == 2) | |
46649d8b ACO |
2229 | return false; |
2230 | ||
c750bdd3 | 2231 | return true; |
71800632 VS |
2232 | } |
2233 | ||
60436fd4 SS |
2234 | static bool |
2235 | intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |
2236 | struct intel_crtc_state *config, | |
cd9e11a8 RS |
2237 | int *clock_12bpc, int *clock_10bpc, |
2238 | int *clock_8bpc) | |
60436fd4 | 2239 | { |
e5c05931 SS |
2240 | struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); |
2241 | ||
60436fd4 SS |
2242 | if (!connector->ycbcr_420_allowed) { |
2243 | DRM_ERROR("Platform doesn't support YCBCR420 output\n"); | |
2244 | return false; | |
2245 | } | |
2246 | ||
2247 | /* YCBCR420 TMDS rate requirement is half the pixel clock */ | |
2248 | config->port_clock /= 2; | |
2249 | *clock_12bpc /= 2; | |
cd9e11a8 | 2250 | *clock_10bpc /= 2; |
60436fd4 | 2251 | *clock_8bpc /= 2; |
33b7f3ee | 2252 | config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
e5c05931 SS |
2253 | |
2254 | /* YCBCR 420 output conversion needs a scaler */ | |
2255 | if (skl_update_scaler_crtc(config)) { | |
2256 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
2257 | return false; | |
2258 | } | |
2259 | ||
2260 | intel_pch_panel_fitting(intel_crtc, config, | |
2261 | DRM_MODE_SCALE_FULLSCREEN); | |
2262 | ||
60436fd4 SS |
2263 | return true; |
2264 | } | |
2265 | ||
204474a6 LP |
2266 | int intel_hdmi_compute_config(struct intel_encoder *encoder, |
2267 | struct intel_crtc_state *pipe_config, | |
2268 | struct drm_connector_state *conn_state) | |
7d57382e | 2269 | { |
5bfe2ac0 | 2270 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 2271 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 2272 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
60436fd4 SS |
2273 | struct drm_connector *connector = conn_state->connector; |
2274 | struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; | |
7a5ca19f ML |
2275 | struct intel_digital_connector_state *intel_conn_state = |
2276 | to_intel_digital_connector_state(conn_state); | |
e64e739e | 2277 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
cd9e11a8 | 2278 | int clock_10bpc = clock_8bpc * 5 / 4; |
e64e739e | 2279 | int clock_12bpc = clock_8bpc * 3 / 2; |
e29c22c0 | 2280 | int desired_bpp; |
7a5ca19f | 2281 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
3685a8f3 | 2282 | |
e4dd27aa | 2283 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 2284 | return -EINVAL; |
e4dd27aa | 2285 | |
d9facae6 | 2286 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
7a5ca19f | 2287 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
6897b4b5 | 2288 | |
e43823ec JB |
2289 | if (pipe_config->has_hdmi_sink) |
2290 | pipe_config->has_infoframe = true; | |
2291 | ||
7a5ca19f | 2292 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db | 2293 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
0f2a2a75 VS |
2294 | pipe_config->limited_color_range = |
2295 | pipe_config->has_hdmi_sink && | |
c8127cf0 VS |
2296 | drm_default_rgb_quant_range(adjusted_mode) == |
2297 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
2298 | } else { |
2299 | pipe_config->limited_color_range = | |
7a5ca19f | 2300 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
2301 | } |
2302 | ||
697c4078 CT |
2303 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
2304 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 2305 | clock_8bpc *= 2; |
cd9e11a8 | 2306 | clock_10bpc *= 2; |
3320e37f | 2307 | clock_12bpc *= 2; |
697c4078 CT |
2308 | } |
2309 | ||
60436fd4 SS |
2310 | if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { |
2311 | if (!intel_hdmi_ycbcr420_config(connector, pipe_config, | |
cd9e11a8 RS |
2312 | &clock_12bpc, &clock_10bpc, |
2313 | &clock_8bpc)) { | |
60436fd4 | 2314 | DRM_ERROR("Can't support YCBCR420 output\n"); |
204474a6 | 2315 | return -EINVAL; |
60436fd4 SS |
2316 | } |
2317 | } | |
2318 | ||
4f8036a2 | 2319 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
2320 | pipe_config->has_pch_encoder = true; |
2321 | ||
7a5ca19f ML |
2322 | if (pipe_config->has_hdmi_sink) { |
2323 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
2324 | pipe_config->has_audio = intel_hdmi->has_audio; | |
2325 | else | |
2326 | pipe_config->has_audio = | |
2327 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
2328 | } | |
9ed109a7 | 2329 | |
4e53c2e0 | 2330 | /* |
cd9e11a8 RS |
2331 | * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need |
2332 | * to check that the higher clock still fits within limits. | |
4e53c2e0 | 2333 | */ |
cd9e11a8 RS |
2334 | if (hdmi_deep_color_possible(pipe_config, 12) && |
2335 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, | |
2336 | true, force_dvi) == MODE_OK) { | |
e29c22c0 DV |
2337 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
2338 | desired_bpp = 12*3; | |
325b9d04 DV |
2339 | |
2340 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 2341 | pipe_config->port_clock = clock_12bpc; |
cd9e11a8 RS |
2342 | } else if (hdmi_deep_color_possible(pipe_config, 10) && |
2343 | hdmi_port_clock_valid(intel_hdmi, clock_10bpc, | |
2344 | true, force_dvi) == MODE_OK) { | |
2345 | DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n"); | |
2346 | desired_bpp = 10 * 3; | |
2347 | ||
2348 | /* Need to adjust the port link by 1.25x for 10bpc. */ | |
2349 | pipe_config->port_clock = clock_10bpc; | |
4e53c2e0 | 2350 | } else { |
e29c22c0 DV |
2351 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
2352 | desired_bpp = 8*3; | |
e64e739e VS |
2353 | |
2354 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
2355 | } |
2356 | ||
2357 | if (!pipe_config->bw_constrained) { | |
b64b7a60 | 2358 | DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp); |
e29c22c0 | 2359 | pipe_config->pipe_bpp = desired_bpp; |
4e53c2e0 DV |
2360 | } |
2361 | ||
e64e739e | 2362 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
7a5ca19f | 2363 | false, force_dvi) != MODE_OK) { |
e64e739e | 2364 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
204474a6 | 2365 | return -EINVAL; |
325b9d04 DV |
2366 | } |
2367 | ||
28b468a0 | 2368 | /* Set user selected PAR to incoming mode's member */ |
0e9f25d0 | 2369 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
28b468a0 | 2370 | |
d4d6279a ACO |
2371 | pipe_config->lane_count = 4; |
2372 | ||
9672a69c RV |
2373 | if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || |
2374 | IS_GEMINILAKE(dev_priv))) { | |
15953637 SS |
2375 | if (scdc->scrambling.low_rates) |
2376 | pipe_config->hdmi_scrambling = true; | |
2377 | ||
2378 | if (pipe_config->port_clock > 340000) { | |
2379 | pipe_config->hdmi_scrambling = true; | |
2380 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
2381 | } | |
2382 | } | |
2383 | ||
fbf08556 VS |
2384 | intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); |
2385 | ||
2386 | if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { | |
2387 | DRM_DEBUG_KMS("bad AVI infoframe\n"); | |
2388 | return -EINVAL; | |
2389 | } | |
2390 | ||
2391 | if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { | |
2392 | DRM_DEBUG_KMS("bad SPD infoframe\n"); | |
2393 | return -EINVAL; | |
2394 | } | |
2395 | ||
2396 | if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { | |
2397 | DRM_DEBUG_KMS("bad HDMI infoframe\n"); | |
2398 | return -EINVAL; | |
2399 | } | |
2400 | ||
204474a6 | 2401 | return 0; |
7d57382e EA |
2402 | } |
2403 | ||
953ece69 CW |
2404 | static void |
2405 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 2406 | { |
df0e9248 | 2407 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 2408 | |
953ece69 CW |
2409 | intel_hdmi->has_hdmi_sink = false; |
2410 | intel_hdmi->has_audio = false; | |
953ece69 | 2411 | |
b1ba124d VS |
2412 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
2413 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
2414 | ||
953ece69 CW |
2415 | kfree(to_intel_connector(connector)->detect_edid); |
2416 | to_intel_connector(connector)->detect_edid = NULL; | |
2417 | } | |
2418 | ||
b1ba124d | 2419 | static void |
d6199256 | 2420 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
2421 | { |
2422 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2423 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
8f4f2797 | 2424 | enum port port = hdmi_to_dig_port(hdmi)->base.port; |
b1ba124d VS |
2425 | struct i2c_adapter *adapter = |
2426 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
2427 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
2428 | ||
d6199256 VS |
2429 | /* |
2430 | * Type 1 DVI adaptors are not required to implement any | |
2431 | * registers, so we can't always detect their presence. | |
2432 | * Ideally we should be able to check the state of the | |
2433 | * CONFIG1 pin, but no such luck on our hardware. | |
2434 | * | |
2435 | * The only method left to us is to check the VBT to see | |
2436 | * if the port is a dual mode capable DP port. But let's | |
2437 | * only do that when we sucesfully read the EDID, to avoid | |
2438 | * confusing log messages about DP dual mode adaptors when | |
2439 | * there's nothing connected to the port. | |
2440 | */ | |
2441 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
30190629 AJ |
2442 | /* An overridden EDID imply that we want this port for testing. |
2443 | * Make sure not to set limits for that port. | |
2444 | */ | |
2445 | if (has_edid && !connector->override_edid && | |
d6199256 VS |
2446 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { |
2447 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
2448 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
2449 | } else { | |
2450 | type = DRM_DP_DUAL_MODE_NONE; | |
2451 | } | |
2452 | } | |
2453 | ||
2454 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
2455 | return; |
2456 | ||
2457 | hdmi->dp_dual_mode.type = type; | |
2458 | hdmi->dp_dual_mode.max_tmds_clock = | |
2459 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
2460 | ||
2461 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
2462 | drm_dp_get_dual_mode_type_name(type), | |
2463 | hdmi->dp_dual_mode.max_tmds_clock); | |
2464 | } | |
2465 | ||
953ece69 | 2466 | static bool |
23f889bd | 2467 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
2468 | { |
2469 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2470 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
0e6e0be4 | 2471 | intel_wakeref_t wakeref; |
23f889bd | 2472 | struct edid *edid; |
953ece69 | 2473 | bool connected = false; |
cfb926e1 | 2474 | struct i2c_adapter *i2c; |
164c8598 | 2475 | |
0e6e0be4 | 2476 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 2477 | |
cfb926e1 SB |
2478 | i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); |
2479 | ||
2480 | edid = drm_get_edid(connector, i2c); | |
2481 | ||
2482 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
2483 | DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
2484 | intel_gmbus_force_bit(i2c, true); | |
2485 | edid = drm_get_edid(connector, i2c); | |
2486 | intel_gmbus_force_bit(i2c, false); | |
2487 | } | |
2ded9e27 | 2488 | |
23f889bd | 2489 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 2490 | |
0e6e0be4 | 2491 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
30ad48b7 | 2492 | |
953ece69 CW |
2493 | to_intel_connector(connector)->detect_edid = edid; |
2494 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
953ece69 | 2495 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
7a5ca19f | 2496 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
2497 | |
2498 | connected = true; | |
55b7d6e8 CW |
2499 | } |
2500 | ||
9c229127 NA |
2501 | cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); |
2502 | ||
953ece69 CW |
2503 | return connected; |
2504 | } | |
2505 | ||
8166fcea DV |
2506 | static enum drm_connector_status |
2507 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 2508 | { |
39d1e234 | 2509 | enum drm_connector_status status = connector_status_disconnected; |
8166fcea | 2510 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
9c229127 | 2511 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
39d1e234 | 2512 | struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; |
0e6e0be4 | 2513 | intel_wakeref_t wakeref; |
953ece69 | 2514 | |
8166fcea DV |
2515 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2516 | connector->base.id, connector->name); | |
2517 | ||
0e6e0be4 | 2518 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
29bb94bb | 2519 | |
2dd24a9c | 2520 | if (INTEL_GEN(dev_priv) >= 11 && |
39d1e234 PZ |
2521 | !intel_digital_port_connected(encoder)) |
2522 | goto out; | |
2523 | ||
8166fcea | 2524 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 2525 | |
7e732cac | 2526 | if (intel_hdmi_set_edid(connector)) |
953ece69 | 2527 | status = connector_status_connected; |
671dedd2 | 2528 | |
39d1e234 | 2529 | out: |
0e6e0be4 | 2530 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
29bb94bb | 2531 | |
9c229127 NA |
2532 | if (status != connector_status_connected) |
2533 | cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); | |
2534 | ||
2ded9e27 | 2535 | return status; |
7d57382e EA |
2536 | } |
2537 | ||
953ece69 CW |
2538 | static void |
2539 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 2540 | { |
953ece69 CW |
2541 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2542 | connector->base.id, connector->name); | |
7d57382e | 2543 | |
953ece69 | 2544 | intel_hdmi_unset_edid(connector); |
671dedd2 | 2545 | |
953ece69 CW |
2546 | if (connector->status != connector_status_connected) |
2547 | return; | |
671dedd2 | 2548 | |
23f889bd | 2549 | intel_hdmi_set_edid(connector); |
953ece69 | 2550 | } |
671dedd2 | 2551 | |
953ece69 CW |
2552 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
2553 | { | |
2554 | struct edid *edid; | |
2555 | ||
2556 | edid = to_intel_connector(connector)->detect_edid; | |
2557 | if (edid == NULL) | |
2558 | return 0; | |
671dedd2 | 2559 | |
953ece69 | 2560 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
2561 | } |
2562 | ||
fd6bbda9 | 2563 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2564 | const struct intel_crtc_state *pipe_config, |
2565 | const struct drm_connector_state *conn_state) | |
13732ba7 | 2566 | { |
f99be1b3 VS |
2567 | struct intel_digital_port *intel_dig_port = |
2568 | enc_to_dig_port(&encoder->base); | |
13732ba7 | 2569 | |
ac240288 | 2570 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2571 | |
790ea70c | 2572 | intel_dig_port->set_infoframes(encoder, |
f99be1b3 VS |
2573 | pipe_config->has_infoframe, |
2574 | pipe_config, conn_state); | |
13732ba7 JB |
2575 | } |
2576 | ||
fd6bbda9 | 2577 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2578 | const struct intel_crtc_state *pipe_config, |
2579 | const struct drm_connector_state *conn_state) | |
89b667f8 JB |
2580 | { |
2581 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2e1029c6 | 2582 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5f68c275 | 2583 | |
2e1029c6 | 2584 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
b76cf76b | 2585 | |
53d98725 ACO |
2586 | /* HDMI 1.0V-2dB */ |
2587 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
2588 | 0x2b247878); | |
2589 | ||
790ea70c | 2590 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2591 | pipe_config->has_infoframe, |
2592 | pipe_config, conn_state); | |
13732ba7 | 2593 | |
fd6bbda9 | 2594 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 2595 | |
9b6de0a1 | 2596 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
2597 | } |
2598 | ||
fd6bbda9 | 2599 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2600 | const struct intel_crtc_state *pipe_config, |
2601 | const struct drm_connector_state *conn_state) | |
89b667f8 | 2602 | { |
ac240288 | 2603 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2604 | |
2e1029c6 | 2605 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
89b667f8 JB |
2606 | } |
2607 | ||
fd6bbda9 | 2608 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2609 | const struct intel_crtc_state *pipe_config, |
2610 | const struct drm_connector_state *conn_state) | |
9197c88b | 2611 | { |
ac240288 | 2612 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 2613 | |
2e1029c6 | 2614 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
2615 | } |
2616 | ||
fd6bbda9 | 2617 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2618 | const struct intel_crtc_state *old_crtc_state, |
2619 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 2620 | { |
2e1029c6 | 2621 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
2622 | } |
2623 | ||
fd6bbda9 | 2624 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2625 | const struct intel_crtc_state *old_crtc_state, |
2626 | const struct drm_connector_state *old_conn_state) | |
89b667f8 | 2627 | { |
89b667f8 | 2628 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
2e1029c6 | 2629 | vlv_phy_reset_lanes(encoder, old_crtc_state); |
89b667f8 JB |
2630 | } |
2631 | ||
fd6bbda9 | 2632 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2633 | const struct intel_crtc_state *old_crtc_state, |
2634 | const struct drm_connector_state *old_conn_state) | |
580d3811 | 2635 | { |
580d3811 | 2636 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2637 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 2638 | |
221c7862 | 2639 | vlv_dpio_get(dev_priv); |
580d3811 | 2640 | |
a8f327fb | 2641 | /* Assert data lane reset */ |
2e1029c6 | 2642 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 2643 | |
221c7862 | 2644 | vlv_dpio_put(dev_priv); |
580d3811 VS |
2645 | } |
2646 | ||
fd6bbda9 | 2647 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2648 | const struct intel_crtc_state *pipe_config, |
2649 | const struct drm_connector_state *conn_state) | |
e4a1d846 CML |
2650 | { |
2651 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2652 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2653 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 2654 | |
2e1029c6 | 2655 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
a02ef3c7 | 2656 | |
e4a1d846 CML |
2657 | /* FIXME: Program the support xxx V-dB */ |
2658 | /* Use 800mV-0dB */ | |
b7fa22d8 | 2659 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 2660 | |
790ea70c | 2661 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2662 | pipe_config->has_infoframe, |
2663 | pipe_config, conn_state); | |
b4eb1564 | 2664 | |
fd6bbda9 | 2665 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 2666 | |
9b6de0a1 | 2667 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
2668 | |
2669 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2670 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2671 | } |
2672 | ||
bdc93fe0 R |
2673 | static int |
2674 | intel_hdmi_connector_register(struct drm_connector *connector) | |
2675 | { | |
2676 | int ret; | |
2677 | ||
2678 | ret = intel_connector_register(connector); | |
2679 | if (ret) | |
2680 | return ret; | |
2681 | ||
2682 | i915_debugfs_connector_add(connector); | |
2683 | ||
2684 | return ret; | |
2685 | } | |
2686 | ||
7d57382e EA |
2687 | static void intel_hdmi_destroy(struct drm_connector *connector) |
2688 | { | |
9c229127 NA |
2689 | if (intel_attached_hdmi(connector)->cec_notifier) |
2690 | cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier); | |
d4b26e4f JN |
2691 | |
2692 | intel_connector_destroy(connector); | |
7d57382e EA |
2693 | } |
2694 | ||
7d57382e | 2695 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
7d57382e | 2696 | .detect = intel_hdmi_detect, |
953ece69 | 2697 | .force = intel_hdmi_force, |
7d57382e | 2698 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
2699 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
2700 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
bdc93fe0 | 2701 | .late_register = intel_hdmi_connector_register, |
c191eca1 | 2702 | .early_unregister = intel_connector_unregister, |
7d57382e | 2703 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 2704 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 2705 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
2706 | }; |
2707 | ||
2708 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
2709 | .get_modes = intel_hdmi_get_modes, | |
2710 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 2711 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
2712 | }; |
2713 | ||
7d57382e | 2714 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 2715 | .destroy = intel_encoder_destroy, |
7d57382e EA |
2716 | }; |
2717 | ||
55b7d6e8 CW |
2718 | static void |
2719 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
2720 | { | |
f1a12172 | 2721 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
2f146b78 US |
2722 | struct intel_digital_port *intel_dig_port = |
2723 | hdmi_to_dig_port(intel_hdmi); | |
f1a12172 | 2724 | |
3f43c48d | 2725 | intel_attach_force_audio_property(connector); |
e953fd7b | 2726 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 2727 | intel_attach_aspect_ratio_property(connector); |
2f146b78 US |
2728 | |
2729 | /* | |
2730 | * Attach Colorspace property for Non LSPCON based device | |
2731 | * ToDo: This needs to be extended for LSPCON implementation | |
2732 | * as well. Will be implemented separately. | |
2733 | */ | |
2734 | if (!intel_dig_port->lspcon.active) | |
2735 | intel_attach_colorspace_property(connector); | |
2736 | ||
6553b123 | 2737 | drm_connector_attach_content_type_property(connector); |
0e9f25d0 | 2738 | connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
f1a12172 | 2739 | |
b2ae318a | 2740 | if (!HAS_GMCH(dev_priv)) |
f1a12172 | 2741 | drm_connector_attach_max_bpc_property(connector, 8, 12); |
55b7d6e8 CW |
2742 | } |
2743 | ||
15953637 SS |
2744 | /* |
2745 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
2746 | * @encoder: intel_encoder | |
2747 | * @connector: drm_connector | |
2748 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
2749 | * or reset the high tmds clock ratio for scrambling | |
2750 | * @scrambling: bool to Indicate if the function needs to set or reset | |
2751 | * sink scrambling | |
2752 | * | |
2753 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
2754 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
2755 | * it enables scrambling. This should be called before enabling the HDMI | |
2756 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
2757 | * detect a scrambled clock within 100 ms. | |
277ab5ab VS |
2758 | * |
2759 | * Returns: | |
2760 | * True on success, false on failure. | |
15953637 | 2761 | */ |
277ab5ab | 2762 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
15953637 SS |
2763 | struct drm_connector *connector, |
2764 | bool high_tmds_clock_ratio, | |
2765 | bool scrambling) | |
2766 | { | |
277ab5ab | 2767 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
15953637 | 2768 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
15953637 | 2769 | struct drm_scrambling *sink_scrambling = |
277ab5ab VS |
2770 | &connector->display_info.hdmi.scdc.scrambling; |
2771 | struct i2c_adapter *adapter = | |
2772 | intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); | |
15953637 SS |
2773 | |
2774 | if (!sink_scrambling->supported) | |
277ab5ab | 2775 | return true; |
15953637 | 2776 | |
277ab5ab VS |
2777 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", |
2778 | connector->base.id, connector->name, | |
2779 | yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); | |
15953637 | 2780 | |
277ab5ab VS |
2781 | /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ |
2782 | return drm_scdc_set_high_tmds_clock_ratio(adapter, | |
2783 | high_tmds_clock_ratio) && | |
2784 | drm_scdc_set_scrambling(adapter, scrambling); | |
15953637 SS |
2785 | } |
2786 | ||
cec3bb01 | 2787 | static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
e4ab73a1 | 2788 | { |
e4ab73a1 VS |
2789 | u8 ddc_pin; |
2790 | ||
cec3bb01 AS |
2791 | switch (port) { |
2792 | case PORT_B: | |
2793 | ddc_pin = GMBUS_PIN_DPB; | |
2794 | break; | |
2795 | case PORT_C: | |
2796 | ddc_pin = GMBUS_PIN_DPC; | |
2797 | break; | |
2798 | case PORT_D: | |
2799 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
2800 | break; | |
2801 | default: | |
2802 | MISSING_CASE(port); | |
2803 | ddc_pin = GMBUS_PIN_DPB; | |
2804 | break; | |
e4ab73a1 | 2805 | } |
cec3bb01 AS |
2806 | return ddc_pin; |
2807 | } | |
2808 | ||
2809 | static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) | |
2810 | { | |
2811 | u8 ddc_pin; | |
e4ab73a1 VS |
2812 | |
2813 | switch (port) { | |
2814 | case PORT_B: | |
cec3bb01 | 2815 | ddc_pin = GMBUS_PIN_1_BXT; |
e4ab73a1 VS |
2816 | break; |
2817 | case PORT_C: | |
cec3bb01 AS |
2818 | ddc_pin = GMBUS_PIN_2_BXT; |
2819 | break; | |
2820 | default: | |
2821 | MISSING_CASE(port); | |
2822 | ddc_pin = GMBUS_PIN_1_BXT; | |
2823 | break; | |
2824 | } | |
2825 | return ddc_pin; | |
2826 | } | |
2827 | ||
2828 | static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
2829 | enum port port) | |
2830 | { | |
2831 | u8 ddc_pin; | |
2832 | ||
2833 | switch (port) { | |
2834 | case PORT_B: | |
2835 | ddc_pin = GMBUS_PIN_1_BXT; | |
2836 | break; | |
2837 | case PORT_C: | |
2838 | ddc_pin = GMBUS_PIN_2_BXT; | |
e4ab73a1 VS |
2839 | break; |
2840 | case PORT_D: | |
cec3bb01 AS |
2841 | ddc_pin = GMBUS_PIN_4_CNP; |
2842 | break; | |
3a2a59cc RV |
2843 | case PORT_F: |
2844 | ddc_pin = GMBUS_PIN_3_BXT; | |
2845 | break; | |
cec3bb01 AS |
2846 | default: |
2847 | MISSING_CASE(port); | |
2848 | ddc_pin = GMBUS_PIN_1_BXT; | |
2849 | break; | |
2850 | } | |
2851 | return ddc_pin; | |
2852 | } | |
2853 | ||
5c749c52 AS |
2854 | static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
2855 | { | |
2856 | u8 ddc_pin; | |
2857 | ||
2858 | switch (port) { | |
2859 | case PORT_A: | |
2860 | ddc_pin = GMBUS_PIN_1_BXT; | |
2861 | break; | |
2862 | case PORT_B: | |
2863 | ddc_pin = GMBUS_PIN_2_BXT; | |
2864 | break; | |
2865 | case PORT_C: | |
2866 | ddc_pin = GMBUS_PIN_9_TC1_ICP; | |
2867 | break; | |
2868 | case PORT_D: | |
2869 | ddc_pin = GMBUS_PIN_10_TC2_ICP; | |
2870 | break; | |
2871 | case PORT_E: | |
2872 | ddc_pin = GMBUS_PIN_11_TC3_ICP; | |
2873 | break; | |
2874 | case PORT_F: | |
2875 | ddc_pin = GMBUS_PIN_12_TC4_ICP; | |
2876 | break; | |
2877 | default: | |
2878 | MISSING_CASE(port); | |
2879 | ddc_pin = GMBUS_PIN_2_BXT; | |
2880 | break; | |
2881 | } | |
2882 | return ddc_pin; | |
2883 | } | |
2884 | ||
cec3bb01 AS |
2885 | static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, |
2886 | enum port port) | |
2887 | { | |
2888 | u8 ddc_pin; | |
2889 | ||
2890 | switch (port) { | |
2891 | case PORT_B: | |
2892 | ddc_pin = GMBUS_PIN_DPB; | |
2893 | break; | |
2894 | case PORT_C: | |
2895 | ddc_pin = GMBUS_PIN_DPC; | |
2896 | break; | |
2897 | case PORT_D: | |
2898 | ddc_pin = GMBUS_PIN_DPD; | |
e4ab73a1 VS |
2899 | break; |
2900 | default: | |
2901 | MISSING_CASE(port); | |
2902 | ddc_pin = GMBUS_PIN_DPB; | |
2903 | break; | |
2904 | } | |
cec3bb01 AS |
2905 | return ddc_pin; |
2906 | } | |
2907 | ||
2908 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, | |
2909 | enum port port) | |
2910 | { | |
2911 | const struct ddi_vbt_port_info *info = | |
2912 | &dev_priv->vbt.ddi_port_info[port]; | |
2913 | u8 ddc_pin; | |
2914 | ||
2915 | if (info->alternate_ddc_pin) { | |
2916 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
2917 | info->alternate_ddc_pin, port_name(port)); | |
2918 | return info->alternate_ddc_pin; | |
2919 | } | |
2920 | ||
e0f83eb5 RV |
2921 | if (HAS_PCH_ICP(dev_priv)) |
2922 | ddc_pin = icl_port_to_ddc_pin(dev_priv, port); | |
cec3bb01 AS |
2923 | else if (HAS_PCH_CNP(dev_priv)) |
2924 | ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); | |
e0f83eb5 RV |
2925 | else if (IS_GEN9_LP(dev_priv)) |
2926 | ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); | |
2927 | else if (IS_CHERRYVIEW(dev_priv)) | |
2928 | ddc_pin = chv_port_to_ddc_pin(dev_priv, port); | |
cec3bb01 AS |
2929 | else |
2930 | ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); | |
e4ab73a1 VS |
2931 | |
2932 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
2933 | ddc_pin, port_name(port)); | |
2934 | ||
2935 | return ddc_pin; | |
2936 | } | |
2937 | ||
385e4de0 VS |
2938 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port) |
2939 | { | |
2940 | struct drm_i915_private *dev_priv = | |
2941 | to_i915(intel_dig_port->base.base.dev); | |
2942 | ||
2943 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
2944 | intel_dig_port->write_infoframe = vlv_write_infoframe; | |
f2a10d61 | 2945 | intel_dig_port->read_infoframe = vlv_read_infoframe; |
385e4de0 | 2946 | intel_dig_port->set_infoframes = vlv_set_infoframes; |
509efa2b | 2947 | intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; |
385e4de0 VS |
2948 | } else if (IS_G4X(dev_priv)) { |
2949 | intel_dig_port->write_infoframe = g4x_write_infoframe; | |
f2a10d61 | 2950 | intel_dig_port->read_infoframe = g4x_read_infoframe; |
385e4de0 | 2951 | intel_dig_port->set_infoframes = g4x_set_infoframes; |
509efa2b | 2952 | intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; |
385e4de0 | 2953 | } else if (HAS_DDI(dev_priv)) { |
06c812d7 | 2954 | if (intel_dig_port->lspcon.active) { |
509efa2b | 2955 | intel_dig_port->write_infoframe = lspcon_write_infoframe; |
f2a10d61 | 2956 | intel_dig_port->read_infoframe = lspcon_read_infoframe; |
06c812d7 | 2957 | intel_dig_port->set_infoframes = lspcon_set_infoframes; |
509efa2b | 2958 | intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; |
06c812d7 | 2959 | } else { |
06c812d7 | 2960 | intel_dig_port->write_infoframe = hsw_write_infoframe; |
f2a10d61 | 2961 | intel_dig_port->read_infoframe = hsw_read_infoframe; |
509efa2b VS |
2962 | intel_dig_port->set_infoframes = hsw_set_infoframes; |
2963 | intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; | |
06c812d7 | 2964 | } |
385e4de0 VS |
2965 | } else if (HAS_PCH_IBX(dev_priv)) { |
2966 | intel_dig_port->write_infoframe = ibx_write_infoframe; | |
f2a10d61 | 2967 | intel_dig_port->read_infoframe = ibx_read_infoframe; |
385e4de0 | 2968 | intel_dig_port->set_infoframes = ibx_set_infoframes; |
509efa2b | 2969 | intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; |
385e4de0 VS |
2970 | } else { |
2971 | intel_dig_port->write_infoframe = cpt_write_infoframe; | |
f2a10d61 | 2972 | intel_dig_port->read_infoframe = cpt_read_infoframe; |
385e4de0 | 2973 | intel_dig_port->set_infoframes = cpt_set_infoframes; |
509efa2b | 2974 | intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; |
385e4de0 VS |
2975 | } |
2976 | } | |
2977 | ||
00c09d70 PZ |
2978 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2979 | struct intel_connector *intel_connector) | |
7d57382e | 2980 | { |
b9cb234c PZ |
2981 | struct drm_connector *connector = &intel_connector->base; |
2982 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
2983 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2984 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 2985 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 2986 | enum port port = intel_encoder->port; |
373a3cf7 | 2987 | |
22f35042 VS |
2988 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2989 | port_name(port)); | |
2990 | ||
ccb1a831 VS |
2991 | if (WARN(intel_dig_port->max_lanes < 4, |
2992 | "Not enough lanes (%d) for HDMI on port %c\n", | |
2993 | intel_dig_port->max_lanes, port_name(port))) | |
2994 | return; | |
2995 | ||
7d57382e | 2996 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 2997 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
2998 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2999 | ||
c3febcc4 | 3000 | connector->interlace_allowed = 1; |
7d57382e | 3001 | connector->doublescan_allowed = 0; |
573e74ad | 3002 | connector->stereo_allowed = 1; |
66a9278e | 3003 | |
9672a69c | 3004 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
eadc2e51 SS |
3005 | connector->ycbcr_420_allowed = true; |
3006 | ||
e4ab73a1 VS |
3007 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
3008 | ||
f761bef2 | 3009 | if (WARN_ON(port == PORT_A)) |
e4ab73a1 | 3010 | return; |
cf53902f | 3011 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
7d57382e | 3012 | |
4f8036a2 | 3013 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
3014 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3015 | else | |
3016 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
3017 | |
3018 | intel_hdmi_add_properties(intel_hdmi, connector); | |
3019 | ||
04707f97 R |
3020 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
3021 | intel_hdmi->attached_connector = intel_connector; | |
3022 | ||
fdddd08c | 3023 | if (is_hdcp_supported(dev_priv, port)) { |
2320175f SP |
3024 | int ret = intel_hdcp_init(intel_connector, |
3025 | &intel_hdmi_hdcp_shim); | |
3026 | if (ret) | |
3027 | DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); | |
3028 | } | |
3029 | ||
b9cb234c PZ |
3030 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3031 | * 0xd. Failure to do so will result in spurious interrupts being | |
3032 | * generated on the port when a cable is not attached. | |
3033 | */ | |
1c0f1b3d | 3034 | if (IS_G45(dev_priv)) { |
b9cb234c PZ |
3035 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
3036 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
3037 | } | |
9c229127 NA |
3038 | |
3039 | intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev, | |
3040 | port_identifier(port)); | |
3041 | if (!intel_hdmi->cec_notifier) | |
3042 | DRM_DEBUG_KMS("CEC notifier get failed\n"); | |
b9cb234c PZ |
3043 | } |
3044 | ||
c39055b0 | 3045 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 3046 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
3047 | { |
3048 | struct intel_digital_port *intel_dig_port; | |
3049 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
3050 | struct intel_connector *intel_connector; |
3051 | ||
b14c5679 | 3052 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
3053 | if (!intel_dig_port) |
3054 | return; | |
3055 | ||
08d9bc92 | 3056 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
3057 | if (!intel_connector) { |
3058 | kfree(intel_dig_port); | |
3059 | return; | |
3060 | } | |
3061 | ||
3062 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 3063 | |
c39055b0 ACO |
3064 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
3065 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
3066 | "HDMI %c", port_name(port)); | |
00c09d70 | 3067 | |
dba14b27 | 3068 | intel_encoder->hotplug = intel_encoder_hotplug; |
5bfe2ac0 | 3069 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 3070 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
3071 | intel_encoder->disable = pch_disable_hdmi; |
3072 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
3073 | } else { | |
3074 | intel_encoder->disable = g4x_disable_hdmi; | |
3075 | } | |
00c09d70 | 3076 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 3077 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 3078 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 3079 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
3080 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
3081 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 3082 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 3083 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 3084 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
3085 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
3086 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 3087 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 3088 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 3089 | } else { |
13732ba7 | 3090 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 3091 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 3092 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 3093 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 3094 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 3095 | else |
bf868c7d | 3096 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 3097 | } |
5ab432ef | 3098 | |
b9cb234c | 3099 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 3100 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 3101 | intel_encoder->port = port; |
920a14b2 | 3102 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
3103 | if (port == PORT_D) |
3104 | intel_encoder->crtc_mask = 1 << 2; | |
3105 | else | |
3106 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
3107 | } else { | |
3108 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
3109 | } | |
301ea74a | 3110 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
3111 | /* |
3112 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
3113 | * to work on real hardware. And since g4x can send infoframes to | |
3114 | * only one port anyway, nothing is lost by allowing it. | |
3115 | */ | |
9beb5fea | 3116 | if (IS_G4X(dev_priv)) |
c6f1495d | 3117 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 3118 | |
b242b7f7 | 3119 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 3120 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 3121 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 3122 | |
385e4de0 VS |
3123 | intel_infoframe_init(intel_dig_port); |
3124 | ||
39053089 | 3125 | intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
b9cb234c | 3126 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 3127 | } |