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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
ea5b213a CW |
40 | struct intel_hdmi { |
41 | struct intel_encoder base; | |
7d57382e | 42 | u32 sdvox_reg; |
f899fc64 | 43 | int ddc_bus; |
9dff6af8 | 44 | bool has_hdmi_sink; |
7d57382e EA |
45 | }; |
46 | ||
ea5b213a CW |
47 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
48 | { | |
4ef69c7a | 49 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
50 | } |
51 | ||
df0e9248 CW |
52 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
53 | { | |
54 | return container_of(intel_attached_encoder(connector), | |
55 | struct intel_hdmi, base); | |
56 | } | |
57 | ||
7d57382e EA |
58 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
59 | struct drm_display_mode *mode, | |
60 | struct drm_display_mode *adjusted_mode) | |
61 | { | |
62 | struct drm_device *dev = encoder->dev; | |
63 | struct drm_i915_private *dev_priv = dev->dev_private; | |
64 | struct drm_crtc *crtc = encoder->crtc; | |
65 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea5b213a | 66 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
67 | u32 sdvox; |
68 | ||
b599c0bc AJ |
69 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
70 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
71 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
72 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
73 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 74 | |
ea5b213a | 75 | if (intel_hdmi->has_hdmi_sink) { |
7d57382e | 76 | sdvox |= SDVO_AUDIO_ENABLE; |
467b200d ZW |
77 | if (HAS_PCH_CPT(dev)) |
78 | sdvox |= HDMI_MODE_SELECT; | |
79 | } | |
7d57382e | 80 | |
0f229062 ZW |
81 | if (intel_crtc->pipe == 1) { |
82 | if (HAS_PCH_CPT(dev)) | |
83 | sdvox |= PORT_TRANS_B_SEL_CPT; | |
84 | else | |
85 | sdvox |= SDVO_PIPE_B_SELECT; | |
86 | } | |
7d57382e | 87 | |
ea5b213a CW |
88 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
89 | POSTING_READ(intel_hdmi->sdvox_reg); | |
7d57382e EA |
90 | } |
91 | ||
92 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
93 | { | |
94 | struct drm_device *dev = encoder->dev; | |
95 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 96 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
97 | u32 temp; |
98 | ||
ea5b213a | 99 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
100 | |
101 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
102 | * we do this anyway which shows more stable in testing. | |
103 | */ | |
c619eed4 | 104 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
105 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
106 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
107 | } |
108 | ||
109 | if (mode != DRM_MODE_DPMS_ON) { | |
110 | temp &= ~SDVO_ENABLE; | |
7d57382e | 111 | } else { |
d8a2d0e0 | 112 | temp |= SDVO_ENABLE; |
7d57382e | 113 | } |
d8a2d0e0 | 114 | |
ea5b213a CW |
115 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
116 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
117 | |
118 | /* HW workaround, need to write this twice for issue that may result | |
119 | * in first write getting masked. | |
120 | */ | |
c619eed4 | 121 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
122 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
123 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 124 | } |
7d57382e EA |
125 | } |
126 | ||
7d57382e EA |
127 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
128 | struct drm_display_mode *mode) | |
129 | { | |
130 | if (mode->clock > 165000) | |
131 | return MODE_CLOCK_HIGH; | |
132 | if (mode->clock < 20000) | |
133 | return MODE_CLOCK_HIGH; | |
134 | ||
135 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
136 | return MODE_NO_DBLESCAN; | |
137 | ||
138 | return MODE_OK; | |
139 | } | |
140 | ||
141 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
142 | struct drm_display_mode *mode, | |
143 | struct drm_display_mode *adjusted_mode) | |
144 | { | |
145 | return true; | |
146 | } | |
147 | ||
aa93d632 | 148 | static enum drm_connector_status |
930a9e28 | 149 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 150 | { |
df0e9248 | 151 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
152 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
153 | struct edid *edid; | |
aa93d632 | 154 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 155 | |
ea5b213a | 156 | intel_hdmi->has_hdmi_sink = false; |
f899fc64 CW |
157 | edid = drm_get_edid(connector, |
158 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); | |
2ded9e27 | 159 | |
aa93d632 | 160 | if (edid) { |
be9f1c4f | 161 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 162 | status = connector_status_connected; |
ea5b213a | 163 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
aa93d632 | 164 | } |
674e2d08 | 165 | connector->display_info.raw_edid = NULL; |
aa93d632 | 166 | kfree(edid); |
9dff6af8 | 167 | } |
30ad48b7 | 168 | |
2ded9e27 | 169 | return status; |
7d57382e EA |
170 | } |
171 | ||
172 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
173 | { | |
df0e9248 | 174 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 175 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
176 | |
177 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
178 | * we can send audio to it. | |
179 | */ | |
180 | ||
f899fc64 CW |
181 | return intel_ddc_get_modes(connector, |
182 | &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter); | |
7d57382e EA |
183 | } |
184 | ||
185 | static void intel_hdmi_destroy(struct drm_connector *connector) | |
186 | { | |
7d57382e EA |
187 | drm_sysfs_connector_remove(connector); |
188 | drm_connector_cleanup(connector); | |
674e2d08 | 189 | kfree(connector); |
7d57382e EA |
190 | } |
191 | ||
192 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
193 | .dpms = intel_hdmi_dpms, | |
194 | .mode_fixup = intel_hdmi_mode_fixup, | |
195 | .prepare = intel_encoder_prepare, | |
196 | .mode_set = intel_hdmi_mode_set, | |
197 | .commit = intel_encoder_commit, | |
198 | }; | |
199 | ||
200 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 201 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
202 | .detect = intel_hdmi_detect, |
203 | .fill_modes = drm_helper_probe_single_connector_modes, | |
204 | .destroy = intel_hdmi_destroy, | |
205 | }; | |
206 | ||
207 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
208 | .get_modes = intel_hdmi_get_modes, | |
209 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 210 | .best_encoder = intel_best_encoder, |
7d57382e EA |
211 | }; |
212 | ||
7d57382e | 213 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 214 | .destroy = intel_encoder_destroy, |
7d57382e EA |
215 | }; |
216 | ||
7d57382e EA |
217 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | struct drm_connector *connector; | |
21d40d37 | 221 | struct intel_encoder *intel_encoder; |
674e2d08 | 222 | struct intel_connector *intel_connector; |
ea5b213a | 223 | struct intel_hdmi *intel_hdmi; |
7d57382e | 224 | |
ea5b213a CW |
225 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
226 | if (!intel_hdmi) | |
7d57382e | 227 | return; |
674e2d08 ZW |
228 | |
229 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
230 | if (!intel_connector) { | |
ea5b213a | 231 | kfree(intel_hdmi); |
674e2d08 ZW |
232 | return; |
233 | } | |
234 | ||
ea5b213a | 235 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
236 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
237 | DRM_MODE_ENCODER_TMDS); | |
238 | ||
674e2d08 | 239 | connector = &intel_connector->base; |
7d57382e | 240 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 241 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
242 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
243 | ||
21d40d37 | 244 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 245 | |
eb1f8e4f | 246 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
7d57382e EA |
247 | connector->interlace_allowed = 0; |
248 | connector->doublescan_allowed = 0; | |
21d40d37 | 249 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
7d57382e EA |
250 | |
251 | /* Set up the DDC bus. */ | |
f8aed700 | 252 | if (sdvox_reg == SDVOB) { |
21d40d37 | 253 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 254 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 255 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 256 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 257 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 258 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 259 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 260 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 261 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 262 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 263 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 264 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 265 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 266 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 267 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 268 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 269 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 270 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 271 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
f8aed700 | 272 | } |
7d57382e | 273 | |
ea5b213a | 274 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 275 | |
4ef69c7a | 276 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
7d57382e | 277 | |
df0e9248 | 278 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
279 | drm_sysfs_connector_add(connector); |
280 | ||
281 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
282 | * 0xd. Failure to do so will result in spurious interrupts being | |
283 | * generated on the port when a cable is not attached. | |
284 | */ | |
285 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
286 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
287 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
288 | } | |
7d57382e | 289 | } |