[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_hdmi.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_edid.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

struct intel_hdmi {
	struct intel_encoder base;
	u32 sdvox_reg;
	int ddc_bus;
	uint32_t color_range;
	bool has_hdmi_sink;
	bool has_audio;
	int force_audio;
	void (*write_infoframe)(struct drm_encoder *encoder,
				struct dip_infoframe *frame);
};

static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_hdmi, base.base);
}

static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_hdmi, base);
}

void intel_dip_infoframe_csum(struct dip_infoframe *frame)
{
	uint8_t *data = (uint8_t *)frame;
	uint8_t sum = 0;
	unsigned i;

	frame->checksum = 0;
	frame->ecc = 0;

	for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
		sum += data[i];

	frame->checksum = 0x100 - sum;
}

static u32 intel_infoframe_index(struct dip_infoframe *frame)
{
	u32 flags = 0;

	switch (frame->type) {
	case DIP_TYPE_AVI:
		flags |= VIDEO_DIP_SELECT_AVI;
		break;
	case DIP_TYPE_SPD:
		flags |= VIDEO_DIP_SELECT_SPD;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		break;
	}

	return flags;
}

static u32 intel_infoframe_flags(struct dip_infoframe *frame)
{
	u32 flags = 0;

	switch (frame->type) {
	case DIP_TYPE_AVI:
		flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
		break;
	case DIP_TYPE_SPD:
		flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_VSYNC;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		break;
	}

	return flags;
}

static void i9xx_write_infoframe(struct drm_encoder *encoder,
				 struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;


	/* XXX first guess at handling video port, is this corrent? */
	if (intel_hdmi->sdvox_reg == SDVOB)
		port = VIDEO_DIP_PORT_B;
	else if (intel_hdmi->sdvox_reg == SDVOC)
		port = VIDEO_DIP_PORT_C;
	else
		return;

	flags = intel_infoframe_index(frame);

	val &= ~VIDEO_DIP_SELECT_MASK;

	I915_WRITE(VIDEO_DIP_CTL, val | port | flags);

	for (i = 0; i < len; i += 4) {
		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}

	flags |= intel_infoframe_flags(frame);

	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
}

static void ironlake_write_infoframe(struct drm_encoder *encoder,
				     struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
	u32 flags, val = I915_READ(reg);

	intel_wait_for_vblank(dev, intel_crtc->pipe);

	flags = intel_infoframe_index(frame);

	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */

	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);

	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}

	flags |= intel_infoframe_flags(frame);

	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
}
static void intel_set_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	if (!intel_hdmi->has_hdmi_sink)
		return;

	intel_dip_infoframe_csum(frame);
	intel_hdmi->write_infoframe(encoder, frame);
}

static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
{
	struct dip_infoframe avi_if = {
		.type = DIP_TYPE_AVI,
		.ver = DIP_VERSION_AVI,
		.len = DIP_LEN_AVI,
	};

	intel_set_infoframe(encoder, &avi_if);
}

static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
{
	struct dip_infoframe spd_if;

	memset(&spd_if, 0, sizeof(spd_if));
	spd_if.type = DIP_TYPE_SPD;
	spd_if.ver = DIP_VERSION_SPD;
	spd_if.len = DIP_LEN_SPD;
	strcpy(spd_if.body.spd.vn, "Intel");
	strcpy(spd_if.body.spd.pd, "Integrated gfx");
	spd_if.body.spd.sdi = DIP_SPD_PC;

	intel_set_infoframe(encoder, &spd_if);
}

static void intel_hdmi_mode_set(struct drm_encoder *encoder,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 sdvox;

	sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
	if (!HAS_PCH_SPLIT(dev))
		sdvox |= intel_hdmi->color_range;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		sdvox |= SDVO_HSYNC_ACTIVE_HIGH;

	if (intel_crtc->bpp > 24)
		sdvox |= COLOR_FORMAT_12bpc;
	else
		sdvox |= COLOR_FORMAT_8bpc;

	/* Required on CPT */
	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
		sdvox |= HDMI_MODE_SELECT;

	if (intel_hdmi->has_audio) {
		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
		sdvox |= SDVO_AUDIO_ENABLE;
		sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
		intel_write_eld(encoder, adjusted_mode);
	}

	if (HAS_PCH_CPT(dev))
		sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
	else if (intel_crtc->pipe == 1)
		sdvox |= SDVO_PIPE_B_SELECT;

	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
	POSTING_READ(intel_hdmi->sdvox_reg);

	intel_hdmi_set_avi_infoframe(encoder);
	intel_hdmi_set_spd_infoframe(encoder);
}

static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 temp;
	u32 enable_bits = SDVO_ENABLE;

	if (intel_hdmi->has_audio)
		enable_bits |= SDVO_AUDIO_ENABLE;

	temp = I915_READ(intel_hdmi->sdvox_reg);

	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}

	if (mode != DRM_MODE_DPMS_ON) {
		temp &= ~enable_bits;
	} else {
		temp |= enable_bits;
	}

	I915_WRITE(intel_hdmi->sdvox_reg, temp);
	POSTING_READ(intel_hdmi->sdvox_reg);

	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}
}

static int intel_hdmi_mode_valid(struct drm_connector *connector,
				 struct drm_display_mode *mode)
{
	if (mode->clock > 165000)
		return MODE_CLOCK_HIGH;
	if (mode->clock < 20000)
		return MODE_CLOCK_LOW;

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	return MODE_OK;
}

static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
				  struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	return true;
}

static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	enum drm_connector_status status = connector_status_disconnected;

	intel_hdmi->has_hdmi_sink = false;
	intel_hdmi->has_audio = false;
	edid = drm_get_edid(connector,
			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);

	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
			status = connector_status_connected;
			intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
		}
		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	if (status == connector_status_connected) {
		if (intel_hdmi->force_audio)
			intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
	}

	return status;
}

static int intel_hdmi_get_modes(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	/* We should parse the EDID data and find out if it's an HDMI sink so
	 * we can send audio to it.
	 */

	return intel_ddc_get_modes(connector,
				   &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
}

static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	bool has_audio = false;

	edid = drm_get_edid(connector,
			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL)
			has_audio = drm_detect_monitor_audio(edid);

		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	return has_audio;
}

static int
intel_hdmi_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	int ret;

	ret = drm_connector_property_set_value(connector, property, val);
	if (ret)
		return ret;

	if (property == dev_priv->force_audio_property) {
		int i = val;
		bool has_audio;

		if (i == intel_hdmi->force_audio)
			return 0;

		intel_hdmi->force_audio = i;

		if (i == 0)
			has_audio = intel_hdmi_detect_audio(connector);
		else
			has_audio = i > 0;

		if (has_audio == intel_hdmi->has_audio)
			return 0;

		intel_hdmi->has_audio = has_audio;
		goto done;
	}

	if (property == dev_priv->broadcast_rgb_property) {
		if (val == !!intel_hdmi->color_range)
			return 0;

		intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
		goto done;
	}

	return -EINVAL;

done:
	if (intel_hdmi->base.base.crtc) {
		struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
		drm_crtc_helper_set_mode(crtc, &crtc->mode,
					 crtc->x, crtc->y,
					 crtc->fb);
	}

	return 0;
}

static void intel_hdmi_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	.dpms = intel_hdmi_dpms,
	.mode_fixup = intel_hdmi_mode_fixup,
	.prepare = intel_encoder_prepare,
	.mode_set = intel_hdmi_mode_set,
	.commit = intel_encoder_commit,
};

static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = intel_hdmi_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.set_property = intel_hdmi_set_property,
	.destroy = intel_hdmi_destroy,
};

static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
	.best_encoder = intel_best_encoder,
};

static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
	.destroy = intel_encoder_destroy,
};

static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
	intel_attach_force_audio_property(connector);
	intel_attach_broadcast_rgb_property(connector);
}

void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
	struct intel_encoder *intel_encoder;
	struct intel_connector *intel_connector;
	struct intel_hdmi *intel_hdmi;
	int i;

	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
	if (!intel_hdmi)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_hdmi);
		return;
	}

	intel_encoder = &intel_hdmi->base;
	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

	connector = &intel_connector->base;
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
			   DRM_MODE_CONNECTOR_HDMIA);
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

	intel_encoder->type = INTEL_OUTPUT_HDMI;

	connector->polled = DRM_CONNECTOR_POLL_HPD;
	connector->interlace_allowed = 0;
	connector->doublescan_allowed = 0;
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);

	/* Set up the DDC bus. */
	if (sdvox_reg == SDVOB) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == SDVOC) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMIB) {
		intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMIC) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMID) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
	}

	intel_hdmi->sdvox_reg = sdvox_reg;

	if (!HAS_PCH_SPLIT(dev)) {
		intel_hdmi->write_infoframe = i9xx_write_infoframe;
		I915_WRITE(VIDEO_DIP_CTL, 0);
	} else {
		intel_hdmi->write_infoframe = ironlake_write_infoframe;
		for_each_pipe(i)
			I915_WRITE(TVIDEO_DIP_CTL(i), 0);
	}

	drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);

	intel_hdmi_add_properties(intel_hdmi, connector);

	intel_connector_attach_encoder(intel_connector, intel_encoder);
	drm_sysfs_connector_add(connector);

	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}
Commit	Line	Data
7d57382e EA	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2009 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	* Jesse Barnes <jesse.barnes@intel.com>
	27	*/
	28
	29	#include <linux/i2c.h>
5a0e3ad6	30	#include <linux/slab.h>
7d57382e EA	31	#include <linux/delay.h>
	32	#include "drmP.h"
	33	#include "drm.h"
	34	#include "drm_crtc.h"
aa93d632	35	#include "drm_edid.h"
7d57382e EA	36	#include "intel_drv.h"
	37	#include "i915_drm.h"
	38	#include "i915_drv.h"
	39
ea5b213a CW	40	struct intel_hdmi {
ea5b213a CW	41	struct intel_encoder base;
7d57382e	42	u32 sdvox_reg;
f899fc64	43	int ddc_bus;
e953fd7b	44	uint32_t color_range;
9dff6af8	45	bool has_hdmi_sink;
2e3d6006	46	bool has_audio;
55b7d6e8	47	int force_audio;
45187ace JB	48	void (write_infoframe)(struct drm_encoder encoder,
45187ace JB	49	struct dip_infoframe *frame);
7d57382e EA	50	};
7d57382e EA	51
ea5b213a CW	52	static struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)
ea5b213a CW	53	{
4ef69c7a	54	return container_of(encoder, struct intel_hdmi, base.base);
ea5b213a CW	55	}
ea5b213a CW	56
df0e9248 CW	57	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)
	58	{
	59	return container_of(intel_attached_encoder(connector),
	60	struct intel_hdmi, base);
	61	}
	62
45187ace	63	void intel_dip_infoframe_csum(struct dip_infoframe *frame)
3c17fe4b	64	{
45187ace	65	uint8_t data = (uint8_t )frame;
3c17fe4b DH	66	uint8_t sum = 0;
	67	unsigned i;
	68
45187ace JB	69	frame->checksum = 0;
45187ace JB	70	frame->ecc = 0;
3c17fe4b	71
64a8fc01	72	for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++)
3c17fe4b DH	73	sum += data[i];
3c17fe4b DH	74
45187ace	75	frame->checksum = 0x100 - sum;
3c17fe4b DH	76	}
3c17fe4b DH	77
45187ace	78	static u32 intel_infoframe_index(struct dip_infoframe *frame)
3c17fe4b	79	{
45187ace JB	80	u32 flags = 0;
	81
	82	switch (frame->type) {
	83	case DIP_TYPE_AVI:
	84	flags \|= VIDEO_DIP_SELECT_AVI;
	85	break;
	86	case DIP_TYPE_SPD:
	87	flags \|= VIDEO_DIP_SELECT_SPD;
	88	break;
	89	default:
	90	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
	91	break;
	92	}
	93
	94	return flags;
	95	}
	96
	97	static u32 intel_infoframe_flags(struct dip_infoframe *frame)
	98	{
	99	u32 flags = 0;
	100
	101	switch (frame->type) {
	102	case DIP_TYPE_AVI:
	103	flags \|= VIDEO_DIP_ENABLE_AVI \| VIDEO_DIP_FREQ_VSYNC;
	104	break;
	105	case DIP_TYPE_SPD:
64a8fc01	106	flags \|= VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_FREQ_VSYNC;
45187ace JB	107	break;
	108	default:
	109	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
	110	break;
	111	}
	112
	113	return flags;
	114	}
	115
	116	static void i9xx_write_infoframe(struct drm_encoder *encoder,
	117	struct dip_infoframe *frame)
	118	{
	119	uint32_t data = (uint32_t )frame;
3c17fe4b DH	120	struct drm_device *dev = encoder->dev;
	121	struct drm_i915_private *dev_priv = dev->dev_private;
	122	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
45187ace JB	123	u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
45187ace JB	124	unsigned i, len = DIP_HEADER_SIZE + frame->len;
3c17fe4b	125
3c17fe4b DH	126
	127	/* XXX first guess at handling video port, is this corrent? */
	128	if (intel_hdmi->sdvox_reg == SDVOB)
	129	port = VIDEO_DIP_PORT_B;
	130	else if (intel_hdmi->sdvox_reg == SDVOC)
	131	port = VIDEO_DIP_PORT_C;
	132	else
	133	return;
	134
45187ace JB	135	flags = intel_infoframe_index(frame);
	136
	137	val &= ~VIDEO_DIP_SELECT_MASK;
	138
	139	I915_WRITE(VIDEO_DIP_CTL, val \| port \| flags);
3c17fe4b	140
45187ace	141	for (i = 0; i < len; i += 4) {
3c17fe4b DH	142	I915_WRITE(VIDEO_DIP_DATA, *data);
	143	data++;
	144	}
	145
45187ace JB	146	flags \|= intel_infoframe_flags(frame);
	147
	148	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE \| val \| port \| flags);
3c17fe4b DH	149	}
3c17fe4b DH	150
45187ace JB	151	static void ironlake_write_infoframe(struct drm_encoder *encoder,
45187ace JB	152	struct dip_infoframe *frame)
b055c8f3	153	{
45187ace	154	uint32_t data = (uint32_t )frame;
b055c8f3 JB	155	struct drm_device *dev = encoder->dev;
b055c8f3 JB	156	struct drm_i915_private *dev_priv = dev->dev_private;
b055c8f3 JB	157	struct drm_crtc *crtc = encoder->crtc;
	158	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	159	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
45187ace JB	160	unsigned i, len = DIP_HEADER_SIZE + frame->len;
45187ace JB	161	u32 flags, val = I915_READ(reg);
b055c8f3 JB	162
	163	intel_wait_for_vblank(dev, intel_crtc->pipe);
	164
45187ace	165	flags = intel_infoframe_index(frame);
b055c8f3	166
64a8fc01	167	val &= ~(VIDEO_DIP_SELECT_MASK \| 0xf); /* clear DIP data offset */
45187ace	168
64a8fc01	169	I915_WRITE(reg, VIDEO_DIP_ENABLE \| val \| flags);
45187ace JB	170
45187ace JB	171	for (i = 0; i < len; i += 4) {
b055c8f3 JB	172	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
	173	data++;
	174	}
	175
45187ace JB	176	flags \|= intel_infoframe_flags(frame);
	177
	178	I915_WRITE(reg, VIDEO_DIP_ENABLE \| val \| flags);
	179	}
	180	static void intel_set_infoframe(struct drm_encoder *encoder,
	181	struct dip_infoframe *frame)
	182	{
	183	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	184
	185	if (!intel_hdmi->has_hdmi_sink)
	186	return;
	187
	188	intel_dip_infoframe_csum(frame);
	189	intel_hdmi->write_infoframe(encoder, frame);
	190	}
	191
	192	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
	193	{
	194	struct dip_infoframe avi_if = {
	195	.type = DIP_TYPE_AVI,
	196	.ver = DIP_VERSION_AVI,
	197	.len = DIP_LEN_AVI,
	198	};
	199
	200	intel_set_infoframe(encoder, &avi_if);
b055c8f3 JB	201	}
b055c8f3 JB	202
c0864cb3 JB	203	static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
	204	{
	205	struct dip_infoframe spd_if;
	206
	207	memset(&spd_if, 0, sizeof(spd_if));
	208	spd_if.type = DIP_TYPE_SPD;
	209	spd_if.ver = DIP_VERSION_SPD;
	210	spd_if.len = DIP_LEN_SPD;
	211	strcpy(spd_if.body.spd.vn, "Intel");
	212	strcpy(spd_if.body.spd.pd, "Integrated gfx");
	213	spd_if.body.spd.sdi = DIP_SPD_PC;
	214
	215	intel_set_infoframe(encoder, &spd_if);
	216	}
	217
7d57382e EA	218	static void intel_hdmi_mode_set(struct drm_encoder *encoder,
	219	struct drm_display_mode *mode,
	220	struct drm_display_mode *adjusted_mode)
	221	{
	222	struct drm_device *dev = encoder->dev;
	223	struct drm_i915_private *dev_priv = dev->dev_private;
	224	struct drm_crtc *crtc = encoder->crtc;
	225	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a	226	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
7d57382e EA	227	u32 sdvox;
7d57382e EA	228
b599c0bc	229	sdvox = SDVO_ENCODING_HDMI \| SDVO_BORDER_ENABLE;
5d4fac97 JB	230	if (!HAS_PCH_SPLIT(dev))
5d4fac97 JB	231	sdvox \|= intel_hdmi->color_range;
b599c0bc AJ	232	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	233	sdvox \|= SDVO_VSYNC_ACTIVE_HIGH;
	234	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	235	sdvox \|= SDVO_HSYNC_ACTIVE_HIGH;
7d57382e	236
020f6704 JB	237	if (intel_crtc->bpp > 24)
	238	sdvox \|= COLOR_FORMAT_12bpc;
	239	else
	240	sdvox \|= COLOR_FORMAT_8bpc;
	241
2e3d6006 ZW	242	/* Required on CPT */
	243	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
	244	sdvox \|= HDMI_MODE_SELECT;
	245
3c17fe4b	246	if (intel_hdmi->has_audio) {
e0dac65e WF	247	DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
e0dac65e WF	248	pipe_name(intel_crtc->pipe));
7d57382e	249	sdvox \|= SDVO_AUDIO_ENABLE;
3c17fe4b	250	sdvox \|= SDVO_NULL_PACKETS_DURING_VSYNC;
e0dac65e	251	intel_write_eld(encoder, adjusted_mode);
3c17fe4b	252	}
7d57382e	253
75770564 JB	254	if (HAS_PCH_CPT(dev))
	255	sdvox \|= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
	256	else if (intel_crtc->pipe == 1)
	257	sdvox \|= SDVO_PIPE_B_SELECT;
7d57382e	258
ea5b213a CW	259	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
ea5b213a CW	260	POSTING_READ(intel_hdmi->sdvox_reg);
3c17fe4b	261
45187ace	262	intel_hdmi_set_avi_infoframe(encoder);
c0864cb3	263	intel_hdmi_set_spd_infoframe(encoder);
7d57382e EA	264	}
	265
	266	static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
	267	{
	268	struct drm_device *dev = encoder->dev;
	269	struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a	270	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
7d57382e	271	u32 temp;
2deed761 WF	272	u32 enable_bits = SDVO_ENABLE;
	273
	274	if (intel_hdmi->has_audio)
	275	enable_bits \|= SDVO_AUDIO_ENABLE;
7d57382e	276
ea5b213a	277	temp = I915_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	278
	279	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	280	* we do this anyway which shows more stable in testing.
	281	*/
c619eed4	282	if (HAS_PCH_SPLIT(dev)) {
ea5b213a CW	283	I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
ea5b213a CW	284	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	285	}
	286
	287	if (mode != DRM_MODE_DPMS_ON) {
2deed761	288	temp &= ~enable_bits;
7d57382e	289	} else {
2deed761	290	temp \|= enable_bits;
7d57382e	291	}
d8a2d0e0	292
ea5b213a CW	293	I915_WRITE(intel_hdmi->sdvox_reg, temp);
ea5b213a CW	294	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	295
	296	/* HW workaround, need to write this twice for issue that may result
	297	* in first write getting masked.
	298	*/
c619eed4	299	if (HAS_PCH_SPLIT(dev)) {
ea5b213a CW	300	I915_WRITE(intel_hdmi->sdvox_reg, temp);
ea5b213a CW	301	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0	302	}
7d57382e EA	303	}
7d57382e EA	304
7d57382e EA	305	static int intel_hdmi_mode_valid(struct drm_connector *connector,
	306	struct drm_display_mode *mode)
	307	{
	308	if (mode->clock > 165000)
	309	return MODE_CLOCK_HIGH;
	310	if (mode->clock < 20000)
5cbba41d	311	return MODE_CLOCK_LOW;
7d57382e EA	312
	313	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	314	return MODE_NO_DBLESCAN;
	315
	316	return MODE_OK;
	317	}
	318
	319	static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
	320	struct drm_display_mode *mode,
	321	struct drm_display_mode *adjusted_mode)
	322	{
	323	return true;
	324	}
	325
aa93d632	326	static enum drm_connector_status
930a9e28	327	intel_hdmi_detect(struct drm_connector *connector, bool force)
9dff6af8	328	{
df0e9248	329	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
f899fc64 CW	330	struct drm_i915_private *dev_priv = connector->dev->dev_private;
f899fc64 CW	331	struct edid *edid;
aa93d632	332	enum drm_connector_status status = connector_status_disconnected;
9dff6af8	333
ea5b213a	334	intel_hdmi->has_hdmi_sink = false;
2e3d6006	335	intel_hdmi->has_audio = false;
f899fc64 CW	336	edid = drm_get_edid(connector,
f899fc64 CW	337	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
2ded9e27	338
aa93d632	339	if (edid) {
be9f1c4f	340	if (edid->input & DRM_EDID_INPUT_DIGITAL) {
aa93d632	341	status = connector_status_connected;
ea5b213a	342	intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2e3d6006	343	intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
aa93d632	344	}
674e2d08	345	connector->display_info.raw_edid = NULL;
aa93d632	346	kfree(edid);
9dff6af8	347	}
30ad48b7	348
55b7d6e8 CW	349	if (status == connector_status_connected) {
	350	if (intel_hdmi->force_audio)
	351	intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
	352	}
	353
2ded9e27	354	return status;
7d57382e EA	355	}
	356
	357	static int intel_hdmi_get_modes(struct drm_connector *connector)
	358	{
df0e9248	359	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
f899fc64	360	struct drm_i915_private *dev_priv = connector->dev->dev_private;
7d57382e EA	361
	362	/* We should parse the EDID data and find out if it's an HDMI sink so
	363	* we can send audio to it.
	364	*/
	365
f899fc64 CW	366	return intel_ddc_get_modes(connector,
f899fc64 CW	367	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
7d57382e EA	368	}
7d57382e EA	369
1aad7ac0 CW	370	static bool
	371	intel_hdmi_detect_audio(struct drm_connector *connector)
	372	{
	373	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	374	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	375	struct edid *edid;
	376	bool has_audio = false;
	377
	378	edid = drm_get_edid(connector,
	379	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
	380	if (edid) {
	381	if (edid->input & DRM_EDID_INPUT_DIGITAL)
	382	has_audio = drm_detect_monitor_audio(edid);
	383
	384	connector->display_info.raw_edid = NULL;
	385	kfree(edid);
	386	}
	387
	388	return has_audio;
	389	}
	390
55b7d6e8 CW	391	static int
	392	intel_hdmi_set_property(struct drm_connector *connector,
	393	struct drm_property *property,
	394	uint64_t val)
	395	{
	396	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
e953fd7b	397	struct drm_i915_private *dev_priv = connector->dev->dev_private;
55b7d6e8 CW	398	int ret;
	399
	400	ret = drm_connector_property_set_value(connector, property, val);
	401	if (ret)
	402	return ret;
	403
3f43c48d	404	if (property == dev_priv->force_audio_property) {
1aad7ac0 CW	405	int i = val;
	406	bool has_audio;
	407
	408	if (i == intel_hdmi->force_audio)
55b7d6e8 CW	409	return 0;
55b7d6e8 CW	410
1aad7ac0	411	intel_hdmi->force_audio = i;
55b7d6e8	412
1aad7ac0 CW	413	if (i == 0)
	414	has_audio = intel_hdmi_detect_audio(connector);
	415	else
	416	has_audio = i > 0;
	417
	418	if (has_audio == intel_hdmi->has_audio)
55b7d6e8 CW	419	return 0;
55b7d6e8 CW	420
1aad7ac0	421	intel_hdmi->has_audio = has_audio;
55b7d6e8 CW	422	goto done;
	423	}
	424
e953fd7b CW	425	if (property == dev_priv->broadcast_rgb_property) {
	426	if (val == !!intel_hdmi->color_range)
	427	return 0;
	428
	429	intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
	430	goto done;
	431	}
	432
55b7d6e8 CW	433	return -EINVAL;
	434
	435	done:
	436	if (intel_hdmi->base.base.crtc) {
	437	struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
	438	drm_crtc_helper_set_mode(crtc, &crtc->mode,
	439	crtc->x, crtc->y,
	440	crtc->fb);
	441	}
	442
	443	return 0;
	444	}
	445
7d57382e EA	446	static void intel_hdmi_destroy(struct drm_connector *connector)
7d57382e EA	447	{
7d57382e EA	448	drm_sysfs_connector_remove(connector);
7d57382e EA	449	drm_connector_cleanup(connector);
674e2d08	450	kfree(connector);
7d57382e EA	451	}
	452
	453	static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	454	.dpms = intel_hdmi_dpms,
	455	.mode_fixup = intel_hdmi_mode_fixup,
	456	.prepare = intel_encoder_prepare,
	457	.mode_set = intel_hdmi_mode_set,
	458	.commit = intel_encoder_commit,
	459	};
	460
	461	static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
c9fb15f6	462	.dpms = drm_helper_connector_dpms,
7d57382e EA	463	.detect = intel_hdmi_detect,
7d57382e EA	464	.fill_modes = drm_helper_probe_single_connector_modes,
55b7d6e8	465	.set_property = intel_hdmi_set_property,
7d57382e EA	466	.destroy = intel_hdmi_destroy,
	467	};
	468
	469	static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	470	.get_modes = intel_hdmi_get_modes,
	471	.mode_valid = intel_hdmi_mode_valid,
df0e9248	472	.best_encoder = intel_best_encoder,
7d57382e EA	473	};
7d57382e EA	474
7d57382e	475	static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
ea5b213a	476	.destroy = intel_encoder_destroy,
7d57382e EA	477	};
7d57382e EA	478
55b7d6e8 CW	479	static void
	480	intel_hdmi_add_properties(struct intel_hdmi intel_hdmi, struct drm_connector connector)
	481	{
3f43c48d	482	intel_attach_force_audio_property(connector);
e953fd7b	483	intel_attach_broadcast_rgb_property(connector);
55b7d6e8 CW	484	}
55b7d6e8 CW	485
7d57382e EA	486	void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
	487	{
	488	struct drm_i915_private *dev_priv = dev->dev_private;
	489	struct drm_connector *connector;
21d40d37	490	struct intel_encoder *intel_encoder;
674e2d08	491	struct intel_connector *intel_connector;
ea5b213a	492	struct intel_hdmi *intel_hdmi;
64a8fc01	493	int i;
7d57382e	494
ea5b213a CW	495	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
ea5b213a CW	496	if (!intel_hdmi)
7d57382e	497	return;
674e2d08 ZW	498
	499	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	500	if (!intel_connector) {
ea5b213a	501	kfree(intel_hdmi);
674e2d08 ZW	502	return;
	503	}
	504
ea5b213a	505	intel_encoder = &intel_hdmi->base;
373a3cf7 CW	506	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
	507	DRM_MODE_ENCODER_TMDS);
	508
674e2d08	509	connector = &intel_connector->base;
7d57382e	510	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
8d91104a	511	DRM_MODE_CONNECTOR_HDMIA);
7d57382e EA	512	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
7d57382e EA	513
21d40d37	514	intel_encoder->type = INTEL_OUTPUT_HDMI;
7d57382e	515
eb1f8e4f	516	connector->polled = DRM_CONNECTOR_POLL_HPD;
7d57382e EA	517	connector->interlace_allowed = 0;
7d57382e EA	518	connector->doublescan_allowed = 0;
27f8227b	519	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1) \| (1 << 2);
7d57382e EA	520
7d57382e EA	521	/* Set up the DDC bus. */
f8aed700	522	if (sdvox_reg == SDVOB) {
21d40d37	523	intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
f899fc64	524	intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
b01f2c3a	525	dev_priv->hotplug_supported_mask \|= HDMIB_HOTPLUG_INT_STATUS;
f8aed700	526	} else if (sdvox_reg == SDVOC) {
21d40d37	527	intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
f899fc64	528	intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
b01f2c3a	529	dev_priv->hotplug_supported_mask \|= HDMIC_HOTPLUG_INT_STATUS;
f8aed700	530	} else if (sdvox_reg == HDMIB) {
21d40d37	531	intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
f899fc64	532	intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
b01f2c3a	533	dev_priv->hotplug_supported_mask \|= HDMIB_HOTPLUG_INT_STATUS;
f8aed700	534	} else if (sdvox_reg == HDMIC) {
21d40d37	535	intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
f899fc64	536	intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
b01f2c3a	537	dev_priv->hotplug_supported_mask \|= HDMIC_HOTPLUG_INT_STATUS;
f8aed700	538	} else if (sdvox_reg == HDMID) {
21d40d37	539	intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
f899fc64	540	intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
b01f2c3a	541	dev_priv->hotplug_supported_mask \|= HDMID_HOTPLUG_INT_STATUS;
f8aed700	542	}
7d57382e	543
ea5b213a	544	intel_hdmi->sdvox_reg = sdvox_reg;
7d57382e	545
64a8fc01	546	if (!HAS_PCH_SPLIT(dev)) {
45187ace	547	intel_hdmi->write_infoframe = i9xx_write_infoframe;
64a8fc01 JB	548	I915_WRITE(VIDEO_DIP_CTL, 0);
64a8fc01 JB	549	} else {
45187ace	550	intel_hdmi->write_infoframe = ironlake_write_infoframe;
64a8fc01 JB	551	for_each_pipe(i)
	552	I915_WRITE(TVIDEO_DIP_CTL(i), 0);
	553	}
45187ace	554
4ef69c7a	555	drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
7d57382e	556
55b7d6e8 CW	557	intel_hdmi_add_properties(intel_hdmi, connector);
55b7d6e8 CW	558
df0e9248	559	intel_connector_attach_encoder(intel_connector, intel_encoder);
7d57382e EA	560	drm_sysfs_connector_add(connector);
	561
	562	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	563	* 0xd. Failure to do so will result in spurious interrupts being
	564	* generated on the port when a cable is not attached.
	565	*/
	566	if (IS_G4X(dev) && !IS_GM45(dev)) {
	567	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
	568	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
	569	}
7d57382e	570	}