Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_edid.h> | |
7d57382e | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
7d57382e EA |
37 | #include "i915_drv.h" |
38 | ||
30add22d PZ |
39 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
40 | { | |
da63a9f2 | 41 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
42 | } |
43 | ||
afba0188 DV |
44 | static void |
45 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
46 | { | |
30add22d | 47 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
48 | struct drm_i915_private *dev_priv = dev->dev_private; |
49 | uint32_t enabled_bits; | |
50 | ||
affa9354 | 51 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 DV |
52 | |
53 | WARN(I915_READ(intel_hdmi->sdvox_reg) & enabled_bits, | |
54 | "HDMI port enabled, expecting disabled\n"); | |
55 | } | |
56 | ||
f5bbfca3 | 57 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
da63a9f2 PZ |
59 | struct intel_digital_port *intel_dig_port = |
60 | container_of(encoder, struct intel_digital_port, base.base); | |
61 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
62 | } |
63 | ||
df0e9248 CW |
64 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
65 | { | |
da63a9f2 | 66 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
67 | } |
68 | ||
45187ace | 69 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 70 | { |
45187ace | 71 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
72 | uint8_t sum = 0; |
73 | unsigned i; | |
74 | ||
45187ace JB |
75 | frame->checksum = 0; |
76 | frame->ecc = 0; | |
3c17fe4b | 77 | |
64a8fc01 | 78 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
79 | sum += data[i]; |
80 | ||
45187ace | 81 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
82 | } |
83 | ||
bc2481f3 | 84 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 85 | { |
45187ace JB |
86 | switch (frame->type) { |
87 | case DIP_TYPE_AVI: | |
ed517fbb | 88 | return VIDEO_DIP_SELECT_AVI; |
45187ace | 89 | case DIP_TYPE_SPD: |
ed517fbb | 90 | return VIDEO_DIP_SELECT_SPD; |
45187ace JB |
91 | default: |
92 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 93 | return 0; |
45187ace | 94 | } |
45187ace JB |
95 | } |
96 | ||
bc2481f3 | 97 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace | 98 | { |
45187ace JB |
99 | switch (frame->type) { |
100 | case DIP_TYPE_AVI: | |
ed517fbb | 101 | return VIDEO_DIP_ENABLE_AVI; |
45187ace | 102 | case DIP_TYPE_SPD: |
ed517fbb | 103 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 PZ |
104 | default: |
105 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
ed517fbb | 106 | return 0; |
fa193ff7 | 107 | } |
fa193ff7 PZ |
108 | } |
109 | ||
2da8af54 PZ |
110 | static u32 hsw_infoframe_enable(struct dip_infoframe *frame) |
111 | { | |
112 | switch (frame->type) { | |
113 | case DIP_TYPE_AVI: | |
114 | return VIDEO_DIP_ENABLE_AVI_HSW; | |
115 | case DIP_TYPE_SPD: | |
116 | return VIDEO_DIP_ENABLE_SPD_HSW; | |
117 | default: | |
118 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
119 | return 0; | |
120 | } | |
121 | } | |
122 | ||
123 | static u32 hsw_infoframe_data_reg(struct dip_infoframe *frame, enum pipe pipe) | |
124 | { | |
125 | switch (frame->type) { | |
126 | case DIP_TYPE_AVI: | |
127 | return HSW_TVIDEO_DIP_AVI_DATA(pipe); | |
128 | case DIP_TYPE_SPD: | |
129 | return HSW_TVIDEO_DIP_SPD_DATA(pipe); | |
130 | default: | |
131 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
132 | return 0; | |
133 | } | |
134 | } | |
135 | ||
a3da1df7 DV |
136 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
137 | struct dip_infoframe *frame) | |
45187ace JB |
138 | { |
139 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
140 | struct drm_device *dev = encoder->dev; |
141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 142 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 143 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 144 | |
822974ae PZ |
145 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
146 | ||
1d4f85ac | 147 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 148 | val |= g4x_infoframe_index(frame); |
22509ec8 | 149 | |
bc2481f3 | 150 | val &= ~g4x_infoframe_enable(frame); |
45187ace | 151 | |
22509ec8 | 152 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 153 | |
9d9740f0 | 154 | mmiowb(); |
45187ace | 155 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
156 | I915_WRITE(VIDEO_DIP_DATA, *data); |
157 | data++; | |
158 | } | |
adf00b26 PZ |
159 | /* Write every possible data byte to force correct ECC calculation. */ |
160 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
161 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 162 | mmiowb(); |
3c17fe4b | 163 | |
bc2481f3 | 164 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 165 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 166 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 167 | |
22509ec8 | 168 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 169 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
170 | } |
171 | ||
fdf1250a PZ |
172 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
173 | struct dip_infoframe *frame) | |
174 | { | |
175 | uint32_t *data = (uint32_t *)frame; | |
176 | struct drm_device *dev = encoder->dev; | |
177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 178 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
fdf1250a PZ |
179 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
180 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
181 | u32 val = I915_READ(reg); | |
182 | ||
822974ae PZ |
183 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
184 | ||
fdf1250a | 185 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 186 | val |= g4x_infoframe_index(frame); |
fdf1250a | 187 | |
bc2481f3 | 188 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
189 | |
190 | I915_WRITE(reg, val); | |
191 | ||
9d9740f0 | 192 | mmiowb(); |
fdf1250a PZ |
193 | for (i = 0; i < len; i += 4) { |
194 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
195 | data++; | |
196 | } | |
adf00b26 PZ |
197 | /* Write every possible data byte to force correct ECC calculation. */ |
198 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
199 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 200 | mmiowb(); |
fdf1250a | 201 | |
bc2481f3 | 202 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 203 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 204 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
205 | |
206 | I915_WRITE(reg, val); | |
9d9740f0 | 207 | POSTING_READ(reg); |
fdf1250a PZ |
208 | } |
209 | ||
210 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
211 | struct dip_infoframe *frame) | |
b055c8f3 | 212 | { |
45187ace | 213 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
214 | struct drm_device *dev = encoder->dev; |
215 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 216 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
b055c8f3 | 217 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
45187ace | 218 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 219 | u32 val = I915_READ(reg); |
b055c8f3 | 220 | |
822974ae PZ |
221 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
222 | ||
64a8fc01 | 223 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 224 | val |= g4x_infoframe_index(frame); |
45187ace | 225 | |
ecb97851 PZ |
226 | /* The DIP control register spec says that we need to update the AVI |
227 | * infoframe without clearing its enable bit */ | |
822974ae | 228 | if (frame->type != DIP_TYPE_AVI) |
bc2481f3 | 229 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 230 | |
22509ec8 | 231 | I915_WRITE(reg, val); |
45187ace | 232 | |
9d9740f0 | 233 | mmiowb(); |
45187ace | 234 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
235 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
236 | data++; | |
237 | } | |
adf00b26 PZ |
238 | /* Write every possible data byte to force correct ECC calculation. */ |
239 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
240 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 241 | mmiowb(); |
b055c8f3 | 242 | |
bc2481f3 | 243 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 244 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 245 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 246 | |
22509ec8 | 247 | I915_WRITE(reg, val); |
9d9740f0 | 248 | POSTING_READ(reg); |
45187ace | 249 | } |
90b107c8 SK |
250 | |
251 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
252 | struct dip_infoframe *frame) | |
253 | { | |
254 | uint32_t *data = (uint32_t *)frame; | |
255 | struct drm_device *dev = encoder->dev; | |
256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 257 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
90b107c8 SK |
258 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
259 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 260 | u32 val = I915_READ(reg); |
90b107c8 | 261 | |
822974ae PZ |
262 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
263 | ||
90b107c8 | 264 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 265 | val |= g4x_infoframe_index(frame); |
22509ec8 | 266 | |
bc2481f3 | 267 | val &= ~g4x_infoframe_enable(frame); |
90b107c8 | 268 | |
22509ec8 | 269 | I915_WRITE(reg, val); |
90b107c8 | 270 | |
9d9740f0 | 271 | mmiowb(); |
90b107c8 SK |
272 | for (i = 0; i < len; i += 4) { |
273 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
274 | data++; | |
275 | } | |
adf00b26 PZ |
276 | /* Write every possible data byte to force correct ECC calculation. */ |
277 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
278 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 279 | mmiowb(); |
90b107c8 | 280 | |
bc2481f3 | 281 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 282 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 283 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 284 | |
22509ec8 | 285 | I915_WRITE(reg, val); |
9d9740f0 | 286 | POSTING_READ(reg); |
90b107c8 SK |
287 | } |
288 | ||
8c5f5f7c | 289 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ed517fbb | 290 | struct dip_infoframe *frame) |
8c5f5f7c | 291 | { |
2da8af54 PZ |
292 | uint32_t *data = (uint32_t *)frame; |
293 | struct drm_device *dev = encoder->dev; | |
294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
295 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
296 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
297 | u32 data_reg = hsw_infoframe_data_reg(frame, intel_crtc->pipe); | |
298 | unsigned int i, len = DIP_HEADER_SIZE + frame->len; | |
299 | u32 val = I915_READ(ctl_reg); | |
8c5f5f7c | 300 | |
2da8af54 PZ |
301 | if (data_reg == 0) |
302 | return; | |
303 | ||
2da8af54 PZ |
304 | val &= ~hsw_infoframe_enable(frame); |
305 | I915_WRITE(ctl_reg, val); | |
306 | ||
9d9740f0 | 307 | mmiowb(); |
2da8af54 PZ |
308 | for (i = 0; i < len; i += 4) { |
309 | I915_WRITE(data_reg + i, *data); | |
310 | data++; | |
311 | } | |
adf00b26 PZ |
312 | /* Write every possible data byte to force correct ECC calculation. */ |
313 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
314 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 315 | mmiowb(); |
8c5f5f7c | 316 | |
2da8af54 PZ |
317 | val |= hsw_infoframe_enable(frame); |
318 | I915_WRITE(ctl_reg, val); | |
9d9740f0 | 319 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
320 | } |
321 | ||
45187ace JB |
322 | static void intel_set_infoframe(struct drm_encoder *encoder, |
323 | struct dip_infoframe *frame) | |
324 | { | |
325 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
326 | ||
45187ace JB |
327 | intel_dip_infoframe_csum(frame); |
328 | intel_hdmi->write_infoframe(encoder, frame); | |
329 | } | |
330 | ||
687f4d06 | 331 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 332 | struct drm_display_mode *adjusted_mode) |
45187ace | 333 | { |
abedc077 | 334 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
45187ace JB |
335 | struct dip_infoframe avi_if = { |
336 | .type = DIP_TYPE_AVI, | |
337 | .ver = DIP_VERSION_AVI, | |
338 | .len = DIP_LEN_AVI, | |
339 | }; | |
340 | ||
c846b619 PZ |
341 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
342 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
343 | ||
abedc077 VS |
344 | if (intel_hdmi->rgb_quant_range_selectable) { |
345 | if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE) | |
346 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; | |
347 | else | |
348 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; | |
349 | } | |
350 | ||
9a69b885 PZ |
351 | avi_if.body.avi.VIC = drm_mode_cea_vic(adjusted_mode); |
352 | ||
45187ace | 353 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
354 | } |
355 | ||
687f4d06 | 356 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
357 | { |
358 | struct dip_infoframe spd_if; | |
359 | ||
360 | memset(&spd_if, 0, sizeof(spd_if)); | |
361 | spd_if.type = DIP_TYPE_SPD; | |
362 | spd_if.ver = DIP_VERSION_SPD; | |
363 | spd_if.len = DIP_LEN_SPD; | |
364 | strcpy(spd_if.body.spd.vn, "Intel"); | |
365 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
366 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
367 | ||
368 | intel_set_infoframe(encoder, &spd_if); | |
369 | } | |
370 | ||
687f4d06 PZ |
371 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
372 | struct drm_display_mode *adjusted_mode) | |
373 | { | |
0c14c7f9 PZ |
374 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
375 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
376 | u32 reg = VIDEO_DIP_CTL; | |
377 | u32 val = I915_READ(reg); | |
72b78c9d | 378 | u32 port; |
0c14c7f9 | 379 | |
afba0188 DV |
380 | assert_hdmi_port_disabled(intel_hdmi); |
381 | ||
0c14c7f9 PZ |
382 | /* If the registers were not initialized yet, they might be zeroes, |
383 | * which means we're selecting the AVI DIP and we're setting its | |
384 | * frequency to once. This seems to really confuse the HW and make | |
385 | * things stop working (the register spec says the AVI always needs to | |
386 | * be sent every VSync). So here we avoid writing to the register more | |
387 | * than we need and also explicitly select the AVI DIP and explicitly | |
388 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
389 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
390 | * either. */ | |
391 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
392 | ||
393 | if (!intel_hdmi->has_hdmi_sink) { | |
394 | if (!(val & VIDEO_DIP_ENABLE)) | |
395 | return; | |
396 | val &= ~VIDEO_DIP_ENABLE; | |
397 | I915_WRITE(reg, val); | |
9d9740f0 | 398 | POSTING_READ(reg); |
0c14c7f9 PZ |
399 | return; |
400 | } | |
401 | ||
f278d972 PZ |
402 | switch (intel_hdmi->sdvox_reg) { |
403 | case SDVOB: | |
72b78c9d | 404 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
405 | break; |
406 | case SDVOC: | |
72b78c9d | 407 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
408 | break; |
409 | default: | |
57df2ae9 | 410 | BUG(); |
f278d972 PZ |
411 | return; |
412 | } | |
413 | ||
72b78c9d PZ |
414 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
415 | if (val & VIDEO_DIP_ENABLE) { | |
416 | val &= ~VIDEO_DIP_ENABLE; | |
417 | I915_WRITE(reg, val); | |
9d9740f0 | 418 | POSTING_READ(reg); |
72b78c9d PZ |
419 | } |
420 | val &= ~VIDEO_DIP_PORT_MASK; | |
421 | val |= port; | |
422 | } | |
423 | ||
822974ae | 424 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 425 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 426 | |
f278d972 | 427 | I915_WRITE(reg, val); |
9d9740f0 | 428 | POSTING_READ(reg); |
f278d972 | 429 | |
687f4d06 PZ |
430 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
431 | intel_hdmi_set_spd_infoframe(encoder); | |
432 | } | |
433 | ||
434 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
435 | struct drm_display_mode *adjusted_mode) | |
436 | { | |
0c14c7f9 PZ |
437 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
438 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
439 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
440 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
441 | u32 val = I915_READ(reg); | |
72b78c9d | 442 | u32 port; |
0c14c7f9 | 443 | |
afba0188 DV |
444 | assert_hdmi_port_disabled(intel_hdmi); |
445 | ||
0c14c7f9 PZ |
446 | /* See the big comment in g4x_set_infoframes() */ |
447 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
448 | ||
449 | if (!intel_hdmi->has_hdmi_sink) { | |
450 | if (!(val & VIDEO_DIP_ENABLE)) | |
451 | return; | |
452 | val &= ~VIDEO_DIP_ENABLE; | |
453 | I915_WRITE(reg, val); | |
9d9740f0 | 454 | POSTING_READ(reg); |
0c14c7f9 PZ |
455 | return; |
456 | } | |
457 | ||
f278d972 PZ |
458 | switch (intel_hdmi->sdvox_reg) { |
459 | case HDMIB: | |
72b78c9d | 460 | port = VIDEO_DIP_PORT_B; |
f278d972 PZ |
461 | break; |
462 | case HDMIC: | |
72b78c9d | 463 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
464 | break; |
465 | case HDMID: | |
72b78c9d | 466 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
467 | break; |
468 | default: | |
57df2ae9 | 469 | BUG(); |
f278d972 PZ |
470 | return; |
471 | } | |
472 | ||
72b78c9d PZ |
473 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
474 | if (val & VIDEO_DIP_ENABLE) { | |
475 | val &= ~VIDEO_DIP_ENABLE; | |
476 | I915_WRITE(reg, val); | |
9d9740f0 | 477 | POSTING_READ(reg); |
72b78c9d PZ |
478 | } |
479 | val &= ~VIDEO_DIP_PORT_MASK; | |
480 | val |= port; | |
481 | } | |
482 | ||
822974ae | 483 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
484 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
485 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 486 | |
f278d972 | 487 | I915_WRITE(reg, val); |
9d9740f0 | 488 | POSTING_READ(reg); |
f278d972 | 489 | |
687f4d06 PZ |
490 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
491 | intel_hdmi_set_spd_infoframe(encoder); | |
492 | } | |
493 | ||
494 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
495 | struct drm_display_mode *adjusted_mode) | |
496 | { | |
0c14c7f9 PZ |
497 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
498 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
499 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
500 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
501 | u32 val = I915_READ(reg); | |
502 | ||
afba0188 DV |
503 | assert_hdmi_port_disabled(intel_hdmi); |
504 | ||
0c14c7f9 PZ |
505 | /* See the big comment in g4x_set_infoframes() */ |
506 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
507 | ||
508 | if (!intel_hdmi->has_hdmi_sink) { | |
509 | if (!(val & VIDEO_DIP_ENABLE)) | |
510 | return; | |
511 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
512 | I915_WRITE(reg, val); | |
9d9740f0 | 513 | POSTING_READ(reg); |
0c14c7f9 PZ |
514 | return; |
515 | } | |
516 | ||
822974ae PZ |
517 | /* Set both together, unset both together: see the spec. */ |
518 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
519 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
520 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
521 | |
522 | I915_WRITE(reg, val); | |
9d9740f0 | 523 | POSTING_READ(reg); |
822974ae | 524 | |
687f4d06 PZ |
525 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
526 | intel_hdmi_set_spd_infoframe(encoder); | |
527 | } | |
528 | ||
529 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
530 | struct drm_display_mode *adjusted_mode) | |
531 | { | |
0c14c7f9 PZ |
532 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
533 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
534 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
535 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
536 | u32 val = I915_READ(reg); | |
537 | ||
afba0188 DV |
538 | assert_hdmi_port_disabled(intel_hdmi); |
539 | ||
0c14c7f9 PZ |
540 | /* See the big comment in g4x_set_infoframes() */ |
541 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
542 | ||
543 | if (!intel_hdmi->has_hdmi_sink) { | |
544 | if (!(val & VIDEO_DIP_ENABLE)) | |
545 | return; | |
546 | val &= ~VIDEO_DIP_ENABLE; | |
547 | I915_WRITE(reg, val); | |
9d9740f0 | 548 | POSTING_READ(reg); |
0c14c7f9 PZ |
549 | return; |
550 | } | |
551 | ||
822974ae | 552 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
553 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
554 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
555 | |
556 | I915_WRITE(reg, val); | |
9d9740f0 | 557 | POSTING_READ(reg); |
822974ae | 558 | |
687f4d06 PZ |
559 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
560 | intel_hdmi_set_spd_infoframe(encoder); | |
561 | } | |
562 | ||
563 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
564 | struct drm_display_mode *adjusted_mode) | |
565 | { | |
0c14c7f9 PZ |
566 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
567 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
568 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
569 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
0dd87d20 | 570 | u32 val = I915_READ(reg); |
0c14c7f9 | 571 | |
afba0188 DV |
572 | assert_hdmi_port_disabled(intel_hdmi); |
573 | ||
0c14c7f9 PZ |
574 | if (!intel_hdmi->has_hdmi_sink) { |
575 | I915_WRITE(reg, 0); | |
9d9740f0 | 576 | POSTING_READ(reg); |
0c14c7f9 PZ |
577 | return; |
578 | } | |
579 | ||
0dd87d20 PZ |
580 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
581 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
582 | ||
583 | I915_WRITE(reg, val); | |
9d9740f0 | 584 | POSTING_READ(reg); |
0dd87d20 | 585 | |
687f4d06 PZ |
586 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
587 | intel_hdmi_set_spd_infoframe(encoder); | |
588 | } | |
589 | ||
7d57382e EA |
590 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
591 | struct drm_display_mode *mode, | |
592 | struct drm_display_mode *adjusted_mode) | |
593 | { | |
594 | struct drm_device *dev = encoder->dev; | |
595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 596 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
ea5b213a | 597 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
598 | u32 sdvox; |
599 | ||
b659c3db | 600 | sdvox = SDVO_ENCODING_HDMI; |
5d4fac97 JB |
601 | if (!HAS_PCH_SPLIT(dev)) |
602 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
603 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
604 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
605 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
606 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 607 | |
020f6704 JB |
608 | if (intel_crtc->bpp > 24) |
609 | sdvox |= COLOR_FORMAT_12bpc; | |
610 | else | |
611 | sdvox |= COLOR_FORMAT_8bpc; | |
612 | ||
2e3d6006 ZW |
613 | /* Required on CPT */ |
614 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
615 | sdvox |= HDMI_MODE_SELECT; | |
616 | ||
3c17fe4b | 617 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
618 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
619 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 620 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 621 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 622 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 623 | } |
7d57382e | 624 | |
75770564 JB |
625 | if (HAS_PCH_CPT(dev)) |
626 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
7a87c289 | 627 | else if (intel_crtc->pipe == PIPE_B) |
75770564 | 628 | sdvox |= SDVO_PIPE_B_SELECT; |
7d57382e | 629 | |
ea5b213a CW |
630 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
631 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 632 | |
687f4d06 | 633 | intel_hdmi->set_infoframes(encoder, adjusted_mode); |
7d57382e EA |
634 | } |
635 | ||
85234cdc DV |
636 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
637 | enum pipe *pipe) | |
7d57382e | 638 | { |
85234cdc | 639 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 640 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
641 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
642 | u32 tmp; | |
643 | ||
644 | tmp = I915_READ(intel_hdmi->sdvox_reg); | |
645 | ||
646 | if (!(tmp & SDVO_ENABLE)) | |
647 | return false; | |
648 | ||
649 | if (HAS_PCH_CPT(dev)) | |
650 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
651 | else | |
652 | *pipe = PORT_TO_PIPE(tmp); | |
653 | ||
654 | return true; | |
655 | } | |
656 | ||
5ab432ef | 657 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 658 | { |
5ab432ef | 659 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 660 | struct drm_i915_private *dev_priv = dev->dev_private; |
5ab432ef | 661 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 662 | u32 temp; |
2deed761 WF |
663 | u32 enable_bits = SDVO_ENABLE; |
664 | ||
665 | if (intel_hdmi->has_audio) | |
666 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 667 | |
ea5b213a | 668 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 | 669 | |
7a87c289 DV |
670 | /* HW workaround for IBX, we need to move the port to transcoder A |
671 | * before disabling it. */ | |
672 | if (HAS_PCH_IBX(dev)) { | |
5ab432ef | 673 | struct drm_crtc *crtc = encoder->base.crtc; |
7a87c289 DV |
674 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; |
675 | ||
5ab432ef DV |
676 | /* Restore the transcoder select bit. */ |
677 | if (pipe == PIPE_B) | |
678 | enable_bits |= SDVO_PIPE_B_SELECT; | |
7a87c289 DV |
679 | } |
680 | ||
d8a2d0e0 ZW |
681 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
682 | * we do this anyway which shows more stable in testing. | |
683 | */ | |
c619eed4 | 684 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
685 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
686 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
687 | } |
688 | ||
5ab432ef DV |
689 | temp |= enable_bits; |
690 | ||
691 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
692 | POSTING_READ(intel_hdmi->sdvox_reg); | |
693 | ||
694 | /* HW workaround, need to write this twice for issue that may result | |
695 | * in first write getting masked. | |
696 | */ | |
697 | if (HAS_PCH_SPLIT(dev)) { | |
698 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
699 | POSTING_READ(intel_hdmi->sdvox_reg); | |
7d57382e | 700 | } |
5ab432ef DV |
701 | } |
702 | ||
703 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
704 | { | |
705 | struct drm_device *dev = encoder->base.dev; | |
706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
707 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
708 | u32 temp; | |
3cce574f | 709 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef DV |
710 | |
711 | temp = I915_READ(intel_hdmi->sdvox_reg); | |
712 | ||
713 | /* HW workaround for IBX, we need to move the port to transcoder A | |
714 | * before disabling it. */ | |
715 | if (HAS_PCH_IBX(dev)) { | |
716 | struct drm_crtc *crtc = encoder->base.crtc; | |
717 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
718 | ||
719 | if (temp & SDVO_PIPE_B_SELECT) { | |
720 | temp &= ~SDVO_PIPE_B_SELECT; | |
721 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
722 | POSTING_READ(intel_hdmi->sdvox_reg); | |
723 | ||
724 | /* Again we need to write this twice. */ | |
725 | I915_WRITE(intel_hdmi->sdvox_reg, temp); | |
726 | POSTING_READ(intel_hdmi->sdvox_reg); | |
727 | ||
728 | /* Transcoder selection bits only update | |
729 | * effectively on vblank. */ | |
730 | if (crtc) | |
731 | intel_wait_for_vblank(dev, pipe); | |
732 | else | |
733 | msleep(50); | |
734 | } | |
7d57382e | 735 | } |
d8a2d0e0 | 736 | |
5ab432ef DV |
737 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
738 | * we do this anyway which shows more stable in testing. | |
739 | */ | |
740 | if (HAS_PCH_SPLIT(dev)) { | |
741 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); | |
742 | POSTING_READ(intel_hdmi->sdvox_reg); | |
743 | } | |
744 | ||
745 | temp &= ~enable_bits; | |
d8a2d0e0 | 746 | |
ea5b213a CW |
747 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
748 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
749 | |
750 | /* HW workaround, need to write this twice for issue that may result | |
751 | * in first write getting masked. | |
752 | */ | |
c619eed4 | 753 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
754 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
755 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 756 | } |
7d57382e EA |
757 | } |
758 | ||
7d57382e EA |
759 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
760 | struct drm_display_mode *mode) | |
761 | { | |
762 | if (mode->clock > 165000) | |
763 | return MODE_CLOCK_HIGH; | |
764 | if (mode->clock < 20000) | |
5cbba41d | 765 | return MODE_CLOCK_LOW; |
7d57382e EA |
766 | |
767 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
768 | return MODE_NO_DBLESCAN; | |
769 | ||
770 | return MODE_OK; | |
771 | } | |
772 | ||
00c09d70 PZ |
773 | bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, |
774 | const struct drm_display_mode *mode, | |
775 | struct drm_display_mode *adjusted_mode) | |
7d57382e | 776 | { |
3685a8f3 VS |
777 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
778 | ||
55bc60db VS |
779 | if (intel_hdmi->color_range_auto) { |
780 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
781 | if (intel_hdmi->has_hdmi_sink && | |
782 | drm_mode_cea_vic(adjusted_mode) > 1) | |
783 | intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235; | |
784 | else | |
785 | intel_hdmi->color_range = 0; | |
786 | } | |
787 | ||
3685a8f3 VS |
788 | if (intel_hdmi->color_range) |
789 | adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; | |
790 | ||
7d57382e EA |
791 | return true; |
792 | } | |
793 | ||
8ec22b21 CW |
794 | static bool g4x_hdmi_connected(struct intel_hdmi *intel_hdmi) |
795 | { | |
30add22d | 796 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
8ec22b21 CW |
797 | struct drm_i915_private *dev_priv = dev->dev_private; |
798 | uint32_t bit; | |
799 | ||
800 | switch (intel_hdmi->sdvox_reg) { | |
eeafaaca | 801 | case SDVOB: |
8ec22b21 CW |
802 | bit = HDMIB_HOTPLUG_LIVE_STATUS; |
803 | break; | |
eeafaaca | 804 | case SDVOC: |
8ec22b21 CW |
805 | bit = HDMIC_HOTPLUG_LIVE_STATUS; |
806 | break; | |
8ec22b21 CW |
807 | default: |
808 | bit = 0; | |
809 | break; | |
810 | } | |
811 | ||
812 | return I915_READ(PORT_HOTPLUG_STAT) & bit; | |
813 | } | |
814 | ||
aa93d632 | 815 | static enum drm_connector_status |
930a9e28 | 816 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 817 | { |
b0ea7d37 | 818 | struct drm_device *dev = connector->dev; |
df0e9248 | 819 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
820 | struct intel_digital_port *intel_dig_port = |
821 | hdmi_to_dig_port(intel_hdmi); | |
822 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 823 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 824 | struct edid *edid; |
aa93d632 | 825 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 826 | |
b0ea7d37 DL |
827 | |
828 | if (IS_G4X(dev) && !g4x_hdmi_connected(intel_hdmi)) | |
8ec22b21 | 829 | return status; |
b0ea7d37 DL |
830 | else if (HAS_PCH_SPLIT(dev) && |
831 | !ibx_digital_port_connected(dev_priv, intel_dig_port)) | |
832 | return status; | |
8ec22b21 | 833 | |
ea5b213a | 834 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 835 | intel_hdmi->has_audio = false; |
abedc077 | 836 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 837 | edid = drm_get_edid(connector, |
3bd7d909 DK |
838 | intel_gmbus_get_adapter(dev_priv, |
839 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 840 | |
aa93d632 | 841 | if (edid) { |
be9f1c4f | 842 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 843 | status = connector_status_connected; |
b1d7e4b4 WF |
844 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
845 | intel_hdmi->has_hdmi_sink = | |
846 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 847 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
848 | intel_hdmi->rgb_quant_range_selectable = |
849 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 850 | } |
aa93d632 | 851 | kfree(edid); |
9dff6af8 | 852 | } |
30ad48b7 | 853 | |
55b7d6e8 | 854 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
855 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
856 | intel_hdmi->has_audio = | |
857 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 858 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
859 | } |
860 | ||
2ded9e27 | 861 | return status; |
7d57382e EA |
862 | } |
863 | ||
864 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
865 | { | |
df0e9248 | 866 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 867 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
868 | |
869 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
870 | * we can send audio to it. | |
871 | */ | |
872 | ||
f899fc64 | 873 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
874 | intel_gmbus_get_adapter(dev_priv, |
875 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
876 | } |
877 | ||
1aad7ac0 CW |
878 | static bool |
879 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
880 | { | |
881 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
882 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
883 | struct edid *edid; | |
884 | bool has_audio = false; | |
885 | ||
886 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
887 | intel_gmbus_get_adapter(dev_priv, |
888 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
889 | if (edid) { |
890 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
891 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
892 | kfree(edid); |
893 | } | |
894 | ||
895 | return has_audio; | |
896 | } | |
897 | ||
55b7d6e8 CW |
898 | static int |
899 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
900 | struct drm_property *property, |
901 | uint64_t val) | |
55b7d6e8 CW |
902 | { |
903 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
904 | struct intel_digital_port *intel_dig_port = |
905 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 906 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
907 | int ret; |
908 | ||
662595df | 909 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
910 | if (ret) |
911 | return ret; | |
912 | ||
3f43c48d | 913 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 914 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
915 | bool has_audio; |
916 | ||
917 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
918 | return 0; |
919 | ||
1aad7ac0 | 920 | intel_hdmi->force_audio = i; |
55b7d6e8 | 921 | |
b1d7e4b4 | 922 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
923 | has_audio = intel_hdmi_detect_audio(connector); |
924 | else | |
b1d7e4b4 | 925 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 926 | |
b1d7e4b4 WF |
927 | if (i == HDMI_AUDIO_OFF_DVI) |
928 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 929 | |
1aad7ac0 | 930 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
931 | goto done; |
932 | } | |
933 | ||
e953fd7b | 934 | if (property == dev_priv->broadcast_rgb_property) { |
55bc60db VS |
935 | switch (val) { |
936 | case INTEL_BROADCAST_RGB_AUTO: | |
937 | intel_hdmi->color_range_auto = true; | |
938 | break; | |
939 | case INTEL_BROADCAST_RGB_FULL: | |
940 | intel_hdmi->color_range_auto = false; | |
941 | intel_hdmi->color_range = 0; | |
942 | break; | |
943 | case INTEL_BROADCAST_RGB_LIMITED: | |
944 | intel_hdmi->color_range_auto = false; | |
945 | intel_hdmi->color_range = SDVO_COLOR_RANGE_16_235; | |
946 | break; | |
947 | default: | |
948 | return -EINVAL; | |
949 | } | |
e953fd7b CW |
950 | goto done; |
951 | } | |
952 | ||
55b7d6e8 CW |
953 | return -EINVAL; |
954 | ||
955 | done: | |
c0c36b94 CW |
956 | if (intel_dig_port->base.base.crtc) |
957 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
958 | |
959 | return 0; | |
960 | } | |
961 | ||
7d57382e EA |
962 | static void intel_hdmi_destroy(struct drm_connector *connector) |
963 | { | |
7d57382e EA |
964 | drm_sysfs_connector_remove(connector); |
965 | drm_connector_cleanup(connector); | |
674e2d08 | 966 | kfree(connector); |
7d57382e EA |
967 | } |
968 | ||
969 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
7d57382e | 970 | .mode_fixup = intel_hdmi_mode_fixup, |
7d57382e | 971 | .mode_set = intel_hdmi_mode_set, |
1f703855 | 972 | .disable = intel_encoder_noop, |
7d57382e EA |
973 | }; |
974 | ||
975 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
5ab432ef | 976 | .dpms = intel_connector_dpms, |
7d57382e EA |
977 | .detect = intel_hdmi_detect, |
978 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 979 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
980 | .destroy = intel_hdmi_destroy, |
981 | }; | |
982 | ||
983 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
984 | .get_modes = intel_hdmi_get_modes, | |
985 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 986 | .best_encoder = intel_best_encoder, |
7d57382e EA |
987 | }; |
988 | ||
7d57382e | 989 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 990 | .destroy = intel_encoder_destroy, |
7d57382e EA |
991 | }; |
992 | ||
55b7d6e8 CW |
993 | static void |
994 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
995 | { | |
3f43c48d | 996 | intel_attach_force_audio_property(connector); |
e953fd7b | 997 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 998 | intel_hdmi->color_range_auto = true; |
55b7d6e8 CW |
999 | } |
1000 | ||
00c09d70 PZ |
1001 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1002 | struct intel_connector *intel_connector) | |
7d57382e | 1003 | { |
b9cb234c PZ |
1004 | struct drm_connector *connector = &intel_connector->base; |
1005 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1006 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1007 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1008 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1009 | enum port port = intel_dig_port->port; |
373a3cf7 | 1010 | |
7d57382e | 1011 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1012 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1013 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1014 | ||
eb1f8e4f | 1015 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 1016 | connector->interlace_allowed = 1; |
7d57382e | 1017 | connector->doublescan_allowed = 0; |
66a9278e | 1018 | |
08d644ad DV |
1019 | switch (port) { |
1020 | case PORT_B: | |
f899fc64 | 1021 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 1022 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
08d644ad DV |
1023 | break; |
1024 | case PORT_C: | |
7ceae0a5 | 1025 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
7ceae0a5 | 1026 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
08d644ad DV |
1027 | break; |
1028 | case PORT_D: | |
7ceae0a5 | 1029 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
7ceae0a5 | 1030 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
08d644ad DV |
1031 | break; |
1032 | case PORT_A: | |
1033 | /* Internal port only for eDP. */ | |
1034 | default: | |
6e4c1677 | 1035 | BUG(); |
f8aed700 | 1036 | } |
7d57382e | 1037 | |
64a8fc01 | 1038 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 1039 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
687f4d06 | 1040 | intel_hdmi->set_infoframes = g4x_set_infoframes; |
90b107c8 SK |
1041 | } else if (IS_VALLEYVIEW(dev)) { |
1042 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
687f4d06 | 1043 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
8c5f5f7c | 1044 | } else if (IS_HASWELL(dev)) { |
8c5f5f7c | 1045 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1046 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1047 | } else if (HAS_PCH_IBX(dev)) { |
1048 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1049 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1050 | } else { |
1051 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1052 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1053 | } |
45187ace | 1054 | |
affa9354 | 1055 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1056 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1057 | else | |
1058 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1059 | |
1060 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1061 | ||
1062 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1063 | drm_sysfs_connector_add(connector); | |
1064 | ||
1065 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1066 | * 0xd. Failure to do so will result in spurious interrupts being | |
1067 | * generated on the port when a cable is not attached. | |
1068 | */ | |
1069 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1070 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1071 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1072 | } | |
1073 | } | |
1074 | ||
1075 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg, enum port port) | |
1076 | { | |
1077 | struct intel_digital_port *intel_dig_port; | |
1078 | struct intel_encoder *intel_encoder; | |
1079 | struct drm_encoder *encoder; | |
1080 | struct intel_connector *intel_connector; | |
1081 | ||
1082 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); | |
1083 | if (!intel_dig_port) | |
1084 | return; | |
1085 | ||
1086 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
1087 | if (!intel_connector) { | |
1088 | kfree(intel_dig_port); | |
1089 | return; | |
1090 | } | |
1091 | ||
1092 | intel_encoder = &intel_dig_port->base; | |
1093 | encoder = &intel_encoder->base; | |
1094 | ||
1095 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1096 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 PZ |
1097 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
1098 | ||
1099 | intel_encoder->enable = intel_enable_hdmi; | |
1100 | intel_encoder->disable = intel_disable_hdmi; | |
1101 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
5ab432ef | 1102 | |
b9cb234c PZ |
1103 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1104 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1105 | intel_encoder->cloneable = false; | |
7d57382e | 1106 | |
174edf1f | 1107 | intel_dig_port->port = port; |
b9cb234c PZ |
1108 | intel_dig_port->hdmi.sdvox_reg = sdvox_reg; |
1109 | intel_dig_port->dp.output_reg = 0; | |
55b7d6e8 | 1110 | |
b9cb234c | 1111 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1112 | } |