Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
178f736a | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 71 | { |
178f736a DL |
72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 74 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 76 | return VIDEO_DIP_SELECT_SPD; |
45187ace | 77 | default: |
178f736a | 78 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 79 | return 0; |
45187ace | 80 | } |
45187ace JB |
81 | } |
82 | ||
178f736a | 83 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 84 | { |
178f736a DL |
85 | switch (type) { |
86 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 87 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 88 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 89 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 | 90 | default: |
178f736a | 91 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 92 | return 0; |
fa193ff7 | 93 | } |
fa193ff7 PZ |
94 | } |
95 | ||
178f736a | 96 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 97 | { |
178f736a DL |
98 | switch (type) { |
99 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 100 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 101 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 PZ |
102 | return VIDEO_DIP_ENABLE_SPD_HSW; |
103 | default: | |
178f736a | 104 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
105 | return 0; |
106 | } | |
107 | } | |
108 | ||
178f736a | 109 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
7d9bcebe | 110 | enum transcoder cpu_transcoder) |
2da8af54 | 111 | { |
178f736a DL |
112 | switch (type) { |
113 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 114 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 115 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 116 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
2da8af54 | 117 | default: |
178f736a | 118 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
119 | return 0; |
120 | } | |
121 | } | |
122 | ||
a3da1df7 | 123 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a DL |
124 | enum hdmi_infoframe_type type, |
125 | const uint8_t *frame, ssize_t len) | |
45187ace JB |
126 | { |
127 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
128 | struct drm_device *dev = encoder->dev; |
129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 130 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 131 | int i; |
3c17fe4b | 132 | |
822974ae PZ |
133 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
134 | ||
1d4f85ac | 135 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 136 | val |= g4x_infoframe_index(type); |
22509ec8 | 137 | |
178f736a | 138 | val &= ~g4x_infoframe_enable(type); |
45187ace | 139 | |
22509ec8 | 140 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 141 | |
9d9740f0 | 142 | mmiowb(); |
45187ace | 143 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
144 | I915_WRITE(VIDEO_DIP_DATA, *data); |
145 | data++; | |
146 | } | |
adf00b26 PZ |
147 | /* Write every possible data byte to force correct ECC calculation. */ |
148 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
149 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 150 | mmiowb(); |
3c17fe4b | 151 | |
178f736a | 152 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 153 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 154 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 155 | |
22509ec8 | 156 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 157 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
158 | } |
159 | ||
fdf1250a | 160 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a DL |
161 | enum hdmi_infoframe_type type, |
162 | const uint8_t *frame, ssize_t len) | |
fdf1250a PZ |
163 | { |
164 | uint32_t *data = (uint32_t *)frame; | |
165 | struct drm_device *dev = encoder->dev; | |
166 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 167 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 168 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
169 | u32 val = I915_READ(reg); |
170 | ||
822974ae PZ |
171 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
172 | ||
fdf1250a | 173 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 174 | val |= g4x_infoframe_index(type); |
fdf1250a | 175 | |
178f736a | 176 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
177 | |
178 | I915_WRITE(reg, val); | |
179 | ||
9d9740f0 | 180 | mmiowb(); |
fdf1250a PZ |
181 | for (i = 0; i < len; i += 4) { |
182 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
183 | data++; | |
184 | } | |
adf00b26 PZ |
185 | /* Write every possible data byte to force correct ECC calculation. */ |
186 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
187 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 188 | mmiowb(); |
fdf1250a | 189 | |
178f736a | 190 | val |= g4x_infoframe_enable(type); |
fdf1250a | 191 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 192 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
193 | |
194 | I915_WRITE(reg, val); | |
9d9740f0 | 195 | POSTING_READ(reg); |
fdf1250a PZ |
196 | } |
197 | ||
198 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
178f736a DL |
199 | enum hdmi_infoframe_type type, |
200 | const uint8_t *frame, ssize_t len) | |
b055c8f3 | 201 | { |
45187ace | 202 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
203 | struct drm_device *dev = encoder->dev; |
204 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 205 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 206 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 207 | u32 val = I915_READ(reg); |
b055c8f3 | 208 | |
822974ae PZ |
209 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
210 | ||
64a8fc01 | 211 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 212 | val |= g4x_infoframe_index(type); |
45187ace | 213 | |
ecb97851 PZ |
214 | /* The DIP control register spec says that we need to update the AVI |
215 | * infoframe without clearing its enable bit */ | |
178f736a DL |
216 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
217 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 218 | |
22509ec8 | 219 | I915_WRITE(reg, val); |
45187ace | 220 | |
9d9740f0 | 221 | mmiowb(); |
45187ace | 222 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
223 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
224 | data++; | |
225 | } | |
adf00b26 PZ |
226 | /* Write every possible data byte to force correct ECC calculation. */ |
227 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
228 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 229 | mmiowb(); |
b055c8f3 | 230 | |
178f736a | 231 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 232 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 233 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 234 | |
22509ec8 | 235 | I915_WRITE(reg, val); |
9d9740f0 | 236 | POSTING_READ(reg); |
45187ace | 237 | } |
90b107c8 SK |
238 | |
239 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
178f736a DL |
240 | enum hdmi_infoframe_type type, |
241 | const uint8_t *frame, ssize_t len) | |
90b107c8 SK |
242 | { |
243 | uint32_t *data = (uint32_t *)frame; | |
244 | struct drm_device *dev = encoder->dev; | |
245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 246 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 247 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 248 | u32 val = I915_READ(reg); |
90b107c8 | 249 | |
822974ae PZ |
250 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
251 | ||
90b107c8 | 252 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 253 | val |= g4x_infoframe_index(type); |
22509ec8 | 254 | |
178f736a | 255 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 256 | |
22509ec8 | 257 | I915_WRITE(reg, val); |
90b107c8 | 258 | |
9d9740f0 | 259 | mmiowb(); |
90b107c8 SK |
260 | for (i = 0; i < len; i += 4) { |
261 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
262 | data++; | |
263 | } | |
adf00b26 PZ |
264 | /* Write every possible data byte to force correct ECC calculation. */ |
265 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
266 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 267 | mmiowb(); |
90b107c8 | 268 | |
178f736a | 269 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 270 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 271 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 272 | |
22509ec8 | 273 | I915_WRITE(reg, val); |
9d9740f0 | 274 | POSTING_READ(reg); |
90b107c8 SK |
275 | } |
276 | ||
8c5f5f7c | 277 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a DL |
278 | enum hdmi_infoframe_type type, |
279 | const uint8_t *frame, ssize_t len) | |
8c5f5f7c | 280 | { |
2da8af54 PZ |
281 | uint32_t *data = (uint32_t *)frame; |
282 | struct drm_device *dev = encoder->dev; | |
283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
284 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f | 285 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
178f736a DL |
286 | u32 data_reg; |
287 | int i; | |
2da8af54 | 288 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 289 | |
178f736a DL |
290 | data_reg = hsw_infoframe_data_reg(type, |
291 | intel_crtc->config.cpu_transcoder); | |
2da8af54 PZ |
292 | if (data_reg == 0) |
293 | return; | |
294 | ||
178f736a | 295 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
296 | I915_WRITE(ctl_reg, val); |
297 | ||
9d9740f0 | 298 | mmiowb(); |
2da8af54 PZ |
299 | for (i = 0; i < len; i += 4) { |
300 | I915_WRITE(data_reg + i, *data); | |
301 | data++; | |
302 | } | |
adf00b26 PZ |
303 | /* Write every possible data byte to force correct ECC calculation. */ |
304 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
305 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 306 | mmiowb(); |
8c5f5f7c | 307 | |
178f736a | 308 | val |= hsw_infoframe_enable(type); |
2da8af54 | 309 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 310 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
311 | } |
312 | ||
5adaea79 DL |
313 | /* |
314 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
315 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
316 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
317 | * used for both technologies. | |
318 | * | |
319 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
320 | * DW1: DB3 | DB2 | DB1 | DB0 | |
321 | * DW2: DB7 | DB6 | DB5 | DB4 | |
322 | * DW3: ... | |
323 | * | |
324 | * (HB is Header Byte, DB is Data Byte) | |
325 | * | |
326 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
327 | * trick them by giving an offset into the buffer and moving back the header | |
328 | * bytes by one. | |
329 | */ | |
9198ee5b DL |
330 | static void intel_write_infoframe(struct drm_encoder *encoder, |
331 | union hdmi_infoframe *frame) | |
45187ace JB |
332 | { |
333 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
334 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
335 | ssize_t len; | |
45187ace | 336 | |
5adaea79 DL |
337 | /* see comment above for the reason for this offset */ |
338 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
339 | if (len < 0) | |
340 | return; | |
341 | ||
342 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
343 | buffer[0] = buffer[1]; | |
344 | buffer[1] = buffer[2]; | |
345 | buffer[2] = buffer[3]; | |
346 | buffer[3] = 0; | |
347 | len++; | |
45187ace | 348 | |
5adaea79 | 349 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
350 | } |
351 | ||
687f4d06 | 352 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 353 | struct drm_display_mode *adjusted_mode) |
45187ace | 354 | { |
abedc077 | 355 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 356 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
357 | union hdmi_infoframe frame; |
358 | int ret; | |
45187ace | 359 | |
5adaea79 DL |
360 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
361 | adjusted_mode); | |
362 | if (ret < 0) { | |
363 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
364 | return; | |
365 | } | |
c846b619 | 366 | |
abedc077 | 367 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 368 | if (intel_crtc->config.limited_color_range) |
5adaea79 DL |
369 | frame.avi.quantization_range = |
370 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 371 | else |
5adaea79 DL |
372 | frame.avi.quantization_range = |
373 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
374 | } |
375 | ||
9198ee5b | 376 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
377 | } |
378 | ||
687f4d06 | 379 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 380 | { |
5adaea79 DL |
381 | union hdmi_infoframe frame; |
382 | int ret; | |
383 | ||
384 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
385 | if (ret < 0) { | |
386 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
387 | return; | |
388 | } | |
c0864cb3 | 389 | |
5adaea79 | 390 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 391 | |
9198ee5b | 392 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
393 | } |
394 | ||
687f4d06 PZ |
395 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
396 | struct drm_display_mode *adjusted_mode) | |
397 | { | |
0c14c7f9 | 398 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
399 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
400 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
401 | u32 reg = VIDEO_DIP_CTL; |
402 | u32 val = I915_READ(reg); | |
72b78c9d | 403 | u32 port; |
0c14c7f9 | 404 | |
afba0188 DV |
405 | assert_hdmi_port_disabled(intel_hdmi); |
406 | ||
0c14c7f9 PZ |
407 | /* If the registers were not initialized yet, they might be zeroes, |
408 | * which means we're selecting the AVI DIP and we're setting its | |
409 | * frequency to once. This seems to really confuse the HW and make | |
410 | * things stop working (the register spec says the AVI always needs to | |
411 | * be sent every VSync). So here we avoid writing to the register more | |
412 | * than we need and also explicitly select the AVI DIP and explicitly | |
413 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
414 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
415 | * either. */ | |
416 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
417 | ||
418 | if (!intel_hdmi->has_hdmi_sink) { | |
419 | if (!(val & VIDEO_DIP_ENABLE)) | |
420 | return; | |
421 | val &= ~VIDEO_DIP_ENABLE; | |
422 | I915_WRITE(reg, val); | |
9d9740f0 | 423 | POSTING_READ(reg); |
0c14c7f9 PZ |
424 | return; |
425 | } | |
426 | ||
69fde0a6 VS |
427 | switch (intel_dig_port->port) { |
428 | case PORT_B: | |
72b78c9d | 429 | port = VIDEO_DIP_PORT_B; |
f278d972 | 430 | break; |
69fde0a6 | 431 | case PORT_C: |
72b78c9d | 432 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
433 | break; |
434 | default: | |
57df2ae9 | 435 | BUG(); |
f278d972 PZ |
436 | return; |
437 | } | |
438 | ||
72b78c9d PZ |
439 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
440 | if (val & VIDEO_DIP_ENABLE) { | |
441 | val &= ~VIDEO_DIP_ENABLE; | |
442 | I915_WRITE(reg, val); | |
9d9740f0 | 443 | POSTING_READ(reg); |
72b78c9d PZ |
444 | } |
445 | val &= ~VIDEO_DIP_PORT_MASK; | |
446 | val |= port; | |
447 | } | |
448 | ||
822974ae | 449 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 450 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 451 | |
f278d972 | 452 | I915_WRITE(reg, val); |
9d9740f0 | 453 | POSTING_READ(reg); |
f278d972 | 454 | |
687f4d06 PZ |
455 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
456 | intel_hdmi_set_spd_infoframe(encoder); | |
457 | } | |
458 | ||
459 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
460 | struct drm_display_mode *adjusted_mode) | |
461 | { | |
0c14c7f9 PZ |
462 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
463 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
464 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
465 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
466 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
467 | u32 val = I915_READ(reg); | |
72b78c9d | 468 | u32 port; |
0c14c7f9 | 469 | |
afba0188 DV |
470 | assert_hdmi_port_disabled(intel_hdmi); |
471 | ||
0c14c7f9 PZ |
472 | /* See the big comment in g4x_set_infoframes() */ |
473 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
474 | ||
475 | if (!intel_hdmi->has_hdmi_sink) { | |
476 | if (!(val & VIDEO_DIP_ENABLE)) | |
477 | return; | |
478 | val &= ~VIDEO_DIP_ENABLE; | |
479 | I915_WRITE(reg, val); | |
9d9740f0 | 480 | POSTING_READ(reg); |
0c14c7f9 PZ |
481 | return; |
482 | } | |
483 | ||
69fde0a6 VS |
484 | switch (intel_dig_port->port) { |
485 | case PORT_B: | |
72b78c9d | 486 | port = VIDEO_DIP_PORT_B; |
f278d972 | 487 | break; |
69fde0a6 | 488 | case PORT_C: |
72b78c9d | 489 | port = VIDEO_DIP_PORT_C; |
f278d972 | 490 | break; |
69fde0a6 | 491 | case PORT_D: |
72b78c9d | 492 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
493 | break; |
494 | default: | |
57df2ae9 | 495 | BUG(); |
f278d972 PZ |
496 | return; |
497 | } | |
498 | ||
72b78c9d PZ |
499 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
500 | if (val & VIDEO_DIP_ENABLE) { | |
501 | val &= ~VIDEO_DIP_ENABLE; | |
502 | I915_WRITE(reg, val); | |
9d9740f0 | 503 | POSTING_READ(reg); |
72b78c9d PZ |
504 | } |
505 | val &= ~VIDEO_DIP_PORT_MASK; | |
506 | val |= port; | |
507 | } | |
508 | ||
822974ae | 509 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
510 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
511 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 512 | |
f278d972 | 513 | I915_WRITE(reg, val); |
9d9740f0 | 514 | POSTING_READ(reg); |
f278d972 | 515 | |
687f4d06 PZ |
516 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
517 | intel_hdmi_set_spd_infoframe(encoder); | |
518 | } | |
519 | ||
520 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
521 | struct drm_display_mode *adjusted_mode) | |
522 | { | |
0c14c7f9 PZ |
523 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
524 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
525 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
526 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
527 | u32 val = I915_READ(reg); | |
528 | ||
afba0188 DV |
529 | assert_hdmi_port_disabled(intel_hdmi); |
530 | ||
0c14c7f9 PZ |
531 | /* See the big comment in g4x_set_infoframes() */ |
532 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
533 | ||
534 | if (!intel_hdmi->has_hdmi_sink) { | |
535 | if (!(val & VIDEO_DIP_ENABLE)) | |
536 | return; | |
537 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
538 | I915_WRITE(reg, val); | |
9d9740f0 | 539 | POSTING_READ(reg); |
0c14c7f9 PZ |
540 | return; |
541 | } | |
542 | ||
822974ae PZ |
543 | /* Set both together, unset both together: see the spec. */ |
544 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
545 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
546 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
547 | |
548 | I915_WRITE(reg, val); | |
9d9740f0 | 549 | POSTING_READ(reg); |
822974ae | 550 | |
687f4d06 PZ |
551 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
552 | intel_hdmi_set_spd_infoframe(encoder); | |
553 | } | |
554 | ||
555 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
556 | struct drm_display_mode *adjusted_mode) | |
557 | { | |
0c14c7f9 PZ |
558 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
559 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
560 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
561 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
562 | u32 val = I915_READ(reg); | |
563 | ||
afba0188 DV |
564 | assert_hdmi_port_disabled(intel_hdmi); |
565 | ||
0c14c7f9 PZ |
566 | /* See the big comment in g4x_set_infoframes() */ |
567 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
568 | ||
569 | if (!intel_hdmi->has_hdmi_sink) { | |
570 | if (!(val & VIDEO_DIP_ENABLE)) | |
571 | return; | |
572 | val &= ~VIDEO_DIP_ENABLE; | |
573 | I915_WRITE(reg, val); | |
9d9740f0 | 574 | POSTING_READ(reg); |
0c14c7f9 PZ |
575 | return; |
576 | } | |
577 | ||
822974ae | 578 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
579 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
580 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
581 | |
582 | I915_WRITE(reg, val); | |
9d9740f0 | 583 | POSTING_READ(reg); |
822974ae | 584 | |
687f4d06 PZ |
585 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
586 | intel_hdmi_set_spd_infoframe(encoder); | |
587 | } | |
588 | ||
589 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
590 | struct drm_display_mode *adjusted_mode) | |
591 | { | |
0c14c7f9 PZ |
592 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
593 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
594 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 595 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 596 | u32 val = I915_READ(reg); |
0c14c7f9 | 597 | |
afba0188 DV |
598 | assert_hdmi_port_disabled(intel_hdmi); |
599 | ||
0c14c7f9 PZ |
600 | if (!intel_hdmi->has_hdmi_sink) { |
601 | I915_WRITE(reg, 0); | |
9d9740f0 | 602 | POSTING_READ(reg); |
0c14c7f9 PZ |
603 | return; |
604 | } | |
605 | ||
0dd87d20 PZ |
606 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
607 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
608 | ||
609 | I915_WRITE(reg, val); | |
9d9740f0 | 610 | POSTING_READ(reg); |
0dd87d20 | 611 | |
687f4d06 PZ |
612 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
613 | intel_hdmi_set_spd_infoframe(encoder); | |
614 | } | |
615 | ||
c59423a3 | 616 | static void intel_hdmi_mode_set(struct intel_encoder *encoder) |
7d57382e | 617 | { |
c59423a3 | 618 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 619 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
620 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
621 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
622 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
b242b7f7 | 623 | u32 hdmi_val; |
7d57382e | 624 | |
b242b7f7 | 625 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 626 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 627 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 628 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 629 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 630 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 631 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 632 | |
c59423a3 | 633 | if (crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 634 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 635 | else |
4f3a8bc7 | 636 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 637 | |
2e3d6006 ZW |
638 | /* Required on CPT */ |
639 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
dc0fa718 | 640 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 641 | |
3c17fe4b | 642 | if (intel_hdmi->has_audio) { |
e0dac65e | 643 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
c59423a3 | 644 | pipe_name(crtc->pipe)); |
b242b7f7 | 645 | hdmi_val |= SDVO_AUDIO_ENABLE; |
dc0fa718 | 646 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
c59423a3 | 647 | intel_write_eld(&encoder->base, adjusted_mode); |
3c17fe4b | 648 | } |
7d57382e | 649 | |
75770564 | 650 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 651 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
dc0fa718 | 652 | else |
c59423a3 | 653 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 654 | |
b242b7f7 PZ |
655 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
656 | POSTING_READ(intel_hdmi->hdmi_reg); | |
3c17fe4b | 657 | |
c59423a3 | 658 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
7d57382e EA |
659 | } |
660 | ||
85234cdc DV |
661 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
662 | enum pipe *pipe) | |
7d57382e | 663 | { |
85234cdc | 664 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 665 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
666 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
667 | u32 tmp; | |
668 | ||
b242b7f7 | 669 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
670 | |
671 | if (!(tmp & SDVO_ENABLE)) | |
672 | return false; | |
673 | ||
674 | if (HAS_PCH_CPT(dev)) | |
675 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
676 | else | |
677 | *pipe = PORT_TO_PIPE(tmp); | |
678 | ||
679 | return true; | |
680 | } | |
681 | ||
045ac3b5 JB |
682 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
683 | struct intel_crtc_config *pipe_config) | |
684 | { | |
685 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
686 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
687 | u32 tmp, flags = 0; | |
688 | ||
689 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
690 | ||
691 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
692 | flags |= DRM_MODE_FLAG_PHSYNC; | |
693 | else | |
694 | flags |= DRM_MODE_FLAG_NHSYNC; | |
695 | ||
696 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
697 | flags |= DRM_MODE_FLAG_PVSYNC; | |
698 | else | |
699 | flags |= DRM_MODE_FLAG_NVSYNC; | |
700 | ||
701 | pipe_config->adjusted_mode.flags |= flags; | |
702 | } | |
703 | ||
5ab432ef | 704 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 705 | { |
5ab432ef | 706 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 707 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 708 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 709 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 710 | u32 temp; |
2deed761 WF |
711 | u32 enable_bits = SDVO_ENABLE; |
712 | ||
713 | if (intel_hdmi->has_audio) | |
714 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 715 | |
b242b7f7 | 716 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 717 | |
7a87c289 | 718 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
719 | * before disabling it, so restore the transcoder select bit here. */ |
720 | if (HAS_PCH_IBX(dev)) | |
721 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 722 | |
d8a2d0e0 ZW |
723 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
724 | * we do this anyway which shows more stable in testing. | |
725 | */ | |
c619eed4 | 726 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
727 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
728 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
729 | } |
730 | ||
5ab432ef DV |
731 | temp |= enable_bits; |
732 | ||
b242b7f7 PZ |
733 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
734 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
735 | |
736 | /* HW workaround, need to write this twice for issue that may result | |
737 | * in first write getting masked. | |
738 | */ | |
739 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
740 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
741 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 742 | } |
b76cf76b | 743 | } |
89b667f8 | 744 | |
b76cf76b JN |
745 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
746 | { | |
5ab432ef DV |
747 | } |
748 | ||
749 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
750 | { | |
751 | struct drm_device *dev = encoder->base.dev; | |
752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
753 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
754 | u32 temp; | |
3cce574f | 755 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 756 | |
b242b7f7 | 757 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
758 | |
759 | /* HW workaround for IBX, we need to move the port to transcoder A | |
760 | * before disabling it. */ | |
761 | if (HAS_PCH_IBX(dev)) { | |
762 | struct drm_crtc *crtc = encoder->base.crtc; | |
763 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
764 | ||
765 | if (temp & SDVO_PIPE_B_SELECT) { | |
766 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
767 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
768 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
769 | |
770 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
771 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
772 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
773 | |
774 | /* Transcoder selection bits only update | |
775 | * effectively on vblank. */ | |
776 | if (crtc) | |
777 | intel_wait_for_vblank(dev, pipe); | |
778 | else | |
779 | msleep(50); | |
780 | } | |
7d57382e | 781 | } |
d8a2d0e0 | 782 | |
5ab432ef DV |
783 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
784 | * we do this anyway which shows more stable in testing. | |
785 | */ | |
786 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
787 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
788 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
789 | } |
790 | ||
791 | temp &= ~enable_bits; | |
d8a2d0e0 | 792 | |
b242b7f7 PZ |
793 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
794 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
795 | |
796 | /* HW workaround, need to write this twice for issue that may result | |
797 | * in first write getting masked. | |
798 | */ | |
c619eed4 | 799 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
800 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
801 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 802 | } |
7d57382e EA |
803 | } |
804 | ||
7d148ef5 DV |
805 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi) |
806 | { | |
807 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
808 | ||
809 | if (IS_G4X(dev)) | |
810 | return 165000; | |
811 | else if (IS_HASWELL(dev)) | |
812 | return 300000; | |
813 | else | |
814 | return 225000; | |
815 | } | |
816 | ||
7d57382e EA |
817 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
818 | struct drm_display_mode *mode) | |
819 | { | |
7d148ef5 | 820 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector))) |
7d57382e EA |
821 | return MODE_CLOCK_HIGH; |
822 | if (mode->clock < 20000) | |
5cbba41d | 823 | return MODE_CLOCK_LOW; |
7d57382e EA |
824 | |
825 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
826 | return MODE_NO_DBLESCAN; | |
827 | ||
828 | return MODE_OK; | |
829 | } | |
830 | ||
5bfe2ac0 DV |
831 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
832 | struct intel_crtc_config *pipe_config) | |
7d57382e | 833 | { |
5bfe2ac0 DV |
834 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
835 | struct drm_device *dev = encoder->base.dev; | |
836 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
325b9d04 | 837 | int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2; |
7d148ef5 | 838 | int portclock_limit = hdmi_portclock_limit(intel_hdmi); |
e29c22c0 | 839 | int desired_bpp; |
3685a8f3 | 840 | |
55bc60db VS |
841 | if (intel_hdmi->color_range_auto) { |
842 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
843 | if (intel_hdmi->has_hdmi_sink && | |
18316c8c | 844 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 845 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
846 | else |
847 | intel_hdmi->color_range = 0; | |
848 | } | |
849 | ||
3685a8f3 | 850 | if (intel_hdmi->color_range) |
50f3b016 | 851 | pipe_config->limited_color_range = true; |
3685a8f3 | 852 | |
5bfe2ac0 DV |
853 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
854 | pipe_config->has_pch_encoder = true; | |
855 | ||
4e53c2e0 DV |
856 | /* |
857 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
858 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
859 | * outputs. We also need to check that the higher clock still fits |
860 | * within limits. | |
4e53c2e0 | 861 | */ |
7d148ef5 | 862 | if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit |
325b9d04 | 863 | && HAS_PCH_SPLIT(dev)) { |
e29c22c0 DV |
864 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
865 | desired_bpp = 12*3; | |
325b9d04 DV |
866 | |
867 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 868 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 869 | } else { |
e29c22c0 DV |
870 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
871 | desired_bpp = 8*3; | |
872 | } | |
873 | ||
874 | if (!pipe_config->bw_constrained) { | |
875 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
876 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
877 | } |
878 | ||
7d148ef5 | 879 | if (adjusted_mode->clock > portclock_limit) { |
325b9d04 DV |
880 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
881 | return false; | |
882 | } | |
883 | ||
7d57382e EA |
884 | return true; |
885 | } | |
886 | ||
aa93d632 | 887 | static enum drm_connector_status |
930a9e28 | 888 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 889 | { |
b0ea7d37 | 890 | struct drm_device *dev = connector->dev; |
df0e9248 | 891 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
892 | struct intel_digital_port *intel_dig_port = |
893 | hdmi_to_dig_port(intel_hdmi); | |
894 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 895 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 896 | struct edid *edid; |
aa93d632 | 897 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 898 | |
164c8598 CW |
899 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
900 | connector->base.id, drm_get_connector_name(connector)); | |
901 | ||
ea5b213a | 902 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 903 | intel_hdmi->has_audio = false; |
abedc077 | 904 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 905 | edid = drm_get_edid(connector, |
3bd7d909 DK |
906 | intel_gmbus_get_adapter(dev_priv, |
907 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 908 | |
aa93d632 | 909 | if (edid) { |
be9f1c4f | 910 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 911 | status = connector_status_connected; |
b1d7e4b4 WF |
912 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
913 | intel_hdmi->has_hdmi_sink = | |
914 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 915 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
916 | intel_hdmi->rgb_quant_range_selectable = |
917 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 918 | } |
aa93d632 | 919 | kfree(edid); |
9dff6af8 | 920 | } |
30ad48b7 | 921 | |
55b7d6e8 | 922 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
923 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
924 | intel_hdmi->has_audio = | |
925 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 926 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
927 | } |
928 | ||
2ded9e27 | 929 | return status; |
7d57382e EA |
930 | } |
931 | ||
932 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
933 | { | |
df0e9248 | 934 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 935 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
936 | |
937 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
938 | * we can send audio to it. | |
939 | */ | |
940 | ||
f899fc64 | 941 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
942 | intel_gmbus_get_adapter(dev_priv, |
943 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
944 | } |
945 | ||
1aad7ac0 CW |
946 | static bool |
947 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
948 | { | |
949 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
950 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
951 | struct edid *edid; | |
952 | bool has_audio = false; | |
953 | ||
954 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
955 | intel_gmbus_get_adapter(dev_priv, |
956 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
957 | if (edid) { |
958 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
959 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
960 | kfree(edid); |
961 | } | |
962 | ||
963 | return has_audio; | |
964 | } | |
965 | ||
55b7d6e8 CW |
966 | static int |
967 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
968 | struct drm_property *property, |
969 | uint64_t val) | |
55b7d6e8 CW |
970 | { |
971 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
972 | struct intel_digital_port *intel_dig_port = |
973 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 974 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
975 | int ret; |
976 | ||
662595df | 977 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
978 | if (ret) |
979 | return ret; | |
980 | ||
3f43c48d | 981 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 982 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
983 | bool has_audio; |
984 | ||
985 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
986 | return 0; |
987 | ||
1aad7ac0 | 988 | intel_hdmi->force_audio = i; |
55b7d6e8 | 989 | |
b1d7e4b4 | 990 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
991 | has_audio = intel_hdmi_detect_audio(connector); |
992 | else | |
b1d7e4b4 | 993 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 994 | |
b1d7e4b4 WF |
995 | if (i == HDMI_AUDIO_OFF_DVI) |
996 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 997 | |
1aad7ac0 | 998 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
999 | goto done; |
1000 | } | |
1001 | ||
e953fd7b | 1002 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1003 | bool old_auto = intel_hdmi->color_range_auto; |
1004 | uint32_t old_range = intel_hdmi->color_range; | |
1005 | ||
55bc60db VS |
1006 | switch (val) { |
1007 | case INTEL_BROADCAST_RGB_AUTO: | |
1008 | intel_hdmi->color_range_auto = true; | |
1009 | break; | |
1010 | case INTEL_BROADCAST_RGB_FULL: | |
1011 | intel_hdmi->color_range_auto = false; | |
1012 | intel_hdmi->color_range = 0; | |
1013 | break; | |
1014 | case INTEL_BROADCAST_RGB_LIMITED: | |
1015 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1016 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1017 | break; |
1018 | default: | |
1019 | return -EINVAL; | |
1020 | } | |
ae4edb80 DV |
1021 | |
1022 | if (old_auto == intel_hdmi->color_range_auto && | |
1023 | old_range == intel_hdmi->color_range) | |
1024 | return 0; | |
1025 | ||
e953fd7b CW |
1026 | goto done; |
1027 | } | |
1028 | ||
55b7d6e8 CW |
1029 | return -EINVAL; |
1030 | ||
1031 | done: | |
c0c36b94 CW |
1032 | if (intel_dig_port->base.base.crtc) |
1033 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1034 | |
1035 | return 0; | |
1036 | } | |
1037 | ||
89b667f8 JB |
1038 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1039 | { | |
1040 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1041 | struct drm_device *dev = encoder->base.dev; | |
1042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1043 | struct intel_crtc *intel_crtc = | |
1044 | to_intel_crtc(encoder->base.crtc); | |
1045 | int port = vlv_dport_to_channel(dport); | |
1046 | int pipe = intel_crtc->pipe; | |
1047 | u32 val; | |
1048 | ||
1049 | if (!IS_VALLEYVIEW(dev)) | |
1050 | return; | |
1051 | ||
89b667f8 | 1052 | /* Enable clock channels for this port */ |
0980a60f | 1053 | mutex_lock(&dev_priv->dpio_lock); |
ae99258f | 1054 | val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port)); |
89b667f8 JB |
1055 | val = 0; |
1056 | if (pipe) | |
1057 | val |= (1<<21); | |
1058 | else | |
1059 | val &= ~(1<<21); | |
1060 | val |= 0x001000c4; | |
ae99258f | 1061 | vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val); |
89b667f8 JB |
1062 | |
1063 | /* HDMI 1.0V-2dB */ | |
ae99258f JN |
1064 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0); |
1065 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), | |
89b667f8 | 1066 | 0x2b245f5f); |
ae99258f | 1067 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port), |
89b667f8 | 1068 | 0x5578b83a); |
ae99258f | 1069 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), |
89b667f8 | 1070 | 0x0c782040); |
ae99258f | 1071 | vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port), |
89b667f8 | 1072 | 0x2b247878); |
ae99258f JN |
1073 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000); |
1074 | vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), | |
89b667f8 | 1075 | 0x00002000); |
ae99258f | 1076 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), |
89b667f8 JB |
1077 | DPIO_TX_OCALINIT_EN); |
1078 | ||
1079 | /* Program lane clock */ | |
ae99258f | 1080 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), |
89b667f8 | 1081 | 0x00760018); |
ae99258f | 1082 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), |
89b667f8 | 1083 | 0x00400888); |
0980a60f | 1084 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b JN |
1085 | |
1086 | intel_enable_hdmi(encoder); | |
1087 | ||
1088 | vlv_wait_port_ready(dev_priv, port); | |
89b667f8 JB |
1089 | } |
1090 | ||
1091 | static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder) | |
1092 | { | |
1093 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1094 | struct drm_device *dev = encoder->base.dev; | |
1095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1096 | int port = vlv_dport_to_channel(dport); | |
1097 | ||
1098 | if (!IS_VALLEYVIEW(dev)) | |
1099 | return; | |
1100 | ||
89b667f8 | 1101 | /* Program Tx lane resets to default */ |
0980a60f | 1102 | mutex_lock(&dev_priv->dpio_lock); |
ae99258f | 1103 | vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), |
89b667f8 JB |
1104 | DPIO_PCS_TX_LANE2_RESET | |
1105 | DPIO_PCS_TX_LANE1_RESET); | |
ae99258f | 1106 | vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), |
89b667f8 JB |
1107 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1108 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1109 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1110 | DPIO_PCS_CLK_SOFT_RESET); | |
1111 | ||
1112 | /* Fix up inter-pair skew failure */ | |
ae99258f JN |
1113 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00); |
1114 | vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500); | |
1115 | vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000); | |
89b667f8 | 1116 | |
ae99258f | 1117 | vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), |
89b667f8 | 1118 | 0x00002000); |
ae99258f | 1119 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), |
89b667f8 | 1120 | DPIO_TX_OCALINIT_EN); |
0980a60f | 1121 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1122 | } |
1123 | ||
1124 | static void intel_hdmi_post_disable(struct intel_encoder *encoder) | |
1125 | { | |
1126 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1127 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1128 | int port = vlv_dport_to_channel(dport); | |
1129 | ||
1130 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1131 | mutex_lock(&dev_priv->dpio_lock); | |
ae99258f JN |
1132 | vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000); |
1133 | vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060); | |
89b667f8 JB |
1134 | mutex_unlock(&dev_priv->dpio_lock); |
1135 | } | |
1136 | ||
7d57382e EA |
1137 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1138 | { | |
7d57382e EA |
1139 | drm_sysfs_connector_remove(connector); |
1140 | drm_connector_cleanup(connector); | |
674e2d08 | 1141 | kfree(connector); |
7d57382e EA |
1142 | } |
1143 | ||
7d57382e | 1144 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1145 | .dpms = intel_connector_dpms, |
7d57382e EA |
1146 | .detect = intel_hdmi_detect, |
1147 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 1148 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1149 | .destroy = intel_hdmi_destroy, |
1150 | }; | |
1151 | ||
1152 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1153 | .get_modes = intel_hdmi_get_modes, | |
1154 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1155 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1156 | }; |
1157 | ||
7d57382e | 1158 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1159 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1160 | }; |
1161 | ||
55b7d6e8 CW |
1162 | static void |
1163 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1164 | { | |
3f43c48d | 1165 | intel_attach_force_audio_property(connector); |
e953fd7b | 1166 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1167 | intel_hdmi->color_range_auto = true; |
55b7d6e8 CW |
1168 | } |
1169 | ||
00c09d70 PZ |
1170 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1171 | struct intel_connector *intel_connector) | |
7d57382e | 1172 | { |
b9cb234c PZ |
1173 | struct drm_connector *connector = &intel_connector->base; |
1174 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1175 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1176 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1177 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1178 | enum port port = intel_dig_port->port; |
373a3cf7 | 1179 | |
7d57382e | 1180 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1181 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1182 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1183 | ||
c3febcc4 | 1184 | connector->interlace_allowed = 1; |
7d57382e | 1185 | connector->doublescan_allowed = 0; |
66a9278e | 1186 | |
08d644ad DV |
1187 | switch (port) { |
1188 | case PORT_B: | |
f899fc64 | 1189 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1190 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1191 | break; |
1192 | case PORT_C: | |
7ceae0a5 | 1193 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1194 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1195 | break; |
1196 | case PORT_D: | |
7ceae0a5 | 1197 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
1d843f9d | 1198 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1199 | break; |
1200 | case PORT_A: | |
1d843f9d | 1201 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1202 | /* Internal port only for eDP. */ |
1203 | default: | |
6e4c1677 | 1204 | BUG(); |
f8aed700 | 1205 | } |
7d57382e | 1206 | |
7637bfdb | 1207 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1208 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1209 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
7637bfdb JB |
1210 | } else if (!HAS_PCH_SPLIT(dev)) { |
1211 | intel_hdmi->write_infoframe = g4x_write_infoframe; | |
1212 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
22b8bf17 | 1213 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1214 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1215 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1216 | } else if (HAS_PCH_IBX(dev)) { |
1217 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1218 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1219 | } else { |
1220 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1221 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1222 | } |
45187ace | 1223 | |
affa9354 | 1224 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1225 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1226 | else | |
1227 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1228 | |
1229 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1230 | ||
1231 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1232 | drm_sysfs_connector_add(connector); | |
1233 | ||
1234 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1235 | * 0xd. Failure to do so will result in spurious interrupts being | |
1236 | * generated on the port when a cable is not attached. | |
1237 | */ | |
1238 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1239 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1240 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1241 | } | |
1242 | } | |
1243 | ||
b242b7f7 | 1244 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1245 | { |
1246 | struct intel_digital_port *intel_dig_port; | |
1247 | struct intel_encoder *intel_encoder; | |
1248 | struct drm_encoder *encoder; | |
1249 | struct intel_connector *intel_connector; | |
1250 | ||
1251 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); | |
1252 | if (!intel_dig_port) | |
1253 | return; | |
1254 | ||
1255 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
1256 | if (!intel_connector) { | |
1257 | kfree(intel_dig_port); | |
1258 | return; | |
1259 | } | |
1260 | ||
1261 | intel_encoder = &intel_dig_port->base; | |
1262 | encoder = &intel_encoder->base; | |
1263 | ||
1264 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1265 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1266 | |
5bfe2ac0 | 1267 | intel_encoder->compute_config = intel_hdmi_compute_config; |
c59423a3 | 1268 | intel_encoder->mode_set = intel_hdmi_mode_set; |
00c09d70 PZ |
1269 | intel_encoder->disable = intel_disable_hdmi; |
1270 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1271 | intel_encoder->get_config = intel_hdmi_get_config; |
89b667f8 | 1272 | if (IS_VALLEYVIEW(dev)) { |
89b667f8 | 1273 | intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable; |
b76cf76b JN |
1274 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
1275 | intel_encoder->enable = vlv_enable_hdmi; | |
89b667f8 | 1276 | intel_encoder->post_disable = intel_hdmi_post_disable; |
b76cf76b JN |
1277 | } else { |
1278 | intel_encoder->enable = intel_enable_hdmi; | |
89b667f8 | 1279 | } |
5ab432ef | 1280 | |
b9cb234c PZ |
1281 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1282 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1283 | intel_encoder->cloneable = false; | |
7d57382e | 1284 | |
174edf1f | 1285 | intel_dig_port->port = port; |
b242b7f7 | 1286 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1287 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1288 | |
b9cb234c | 1289 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1290 | } |