Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
2320175f | 37 | #include <drm/drm_hdcp.h> |
15953637 | 38 | #include <drm/drm_scdc_helper.h> |
7d57382e | 39 | #include "intel_drv.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
46d196ec | 41 | #include <drm/intel_lpe_audio.h> |
7d57382e EA |
42 | #include "i915_drv.h" |
43 | ||
30add22d PZ |
44 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
45 | { | |
da63a9f2 | 46 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
47 | } |
48 | ||
afba0188 DV |
49 | static void |
50 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
51 | { | |
30add22d | 52 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 53 | struct drm_i915_private *dev_priv = to_i915(dev); |
faa087c4 | 54 | u32 enabled_bits; |
afba0188 | 55 | |
4f8036a2 | 56 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 57 | |
b242b7f7 | 58 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
59 | "HDMI port enabled, expecting disabled\n"); |
60 | } | |
61 | ||
8fc0aa6e ID |
62 | static void |
63 | assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, | |
64 | enum transcoder cpu_transcoder) | |
65 | { | |
66 | WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & | |
67 | TRANS_DDI_FUNC_ENABLE, | |
68 | "HDMI transcoder function enabled, expecting disabled\n"); | |
69 | } | |
70 | ||
f5bbfca3 | 71 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 72 | { |
da63a9f2 PZ |
73 | struct intel_digital_port *intel_dig_port = |
74 | container_of(encoder, struct intel_digital_port, base.base); | |
75 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
76 | } |
77 | ||
df0e9248 CW |
78 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
79 | { | |
da63a9f2 | 80 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
81 | } |
82 | ||
1d776538 | 83 | static u32 g4x_infoframe_index(unsigned int type) |
3c17fe4b | 84 | { |
178f736a DL |
85 | switch (type) { |
86 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 87 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 88 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 89 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
90 | case HDMI_INFOFRAME_TYPE_VENDOR: |
91 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 92 | default: |
ffc85dab | 93 | MISSING_CASE(type); |
ed517fbb | 94 | return 0; |
45187ace | 95 | } |
45187ace JB |
96 | } |
97 | ||
1d776538 | 98 | static u32 g4x_infoframe_enable(unsigned int type) |
45187ace | 99 | { |
178f736a DL |
100 | switch (type) { |
101 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 102 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 103 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 104 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
105 | case HDMI_INFOFRAME_TYPE_VENDOR: |
106 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 107 | default: |
ffc85dab | 108 | MISSING_CASE(type); |
ed517fbb | 109 | return 0; |
fa193ff7 | 110 | } |
fa193ff7 PZ |
111 | } |
112 | ||
1d776538 | 113 | static u32 hsw_infoframe_enable(unsigned int type) |
2da8af54 | 114 | { |
178f736a | 115 | switch (type) { |
1d776538 VS |
116 | case DP_SDP_VSC: |
117 | return VIDEO_DIP_ENABLE_VSC_HSW; | |
178f736a | 118 | case HDMI_INFOFRAME_TYPE_AVI: |
2da8af54 | 119 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 120 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 121 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
122 | case HDMI_INFOFRAME_TYPE_VENDOR: |
123 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 124 | default: |
ffc85dab | 125 | MISSING_CASE(type); |
2da8af54 PZ |
126 | return 0; |
127 | } | |
128 | } | |
129 | ||
f0f59a00 VS |
130 | static i915_reg_t |
131 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
132 | enum transcoder cpu_transcoder, | |
1d776538 | 133 | unsigned int type, |
f0f59a00 | 134 | int i) |
2da8af54 | 135 | { |
178f736a | 136 | switch (type) { |
1d776538 VS |
137 | case DP_SDP_VSC: |
138 | return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); | |
178f736a | 139 | case HDMI_INFOFRAME_TYPE_AVI: |
436c6d4a | 140 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 141 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 142 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 143 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 144 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 145 | default: |
ffc85dab | 146 | MISSING_CASE(type); |
f0f59a00 | 147 | return INVALID_MMIO_REG; |
2da8af54 PZ |
148 | } |
149 | } | |
150 | ||
790ea70c | 151 | static void g4x_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 152 | const struct intel_crtc_state *crtc_state, |
1d776538 | 153 | unsigned int type, |
fff63867 | 154 | const void *frame, ssize_t len) |
45187ace | 155 | { |
faa087c4 | 156 | const u32 *data = frame; |
790ea70c | 157 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
22509ec8 | 158 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 159 | int i; |
3c17fe4b | 160 | |
822974ae PZ |
161 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
162 | ||
1d4f85ac | 163 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 164 | val |= g4x_infoframe_index(type); |
22509ec8 | 165 | |
178f736a | 166 | val &= ~g4x_infoframe_enable(type); |
45187ace | 167 | |
22509ec8 | 168 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 169 | |
9d9740f0 | 170 | mmiowb(); |
45187ace | 171 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
172 | I915_WRITE(VIDEO_DIP_DATA, *data); |
173 | data++; | |
174 | } | |
adf00b26 PZ |
175 | /* Write every possible data byte to force correct ECC calculation. */ |
176 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
177 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 178 | mmiowb(); |
3c17fe4b | 179 | |
178f736a | 180 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 181 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 182 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 183 | |
22509ec8 | 184 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 185 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
186 | } |
187 | ||
790ea70c | 188 | static bool g4x_infoframe_enabled(struct intel_encoder *encoder, |
cda0aaaf | 189 | const struct intel_crtc_state *pipe_config) |
e43823ec | 190 | { |
790ea70c | 191 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e43823ec JB |
192 | u32 val = I915_READ(VIDEO_DIP_CTL); |
193 | ||
ec1dc603 VS |
194 | if ((val & VIDEO_DIP_ENABLE) == 0) |
195 | return false; | |
89a35ecd | 196 | |
790ea70c | 197 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
ec1dc603 VS |
198 | return false; |
199 | ||
200 | return val & (VIDEO_DIP_ENABLE_AVI | | |
201 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
202 | } |
203 | ||
790ea70c | 204 | static void ibx_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 205 | const struct intel_crtc_state *crtc_state, |
1d776538 | 206 | unsigned int type, |
fff63867 | 207 | const void *frame, ssize_t len) |
fdf1250a | 208 | { |
faa087c4 | 209 | const u32 *data = frame; |
790ea70c | 210 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 211 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 212 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 213 | u32 val = I915_READ(reg); |
f0f59a00 | 214 | int i; |
fdf1250a | 215 | |
822974ae PZ |
216 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
217 | ||
fdf1250a | 218 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 219 | val |= g4x_infoframe_index(type); |
fdf1250a | 220 | |
178f736a | 221 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
222 | |
223 | I915_WRITE(reg, val); | |
224 | ||
9d9740f0 | 225 | mmiowb(); |
fdf1250a PZ |
226 | for (i = 0; i < len; i += 4) { |
227 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
228 | data++; | |
229 | } | |
adf00b26 PZ |
230 | /* Write every possible data byte to force correct ECC calculation. */ |
231 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
232 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 233 | mmiowb(); |
fdf1250a | 234 | |
178f736a | 235 | val |= g4x_infoframe_enable(type); |
fdf1250a | 236 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 237 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
238 | |
239 | I915_WRITE(reg, val); | |
9d9740f0 | 240 | POSTING_READ(reg); |
fdf1250a PZ |
241 | } |
242 | ||
790ea70c | 243 | static bool ibx_infoframe_enabled(struct intel_encoder *encoder, |
cda0aaaf | 244 | const struct intel_crtc_state *pipe_config) |
e43823ec | 245 | { |
790ea70c | 246 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
247 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
248 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
249 | u32 val = I915_READ(reg); |
250 | ||
ec1dc603 VS |
251 | if ((val & VIDEO_DIP_ENABLE) == 0) |
252 | return false; | |
253 | ||
790ea70c | 254 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
ec1dc603 | 255 | return false; |
052f62f7 | 256 | |
ec1dc603 VS |
257 | return val & (VIDEO_DIP_ENABLE_AVI | |
258 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
259 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
260 | } |
261 | ||
790ea70c | 262 | static void cpt_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 263 | const struct intel_crtc_state *crtc_state, |
1d776538 | 264 | unsigned int type, |
fff63867 | 265 | const void *frame, ssize_t len) |
b055c8f3 | 266 | { |
faa087c4 | 267 | const u32 *data = frame; |
790ea70c | 268 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 269 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 270 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 271 | u32 val = I915_READ(reg); |
f0f59a00 | 272 | int i; |
b055c8f3 | 273 | |
822974ae PZ |
274 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
275 | ||
64a8fc01 | 276 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 277 | val |= g4x_infoframe_index(type); |
45187ace | 278 | |
ecb97851 PZ |
279 | /* The DIP control register spec says that we need to update the AVI |
280 | * infoframe without clearing its enable bit */ | |
178f736a DL |
281 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
282 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 283 | |
22509ec8 | 284 | I915_WRITE(reg, val); |
45187ace | 285 | |
9d9740f0 | 286 | mmiowb(); |
45187ace | 287 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
288 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
289 | data++; | |
290 | } | |
adf00b26 PZ |
291 | /* Write every possible data byte to force correct ECC calculation. */ |
292 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
293 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 294 | mmiowb(); |
b055c8f3 | 295 | |
178f736a | 296 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 297 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 298 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 299 | |
22509ec8 | 300 | I915_WRITE(reg, val); |
9d9740f0 | 301 | POSTING_READ(reg); |
45187ace | 302 | } |
90b107c8 | 303 | |
790ea70c | 304 | static bool cpt_infoframe_enabled(struct intel_encoder *encoder, |
cda0aaaf | 305 | const struct intel_crtc_state *pipe_config) |
e43823ec | 306 | { |
790ea70c | 307 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
308 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
309 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 310 | |
ec1dc603 VS |
311 | if ((val & VIDEO_DIP_ENABLE) == 0) |
312 | return false; | |
313 | ||
314 | return val & (VIDEO_DIP_ENABLE_AVI | | |
315 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
316 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
317 | } |
318 | ||
790ea70c | 319 | static void vlv_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 320 | const struct intel_crtc_state *crtc_state, |
1d776538 | 321 | unsigned int type, |
fff63867 | 322 | const void *frame, ssize_t len) |
90b107c8 | 323 | { |
faa087c4 | 324 | const u32 *data = frame; |
790ea70c | 325 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 326 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 327 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 328 | u32 val = I915_READ(reg); |
f0f59a00 | 329 | int i; |
90b107c8 | 330 | |
822974ae PZ |
331 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
332 | ||
90b107c8 | 333 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 334 | val |= g4x_infoframe_index(type); |
22509ec8 | 335 | |
178f736a | 336 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 337 | |
22509ec8 | 338 | I915_WRITE(reg, val); |
90b107c8 | 339 | |
9d9740f0 | 340 | mmiowb(); |
90b107c8 SK |
341 | for (i = 0; i < len; i += 4) { |
342 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
343 | data++; | |
344 | } | |
adf00b26 PZ |
345 | /* Write every possible data byte to force correct ECC calculation. */ |
346 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
347 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 348 | mmiowb(); |
90b107c8 | 349 | |
178f736a | 350 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 351 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 352 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 353 | |
22509ec8 | 354 | I915_WRITE(reg, val); |
9d9740f0 | 355 | POSTING_READ(reg); |
90b107c8 SK |
356 | } |
357 | ||
790ea70c | 358 | static bool vlv_infoframe_enabled(struct intel_encoder *encoder, |
cda0aaaf | 359 | const struct intel_crtc_state *pipe_config) |
e43823ec | 360 | { |
790ea70c | 361 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
362 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
363 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 364 | |
ec1dc603 VS |
365 | if ((val & VIDEO_DIP_ENABLE) == 0) |
366 | return false; | |
367 | ||
790ea70c | 368 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
ec1dc603 | 369 | return false; |
535afa2e | 370 | |
ec1dc603 VS |
371 | return val & (VIDEO_DIP_ENABLE_AVI | |
372 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
373 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
374 | } |
375 | ||
790ea70c | 376 | static void hsw_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 377 | const struct intel_crtc_state *crtc_state, |
1d776538 | 378 | unsigned int type, |
fff63867 | 379 | const void *frame, ssize_t len) |
8c5f5f7c | 380 | { |
faa087c4 | 381 | const u32 *data = frame; |
790ea70c | 382 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 383 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 | 384 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
1d776538 VS |
385 | int data_size = type == DP_SDP_VSC ? |
386 | VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE; | |
178f736a | 387 | int i; |
2da8af54 | 388 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 389 | |
178f736a | 390 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
391 | I915_WRITE(ctl_reg, val); |
392 | ||
9d9740f0 | 393 | mmiowb(); |
2da8af54 | 394 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
395 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
396 | type, i >> 2), *data); | |
2da8af54 PZ |
397 | data++; |
398 | } | |
adf00b26 | 399 | /* Write every possible data byte to force correct ECC calculation. */ |
1d776538 | 400 | for (; i < data_size; i += 4) |
436c6d4a VS |
401 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
402 | type, i >> 2), 0); | |
9d9740f0 | 403 | mmiowb(); |
8c5f5f7c | 404 | |
178f736a | 405 | val |= hsw_infoframe_enable(type); |
2da8af54 | 406 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 407 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
408 | } |
409 | ||
790ea70c | 410 | static bool hsw_infoframe_enabled(struct intel_encoder *encoder, |
cda0aaaf | 411 | const struct intel_crtc_state *pipe_config) |
e43823ec | 412 | { |
790ea70c | 413 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf | 414 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); |
e43823ec | 415 | |
ec1dc603 VS |
416 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
417 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
418 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
419 | } |
420 | ||
5adaea79 DL |
421 | /* |
422 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
423 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
424 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
425 | * used for both technologies. | |
426 | * | |
427 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
428 | * DW1: DB3 | DB2 | DB1 | DB0 | |
429 | * DW2: DB7 | DB6 | DB5 | DB4 | |
430 | * DW3: ... | |
431 | * | |
432 | * (HB is Header Byte, DB is Data Byte) | |
433 | * | |
434 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
435 | * trick them by giving an offset into the buffer and moving back the header | |
436 | * bytes by one. | |
437 | */ | |
790ea70c | 438 | static void intel_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 439 | const struct intel_crtc_state *crtc_state, |
9198ee5b | 440 | union hdmi_infoframe *frame) |
45187ace | 441 | { |
790ea70c | 442 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
faa087c4 | 443 | u8 buffer[VIDEO_DIP_DATA_SIZE]; |
5adaea79 | 444 | ssize_t len; |
45187ace | 445 | |
5adaea79 DL |
446 | /* see comment above for the reason for this offset */ |
447 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
448 | if (len < 0) | |
449 | return; | |
450 | ||
451 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
121f0ff5 | 452 | memmove(&buffer[0], &buffer[1], 3); |
5adaea79 DL |
453 | buffer[3] = 0; |
454 | len++; | |
45187ace | 455 | |
790ea70c VS |
456 | intel_dig_port->write_infoframe(encoder, |
457 | crtc_state, | |
458 | frame->any.type, buffer, len); | |
45187ace JB |
459 | } |
460 | ||
790ea70c | 461 | static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder, |
6553b123 SL |
462 | const struct intel_crtc_state *crtc_state, |
463 | const struct drm_connector_state *conn_state) | |
45187ace | 464 | { |
790ea70c | 465 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
779c4c28 VS |
466 | const struct drm_display_mode *adjusted_mode = |
467 | &crtc_state->base.adjusted_mode; | |
0c1f528c | 468 | struct drm_connector *connector = &intel_hdmi->attached_connector->base; |
47164e0b CT |
469 | bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported || |
470 | connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; | |
5adaea79 DL |
471 | union hdmi_infoframe frame; |
472 | int ret; | |
45187ace | 473 | |
5adaea79 | 474 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
0c1f528c SS |
475 | adjusted_mode, |
476 | is_hdmi2_sink); | |
5adaea79 DL |
477 | if (ret < 0) { |
478 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
479 | return; | |
480 | } | |
c846b619 | 481 | |
33b7f3ee | 482 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
2d8bd2bf | 483 | frame.avi.colorspace = HDMI_COLORSPACE_YUV420; |
8c79f844 SS |
484 | else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) |
485 | frame.avi.colorspace = HDMI_COLORSPACE_YUV444; | |
2d8bd2bf SS |
486 | else |
487 | frame.avi.colorspace = HDMI_COLORSPACE_RGB; | |
488 | ||
779c4c28 | 489 | drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, |
a2ce26f8 VS |
490 | crtc_state->limited_color_range ? |
491 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
492 | HDMI_QUANTIZATION_RANGE_FULL, | |
9271c0ca VS |
493 | intel_hdmi->rgb_quant_range_selectable, |
494 | is_hdmi2_sink); | |
abedc077 | 495 | |
6553b123 SL |
496 | drm_hdmi_avi_infoframe_content_type(&frame.avi, |
497 | conn_state); | |
498 | ||
2d8bd2bf | 499 | /* TODO: handle pixel repetition for YCBCR420 outputs */ |
790ea70c VS |
500 | intel_write_infoframe(encoder, crtc_state, |
501 | &frame); | |
b055c8f3 JB |
502 | } |
503 | ||
790ea70c | 504 | static void intel_hdmi_set_spd_infoframe(struct intel_encoder *encoder, |
ac240288 | 505 | const struct intel_crtc_state *crtc_state) |
c0864cb3 | 506 | { |
5adaea79 DL |
507 | union hdmi_infoframe frame; |
508 | int ret; | |
509 | ||
510 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
511 | if (ret < 0) { | |
512 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
513 | return; | |
514 | } | |
c0864cb3 | 515 | |
5adaea79 | 516 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 517 | |
790ea70c VS |
518 | intel_write_infoframe(encoder, crtc_state, |
519 | &frame); | |
c0864cb3 JB |
520 | } |
521 | ||
c8bb75af | 522 | static void |
790ea70c | 523 | intel_hdmi_set_hdmi_infoframe(struct intel_encoder *encoder, |
f1781e9b VS |
524 | const struct intel_crtc_state *crtc_state, |
525 | const struct drm_connector_state *conn_state) | |
c8bb75af LD |
526 | { |
527 | union hdmi_infoframe frame; | |
528 | int ret; | |
529 | ||
530 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
f1781e9b | 531 | conn_state->connector, |
ac240288 | 532 | &crtc_state->base.adjusted_mode); |
c8bb75af LD |
533 | if (ret < 0) |
534 | return; | |
535 | ||
790ea70c VS |
536 | intel_write_infoframe(encoder, crtc_state, |
537 | &frame); | |
c8bb75af LD |
538 | } |
539 | ||
790ea70c | 540 | static void g4x_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 541 | bool enable, |
ac240288 ML |
542 | const struct intel_crtc_state *crtc_state, |
543 | const struct drm_connector_state *conn_state) | |
687f4d06 | 544 | { |
790ea70c VS |
545 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
546 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
69fde0a6 | 547 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 548 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 549 | u32 val = I915_READ(reg); |
790ea70c | 550 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 551 | |
afba0188 DV |
552 | assert_hdmi_port_disabled(intel_hdmi); |
553 | ||
0c14c7f9 PZ |
554 | /* If the registers were not initialized yet, they might be zeroes, |
555 | * which means we're selecting the AVI DIP and we're setting its | |
556 | * frequency to once. This seems to really confuse the HW and make | |
557 | * things stop working (the register spec says the AVI always needs to | |
558 | * be sent every VSync). So here we avoid writing to the register more | |
559 | * than we need and also explicitly select the AVI DIP and explicitly | |
560 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
561 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
562 | * either. */ | |
563 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
564 | ||
6897b4b5 | 565 | if (!enable) { |
0c14c7f9 PZ |
566 | if (!(val & VIDEO_DIP_ENABLE)) |
567 | return; | |
0be6f0c8 VS |
568 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
569 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
570 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
571 | return; | |
572 | } | |
573 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
574 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 575 | I915_WRITE(reg, val); |
9d9740f0 | 576 | POSTING_READ(reg); |
0c14c7f9 PZ |
577 | return; |
578 | } | |
579 | ||
72b78c9d PZ |
580 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
581 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
582 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
583 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
584 | return; | |
72b78c9d PZ |
585 | } |
586 | val &= ~VIDEO_DIP_PORT_MASK; | |
587 | val |= port; | |
588 | } | |
589 | ||
822974ae | 590 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
591 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
592 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 593 | |
f278d972 | 594 | I915_WRITE(reg, val); |
9d9740f0 | 595 | POSTING_READ(reg); |
f278d972 | 596 | |
6553b123 | 597 | intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state); |
ac240288 | 598 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); |
f1781e9b | 599 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
600 | } |
601 | ||
ac240288 | 602 | static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state) |
6d67415f | 603 | { |
ac240288 | 604 | struct drm_connector *connector = conn_state->connector; |
6d67415f VS |
605 | |
606 | /* | |
607 | * HDMI cloning is only supported on g4x which doesn't | |
608 | * support deep color or GCP infoframes anyway so no | |
609 | * need to worry about multiple HDMI sinks here. | |
610 | */ | |
6d67415f | 611 | |
ac240288 | 612 | return connector->display_info.bpc > 8; |
6d67415f VS |
613 | } |
614 | ||
12aa3290 VS |
615 | /* |
616 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
617 | * | |
618 | * From HDMI specification 1.4a: | |
619 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
620 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
621 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
622 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
623 | * phase of 0 | |
624 | */ | |
625 | static bool gcp_default_phase_possible(int pipe_bpp, | |
626 | const struct drm_display_mode *mode) | |
627 | { | |
628 | unsigned int pixels_per_group; | |
629 | ||
630 | switch (pipe_bpp) { | |
631 | case 30: | |
632 | /* 4 pixels in 5 clocks */ | |
633 | pixels_per_group = 4; | |
634 | break; | |
635 | case 36: | |
636 | /* 2 pixels in 3 clocks */ | |
637 | pixels_per_group = 2; | |
638 | break; | |
639 | case 48: | |
640 | /* 1 pixel in 2 clocks */ | |
641 | pixels_per_group = 1; | |
642 | break; | |
643 | default: | |
644 | /* phase information not relevant for 8bpc */ | |
645 | return false; | |
646 | } | |
647 | ||
648 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
649 | mode->crtc_htotal % pixels_per_group == 0 && | |
650 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
651 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
652 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
653 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
654 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
655 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
656 | } | |
657 | ||
790ea70c | 658 | static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, |
ac240288 ML |
659 | const struct intel_crtc_state *crtc_state, |
660 | const struct drm_connector_state *conn_state) | |
6d67415f | 661 | { |
790ea70c | 662 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 663 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 VS |
664 | i915_reg_t reg; |
665 | u32 val = 0; | |
6d67415f VS |
666 | |
667 | if (HAS_DDI(dev_priv)) | |
ac240288 | 668 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 669 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 670 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 671 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
672 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
673 | else | |
674 | return false; | |
675 | ||
676 | /* Indicate color depth whenever the sink supports deep color */ | |
ac240288 | 677 | if (hdmi_sink_is_deep_color(conn_state)) |
6d67415f VS |
678 | val |= GCP_COLOR_INDICATION; |
679 | ||
12aa3290 | 680 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
681 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
682 | &crtc_state->base.adjusted_mode)) | |
12aa3290 VS |
683 | val |= GCP_DEFAULT_PHASE_ENABLE; |
684 | ||
6d67415f VS |
685 | I915_WRITE(reg, val); |
686 | ||
687 | return val != 0; | |
688 | } | |
689 | ||
790ea70c | 690 | static void ibx_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 691 | bool enable, |
ac240288 ML |
692 | const struct intel_crtc_state *crtc_state, |
693 | const struct drm_connector_state *conn_state) | |
687f4d06 | 694 | { |
790ea70c | 695 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 696 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 697 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
69fde0a6 | 698 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 699 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 700 | u32 val = I915_READ(reg); |
790ea70c | 701 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 702 | |
afba0188 DV |
703 | assert_hdmi_port_disabled(intel_hdmi); |
704 | ||
0c14c7f9 PZ |
705 | /* See the big comment in g4x_set_infoframes() */ |
706 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
707 | ||
6897b4b5 | 708 | if (!enable) { |
0c14c7f9 PZ |
709 | if (!(val & VIDEO_DIP_ENABLE)) |
710 | return; | |
0be6f0c8 VS |
711 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
712 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
713 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 714 | I915_WRITE(reg, val); |
9d9740f0 | 715 | POSTING_READ(reg); |
0c14c7f9 PZ |
716 | return; |
717 | } | |
718 | ||
72b78c9d | 719 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
720 | WARN(val & VIDEO_DIP_ENABLE, |
721 | "DIP already enabled on port %c\n", | |
722 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
723 | val &= ~VIDEO_DIP_PORT_MASK; |
724 | val |= port; | |
725 | } | |
726 | ||
822974ae | 727 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
728 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
729 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
730 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 731 | |
ac240288 | 732 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
733 | val |= VIDEO_DIP_ENABLE_GCP; |
734 | ||
f278d972 | 735 | I915_WRITE(reg, val); |
9d9740f0 | 736 | POSTING_READ(reg); |
f278d972 | 737 | |
6553b123 | 738 | intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state); |
ac240288 | 739 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); |
f1781e9b | 740 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
741 | } |
742 | ||
790ea70c | 743 | static void cpt_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 744 | bool enable, |
ac240288 ML |
745 | const struct intel_crtc_state *crtc_state, |
746 | const struct drm_connector_state *conn_state) | |
687f4d06 | 747 | { |
790ea70c | 748 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 749 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 750 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 751 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
752 | u32 val = I915_READ(reg); |
753 | ||
afba0188 DV |
754 | assert_hdmi_port_disabled(intel_hdmi); |
755 | ||
0c14c7f9 PZ |
756 | /* See the big comment in g4x_set_infoframes() */ |
757 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
758 | ||
6897b4b5 | 759 | if (!enable) { |
0c14c7f9 PZ |
760 | if (!(val & VIDEO_DIP_ENABLE)) |
761 | return; | |
0be6f0c8 VS |
762 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
763 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
764 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 765 | I915_WRITE(reg, val); |
9d9740f0 | 766 | POSTING_READ(reg); |
0c14c7f9 PZ |
767 | return; |
768 | } | |
769 | ||
822974ae PZ |
770 | /* Set both together, unset both together: see the spec. */ |
771 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 772 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 773 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 774 | |
ac240288 | 775 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
776 | val |= VIDEO_DIP_ENABLE_GCP; |
777 | ||
822974ae | 778 | I915_WRITE(reg, val); |
9d9740f0 | 779 | POSTING_READ(reg); |
822974ae | 780 | |
6553b123 | 781 | intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state); |
ac240288 | 782 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); |
f1781e9b | 783 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
784 | } |
785 | ||
790ea70c | 786 | static void vlv_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 787 | bool enable, |
ac240288 ML |
788 | const struct intel_crtc_state *crtc_state, |
789 | const struct drm_connector_state *conn_state) | |
687f4d06 | 790 | { |
790ea70c | 791 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 792 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 793 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 794 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 795 | u32 val = I915_READ(reg); |
790ea70c | 796 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 797 | |
afba0188 DV |
798 | assert_hdmi_port_disabled(intel_hdmi); |
799 | ||
0c14c7f9 PZ |
800 | /* See the big comment in g4x_set_infoframes() */ |
801 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
802 | ||
6897b4b5 | 803 | if (!enable) { |
0c14c7f9 PZ |
804 | if (!(val & VIDEO_DIP_ENABLE)) |
805 | return; | |
0be6f0c8 VS |
806 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
807 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
808 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 809 | I915_WRITE(reg, val); |
9d9740f0 | 810 | POSTING_READ(reg); |
0c14c7f9 PZ |
811 | return; |
812 | } | |
813 | ||
6a2b8021 | 814 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
815 | WARN(val & VIDEO_DIP_ENABLE, |
816 | "DIP already enabled on port %c\n", | |
817 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
818 | val &= ~VIDEO_DIP_PORT_MASK; |
819 | val |= port; | |
820 | } | |
821 | ||
822974ae | 822 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
823 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
824 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
825 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 826 | |
ac240288 | 827 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
828 | val |= VIDEO_DIP_ENABLE_GCP; |
829 | ||
822974ae | 830 | I915_WRITE(reg, val); |
9d9740f0 | 831 | POSTING_READ(reg); |
822974ae | 832 | |
6553b123 | 833 | intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state); |
ac240288 | 834 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); |
f1781e9b | 835 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
836 | } |
837 | ||
790ea70c | 838 | static void hsw_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 839 | bool enable, |
ac240288 ML |
840 | const struct intel_crtc_state *crtc_state, |
841 | const struct drm_connector_state *conn_state) | |
687f4d06 | 842 | { |
790ea70c | 843 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 844 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 845 | u32 val = I915_READ(reg); |
0c14c7f9 | 846 | |
8fc0aa6e ID |
847 | assert_hdmi_transcoder_func_disabled(dev_priv, |
848 | crtc_state->cpu_transcoder); | |
afba0188 | 849 | |
0be6f0c8 VS |
850 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
851 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
852 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
853 | ||
6897b4b5 | 854 | if (!enable) { |
0be6f0c8 | 855 | I915_WRITE(reg, val); |
9d9740f0 | 856 | POSTING_READ(reg); |
0c14c7f9 PZ |
857 | return; |
858 | } | |
859 | ||
ac240288 | 860 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
861 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
862 | ||
0dd87d20 | 863 | I915_WRITE(reg, val); |
9d9740f0 | 864 | POSTING_READ(reg); |
0dd87d20 | 865 | |
6553b123 | 866 | intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state); |
ac240288 | 867 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); |
f1781e9b | 868 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
869 | } |
870 | ||
b2ccb822 VS |
871 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
872 | { | |
873 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
874 | struct i2c_adapter *adapter = | |
875 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
876 | ||
877 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
878 | return; | |
879 | ||
880 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
881 | enable ? "Enabling" : "Disabling"); | |
882 | ||
883 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
884 | adapter, enable); | |
885 | } | |
886 | ||
2320175f SP |
887 | static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, |
888 | unsigned int offset, void *buffer, size_t size) | |
889 | { | |
890 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
891 | struct drm_i915_private *dev_priv = | |
892 | intel_dig_port->base.base.dev->dev_private; | |
893 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
894 | hdmi->ddc_bus); | |
895 | int ret; | |
896 | u8 start = offset & 0xff; | |
897 | struct i2c_msg msgs[] = { | |
898 | { | |
899 | .addr = DRM_HDCP_DDC_ADDR, | |
900 | .flags = 0, | |
901 | .len = 1, | |
902 | .buf = &start, | |
903 | }, | |
904 | { | |
905 | .addr = DRM_HDCP_DDC_ADDR, | |
906 | .flags = I2C_M_RD, | |
907 | .len = size, | |
908 | .buf = buffer | |
909 | } | |
910 | }; | |
911 | ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); | |
912 | if (ret == ARRAY_SIZE(msgs)) | |
913 | return 0; | |
914 | return ret >= 0 ? -EIO : ret; | |
915 | } | |
916 | ||
917 | static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, | |
918 | unsigned int offset, void *buffer, size_t size) | |
919 | { | |
920 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
921 | struct drm_i915_private *dev_priv = | |
922 | intel_dig_port->base.base.dev->dev_private; | |
923 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
924 | hdmi->ddc_bus); | |
925 | int ret; | |
926 | u8 *write_buf; | |
927 | struct i2c_msg msg; | |
928 | ||
929 | write_buf = kzalloc(size + 1, GFP_KERNEL); | |
930 | if (!write_buf) | |
931 | return -ENOMEM; | |
932 | ||
933 | write_buf[0] = offset & 0xff; | |
934 | memcpy(&write_buf[1], buffer, size); | |
935 | ||
936 | msg.addr = DRM_HDCP_DDC_ADDR; | |
937 | msg.flags = 0, | |
938 | msg.len = size + 1, | |
939 | msg.buf = write_buf; | |
940 | ||
941 | ret = i2c_transfer(adapter, &msg, 1); | |
942 | if (ret == 1) | |
1b1b1162 RV |
943 | ret = 0; |
944 | else if (ret >= 0) | |
945 | ret = -EIO; | |
946 | ||
947 | kfree(write_buf); | |
948 | return ret; | |
2320175f SP |
949 | } |
950 | ||
951 | static | |
952 | int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
953 | u8 *an) | |
954 | { | |
955 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
956 | struct drm_i915_private *dev_priv = | |
957 | intel_dig_port->base.base.dev->dev_private; | |
958 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
959 | hdmi->ddc_bus); | |
960 | int ret; | |
961 | ||
962 | ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, | |
963 | DRM_HDCP_AN_LEN); | |
964 | if (ret) { | |
3aae21fc | 965 | DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); |
2320175f SP |
966 | return ret; |
967 | } | |
968 | ||
969 | ret = intel_gmbus_output_aksv(adapter); | |
970 | if (ret < 0) { | |
3aae21fc | 971 | DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); |
2320175f SP |
972 | return ret; |
973 | } | |
974 | return 0; | |
975 | } | |
976 | ||
977 | static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
978 | u8 *bksv) | |
979 | { | |
980 | int ret; | |
981 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, | |
982 | DRM_HDCP_KSV_LEN); | |
983 | if (ret) | |
3aae21fc | 984 | DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); |
2320175f SP |
985 | return ret; |
986 | } | |
987 | ||
988 | static | |
989 | int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
990 | u8 *bstatus) | |
991 | { | |
992 | int ret; | |
993 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, | |
994 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
995 | if (ret) | |
3aae21fc | 996 | DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); |
2320175f SP |
997 | return ret; |
998 | } | |
999 | ||
1000 | static | |
1001 | int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
1002 | bool *repeater_present) | |
1003 | { | |
1004 | int ret; | |
1005 | u8 val; | |
1006 | ||
1007 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1008 | if (ret) { | |
3aae21fc | 1009 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1010 | return ret; |
1011 | } | |
1012 | *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; | |
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | static | |
1017 | int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
1018 | u8 *ri_prime) | |
1019 | { | |
1020 | int ret; | |
1021 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, | |
1022 | ri_prime, DRM_HDCP_RI_LEN); | |
1023 | if (ret) | |
3aae21fc | 1024 | DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); |
2320175f SP |
1025 | return ret; |
1026 | } | |
1027 | ||
1028 | static | |
1029 | int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
1030 | bool *ksv_ready) | |
1031 | { | |
1032 | int ret; | |
1033 | u8 val; | |
1034 | ||
1035 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1036 | if (ret) { | |
3aae21fc | 1037 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1038 | return ret; |
1039 | } | |
1040 | *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; | |
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | static | |
1045 | int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
1046 | int num_downstream, u8 *ksv_fifo) | |
1047 | { | |
1048 | int ret; | |
1049 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, | |
1050 | ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); | |
1051 | if (ret) { | |
3aae21fc | 1052 | DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); |
2320175f SP |
1053 | return ret; |
1054 | } | |
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | static | |
1059 | int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
1060 | int i, u32 *part) | |
1061 | { | |
1062 | int ret; | |
1063 | ||
1064 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
1065 | return -EINVAL; | |
1066 | ||
1067 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), | |
1068 | part, DRM_HDCP_V_PRIME_PART_LEN); | |
1069 | if (ret) | |
3aae21fc | 1070 | DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); |
2320175f SP |
1071 | return ret; |
1072 | } | |
1073 | ||
1074 | static | |
1075 | int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
1076 | bool enable) | |
1077 | { | |
1078 | int ret; | |
1079 | ||
1080 | if (!enable) | |
1081 | usleep_range(6, 60); /* Bspec says >= 6us */ | |
1082 | ||
1083 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); | |
1084 | if (ret) { | |
1085 | DRM_ERROR("%s HDCP signalling failed (%d)\n", | |
1086 | enable ? "Enable" : "Disable", ret); | |
1087 | return ret; | |
1088 | } | |
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | static | |
1093 | bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
1094 | { | |
1095 | struct drm_i915_private *dev_priv = | |
1096 | intel_dig_port->base.base.dev->dev_private; | |
1097 | enum port port = intel_dig_port->base.port; | |
1098 | int ret; | |
1099 | union { | |
1100 | u32 reg; | |
1101 | u8 shim[DRM_HDCP_RI_LEN]; | |
1102 | } ri; | |
1103 | ||
1104 | ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); | |
1105 | if (ret) | |
1106 | return false; | |
1107 | ||
1108 | I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); | |
1109 | ||
1110 | /* Wait for Ri prime match */ | |
1111 | if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & | |
1112 | (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { | |
1113 | DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", | |
1114 | I915_READ(PORT_HDCP_STATUS(port))); | |
1115 | return false; | |
1116 | } | |
1117 | return true; | |
1118 | } | |
1119 | ||
1120 | static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { | |
1121 | .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, | |
1122 | .read_bksv = intel_hdmi_hdcp_read_bksv, | |
1123 | .read_bstatus = intel_hdmi_hdcp_read_bstatus, | |
1124 | .repeater_present = intel_hdmi_hdcp_repeater_present, | |
1125 | .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, | |
1126 | .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, | |
1127 | .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, | |
1128 | .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, | |
1129 | .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, | |
1130 | .check_link = intel_hdmi_hdcp_check_link, | |
1131 | }; | |
1132 | ||
ac240288 ML |
1133 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
1134 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 1135 | { |
c59423a3 | 1136 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1137 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1138 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 1139 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 1140 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 1141 | u32 hdmi_val; |
7d57382e | 1142 | |
b2ccb822 VS |
1143 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
1144 | ||
b242b7f7 | 1145 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 1146 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 1147 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 1148 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 1149 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 1150 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 1151 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 1152 | |
ac240288 | 1153 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 1154 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 1155 | else |
4f3a8bc7 | 1156 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 1157 | |
ac240288 | 1158 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 1159 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 1160 | |
6e266956 | 1161 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 1162 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 1163 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1164 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 1165 | else |
c59423a3 | 1166 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 1167 | |
b242b7f7 PZ |
1168 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
1169 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
1170 | } |
1171 | ||
85234cdc DV |
1172 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
1173 | enum pipe *pipe) | |
7d57382e | 1174 | { |
76203467 | 1175 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
85234cdc | 1176 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
5b092174 | 1177 | bool ret; |
85234cdc | 1178 | |
79f255a0 ACO |
1179 | if (!intel_display_power_get_if_enabled(dev_priv, |
1180 | encoder->power_domain)) | |
6d129bea ID |
1181 | return false; |
1182 | ||
76203467 | 1183 | ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); |
5b092174 | 1184 | |
79f255a0 | 1185 | intel_display_power_put(dev_priv, encoder->power_domain); |
5b092174 ID |
1186 | |
1187 | return ret; | |
85234cdc DV |
1188 | } |
1189 | ||
045ac3b5 | 1190 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 1191 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
1192 | { |
1193 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
f99be1b3 | 1194 | struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi); |
8c875fca | 1195 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1196 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 1197 | u32 tmp, flags = 0; |
18442d08 | 1198 | int dotclock; |
045ac3b5 | 1199 | |
e1214b95 VS |
1200 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); |
1201 | ||
045ac3b5 JB |
1202 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
1203 | ||
1204 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
1205 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1206 | else | |
1207 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1208 | ||
1209 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
1210 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1211 | else | |
1212 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1213 | ||
6897b4b5 DV |
1214 | if (tmp & HDMI_MODE_SELECT_HDMI) |
1215 | pipe_config->has_hdmi_sink = true; | |
1216 | ||
790ea70c | 1217 | if (intel_dig_port->infoframe_enabled(encoder, pipe_config)) |
e43823ec JB |
1218 | pipe_config->has_infoframe = true; |
1219 | ||
c84db770 | 1220 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
1221 | pipe_config->has_audio = true; |
1222 | ||
6e266956 | 1223 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
1224 | tmp & HDMI_COLOR_RANGE_16_235) |
1225 | pipe_config->limited_color_range = true; | |
1226 | ||
2d112de7 | 1227 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
1228 | |
1229 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
1230 | dotclock = pipe_config->port_clock * 2 / 3; | |
1231 | else | |
1232 | dotclock = pipe_config->port_clock; | |
1233 | ||
be69a133 VS |
1234 | if (pipe_config->pixel_multiplier) |
1235 | dotclock /= pipe_config->pixel_multiplier; | |
1236 | ||
2d112de7 | 1237 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
1238 | |
1239 | pipe_config->lane_count = 4; | |
045ac3b5 JB |
1240 | } |
1241 | ||
df18e721 | 1242 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
5f88a9c6 VS |
1243 | const struct intel_crtc_state *pipe_config, |
1244 | const struct drm_connector_state *conn_state) | |
d1b1589c | 1245 | { |
ac240288 | 1246 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 1247 | |
ac240288 | 1248 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
1249 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
1250 | pipe_name(crtc->pipe)); | |
bbf35e9d | 1251 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
1252 | } |
1253 | ||
fd6bbda9 | 1254 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1255 | const struct intel_crtc_state *pipe_config, |
1256 | const struct drm_connector_state *conn_state) | |
7d57382e | 1257 | { |
5ab432ef | 1258 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1259 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1260 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1261 | u32 temp; |
1262 | ||
b242b7f7 | 1263 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1264 | |
bf868c7d | 1265 | temp |= SDVO_ENABLE; |
df18e721 | 1266 | if (pipe_config->has_audio) |
bf868c7d | 1267 | temp |= SDVO_AUDIO_ENABLE; |
7a87c289 | 1268 | |
bf868c7d VS |
1269 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1270 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1271 | ||
df18e721 ML |
1272 | if (pipe_config->has_audio) |
1273 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1274 | } |
1275 | ||
fd6bbda9 | 1276 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1277 | const struct intel_crtc_state *pipe_config, |
1278 | const struct drm_connector_state *conn_state) | |
bf868c7d VS |
1279 | { |
1280 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1281 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1282 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1283 | u32 temp; | |
1284 | ||
1285 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1286 | |
bf868c7d | 1287 | temp |= SDVO_ENABLE; |
ac240288 | 1288 | if (pipe_config->has_audio) |
bf868c7d | 1289 | temp |= SDVO_AUDIO_ENABLE; |
5ab432ef | 1290 | |
bf868c7d VS |
1291 | /* |
1292 | * HW workaround, need to write this twice for issue | |
1293 | * that may result in first write getting masked. | |
1294 | */ | |
1295 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1296 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1297 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1298 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1299 | |
bf868c7d VS |
1300 | /* |
1301 | * HW workaround, need to toggle enable bit off and on | |
1302 | * for 12bpc with pixel repeat. | |
1303 | * | |
1304 | * FIXME: BSpec says this should be done at the end of | |
1305 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1306 | */ |
df18e721 ML |
1307 | if (pipe_config->pipe_bpp > 24 && |
1308 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1309 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1310 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1311 | ||
1312 | /* | |
1313 | * HW workaround, need to write this twice for issue | |
1314 | * that may result in first write getting masked. | |
1315 | */ | |
1316 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1317 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1318 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1319 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1320 | } |
c1dec79a | 1321 | |
df18e721 ML |
1322 | if (pipe_config->has_audio) |
1323 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1324 | } |
1325 | ||
fd6bbda9 | 1326 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1327 | const struct intel_crtc_state *pipe_config, |
1328 | const struct drm_connector_state *conn_state) | |
d1b1589c VS |
1329 | { |
1330 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1331 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1332 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1333 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1334 | enum pipe pipe = crtc->pipe; | |
1335 | u32 temp; | |
1336 | ||
1337 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1338 | ||
1339 | temp |= SDVO_ENABLE; | |
df18e721 | 1340 | if (pipe_config->has_audio) |
d1b1589c VS |
1341 | temp |= SDVO_AUDIO_ENABLE; |
1342 | ||
1343 | /* | |
1344 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1345 | * | |
1346 | * The procedure for 12bpc is as follows: | |
1347 | * 1. disable HDMI clock gating | |
1348 | * 2. enable HDMI with 8bpc | |
1349 | * 3. enable HDMI with 12bpc | |
1350 | * 4. enable HDMI clock gating | |
1351 | */ | |
1352 | ||
df18e721 | 1353 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1354 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1355 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1356 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1357 | ||
1358 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1359 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1360 | } |
d1b1589c VS |
1361 | |
1362 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1363 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1364 | ||
df18e721 | 1365 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1366 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1367 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1368 | ||
1369 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1370 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1371 | ||
1372 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1373 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1374 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1375 | } | |
1376 | ||
df18e721 ML |
1377 | if (pipe_config->has_audio) |
1378 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1379 | } |
89b667f8 | 1380 | |
fd6bbda9 | 1381 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1382 | const struct intel_crtc_state *pipe_config, |
1383 | const struct drm_connector_state *conn_state) | |
b76cf76b | 1384 | { |
5ab432ef DV |
1385 | } |
1386 | ||
fd6bbda9 | 1387 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1388 | const struct intel_crtc_state *old_crtc_state, |
1389 | const struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
1390 | { |
1391 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1392 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1393 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f99be1b3 VS |
1394 | struct intel_digital_port *intel_dig_port = |
1395 | hdmi_to_dig_port(intel_hdmi); | |
ac240288 | 1396 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 1397 | u32 temp; |
5ab432ef | 1398 | |
b242b7f7 | 1399 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1400 | |
1612c8bd | 1401 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1402 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1403 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1404 | |
1405 | /* | |
1406 | * HW workaround for IBX, we need to move the port | |
1407 | * to transcoder A after disabling it to allow the | |
1408 | * matching DP port to be enabled on transcoder A. | |
1409 | */ | |
6e266956 | 1410 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
1411 | /* |
1412 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1413 | * doing the workaround. Sweep them under the rug. | |
1414 | */ | |
1415 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1416 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1417 | ||
76203467 VS |
1418 | temp &= ~SDVO_PIPE_SEL_MASK; |
1419 | temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); | |
1612c8bd VS |
1420 | /* |
1421 | * HW workaround, need to write this twice for issue | |
1422 | * that may result in first write getting masked. | |
1423 | */ | |
1424 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1425 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1426 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1427 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1428 | ||
1429 | temp &= ~SDVO_ENABLE; | |
1430 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1431 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 1432 | |
0f0f74bc | 1433 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
1434 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
1435 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 1436 | } |
6d67415f | 1437 | |
790ea70c VS |
1438 | intel_dig_port->set_infoframes(encoder, |
1439 | false, | |
f99be1b3 | 1440 | old_crtc_state, old_conn_state); |
b2ccb822 VS |
1441 | |
1442 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
1443 | } |
1444 | ||
fd6bbda9 | 1445 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1446 | const struct intel_crtc_state *old_crtc_state, |
1447 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 1448 | { |
df18e721 | 1449 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
1450 | intel_audio_codec_disable(encoder, |
1451 | old_crtc_state, old_conn_state); | |
a4790cec | 1452 | |
fd6bbda9 | 1453 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1454 | } |
1455 | ||
fd6bbda9 | 1456 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1457 | const struct intel_crtc_state *old_crtc_state, |
1458 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 1459 | { |
df18e721 | 1460 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
1461 | intel_audio_codec_disable(encoder, |
1462 | old_crtc_state, old_conn_state); | |
a4790cec VS |
1463 | } |
1464 | ||
fd6bbda9 | 1465 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1466 | const struct intel_crtc_state *old_crtc_state, |
1467 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 1468 | { |
fd6bbda9 | 1469 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1470 | } |
1471 | ||
d6038611 | 1472 | static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) |
7d148ef5 | 1473 | { |
d6038611 VS |
1474 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1475 | const struct ddi_vbt_port_info *info = | |
1476 | &dev_priv->vbt.ddi_port_info[encoder->port]; | |
1477 | int max_tmds_clock; | |
1478 | ||
9672a69c | 1479 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
d6038611 VS |
1480 | max_tmds_clock = 594000; |
1481 | else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) | |
1482 | max_tmds_clock = 300000; | |
1483 | else if (INTEL_GEN(dev_priv) >= 5) | |
1484 | max_tmds_clock = 225000; | |
7d148ef5 | 1485 | else |
d6038611 VS |
1486 | max_tmds_clock = 165000; |
1487 | ||
1488 | if (info->max_tmds_clock) | |
1489 | max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); | |
1490 | ||
1491 | return max_tmds_clock; | |
7d148ef5 DV |
1492 | } |
1493 | ||
b1ba124d | 1494 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f ML |
1495 | bool respect_downstream_limits, |
1496 | bool force_dvi) | |
b1ba124d | 1497 | { |
d6038611 VS |
1498 | struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; |
1499 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); | |
b1ba124d VS |
1500 | |
1501 | if (respect_downstream_limits) { | |
8cadab0a VS |
1502 | struct intel_connector *connector = hdmi->attached_connector; |
1503 | const struct drm_display_info *info = &connector->base.display_info; | |
1504 | ||
b1ba124d VS |
1505 | if (hdmi->dp_dual_mode.max_tmds_clock) |
1506 | max_tmds_clock = min(max_tmds_clock, | |
1507 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
1508 | |
1509 | if (info->max_tmds_clock) | |
1510 | max_tmds_clock = min(max_tmds_clock, | |
1511 | info->max_tmds_clock); | |
7a5ca19f | 1512 | else if (!hdmi->has_hdmi_sink || force_dvi) |
b1ba124d VS |
1513 | max_tmds_clock = min(max_tmds_clock, 165000); |
1514 | } | |
1515 | ||
1516 | return max_tmds_clock; | |
1517 | } | |
1518 | ||
e64e739e VS |
1519 | static enum drm_mode_status |
1520 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f ML |
1521 | int clock, bool respect_downstream_limits, |
1522 | bool force_dvi) | |
e64e739e | 1523 | { |
e2d214ae | 1524 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
1525 | |
1526 | if (clock < 25000) | |
1527 | return MODE_CLOCK_LOW; | |
7a5ca19f | 1528 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) |
e64e739e VS |
1529 | return MODE_CLOCK_HIGH; |
1530 | ||
5e6ccc0b | 1531 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 1532 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
1533 | return MODE_CLOCK_RANGE; |
1534 | ||
1535 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 1536 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
1537 | return MODE_CLOCK_RANGE; |
1538 | ||
1539 | return MODE_OK; | |
1540 | } | |
1541 | ||
c19de8eb DL |
1542 | static enum drm_mode_status |
1543 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1544 | struct drm_display_mode *mode) | |
7d57382e | 1545 | { |
e64e739e VS |
1546 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1547 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 1548 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
1549 | enum drm_mode_status status; |
1550 | int clock; | |
587bf496 | 1551 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
7a5ca19f ML |
1552 | bool force_dvi = |
1553 | READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; | |
e64e739e | 1554 | |
e4dd27aa VS |
1555 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
1556 | return MODE_NO_DBLESCAN; | |
1557 | ||
e64e739e | 1558 | clock = mode->clock; |
587bf496 MK |
1559 | |
1560 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
1561 | clock *= 2; | |
1562 | ||
1563 | if (clock > max_dotclk) | |
1564 | return MODE_CLOCK_HIGH; | |
1565 | ||
697c4078 CT |
1566 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1567 | clock *= 2; | |
1568 | ||
b22ca995 SS |
1569 | if (drm_mode_is_420_only(&connector->display_info, mode)) |
1570 | clock /= 2; | |
1571 | ||
e64e739e | 1572 | /* check if we can do 8bpc */ |
7a5ca19f | 1573 | status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); |
7d57382e | 1574 | |
cd9e11a8 RS |
1575 | if (hdmi->has_hdmi_sink && !force_dvi) { |
1576 | /* if we can't do 8bpc we may still be able to do 12bpc */ | |
1577 | if (status != MODE_OK && !HAS_GMCH_DISPLAY(dev_priv)) | |
1578 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, | |
1579 | true, force_dvi); | |
1580 | ||
1581 | /* if we can't do 8,12bpc we may still be able to do 10bpc */ | |
1582 | if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) | |
1583 | status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, | |
1584 | true, force_dvi); | |
1585 | } | |
7d57382e | 1586 | |
e64e739e | 1587 | return status; |
7d57382e EA |
1588 | } |
1589 | ||
cd9e11a8 RS |
1590 | static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, |
1591 | int bpc) | |
71800632 | 1592 | { |
c750bdd3 VS |
1593 | struct drm_i915_private *dev_priv = |
1594 | to_i915(crtc_state->base.crtc->dev); | |
1595 | struct drm_atomic_state *state = crtc_state->base.state; | |
1596 | struct drm_connector_state *connector_state; | |
1597 | struct drm_connector *connector; | |
22dae8a0 RS |
1598 | const struct drm_display_mode *adjusted_mode = |
1599 | &crtc_state->base.adjusted_mode; | |
c750bdd3 | 1600 | int i; |
71800632 | 1601 | |
c750bdd3 | 1602 | if (HAS_GMCH_DISPLAY(dev_priv)) |
71800632 VS |
1603 | return false; |
1604 | ||
cd9e11a8 RS |
1605 | if (bpc == 10 && INTEL_GEN(dev_priv) < 11) |
1606 | return false; | |
1607 | ||
be33be5d VS |
1608 | if (crtc_state->pipe_bpp <= 8*3) |
1609 | return false; | |
1610 | ||
1611 | if (!crtc_state->has_hdmi_sink) | |
1612 | return false; | |
1613 | ||
71800632 | 1614 | /* |
cd9e11a8 | 1615 | * HDMI deep color affects the clocks, so it's only possible |
71800632 VS |
1616 | * when not cloning with other encoder types. |
1617 | */ | |
c750bdd3 VS |
1618 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
1619 | return false; | |
1620 | ||
fe5f6b1f | 1621 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
c750bdd3 VS |
1622 | const struct drm_display_info *info = &connector->display_info; |
1623 | ||
1624 | if (connector_state->crtc != crtc_state->base.crtc) | |
1625 | continue; | |
1626 | ||
33b7f3ee | 1627 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { |
60436fd4 SS |
1628 | const struct drm_hdmi_info *hdmi = &info->hdmi; |
1629 | ||
cd9e11a8 RS |
1630 | if (bpc == 12 && !(hdmi->y420_dc_modes & |
1631 | DRM_EDID_YCBCR420_DC_36)) | |
1632 | return false; | |
1633 | else if (bpc == 10 && !(hdmi->y420_dc_modes & | |
1634 | DRM_EDID_YCBCR420_DC_30)) | |
60436fd4 SS |
1635 | return false; |
1636 | } else { | |
cd9e11a8 RS |
1637 | if (bpc == 12 && !(info->edid_hdmi_dc_modes & |
1638 | DRM_EDID_HDMI_DC_36)) | |
1639 | return false; | |
1640 | else if (bpc == 10 && !(info->edid_hdmi_dc_modes & | |
1641 | DRM_EDID_HDMI_DC_30)) | |
60436fd4 SS |
1642 | return false; |
1643 | } | |
c750bdd3 VS |
1644 | } |
1645 | ||
2abf3c0d | 1646 | /* Display WA #1139: glk */ |
cd9e11a8 | 1647 | if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && |
22dae8a0 RS |
1648 | adjusted_mode->htotal > 5460) |
1649 | return false; | |
1650 | ||
1651 | /* Display Wa_1405510057:icl */ | |
1652 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && | |
1653 | bpc == 10 && IS_ICELAKE(dev_priv) && | |
1654 | (adjusted_mode->crtc_hblank_end - | |
1655 | adjusted_mode->crtc_hblank_start) % 8 == 2) | |
46649d8b ACO |
1656 | return false; |
1657 | ||
c750bdd3 | 1658 | return true; |
71800632 VS |
1659 | } |
1660 | ||
60436fd4 SS |
1661 | static bool |
1662 | intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |
1663 | struct intel_crtc_state *config, | |
cd9e11a8 RS |
1664 | int *clock_12bpc, int *clock_10bpc, |
1665 | int *clock_8bpc) | |
60436fd4 | 1666 | { |
e5c05931 SS |
1667 | struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); |
1668 | ||
60436fd4 SS |
1669 | if (!connector->ycbcr_420_allowed) { |
1670 | DRM_ERROR("Platform doesn't support YCBCR420 output\n"); | |
1671 | return false; | |
1672 | } | |
1673 | ||
1674 | /* YCBCR420 TMDS rate requirement is half the pixel clock */ | |
1675 | config->port_clock /= 2; | |
1676 | *clock_12bpc /= 2; | |
cd9e11a8 | 1677 | *clock_10bpc /= 2; |
60436fd4 | 1678 | *clock_8bpc /= 2; |
33b7f3ee | 1679 | config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
e5c05931 SS |
1680 | |
1681 | /* YCBCR 420 output conversion needs a scaler */ | |
1682 | if (skl_update_scaler_crtc(config)) { | |
1683 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
1684 | return false; | |
1685 | } | |
1686 | ||
1687 | intel_pch_panel_fitting(intel_crtc, config, | |
1688 | DRM_MODE_SCALE_FULLSCREEN); | |
1689 | ||
60436fd4 SS |
1690 | return true; |
1691 | } | |
1692 | ||
5bfe2ac0 | 1693 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1694 | struct intel_crtc_state *pipe_config, |
1695 | struct drm_connector_state *conn_state) | |
7d57382e | 1696 | { |
5bfe2ac0 | 1697 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 1698 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1699 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
60436fd4 SS |
1700 | struct drm_connector *connector = conn_state->connector; |
1701 | struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; | |
7a5ca19f ML |
1702 | struct intel_digital_connector_state *intel_conn_state = |
1703 | to_intel_digital_connector_state(conn_state); | |
e64e739e | 1704 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
cd9e11a8 | 1705 | int clock_10bpc = clock_8bpc * 5 / 4; |
e64e739e | 1706 | int clock_12bpc = clock_8bpc * 3 / 2; |
e29c22c0 | 1707 | int desired_bpp; |
7a5ca19f | 1708 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
3685a8f3 | 1709 | |
e4dd27aa VS |
1710 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
1711 | return false; | |
1712 | ||
d9facae6 | 1713 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
7a5ca19f | 1714 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
6897b4b5 | 1715 | |
e43823ec JB |
1716 | if (pipe_config->has_hdmi_sink) |
1717 | pipe_config->has_infoframe = true; | |
1718 | ||
7a5ca19f | 1719 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db | 1720 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
0f2a2a75 VS |
1721 | pipe_config->limited_color_range = |
1722 | pipe_config->has_hdmi_sink && | |
c8127cf0 VS |
1723 | drm_default_rgb_quant_range(adjusted_mode) == |
1724 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1725 | } else { |
1726 | pipe_config->limited_color_range = | |
7a5ca19f | 1727 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
1728 | } |
1729 | ||
697c4078 CT |
1730 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1731 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1732 | clock_8bpc *= 2; |
cd9e11a8 | 1733 | clock_10bpc *= 2; |
3320e37f | 1734 | clock_12bpc *= 2; |
697c4078 CT |
1735 | } |
1736 | ||
60436fd4 SS |
1737 | if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { |
1738 | if (!intel_hdmi_ycbcr420_config(connector, pipe_config, | |
cd9e11a8 RS |
1739 | &clock_12bpc, &clock_10bpc, |
1740 | &clock_8bpc)) { | |
60436fd4 SS |
1741 | DRM_ERROR("Can't support YCBCR420 output\n"); |
1742 | return false; | |
1743 | } | |
1744 | } | |
1745 | ||
4f8036a2 | 1746 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
1747 | pipe_config->has_pch_encoder = true; |
1748 | ||
7a5ca19f ML |
1749 | if (pipe_config->has_hdmi_sink) { |
1750 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
1751 | pipe_config->has_audio = intel_hdmi->has_audio; | |
1752 | else | |
1753 | pipe_config->has_audio = | |
1754 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
1755 | } | |
9ed109a7 | 1756 | |
4e53c2e0 | 1757 | /* |
cd9e11a8 RS |
1758 | * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need |
1759 | * to check that the higher clock still fits within limits. | |
4e53c2e0 | 1760 | */ |
cd9e11a8 RS |
1761 | if (hdmi_deep_color_possible(pipe_config, 12) && |
1762 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, | |
1763 | true, force_dvi) == MODE_OK) { | |
e29c22c0 DV |
1764 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1765 | desired_bpp = 12*3; | |
325b9d04 DV |
1766 | |
1767 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1768 | pipe_config->port_clock = clock_12bpc; |
cd9e11a8 RS |
1769 | } else if (hdmi_deep_color_possible(pipe_config, 10) && |
1770 | hdmi_port_clock_valid(intel_hdmi, clock_10bpc, | |
1771 | true, force_dvi) == MODE_OK) { | |
1772 | DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n"); | |
1773 | desired_bpp = 10 * 3; | |
1774 | ||
1775 | /* Need to adjust the port link by 1.25x for 10bpc. */ | |
1776 | pipe_config->port_clock = clock_10bpc; | |
4e53c2e0 | 1777 | } else { |
e29c22c0 DV |
1778 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1779 | desired_bpp = 8*3; | |
e64e739e VS |
1780 | |
1781 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1782 | } |
1783 | ||
1784 | if (!pipe_config->bw_constrained) { | |
b64b7a60 | 1785 | DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp); |
e29c22c0 | 1786 | pipe_config->pipe_bpp = desired_bpp; |
4e53c2e0 DV |
1787 | } |
1788 | ||
e64e739e | 1789 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
7a5ca19f | 1790 | false, force_dvi) != MODE_OK) { |
e64e739e | 1791 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
325b9d04 DV |
1792 | return false; |
1793 | } | |
1794 | ||
28b468a0 | 1795 | /* Set user selected PAR to incoming mode's member */ |
0e9f25d0 | 1796 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
28b468a0 | 1797 | |
d4d6279a ACO |
1798 | pipe_config->lane_count = 4; |
1799 | ||
9672a69c RV |
1800 | if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || |
1801 | IS_GEMINILAKE(dev_priv))) { | |
15953637 SS |
1802 | if (scdc->scrambling.low_rates) |
1803 | pipe_config->hdmi_scrambling = true; | |
1804 | ||
1805 | if (pipe_config->port_clock > 340000) { | |
1806 | pipe_config->hdmi_scrambling = true; | |
1807 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
1808 | } | |
1809 | } | |
1810 | ||
7d57382e EA |
1811 | return true; |
1812 | } | |
1813 | ||
953ece69 CW |
1814 | static void |
1815 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1816 | { |
df0e9248 | 1817 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1818 | |
953ece69 CW |
1819 | intel_hdmi->has_hdmi_sink = false; |
1820 | intel_hdmi->has_audio = false; | |
1821 | intel_hdmi->rgb_quant_range_selectable = false; | |
1822 | ||
b1ba124d VS |
1823 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
1824 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
1825 | ||
953ece69 CW |
1826 | kfree(to_intel_connector(connector)->detect_edid); |
1827 | to_intel_connector(connector)->detect_edid = NULL; | |
1828 | } | |
1829 | ||
b1ba124d | 1830 | static void |
d6199256 | 1831 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
1832 | { |
1833 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1834 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
8f4f2797 | 1835 | enum port port = hdmi_to_dig_port(hdmi)->base.port; |
b1ba124d VS |
1836 | struct i2c_adapter *adapter = |
1837 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1838 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
1839 | ||
d6199256 VS |
1840 | /* |
1841 | * Type 1 DVI adaptors are not required to implement any | |
1842 | * registers, so we can't always detect their presence. | |
1843 | * Ideally we should be able to check the state of the | |
1844 | * CONFIG1 pin, but no such luck on our hardware. | |
1845 | * | |
1846 | * The only method left to us is to check the VBT to see | |
1847 | * if the port is a dual mode capable DP port. But let's | |
1848 | * only do that when we sucesfully read the EDID, to avoid | |
1849 | * confusing log messages about DP dual mode adaptors when | |
1850 | * there's nothing connected to the port. | |
1851 | */ | |
1852 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
30190629 AJ |
1853 | /* An overridden EDID imply that we want this port for testing. |
1854 | * Make sure not to set limits for that port. | |
1855 | */ | |
1856 | if (has_edid && !connector->override_edid && | |
d6199256 VS |
1857 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { |
1858 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
1859 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
1860 | } else { | |
1861 | type = DRM_DP_DUAL_MODE_NONE; | |
1862 | } | |
1863 | } | |
1864 | ||
1865 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
1866 | return; |
1867 | ||
1868 | hdmi->dp_dual_mode.type = type; | |
1869 | hdmi->dp_dual_mode.max_tmds_clock = | |
1870 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
1871 | ||
1872 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
1873 | drm_dp_get_dual_mode_type_name(type), | |
1874 | hdmi->dp_dual_mode.max_tmds_clock); | |
1875 | } | |
1876 | ||
953ece69 | 1877 | static bool |
23f889bd | 1878 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
1879 | { |
1880 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1881 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
23f889bd | 1882 | struct edid *edid; |
953ece69 | 1883 | bool connected = false; |
cfb926e1 | 1884 | struct i2c_adapter *i2c; |
164c8598 | 1885 | |
23f889bd | 1886 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 1887 | |
cfb926e1 SB |
1888 | i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); |
1889 | ||
1890 | edid = drm_get_edid(connector, i2c); | |
1891 | ||
1892 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
1893 | DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
1894 | intel_gmbus_force_bit(i2c, true); | |
1895 | edid = drm_get_edid(connector, i2c); | |
1896 | intel_gmbus_force_bit(i2c, false); | |
1897 | } | |
2ded9e27 | 1898 | |
23f889bd | 1899 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 1900 | |
23f889bd | 1901 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
30ad48b7 | 1902 | |
953ece69 CW |
1903 | to_intel_connector(connector)->detect_edid = edid; |
1904 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1905 | intel_hdmi->rgb_quant_range_selectable = | |
1906 | drm_rgb_quant_range_selectable(edid); | |
1907 | ||
1908 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
7a5ca19f | 1909 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
1910 | |
1911 | connected = true; | |
55b7d6e8 CW |
1912 | } |
1913 | ||
9c229127 NA |
1914 | cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); |
1915 | ||
953ece69 CW |
1916 | return connected; |
1917 | } | |
1918 | ||
8166fcea DV |
1919 | static enum drm_connector_status |
1920 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 1921 | { |
39d1e234 | 1922 | enum drm_connector_status status = connector_status_disconnected; |
8166fcea | 1923 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
9c229127 | 1924 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
39d1e234 | 1925 | struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; |
953ece69 | 1926 | |
8166fcea DV |
1927 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1928 | connector->base.id, connector->name); | |
1929 | ||
29bb94bb ID |
1930 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1931 | ||
39d1e234 PZ |
1932 | if (IS_ICELAKE(dev_priv) && |
1933 | !intel_digital_port_connected(encoder)) | |
1934 | goto out; | |
1935 | ||
8166fcea | 1936 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 1937 | |
7e732cac | 1938 | if (intel_hdmi_set_edid(connector)) |
953ece69 | 1939 | status = connector_status_connected; |
671dedd2 | 1940 | |
39d1e234 | 1941 | out: |
29bb94bb ID |
1942 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1943 | ||
9c229127 NA |
1944 | if (status != connector_status_connected) |
1945 | cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); | |
1946 | ||
2ded9e27 | 1947 | return status; |
7d57382e EA |
1948 | } |
1949 | ||
953ece69 CW |
1950 | static void |
1951 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1952 | { |
953ece69 CW |
1953 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1954 | connector->base.id, connector->name); | |
7d57382e | 1955 | |
953ece69 | 1956 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1957 | |
953ece69 CW |
1958 | if (connector->status != connector_status_connected) |
1959 | return; | |
671dedd2 | 1960 | |
23f889bd | 1961 | intel_hdmi_set_edid(connector); |
953ece69 | 1962 | } |
671dedd2 | 1963 | |
953ece69 CW |
1964 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1965 | { | |
1966 | struct edid *edid; | |
1967 | ||
1968 | edid = to_intel_connector(connector)->detect_edid; | |
1969 | if (edid == NULL) | |
1970 | return 0; | |
671dedd2 | 1971 | |
953ece69 | 1972 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1973 | } |
1974 | ||
fd6bbda9 | 1975 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1976 | const struct intel_crtc_state *pipe_config, |
1977 | const struct drm_connector_state *conn_state) | |
13732ba7 | 1978 | { |
f99be1b3 VS |
1979 | struct intel_digital_port *intel_dig_port = |
1980 | enc_to_dig_port(&encoder->base); | |
13732ba7 | 1981 | |
ac240288 | 1982 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1983 | |
790ea70c | 1984 | intel_dig_port->set_infoframes(encoder, |
f99be1b3 VS |
1985 | pipe_config->has_infoframe, |
1986 | pipe_config, conn_state); | |
13732ba7 JB |
1987 | } |
1988 | ||
fd6bbda9 | 1989 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1990 | const struct intel_crtc_state *pipe_config, |
1991 | const struct drm_connector_state *conn_state) | |
89b667f8 JB |
1992 | { |
1993 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2e1029c6 | 1994 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5f68c275 | 1995 | |
2e1029c6 | 1996 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
b76cf76b | 1997 | |
53d98725 ACO |
1998 | /* HDMI 1.0V-2dB */ |
1999 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
2000 | 0x2b247878); | |
2001 | ||
790ea70c | 2002 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2003 | pipe_config->has_infoframe, |
2004 | pipe_config, conn_state); | |
13732ba7 | 2005 | |
fd6bbda9 | 2006 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 2007 | |
9b6de0a1 | 2008 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
2009 | } |
2010 | ||
fd6bbda9 | 2011 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2012 | const struct intel_crtc_state *pipe_config, |
2013 | const struct drm_connector_state *conn_state) | |
89b667f8 | 2014 | { |
ac240288 | 2015 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2016 | |
2e1029c6 | 2017 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
89b667f8 JB |
2018 | } |
2019 | ||
fd6bbda9 | 2020 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2021 | const struct intel_crtc_state *pipe_config, |
2022 | const struct drm_connector_state *conn_state) | |
9197c88b | 2023 | { |
ac240288 | 2024 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 2025 | |
2e1029c6 | 2026 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
2027 | } |
2028 | ||
fd6bbda9 | 2029 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2030 | const struct intel_crtc_state *old_crtc_state, |
2031 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 2032 | { |
2e1029c6 | 2033 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
2034 | } |
2035 | ||
fd6bbda9 | 2036 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2037 | const struct intel_crtc_state *old_crtc_state, |
2038 | const struct drm_connector_state *old_conn_state) | |
89b667f8 | 2039 | { |
89b667f8 | 2040 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
2e1029c6 | 2041 | vlv_phy_reset_lanes(encoder, old_crtc_state); |
89b667f8 JB |
2042 | } |
2043 | ||
fd6bbda9 | 2044 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2045 | const struct intel_crtc_state *old_crtc_state, |
2046 | const struct drm_connector_state *old_conn_state) | |
580d3811 | 2047 | { |
580d3811 | 2048 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2049 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 2050 | |
a580516d | 2051 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 2052 | |
a8f327fb | 2053 | /* Assert data lane reset */ |
2e1029c6 | 2054 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 2055 | |
a580516d | 2056 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2057 | } |
2058 | ||
fd6bbda9 | 2059 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2060 | const struct intel_crtc_state *pipe_config, |
2061 | const struct drm_connector_state *conn_state) | |
e4a1d846 CML |
2062 | { |
2063 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2064 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2065 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 2066 | |
2e1029c6 | 2067 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
a02ef3c7 | 2068 | |
e4a1d846 CML |
2069 | /* FIXME: Program the support xxx V-dB */ |
2070 | /* Use 800mV-0dB */ | |
b7fa22d8 | 2071 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 2072 | |
790ea70c | 2073 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2074 | pipe_config->has_infoframe, |
2075 | pipe_config, conn_state); | |
b4eb1564 | 2076 | |
fd6bbda9 | 2077 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 2078 | |
9b6de0a1 | 2079 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
2080 | |
2081 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2082 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2083 | } |
2084 | ||
bdc93fe0 R |
2085 | static int |
2086 | intel_hdmi_connector_register(struct drm_connector *connector) | |
2087 | { | |
2088 | int ret; | |
2089 | ||
2090 | ret = intel_connector_register(connector); | |
2091 | if (ret) | |
2092 | return ret; | |
2093 | ||
2094 | i915_debugfs_connector_add(connector); | |
2095 | ||
2096 | return ret; | |
2097 | } | |
2098 | ||
7d57382e EA |
2099 | static void intel_hdmi_destroy(struct drm_connector *connector) |
2100 | { | |
9c229127 NA |
2101 | if (intel_attached_hdmi(connector)->cec_notifier) |
2102 | cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier); | |
d4b26e4f JN |
2103 | |
2104 | intel_connector_destroy(connector); | |
7d57382e EA |
2105 | } |
2106 | ||
7d57382e | 2107 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
7d57382e | 2108 | .detect = intel_hdmi_detect, |
953ece69 | 2109 | .force = intel_hdmi_force, |
7d57382e | 2110 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
2111 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
2112 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
bdc93fe0 | 2113 | .late_register = intel_hdmi_connector_register, |
c191eca1 | 2114 | .early_unregister = intel_connector_unregister, |
7d57382e | 2115 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 2116 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 2117 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
2118 | }; |
2119 | ||
2120 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
2121 | .get_modes = intel_hdmi_get_modes, | |
2122 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 2123 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
2124 | }; |
2125 | ||
7d57382e | 2126 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 2127 | .destroy = intel_encoder_destroy, |
7d57382e EA |
2128 | }; |
2129 | ||
55b7d6e8 CW |
2130 | static void |
2131 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
2132 | { | |
f1a12172 RS |
2133 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
2134 | ||
3f43c48d | 2135 | intel_attach_force_audio_property(connector); |
e953fd7b | 2136 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 2137 | intel_attach_aspect_ratio_property(connector); |
6553b123 | 2138 | drm_connector_attach_content_type_property(connector); |
0e9f25d0 | 2139 | connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
f1a12172 RS |
2140 | |
2141 | if (!HAS_GMCH_DISPLAY(dev_priv)) | |
2142 | drm_connector_attach_max_bpc_property(connector, 8, 12); | |
55b7d6e8 CW |
2143 | } |
2144 | ||
15953637 SS |
2145 | /* |
2146 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
2147 | * @encoder: intel_encoder | |
2148 | * @connector: drm_connector | |
2149 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
2150 | * or reset the high tmds clock ratio for scrambling | |
2151 | * @scrambling: bool to Indicate if the function needs to set or reset | |
2152 | * sink scrambling | |
2153 | * | |
2154 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
2155 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
2156 | * it enables scrambling. This should be called before enabling the HDMI | |
2157 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
2158 | * detect a scrambled clock within 100 ms. | |
277ab5ab VS |
2159 | * |
2160 | * Returns: | |
2161 | * True on success, false on failure. | |
15953637 | 2162 | */ |
277ab5ab | 2163 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
15953637 SS |
2164 | struct drm_connector *connector, |
2165 | bool high_tmds_clock_ratio, | |
2166 | bool scrambling) | |
2167 | { | |
277ab5ab | 2168 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
15953637 | 2169 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
15953637 | 2170 | struct drm_scrambling *sink_scrambling = |
277ab5ab VS |
2171 | &connector->display_info.hdmi.scdc.scrambling; |
2172 | struct i2c_adapter *adapter = | |
2173 | intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); | |
15953637 SS |
2174 | |
2175 | if (!sink_scrambling->supported) | |
277ab5ab | 2176 | return true; |
15953637 | 2177 | |
277ab5ab VS |
2178 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", |
2179 | connector->base.id, connector->name, | |
2180 | yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); | |
15953637 | 2181 | |
277ab5ab VS |
2182 | /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ |
2183 | return drm_scdc_set_high_tmds_clock_ratio(adapter, | |
2184 | high_tmds_clock_ratio) && | |
2185 | drm_scdc_set_scrambling(adapter, scrambling); | |
15953637 SS |
2186 | } |
2187 | ||
cec3bb01 | 2188 | static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
e4ab73a1 | 2189 | { |
e4ab73a1 VS |
2190 | u8 ddc_pin; |
2191 | ||
cec3bb01 AS |
2192 | switch (port) { |
2193 | case PORT_B: | |
2194 | ddc_pin = GMBUS_PIN_DPB; | |
2195 | break; | |
2196 | case PORT_C: | |
2197 | ddc_pin = GMBUS_PIN_DPC; | |
2198 | break; | |
2199 | case PORT_D: | |
2200 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
2201 | break; | |
2202 | default: | |
2203 | MISSING_CASE(port); | |
2204 | ddc_pin = GMBUS_PIN_DPB; | |
2205 | break; | |
e4ab73a1 | 2206 | } |
cec3bb01 AS |
2207 | return ddc_pin; |
2208 | } | |
2209 | ||
2210 | static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) | |
2211 | { | |
2212 | u8 ddc_pin; | |
e4ab73a1 VS |
2213 | |
2214 | switch (port) { | |
2215 | case PORT_B: | |
cec3bb01 | 2216 | ddc_pin = GMBUS_PIN_1_BXT; |
e4ab73a1 VS |
2217 | break; |
2218 | case PORT_C: | |
cec3bb01 AS |
2219 | ddc_pin = GMBUS_PIN_2_BXT; |
2220 | break; | |
2221 | default: | |
2222 | MISSING_CASE(port); | |
2223 | ddc_pin = GMBUS_PIN_1_BXT; | |
2224 | break; | |
2225 | } | |
2226 | return ddc_pin; | |
2227 | } | |
2228 | ||
2229 | static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
2230 | enum port port) | |
2231 | { | |
2232 | u8 ddc_pin; | |
2233 | ||
2234 | switch (port) { | |
2235 | case PORT_B: | |
2236 | ddc_pin = GMBUS_PIN_1_BXT; | |
2237 | break; | |
2238 | case PORT_C: | |
2239 | ddc_pin = GMBUS_PIN_2_BXT; | |
e4ab73a1 VS |
2240 | break; |
2241 | case PORT_D: | |
cec3bb01 AS |
2242 | ddc_pin = GMBUS_PIN_4_CNP; |
2243 | break; | |
3a2a59cc RV |
2244 | case PORT_F: |
2245 | ddc_pin = GMBUS_PIN_3_BXT; | |
2246 | break; | |
cec3bb01 AS |
2247 | default: |
2248 | MISSING_CASE(port); | |
2249 | ddc_pin = GMBUS_PIN_1_BXT; | |
2250 | break; | |
2251 | } | |
2252 | return ddc_pin; | |
2253 | } | |
2254 | ||
5c749c52 AS |
2255 | static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
2256 | { | |
2257 | u8 ddc_pin; | |
2258 | ||
2259 | switch (port) { | |
2260 | case PORT_A: | |
2261 | ddc_pin = GMBUS_PIN_1_BXT; | |
2262 | break; | |
2263 | case PORT_B: | |
2264 | ddc_pin = GMBUS_PIN_2_BXT; | |
2265 | break; | |
2266 | case PORT_C: | |
2267 | ddc_pin = GMBUS_PIN_9_TC1_ICP; | |
2268 | break; | |
2269 | case PORT_D: | |
2270 | ddc_pin = GMBUS_PIN_10_TC2_ICP; | |
2271 | break; | |
2272 | case PORT_E: | |
2273 | ddc_pin = GMBUS_PIN_11_TC3_ICP; | |
2274 | break; | |
2275 | case PORT_F: | |
2276 | ddc_pin = GMBUS_PIN_12_TC4_ICP; | |
2277 | break; | |
2278 | default: | |
2279 | MISSING_CASE(port); | |
2280 | ddc_pin = GMBUS_PIN_2_BXT; | |
2281 | break; | |
2282 | } | |
2283 | return ddc_pin; | |
2284 | } | |
2285 | ||
cec3bb01 AS |
2286 | static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, |
2287 | enum port port) | |
2288 | { | |
2289 | u8 ddc_pin; | |
2290 | ||
2291 | switch (port) { | |
2292 | case PORT_B: | |
2293 | ddc_pin = GMBUS_PIN_DPB; | |
2294 | break; | |
2295 | case PORT_C: | |
2296 | ddc_pin = GMBUS_PIN_DPC; | |
2297 | break; | |
2298 | case PORT_D: | |
2299 | ddc_pin = GMBUS_PIN_DPD; | |
e4ab73a1 VS |
2300 | break; |
2301 | default: | |
2302 | MISSING_CASE(port); | |
2303 | ddc_pin = GMBUS_PIN_DPB; | |
2304 | break; | |
2305 | } | |
cec3bb01 AS |
2306 | return ddc_pin; |
2307 | } | |
2308 | ||
2309 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, | |
2310 | enum port port) | |
2311 | { | |
2312 | const struct ddi_vbt_port_info *info = | |
2313 | &dev_priv->vbt.ddi_port_info[port]; | |
2314 | u8 ddc_pin; | |
2315 | ||
2316 | if (info->alternate_ddc_pin) { | |
2317 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
2318 | info->alternate_ddc_pin, port_name(port)); | |
2319 | return info->alternate_ddc_pin; | |
2320 | } | |
2321 | ||
2322 | if (IS_CHERRYVIEW(dev_priv)) | |
2323 | ddc_pin = chv_port_to_ddc_pin(dev_priv, port); | |
2324 | else if (IS_GEN9_LP(dev_priv)) | |
2325 | ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); | |
2326 | else if (HAS_PCH_CNP(dev_priv)) | |
2327 | ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); | |
af1f1b81 | 2328 | else if (HAS_PCH_ICP(dev_priv)) |
5c749c52 | 2329 | ddc_pin = icl_port_to_ddc_pin(dev_priv, port); |
cec3bb01 AS |
2330 | else |
2331 | ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); | |
e4ab73a1 VS |
2332 | |
2333 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
2334 | ddc_pin, port_name(port)); | |
2335 | ||
2336 | return ddc_pin; | |
2337 | } | |
2338 | ||
385e4de0 VS |
2339 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port) |
2340 | { | |
2341 | struct drm_i915_private *dev_priv = | |
2342 | to_i915(intel_dig_port->base.base.dev); | |
2343 | ||
2344 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
2345 | intel_dig_port->write_infoframe = vlv_write_infoframe; | |
2346 | intel_dig_port->set_infoframes = vlv_set_infoframes; | |
2347 | intel_dig_port->infoframe_enabled = vlv_infoframe_enabled; | |
2348 | } else if (IS_G4X(dev_priv)) { | |
2349 | intel_dig_port->write_infoframe = g4x_write_infoframe; | |
2350 | intel_dig_port->set_infoframes = g4x_set_infoframes; | |
2351 | intel_dig_port->infoframe_enabled = g4x_infoframe_enabled; | |
2352 | } else if (HAS_DDI(dev_priv)) { | |
06c812d7 | 2353 | if (intel_dig_port->lspcon.active) { |
7cbf19fd SS |
2354 | intel_dig_port->write_infoframe = |
2355 | lspcon_write_infoframe; | |
06c812d7 SS |
2356 | intel_dig_port->set_infoframes = lspcon_set_infoframes; |
2357 | intel_dig_port->infoframe_enabled = | |
2358 | lspcon_infoframe_enabled; | |
2359 | } else { | |
2360 | intel_dig_port->set_infoframes = hsw_set_infoframes; | |
2361 | intel_dig_port->infoframe_enabled = | |
2362 | hsw_infoframe_enabled; | |
2363 | intel_dig_port->write_infoframe = hsw_write_infoframe; | |
2364 | } | |
385e4de0 VS |
2365 | } else if (HAS_PCH_IBX(dev_priv)) { |
2366 | intel_dig_port->write_infoframe = ibx_write_infoframe; | |
2367 | intel_dig_port->set_infoframes = ibx_set_infoframes; | |
2368 | intel_dig_port->infoframe_enabled = ibx_infoframe_enabled; | |
2369 | } else { | |
2370 | intel_dig_port->write_infoframe = cpt_write_infoframe; | |
2371 | intel_dig_port->set_infoframes = cpt_set_infoframes; | |
2372 | intel_dig_port->infoframe_enabled = cpt_infoframe_enabled; | |
2373 | } | |
2374 | } | |
2375 | ||
00c09d70 PZ |
2376 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2377 | struct intel_connector *intel_connector) | |
7d57382e | 2378 | { |
b9cb234c PZ |
2379 | struct drm_connector *connector = &intel_connector->base; |
2380 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
2381 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2382 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 2383 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 2384 | enum port port = intel_encoder->port; |
373a3cf7 | 2385 | |
22f35042 VS |
2386 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2387 | port_name(port)); | |
2388 | ||
ccb1a831 VS |
2389 | if (WARN(intel_dig_port->max_lanes < 4, |
2390 | "Not enough lanes (%d) for HDMI on port %c\n", | |
2391 | intel_dig_port->max_lanes, port_name(port))) | |
2392 | return; | |
2393 | ||
7d57382e | 2394 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 2395 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
2396 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2397 | ||
c3febcc4 | 2398 | connector->interlace_allowed = 1; |
7d57382e | 2399 | connector->doublescan_allowed = 0; |
573e74ad | 2400 | connector->stereo_allowed = 1; |
66a9278e | 2401 | |
9672a69c | 2402 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
eadc2e51 SS |
2403 | connector->ycbcr_420_allowed = true; |
2404 | ||
e4ab73a1 VS |
2405 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
2406 | ||
f761bef2 | 2407 | if (WARN_ON(port == PORT_A)) |
e4ab73a1 | 2408 | return; |
cf53902f | 2409 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
7d57382e | 2410 | |
4f8036a2 | 2411 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
2412 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2413 | else | |
2414 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
2415 | |
2416 | intel_hdmi_add_properties(intel_hdmi, connector); | |
2417 | ||
fdddd08c | 2418 | if (is_hdcp_supported(dev_priv, port)) { |
2320175f SP |
2419 | int ret = intel_hdcp_init(intel_connector, |
2420 | &intel_hdmi_hdcp_shim); | |
2421 | if (ret) | |
2422 | DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); | |
2423 | } | |
2424 | ||
b9cb234c | 2425 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
d8b4c43a | 2426 | intel_hdmi->attached_connector = intel_connector; |
b9cb234c PZ |
2427 | |
2428 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
2429 | * 0xd. Failure to do so will result in spurious interrupts being | |
2430 | * generated on the port when a cable is not attached. | |
2431 | */ | |
1c0f1b3d | 2432 | if (IS_G45(dev_priv)) { |
b9cb234c PZ |
2433 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2434 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2435 | } | |
9c229127 NA |
2436 | |
2437 | intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev, | |
2438 | port_identifier(port)); | |
2439 | if (!intel_hdmi->cec_notifier) | |
2440 | DRM_DEBUG_KMS("CEC notifier get failed\n"); | |
b9cb234c PZ |
2441 | } |
2442 | ||
c39055b0 | 2443 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 2444 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
2445 | { |
2446 | struct intel_digital_port *intel_dig_port; | |
2447 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
2448 | struct intel_connector *intel_connector; |
2449 | ||
b14c5679 | 2450 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
2451 | if (!intel_dig_port) |
2452 | return; | |
2453 | ||
08d9bc92 | 2454 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
2455 | if (!intel_connector) { |
2456 | kfree(intel_dig_port); | |
2457 | return; | |
2458 | } | |
2459 | ||
2460 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 2461 | |
c39055b0 ACO |
2462 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
2463 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
2464 | "HDMI %c", port_name(port)); | |
00c09d70 | 2465 | |
dba14b27 | 2466 | intel_encoder->hotplug = intel_encoder_hotplug; |
5bfe2ac0 | 2467 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 2468 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
2469 | intel_encoder->disable = pch_disable_hdmi; |
2470 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
2471 | } else { | |
2472 | intel_encoder->disable = g4x_disable_hdmi; | |
2473 | } | |
00c09d70 | 2474 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 2475 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 2476 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 2477 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
2478 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2479 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 2480 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 2481 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 2482 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
2483 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2484 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 2485 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 2486 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 2487 | } else { |
13732ba7 | 2488 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 2489 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 2490 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 2491 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 2492 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 2493 | else |
bf868c7d | 2494 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 2495 | } |
5ab432ef | 2496 | |
b9cb234c | 2497 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 2498 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 2499 | intel_encoder->port = port; |
920a14b2 | 2500 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
2501 | if (port == PORT_D) |
2502 | intel_encoder->crtc_mask = 1 << 2; | |
2503 | else | |
2504 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
2505 | } else { | |
2506 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
2507 | } | |
301ea74a | 2508 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
2509 | /* |
2510 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
2511 | * to work on real hardware. And since g4x can send infoframes to | |
2512 | * only one port anyway, nothing is lost by allowing it. | |
2513 | */ | |
9beb5fea | 2514 | if (IS_G4X(dev_priv)) |
c6f1495d | 2515 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 2516 | |
b242b7f7 | 2517 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 2518 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 2519 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 2520 | |
385e4de0 VS |
2521 | intel_infoframe_init(intel_dig_port); |
2522 | ||
39053089 | 2523 | intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
b9cb234c | 2524 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2525 | } |