Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
ea5b213a CW |
40 | struct intel_hdmi { |
41 | struct intel_encoder base; | |
7d57382e | 42 | u32 sdvox_reg; |
f899fc64 | 43 | int ddc_bus; |
e953fd7b | 44 | uint32_t color_range; |
9dff6af8 | 45 | bool has_hdmi_sink; |
2e3d6006 | 46 | bool has_audio; |
b1d7e4b4 | 47 | enum hdmi_force_audio force_audio; |
45187ace JB |
48 | void (*write_infoframe)(struct drm_encoder *encoder, |
49 | struct dip_infoframe *frame); | |
7d57382e EA |
50 | }; |
51 | ||
ea5b213a CW |
52 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
53 | { | |
4ef69c7a | 54 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
55 | } |
56 | ||
df0e9248 CW |
57 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
58 | { | |
59 | return container_of(intel_attached_encoder(connector), | |
60 | struct intel_hdmi, base); | |
61 | } | |
62 | ||
45187ace | 63 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 64 | { |
45187ace | 65 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
66 | uint8_t sum = 0; |
67 | unsigned i; | |
68 | ||
45187ace JB |
69 | frame->checksum = 0; |
70 | frame->ecc = 0; | |
3c17fe4b | 71 | |
64a8fc01 | 72 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
73 | sum += data[i]; |
74 | ||
45187ace | 75 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
76 | } |
77 | ||
bc2481f3 | 78 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 79 | { |
45187ace JB |
80 | u32 flags = 0; |
81 | ||
82 | switch (frame->type) { | |
83 | case DIP_TYPE_AVI: | |
84 | flags |= VIDEO_DIP_SELECT_AVI; | |
85 | break; | |
86 | case DIP_TYPE_SPD: | |
87 | flags |= VIDEO_DIP_SELECT_SPD; | |
88 | break; | |
89 | default: | |
90 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
91 | break; | |
92 | } | |
93 | ||
94 | return flags; | |
95 | } | |
96 | ||
bc2481f3 | 97 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace JB |
98 | { |
99 | u32 flags = 0; | |
100 | ||
101 | switch (frame->type) { | |
102 | case DIP_TYPE_AVI: | |
fa193ff7 | 103 | flags |= VIDEO_DIP_ENABLE_AVI; |
45187ace JB |
104 | break; |
105 | case DIP_TYPE_SPD: | |
fa193ff7 PZ |
106 | flags |= VIDEO_DIP_ENABLE_SPD; |
107 | break; | |
108 | default: | |
109 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
110 | break; | |
111 | } | |
112 | ||
113 | return flags; | |
114 | } | |
115 | ||
a3da1df7 DV |
116 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
117 | struct dip_infoframe *frame) | |
45187ace JB |
118 | { |
119 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
120 | struct drm_device *dev = encoder->dev; |
121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
122 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
22509ec8 | 123 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 124 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 125 | |
3c17fe4b DH |
126 | |
127 | /* XXX first guess at handling video port, is this corrent? */ | |
3e6e6395 | 128 | val &= ~VIDEO_DIP_PORT_MASK; |
3c17fe4b | 129 | if (intel_hdmi->sdvox_reg == SDVOB) |
22509ec8 | 130 | val |= VIDEO_DIP_PORT_B; |
3c17fe4b | 131 | else if (intel_hdmi->sdvox_reg == SDVOC) |
22509ec8 | 132 | val |= VIDEO_DIP_PORT_C; |
3c17fe4b DH |
133 | else |
134 | return; | |
135 | ||
1d4f85ac | 136 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 137 | val |= g4x_infoframe_index(frame); |
22509ec8 | 138 | |
bc2481f3 | 139 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 140 | val |= VIDEO_DIP_ENABLE; |
45187ace | 141 | |
22509ec8 | 142 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 143 | |
45187ace | 144 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
145 | I915_WRITE(VIDEO_DIP_DATA, *data); |
146 | data++; | |
147 | } | |
148 | ||
bc2481f3 | 149 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 150 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 151 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 152 | |
22509ec8 | 153 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b DH |
154 | } |
155 | ||
fdf1250a PZ |
156 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
157 | struct dip_infoframe *frame) | |
158 | { | |
159 | uint32_t *data = (uint32_t *)frame; | |
160 | struct drm_device *dev = encoder->dev; | |
161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
162 | struct drm_crtc *crtc = encoder->crtc; | |
163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4e89ee17 | 164 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
fdf1250a PZ |
165 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
166 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
167 | u32 val = I915_READ(reg); | |
168 | ||
4e89ee17 PZ |
169 | val &= ~VIDEO_DIP_PORT_MASK; |
170 | switch (intel_hdmi->sdvox_reg) { | |
171 | case HDMIB: | |
172 | val |= VIDEO_DIP_PORT_B; | |
173 | break; | |
174 | case HDMIC: | |
175 | val |= VIDEO_DIP_PORT_C; | |
176 | break; | |
177 | case HDMID: | |
178 | val |= VIDEO_DIP_PORT_D; | |
179 | break; | |
180 | default: | |
181 | return; | |
182 | } | |
183 | ||
fdf1250a PZ |
184 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
185 | ||
186 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
bc2481f3 | 187 | val |= g4x_infoframe_index(frame); |
fdf1250a | 188 | |
bc2481f3 | 189 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
190 | val |= VIDEO_DIP_ENABLE; |
191 | ||
192 | I915_WRITE(reg, val); | |
193 | ||
194 | for (i = 0; i < len; i += 4) { | |
195 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
196 | data++; | |
197 | } | |
198 | ||
bc2481f3 | 199 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 200 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 201 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
202 | |
203 | I915_WRITE(reg, val); | |
204 | } | |
205 | ||
206 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
207 | struct dip_infoframe *frame) | |
b055c8f3 | 208 | { |
45187ace | 209 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
210 | struct drm_device *dev = encoder->dev; |
211 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b055c8f3 JB |
212 | struct drm_crtc *crtc = encoder->crtc; |
213 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
214 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
45187ace | 215 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 216 | u32 val = I915_READ(reg); |
b055c8f3 JB |
217 | |
218 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
219 | ||
64a8fc01 | 220 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 221 | val |= g4x_infoframe_index(frame); |
45187ace | 222 | |
ecb97851 PZ |
223 | /* The DIP control register spec says that we need to update the AVI |
224 | * infoframe without clearing its enable bit */ | |
225 | if (frame->type == DIP_TYPE_AVI) | |
226 | val |= VIDEO_DIP_ENABLE_AVI; | |
227 | else | |
bc2481f3 | 228 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 229 | |
22509ec8 PZ |
230 | val |= VIDEO_DIP_ENABLE; |
231 | ||
232 | I915_WRITE(reg, val); | |
45187ace JB |
233 | |
234 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
235 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
236 | data++; | |
237 | } | |
238 | ||
bc2481f3 | 239 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 240 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 241 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 242 | |
22509ec8 | 243 | I915_WRITE(reg, val); |
45187ace | 244 | } |
90b107c8 SK |
245 | |
246 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
247 | struct dip_infoframe *frame) | |
248 | { | |
249 | uint32_t *data = (uint32_t *)frame; | |
250 | struct drm_device *dev = encoder->dev; | |
251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
252 | struct drm_crtc *crtc = encoder->crtc; | |
253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
254 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
255 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 256 | u32 val = I915_READ(reg); |
90b107c8 SK |
257 | |
258 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
259 | ||
90b107c8 | 260 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 261 | val |= g4x_infoframe_index(frame); |
22509ec8 | 262 | |
bc2481f3 | 263 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 264 | val |= VIDEO_DIP_ENABLE; |
90b107c8 | 265 | |
22509ec8 | 266 | I915_WRITE(reg, val); |
90b107c8 SK |
267 | |
268 | for (i = 0; i < len; i += 4) { | |
269 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
270 | data++; | |
271 | } | |
272 | ||
bc2481f3 | 273 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 274 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 275 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 276 | |
22509ec8 | 277 | I915_WRITE(reg, val); |
90b107c8 SK |
278 | } |
279 | ||
8c5f5f7c ED |
280 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
281 | struct dip_infoframe *frame) | |
282 | { | |
283 | /* Not implemented yet, so avoid doing anything at all. | |
284 | * This is the placeholder for Paulo Zanoni's infoframe writing patch | |
285 | */ | |
286 | DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n"); | |
287 | ||
288 | return; | |
289 | ||
290 | } | |
291 | ||
45187ace JB |
292 | static void intel_set_infoframe(struct drm_encoder *encoder, |
293 | struct dip_infoframe *frame) | |
294 | { | |
295 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
296 | ||
297 | if (!intel_hdmi->has_hdmi_sink) | |
298 | return; | |
299 | ||
300 | intel_dip_infoframe_csum(frame); | |
301 | intel_hdmi->write_infoframe(encoder, frame); | |
302 | } | |
303 | ||
c846b619 PZ |
304 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
305 | struct drm_display_mode *adjusted_mode) | |
45187ace JB |
306 | { |
307 | struct dip_infoframe avi_if = { | |
308 | .type = DIP_TYPE_AVI, | |
309 | .ver = DIP_VERSION_AVI, | |
310 | .len = DIP_LEN_AVI, | |
311 | }; | |
312 | ||
c846b619 PZ |
313 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
314 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
315 | ||
45187ace | 316 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
317 | } |
318 | ||
c0864cb3 JB |
319 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
320 | { | |
321 | struct dip_infoframe spd_if; | |
322 | ||
323 | memset(&spd_if, 0, sizeof(spd_if)); | |
324 | spd_if.type = DIP_TYPE_SPD; | |
325 | spd_if.ver = DIP_VERSION_SPD; | |
326 | spd_if.len = DIP_LEN_SPD; | |
327 | strcpy(spd_if.body.spd.vn, "Intel"); | |
328 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
329 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
330 | ||
331 | intel_set_infoframe(encoder, &spd_if); | |
332 | } | |
333 | ||
7d57382e EA |
334 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
335 | struct drm_display_mode *mode, | |
336 | struct drm_display_mode *adjusted_mode) | |
337 | { | |
338 | struct drm_device *dev = encoder->dev; | |
339 | struct drm_i915_private *dev_priv = dev->dev_private; | |
340 | struct drm_crtc *crtc = encoder->crtc; | |
341 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea5b213a | 342 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
343 | u32 sdvox; |
344 | ||
b599c0bc | 345 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
346 | if (!HAS_PCH_SPLIT(dev)) |
347 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
348 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
349 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
350 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
351 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 352 | |
020f6704 JB |
353 | if (intel_crtc->bpp > 24) |
354 | sdvox |= COLOR_FORMAT_12bpc; | |
355 | else | |
356 | sdvox |= COLOR_FORMAT_8bpc; | |
357 | ||
2e3d6006 ZW |
358 | /* Required on CPT */ |
359 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
360 | sdvox |= HDMI_MODE_SELECT; | |
361 | ||
3c17fe4b | 362 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
363 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
364 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 365 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 366 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 367 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 368 | } |
7d57382e | 369 | |
75770564 JB |
370 | if (HAS_PCH_CPT(dev)) |
371 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
372 | else if (intel_crtc->pipe == 1) | |
373 | sdvox |= SDVO_PIPE_B_SELECT; | |
7d57382e | 374 | |
ea5b213a CW |
375 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
376 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 377 | |
c846b619 | 378 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
c0864cb3 | 379 | intel_hdmi_set_spd_infoframe(encoder); |
7d57382e EA |
380 | } |
381 | ||
382 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
383 | { | |
384 | struct drm_device *dev = encoder->dev; | |
385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 386 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 387 | u32 temp; |
2deed761 WF |
388 | u32 enable_bits = SDVO_ENABLE; |
389 | ||
390 | if (intel_hdmi->has_audio) | |
391 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 392 | |
ea5b213a | 393 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
394 | |
395 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
396 | * we do this anyway which shows more stable in testing. | |
397 | */ | |
c619eed4 | 398 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
399 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
400 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
401 | } |
402 | ||
403 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 404 | temp &= ~enable_bits; |
7d57382e | 405 | } else { |
2deed761 | 406 | temp |= enable_bits; |
7d57382e | 407 | } |
d8a2d0e0 | 408 | |
ea5b213a CW |
409 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
410 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
411 | |
412 | /* HW workaround, need to write this twice for issue that may result | |
413 | * in first write getting masked. | |
414 | */ | |
c619eed4 | 415 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
416 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
417 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 418 | } |
7d57382e EA |
419 | } |
420 | ||
7d57382e EA |
421 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
422 | struct drm_display_mode *mode) | |
423 | { | |
424 | if (mode->clock > 165000) | |
425 | return MODE_CLOCK_HIGH; | |
426 | if (mode->clock < 20000) | |
5cbba41d | 427 | return MODE_CLOCK_LOW; |
7d57382e EA |
428 | |
429 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
430 | return MODE_NO_DBLESCAN; | |
431 | ||
432 | return MODE_OK; | |
433 | } | |
434 | ||
435 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
436 | struct drm_display_mode *mode, | |
437 | struct drm_display_mode *adjusted_mode) | |
438 | { | |
439 | return true; | |
440 | } | |
441 | ||
aa93d632 | 442 | static enum drm_connector_status |
930a9e28 | 443 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 444 | { |
df0e9248 | 445 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
446 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
447 | struct edid *edid; | |
aa93d632 | 448 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 449 | |
ea5b213a | 450 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 451 | intel_hdmi->has_audio = false; |
f899fc64 | 452 | edid = drm_get_edid(connector, |
3bd7d909 DK |
453 | intel_gmbus_get_adapter(dev_priv, |
454 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 455 | |
aa93d632 | 456 | if (edid) { |
be9f1c4f | 457 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 458 | status = connector_status_connected; |
b1d7e4b4 WF |
459 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
460 | intel_hdmi->has_hdmi_sink = | |
461 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 462 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 463 | } |
674e2d08 | 464 | connector->display_info.raw_edid = NULL; |
aa93d632 | 465 | kfree(edid); |
9dff6af8 | 466 | } |
30ad48b7 | 467 | |
55b7d6e8 | 468 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
469 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
470 | intel_hdmi->has_audio = | |
471 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
472 | } |
473 | ||
2ded9e27 | 474 | return status; |
7d57382e EA |
475 | } |
476 | ||
477 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
478 | { | |
df0e9248 | 479 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 480 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
481 | |
482 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
483 | * we can send audio to it. | |
484 | */ | |
485 | ||
f899fc64 | 486 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
487 | intel_gmbus_get_adapter(dev_priv, |
488 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
489 | } |
490 | ||
1aad7ac0 CW |
491 | static bool |
492 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
493 | { | |
494 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
495 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
496 | struct edid *edid; | |
497 | bool has_audio = false; | |
498 | ||
499 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
500 | intel_gmbus_get_adapter(dev_priv, |
501 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
502 | if (edid) { |
503 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
504 | has_audio = drm_detect_monitor_audio(edid); | |
505 | ||
506 | connector->display_info.raw_edid = NULL; | |
507 | kfree(edid); | |
508 | } | |
509 | ||
510 | return has_audio; | |
511 | } | |
512 | ||
55b7d6e8 CW |
513 | static int |
514 | intel_hdmi_set_property(struct drm_connector *connector, | |
515 | struct drm_property *property, | |
516 | uint64_t val) | |
517 | { | |
518 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 519 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
520 | int ret; |
521 | ||
522 | ret = drm_connector_property_set_value(connector, property, val); | |
523 | if (ret) | |
524 | return ret; | |
525 | ||
3f43c48d | 526 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 527 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
528 | bool has_audio; |
529 | ||
530 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
531 | return 0; |
532 | ||
1aad7ac0 | 533 | intel_hdmi->force_audio = i; |
55b7d6e8 | 534 | |
b1d7e4b4 | 535 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
536 | has_audio = intel_hdmi_detect_audio(connector); |
537 | else | |
b1d7e4b4 | 538 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 539 | |
b1d7e4b4 WF |
540 | if (i == HDMI_AUDIO_OFF_DVI) |
541 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 542 | |
1aad7ac0 | 543 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
544 | goto done; |
545 | } | |
546 | ||
e953fd7b CW |
547 | if (property == dev_priv->broadcast_rgb_property) { |
548 | if (val == !!intel_hdmi->color_range) | |
549 | return 0; | |
550 | ||
551 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
552 | goto done; | |
553 | } | |
554 | ||
55b7d6e8 CW |
555 | return -EINVAL; |
556 | ||
557 | done: | |
558 | if (intel_hdmi->base.base.crtc) { | |
559 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
560 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
561 | crtc->x, crtc->y, | |
562 | crtc->fb); | |
563 | } | |
564 | ||
565 | return 0; | |
566 | } | |
567 | ||
7d57382e EA |
568 | static void intel_hdmi_destroy(struct drm_connector *connector) |
569 | { | |
7d57382e EA |
570 | drm_sysfs_connector_remove(connector); |
571 | drm_connector_cleanup(connector); | |
674e2d08 | 572 | kfree(connector); |
7d57382e EA |
573 | } |
574 | ||
575 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
576 | .dpms = intel_hdmi_dpms, | |
577 | .mode_fixup = intel_hdmi_mode_fixup, | |
578 | .prepare = intel_encoder_prepare, | |
579 | .mode_set = intel_hdmi_mode_set, | |
580 | .commit = intel_encoder_commit, | |
581 | }; | |
582 | ||
583 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 584 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
585 | .detect = intel_hdmi_detect, |
586 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 587 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
588 | .destroy = intel_hdmi_destroy, |
589 | }; | |
590 | ||
591 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
592 | .get_modes = intel_hdmi_get_modes, | |
593 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 594 | .best_encoder = intel_best_encoder, |
7d57382e EA |
595 | }; |
596 | ||
7d57382e | 597 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 598 | .destroy = intel_encoder_destroy, |
7d57382e EA |
599 | }; |
600 | ||
55b7d6e8 CW |
601 | static void |
602 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
603 | { | |
3f43c48d | 604 | intel_attach_force_audio_property(connector); |
e953fd7b | 605 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
606 | } |
607 | ||
7d57382e EA |
608 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
609 | { | |
610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
611 | struct drm_connector *connector; | |
21d40d37 | 612 | struct intel_encoder *intel_encoder; |
674e2d08 | 613 | struct intel_connector *intel_connector; |
ea5b213a | 614 | struct intel_hdmi *intel_hdmi; |
64a8fc01 | 615 | int i; |
7d57382e | 616 | |
ea5b213a CW |
617 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
618 | if (!intel_hdmi) | |
7d57382e | 619 | return; |
674e2d08 ZW |
620 | |
621 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
622 | if (!intel_connector) { | |
ea5b213a | 623 | kfree(intel_hdmi); |
674e2d08 ZW |
624 | return; |
625 | } | |
626 | ||
ea5b213a | 627 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
628 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
629 | DRM_MODE_ENCODER_TMDS); | |
630 | ||
674e2d08 | 631 | connector = &intel_connector->base; |
7d57382e | 632 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 633 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
634 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
635 | ||
21d40d37 | 636 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 637 | |
eb1f8e4f | 638 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 639 | connector->interlace_allowed = 1; |
7d57382e | 640 | connector->doublescan_allowed = 0; |
27f8227b | 641 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
642 | |
643 | /* Set up the DDC bus. */ | |
f8aed700 | 644 | if (sdvox_reg == SDVOB) { |
21d40d37 | 645 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 646 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 647 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 648 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 649 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 650 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 651 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 652 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 653 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 654 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 655 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 656 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 657 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 658 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 659 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 660 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 661 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 662 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 663 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
f8aed700 | 664 | } |
7d57382e | 665 | |
ea5b213a | 666 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 667 | |
64a8fc01 | 668 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 669 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
64a8fc01 | 670 | I915_WRITE(VIDEO_DIP_CTL, 0); |
90b107c8 SK |
671 | } else if (IS_VALLEYVIEW(dev)) { |
672 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
673 | for_each_pipe(i) | |
674 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); | |
8c5f5f7c ED |
675 | } else if (IS_HASWELL(dev)) { |
676 | /* FIXME: Haswell has a new set of DIP frame registers, but we are | |
677 | * just doing the minimal required for HDMI to work at this stage. | |
678 | */ | |
679 | intel_hdmi->write_infoframe = hsw_write_infoframe; | |
680 | for_each_pipe(i) | |
681 | I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0); | |
fdf1250a PZ |
682 | } else if (HAS_PCH_IBX(dev)) { |
683 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
684 | for_each_pipe(i) | |
685 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
686 | } else { | |
687 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
64a8fc01 JB |
688 | for_each_pipe(i) |
689 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
690 | } | |
45187ace | 691 | |
4ef69c7a | 692 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
7d57382e | 693 | |
55b7d6e8 CW |
694 | intel_hdmi_add_properties(intel_hdmi, connector); |
695 | ||
df0e9248 | 696 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
697 | drm_sysfs_connector_add(connector); |
698 | ||
699 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
700 | * 0xd. Failure to do so will result in spurious interrupts being | |
701 | * generated on the port when a cable is not attached. | |
702 | */ | |
703 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
704 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
705 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
706 | } | |
7d57382e | 707 | } |