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drm/i915: Return the mask of enabled infoframes from ->inforame_enabled()
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_hdmi.c
CommitLineData
7d57382e
EA		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29#include <linux/i2c.h>
5a0e3ad6 30#include <linux/slab.h>
7d57382e 31#include <linux/delay.h>
178f736a 32#include <linux/hdmi.h>
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
2320175f 36#include <drm/drm_hdcp.h>
15953637 37#include <drm/drm_scdc_helper.h>
7d57382e 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
46d196ec 40#include <drm/intel_lpe_audio.h>
7d57382e
EA		 41#include "i915_drv.h"
42
30add22d
PZ		 43static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
44{
da63a9f2 45 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
30add22d
PZ		 46}
47
afba0188
DV		 48static void
49assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
50{
30add22d 51 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
fac5e23e 52 struct drm_i915_private *dev_priv = to_i915(dev);
faa087c4 53 u32 enabled_bits;
afba0188 54
4f8036a2 55 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
afba0188 56
b242b7f7 57 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
afba0188
DV		 58 "HDMI port enabled, expecting disabled\n");
59}
60
8fc0aa6e
ID		 61static void
62assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
63 enum transcoder cpu_transcoder)
64{
65 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
66 TRANS_DDI_FUNC_ENABLE,
67 "HDMI transcoder function enabled, expecting disabled\n");
68}
69
f5bbfca3 70struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
ea5b213a 71{
da63a9f2
PZ		 72 struct intel_digital_port *intel_dig_port =
73 container_of(encoder, struct intel_digital_port, base.base);
74 return &intel_dig_port->hdmi;
ea5b213a
CW		 75}
76
df0e9248
CW		 77static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
78{
da63a9f2 79 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
df0e9248
CW		 80}
81
1d776538 82static u32 g4x_infoframe_index(unsigned int type)
3c17fe4b 83{
178f736a 84 switch (type) {
5cb3c1a1
VS		 85 case HDMI_PACKET_TYPE_GAMUT_METADATA:
86 return VIDEO_DIP_SELECT_GAMUT;
178f736a 87 case HDMI_INFOFRAME_TYPE_AVI:
ed517fbb 88 return VIDEO_DIP_SELECT_AVI;
178f736a 89 case HDMI_INFOFRAME_TYPE_SPD:
ed517fbb 90 return VIDEO_DIP_SELECT_SPD;
c8bb75af
LD		 91 case HDMI_INFOFRAME_TYPE_VENDOR:
92 return VIDEO_DIP_SELECT_VENDOR;
45187ace 93 default:
ffc85dab 94 MISSING_CASE(type);
ed517fbb 95 return 0;
45187ace 96 }
45187ace
JB		 97}
98
1d776538 99static u32 g4x_infoframe_enable(unsigned int type)
45187ace 100{
178f736a 101 switch (type) {
5cb3c1a1
VS		 102 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
103 return VIDEO_DIP_ENABLE_GCP;
104 case HDMI_PACKET_TYPE_GAMUT_METADATA:
105 return VIDEO_DIP_ENABLE_GAMUT;
509efa2b
VS		 106 case DP_SDP_VSC:
107 return 0;
178f736a 108 case HDMI_INFOFRAME_TYPE_AVI:
ed517fbb 109 return VIDEO_DIP_ENABLE_AVI;
178f736a 110 case HDMI_INFOFRAME_TYPE_SPD:
ed517fbb 111 return VIDEO_DIP_ENABLE_SPD;
c8bb75af
LD		 112 case HDMI_INFOFRAME_TYPE_VENDOR:
113 return VIDEO_DIP_ENABLE_VENDOR;
fa193ff7 114 default:
ffc85dab 115 MISSING_CASE(type);
ed517fbb 116 return 0;
fa193ff7 117 }
fa193ff7
PZ		 118}
119
1d776538 120static u32 hsw_infoframe_enable(unsigned int type)
2da8af54 121{
178f736a 122 switch (type) {
5cb3c1a1
VS		 123 case HDMI_PACKET_TYPE_GENERAL_CONTROL:
124 return VIDEO_DIP_ENABLE_GCP_HSW;
125 case HDMI_PACKET_TYPE_GAMUT_METADATA:
126 return VIDEO_DIP_ENABLE_GMP_HSW;
1d776538
VS		 127 case DP_SDP_VSC:
128 return VIDEO_DIP_ENABLE_VSC_HSW;
4c614831
MN		 129 case DP_SDP_PPS:
130 return VDIP_ENABLE_PPS;
178f736a 131 case HDMI_INFOFRAME_TYPE_AVI:
2da8af54 132 return VIDEO_DIP_ENABLE_AVI_HSW;
178f736a 133 case HDMI_INFOFRAME_TYPE_SPD:
2da8af54 134 return VIDEO_DIP_ENABLE_SPD_HSW;
c8bb75af
LD		 135 case HDMI_INFOFRAME_TYPE_VENDOR:
136 return VIDEO_DIP_ENABLE_VS_HSW;
2da8af54 137 default:
ffc85dab 138 MISSING_CASE(type);
2da8af54
PZ		 139 return 0;
140 }
141}
142
f0f59a00
VS		 143static i915_reg_t
144hsw_dip_data_reg(struct drm_i915_private *dev_priv,
145 enum transcoder cpu_transcoder,
1d776538 146 unsigned int type,
f0f59a00 147 int i)
2da8af54 148{
178f736a 149 switch (type) {
5cb3c1a1
VS		 150 case HDMI_PACKET_TYPE_GAMUT_METADATA:
151 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
1d776538
VS		 152 case DP_SDP_VSC:
153 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
4c614831
MN		 154 case DP_SDP_PPS:
155 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
178f736a 156 case HDMI_INFOFRAME_TYPE_AVI:
436c6d4a 157 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
178f736a 158 case HDMI_INFOFRAME_TYPE_SPD:
436c6d4a 159 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
c8bb75af 160 case HDMI_INFOFRAME_TYPE_VENDOR:
436c6d4a 161 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
2da8af54 162 default:
ffc85dab 163 MISSING_CASE(type);
f0f59a00 164 return INVALID_MMIO_REG;
2da8af54
PZ		 165 }
166}
167
4c614831
MN		 168static int hsw_dip_data_size(unsigned int type)
169{
170 switch (type) {
171 case DP_SDP_VSC:
172 return VIDEO_DIP_VSC_DATA_SIZE;
173 case DP_SDP_PPS:
174 return VIDEO_DIP_PPS_DATA_SIZE;
175 default:
176 return VIDEO_DIP_DATA_SIZE;
177 }
178}
179
790ea70c 180static void g4x_write_infoframe(struct intel_encoder *encoder,
ac240288 181 const struct intel_crtc_state *crtc_state,
1d776538 182 unsigned int type,
fff63867 183 const void *frame, ssize_t len)
45187ace 184{
faa087c4 185 const u32 *data = frame;
790ea70c 186 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
22509ec8 187 u32 val = I915_READ(VIDEO_DIP_CTL);
178f736a 188 int i;
3c17fe4b 189
822974ae
PZ		 190 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
191
1d4f85ac 192 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 193 val |= g4x_infoframe_index(type);
22509ec8 194
178f736a 195 val &= ~g4x_infoframe_enable(type);
45187ace 196
22509ec8 197 I915_WRITE(VIDEO_DIP_CTL, val);
3c17fe4b 198
9d9740f0 199 mmiowb();
45187ace 200 for (i = 0; i < len; i += 4) {
3c17fe4b
DH		 201 I915_WRITE(VIDEO_DIP_DATA, *data);
202 data++;
203 }
adf00b26
PZ		 204 /* Write every possible data byte to force correct ECC calculation. */
205 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
206 I915_WRITE(VIDEO_DIP_DATA, 0);
9d9740f0 207 mmiowb();
3c17fe4b 208
178f736a 209 val |= g4x_infoframe_enable(type);
60c5ea2d 210 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 211 val |= VIDEO_DIP_FREQ_VSYNC;
45187ace 212
22509ec8 213 I915_WRITE(VIDEO_DIP_CTL, val);
9d9740f0 214 POSTING_READ(VIDEO_DIP_CTL);
3c17fe4b
DH		 215}
216
509efa2b 217static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
cda0aaaf 218 const struct intel_crtc_state *pipe_config)
e43823ec 219{
790ea70c 220 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
e43823ec
JB		 221 u32 val = I915_READ(VIDEO_DIP_CTL);
222
ec1dc603 223 if ((val & VIDEO_DIP_ENABLE) == 0)
509efa2b 224 return 0;
89a35ecd 225
790ea70c 226 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
509efa2b 227 return 0;
ec1dc603
VS		 228
229 return val & (VIDEO_DIP_ENABLE_AVI |
230 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
e43823ec
JB		 231}
232
790ea70c 233static void ibx_write_infoframe(struct intel_encoder *encoder,
ac240288 234 const struct intel_crtc_state *crtc_state,
1d776538 235 unsigned int type,
fff63867 236 const void *frame, ssize_t len)
fdf1250a 237{
faa087c4 238 const u32 *data = frame;
790ea70c 239 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ac240288 240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
f0f59a00 241 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
fdf1250a 242 u32 val = I915_READ(reg);
f0f59a00 243 int i;
fdf1250a 244
822974ae
PZ		 245 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
246
fdf1250a 247 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 248 val |= g4x_infoframe_index(type);
fdf1250a 249
178f736a 250 val &= ~g4x_infoframe_enable(type);
fdf1250a
PZ		 251
252 I915_WRITE(reg, val);
253
9d9740f0 254 mmiowb();
fdf1250a
PZ		 255 for (i = 0; i < len; i += 4) {
256 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
257 data++;
258 }
adf00b26
PZ		 259 /* Write every possible data byte to force correct ECC calculation. */
260 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
261 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
9d9740f0 262 mmiowb();
fdf1250a 263
178f736a 264 val |= g4x_infoframe_enable(type);
fdf1250a 265 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 266 val |= VIDEO_DIP_FREQ_VSYNC;
fdf1250a
PZ		 267
268 I915_WRITE(reg, val);
9d9740f0 269 POSTING_READ(reg);
fdf1250a
PZ		 270}
271
509efa2b 272static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
cda0aaaf 273 const struct intel_crtc_state *pipe_config)
e43823ec 274{
790ea70c 275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
cda0aaaf
VS		 276 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
277 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
e43823ec
JB		 278 u32 val = I915_READ(reg);
279
ec1dc603 280 if ((val & VIDEO_DIP_ENABLE) == 0)
509efa2b 281 return 0;
ec1dc603 282
790ea70c 283 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
509efa2b 284 return 0;
052f62f7 285
ec1dc603
VS		 286 return val & (VIDEO_DIP_ENABLE_AVI |
287 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
288 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
e43823ec
JB		 289}
290
790ea70c 291static void cpt_write_infoframe(struct intel_encoder *encoder,
ac240288 292 const struct intel_crtc_state *crtc_state,
1d776538 293 unsigned int type,
fff63867 294 const void *frame, ssize_t len)
b055c8f3 295{
faa087c4 296 const u32 *data = frame;
790ea70c 297 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ac240288 298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
f0f59a00 299 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
22509ec8 300 u32 val = I915_READ(reg);
f0f59a00 301 int i;
b055c8f3 302
822974ae
PZ		 303 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
304
64a8fc01 305 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 306 val |= g4x_infoframe_index(type);
45187ace 307
ecb97851
PZ		 308 /* The DIP control register spec says that we need to update the AVI
309 * infoframe without clearing its enable bit */
178f736a
DL		 310 if (type != HDMI_INFOFRAME_TYPE_AVI)
311 val &= ~g4x_infoframe_enable(type);
ecb97851 312
22509ec8 313 I915_WRITE(reg, val);
45187ace 314
9d9740f0 315 mmiowb();
45187ace 316 for (i = 0; i < len; i += 4) {
b055c8f3
JB		 317 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
318 data++;
319 }
adf00b26
PZ		 320 /* Write every possible data byte to force correct ECC calculation. */
321 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
322 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
9d9740f0 323 mmiowb();
b055c8f3 324
178f736a 325 val |= g4x_infoframe_enable(type);
60c5ea2d 326 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 327 val |= VIDEO_DIP_FREQ_VSYNC;
45187ace 328
22509ec8 329 I915_WRITE(reg, val);
9d9740f0 330 POSTING_READ(reg);
45187ace 331}
90b107c8 332
509efa2b 333static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
cda0aaaf 334 const struct intel_crtc_state *pipe_config)
e43823ec 335{
790ea70c 336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
cda0aaaf
VS		 337 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
338 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
e43823ec 339
ec1dc603 340 if ((val & VIDEO_DIP_ENABLE) == 0)
509efa2b 341 return 0;
ec1dc603
VS		 342
343 return val & (VIDEO_DIP_ENABLE_AVI |
344 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
345 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
e43823ec
JB		 346}
347
790ea70c 348static void vlv_write_infoframe(struct intel_encoder *encoder,
ac240288 349 const struct intel_crtc_state *crtc_state,
1d776538 350 unsigned int type,
fff63867 351 const void *frame, ssize_t len)
90b107c8 352{
faa087c4 353 const u32 *data = frame;
790ea70c 354 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ac240288 355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
f0f59a00 356 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
22509ec8 357 u32 val = I915_READ(reg);
f0f59a00 358 int i;
90b107c8 359
822974ae
PZ		 360 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
361
90b107c8 362 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
178f736a 363 val |= g4x_infoframe_index(type);
22509ec8 364
178f736a 365 val &= ~g4x_infoframe_enable(type);
90b107c8 366
22509ec8 367 I915_WRITE(reg, val);
90b107c8 368
9d9740f0 369 mmiowb();
90b107c8
SK		 370 for (i = 0; i < len; i += 4) {
371 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
372 data++;
373 }
adf00b26
PZ		 374 /* Write every possible data byte to force correct ECC calculation. */
375 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
376 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
9d9740f0 377 mmiowb();
90b107c8 378
178f736a 379 val |= g4x_infoframe_enable(type);
60c5ea2d 380 val &= ~VIDEO_DIP_FREQ_MASK;
4b24c933 381 val |= VIDEO_DIP_FREQ_VSYNC;
90b107c8 382
22509ec8 383 I915_WRITE(reg, val);
9d9740f0 384 POSTING_READ(reg);
90b107c8
SK		 385}
386
509efa2b 387static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
cda0aaaf 388 const struct intel_crtc_state *pipe_config)
e43823ec 389{
790ea70c 390 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
cda0aaaf
VS		 391 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
392 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
e43823ec 393
ec1dc603 394 if ((val & VIDEO_DIP_ENABLE) == 0)
509efa2b 395 return 0;
ec1dc603 396
790ea70c 397 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
509efa2b 398 return 0;
535afa2e 399
ec1dc603
VS		 400 return val & (VIDEO_DIP_ENABLE_AVI |
401 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
402 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
e43823ec
JB		 403}
404
790ea70c 405static void hsw_write_infoframe(struct intel_encoder *encoder,
ac240288 406 const struct intel_crtc_state *crtc_state,
1d776538 407 unsigned int type,
fff63867 408 const void *frame, ssize_t len)
8c5f5f7c 409{
faa087c4 410 const u32 *data = frame;
790ea70c 411 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ac240288 412 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
f0f59a00 413 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
4c614831 414 int data_size;
178f736a 415 int i;
2da8af54 416 u32 val = I915_READ(ctl_reg);
8c5f5f7c 417
4c614831
MN		 418 data_size = hsw_dip_data_size(type);
419
178f736a 420 val &= ~hsw_infoframe_enable(type);
2da8af54
PZ		 421 I915_WRITE(ctl_reg, val);
422
9d9740f0 423 mmiowb();
2da8af54 424 for (i = 0; i < len; i += 4) {
436c6d4a
VS		 425 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
426 type, i >> 2), *data);
2da8af54
PZ		 427 data++;
428 }
adf00b26 429 /* Write every possible data byte to force correct ECC calculation. */
1d776538 430 for (; i < data_size; i += 4)
436c6d4a
VS		 431 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
432 type, i >> 2), 0);
9d9740f0 433 mmiowb();
8c5f5f7c 434
178f736a 435 val |= hsw_infoframe_enable(type);
2da8af54 436 I915_WRITE(ctl_reg, val);
9d9740f0 437 POSTING_READ(ctl_reg);
8c5f5f7c
ED		 438}
439
509efa2b 440static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
cda0aaaf 441 const struct intel_crtc_state *pipe_config)
e43823ec 442{
790ea70c 443 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
cda0aaaf 444 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
e43823ec 445
ec1dc603
VS		 446 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
447 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
448 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
e43823ec
JB		 449}
450
509efa2b
VS		 451static const u8 infoframe_type_to_idx[] = {
452 HDMI_PACKET_TYPE_GENERAL_CONTROL,
453 HDMI_PACKET_TYPE_GAMUT_METADATA,
454 DP_SDP_VSC,
455 HDMI_INFOFRAME_TYPE_AVI,
456 HDMI_INFOFRAME_TYPE_SPD,
457 HDMI_INFOFRAME_TYPE_VENDOR,
458};
459
460u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
461 const struct intel_crtc_state *crtc_state)
462{
463 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
464 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
465 u32 val, ret = 0;
466 int i;
467
468 val = dig_port->infoframes_enabled(encoder, crtc_state);
469
470 /* map from hardware bits to dip idx */
471 for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
472 unsigned int type = infoframe_type_to_idx[i];
473
474 if (HAS_DDI(dev_priv)) {
475 if (val & hsw_infoframe_enable(type))
476 ret |= BIT(i);
477 } else {
478 if (val & g4x_infoframe_enable(type))
479 ret |= BIT(i);
480 }
481 }
482
483 return ret;
484}
485
5adaea79
DL		 486/*
487 * The data we write to the DIP data buffer registers is 1 byte bigger than the
488 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
489 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
490 * used for both technologies.
491 *
492 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
493 * DW1: DB3 | DB2 | DB1 | DB0
494 * DW2: DB7 | DB6 | DB5 | DB4
495 * DW3: ...
496 *
497 * (HB is Header Byte, DB is Data Byte)
498 *
499 * The hdmi pack() functions don't know about that hardware specific hole so we
500 * trick them by giving an offset into the buffer and moving back the header
501 * bytes by one.
502 */
790ea70c 503static void intel_write_infoframe(struct intel_encoder *encoder,
ac240288 504 const struct intel_crtc_state *crtc_state,
9198ee5b 505 union hdmi_infoframe *frame)
45187ace 506{
790ea70c 507 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
faa087c4 508 u8 buffer[VIDEO_DIP_DATA_SIZE];
5adaea79 509 ssize_t len;
45187ace 510
5adaea79
DL		 511 /* see comment above for the reason for this offset */
512 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
513 if (len < 0)
514 return;
515
516 /* Insert the 'hole' (see big comment above) at position 3 */
121f0ff5 517 memmove(&buffer[0], &buffer[1], 3);
5adaea79
DL		 518 buffer[3] = 0;
519 len++;
45187ace 520
790ea70c
VS		 521 intel_dig_port->write_infoframe(encoder,
522 crtc_state,
523 frame->any.type, buffer, len);
45187ace
JB		 524}
525
790ea70c 526static void intel_hdmi_set_avi_infoframe(struct intel_encoder *encoder,
6553b123
SL		 527 const struct intel_crtc_state *crtc_state,
528 const struct drm_connector_state *conn_state)
45187ace 529{
779c4c28
VS		 530 const struct drm_display_mode *adjusted_mode =
531 &crtc_state->base.adjusted_mode;
5adaea79
DL		 532 union hdmi_infoframe frame;
533 int ret;
45187ace 534
5adaea79 535 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
13d0add3
VS		 536 conn_state->connector,
537 adjusted_mode);
5adaea79
DL		 538 if (ret < 0) {
539 DRM_ERROR("couldn't fill AVI infoframe\n");
540 return;
541 }
c846b619 542
33b7f3ee 543 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2d8bd2bf 544 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
8c79f844
SS		 545 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
546 frame.avi.colorspace = HDMI_COLORSPACE_YUV444;
2d8bd2bf
SS		 547 else
548 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
549
13d0add3
VS		 550 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
551 conn_state->connector,
552 adjusted_mode,
a2ce26f8
VS		 553 crtc_state->limited_color_range ?
554 HDMI_QUANTIZATION_RANGE_LIMITED :
1581b2df 555 HDMI_QUANTIZATION_RANGE_FULL);
abedc077 556
6553b123
SL		 557 drm_hdmi_avi_infoframe_content_type(&frame.avi,
558 conn_state);
559
2d8bd2bf 560 /* TODO: handle pixel repetition for YCBCR420 outputs */
790ea70c
VS		 561 intel_write_infoframe(encoder, crtc_state,
562 &frame);
b055c8f3
JB		 563}
564
790ea70c 565static void intel_hdmi_set_spd_infoframe(struct intel_encoder *encoder,
ac240288 566 const struct intel_crtc_state *crtc_state)
c0864cb3 567{
5adaea79
DL		 568 union hdmi_infoframe frame;
569 int ret;
570
571 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
572 if (ret < 0) {
573 DRM_ERROR("couldn't fill SPD infoframe\n");
574 return;
575 }
c0864cb3 576
5adaea79 577 frame.spd.sdi = HDMI_SPD_SDI_PC;
c0864cb3 578
790ea70c
VS		 579 intel_write_infoframe(encoder, crtc_state,
580 &frame);
c0864cb3
JB		 581}
582
c8bb75af 583static void
790ea70c 584intel_hdmi_set_hdmi_infoframe(struct intel_encoder *encoder,
f1781e9b
VS		 585 const struct intel_crtc_state *crtc_state,
586 const struct drm_connector_state *conn_state)
c8bb75af
LD		 587{
588 union hdmi_infoframe frame;
589 int ret;
590
591 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
f1781e9b 592 conn_state->connector,
ac240288 593 &crtc_state->base.adjusted_mode);
c8bb75af
LD		 594 if (ret < 0)
595 return;
596
790ea70c
VS		 597 intel_write_infoframe(encoder, crtc_state,
598 &frame);
c8bb75af
LD		 599}
600
790ea70c 601static void g4x_set_infoframes(struct intel_encoder *encoder,
6897b4b5 602 bool enable,
ac240288
ML		 603 const struct intel_crtc_state *crtc_state,
604 const struct drm_connector_state *conn_state)
687f4d06 605{
790ea70c
VS		 606 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
607 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
69fde0a6 608 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
f0f59a00 609 i915_reg_t reg = VIDEO_DIP_CTL;
0c14c7f9 610 u32 val = I915_READ(reg);
790ea70c 611 u32 port = VIDEO_DIP_PORT(encoder->port);
0c14c7f9 612
afba0188
DV		 613 assert_hdmi_port_disabled(intel_hdmi);
614
0c14c7f9
PZ		 615 /* If the registers were not initialized yet, they might be zeroes,
616 * which means we're selecting the AVI DIP and we're setting its
617 * frequency to once. This seems to really confuse the HW and make
618 * things stop working (the register spec says the AVI always needs to
619 * be sent every VSync). So here we avoid writing to the register more
620 * than we need and also explicitly select the AVI DIP and explicitly
621 * set its frequency to every VSync. Avoiding to write it twice seems to
622 * be enough to solve the problem, but being defensive shouldn't hurt us
623 * either. */
624 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
625
6897b4b5 626 if (!enable) {
0c14c7f9
PZ		 627 if (!(val & VIDEO_DIP_ENABLE))
628 return;
0be6f0c8
VS		 629 if (port != (val & VIDEO_DIP_PORT_MASK)) {
630 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
631 (val & VIDEO_DIP_PORT_MASK) >> 29);
632 return;
633 }
634 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
635 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
0c14c7f9 636 I915_WRITE(reg, val);
9d9740f0 637 POSTING_READ(reg);
0c14c7f9
PZ		 638 return;
639 }
640
72b78c9d
PZ		 641 if (port != (val & VIDEO_DIP_PORT_MASK)) {
642 if (val & VIDEO_DIP_ENABLE) {
0be6f0c8
VS		 643 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
644 (val & VIDEO_DIP_PORT_MASK) >> 29);
645 return;
72b78c9d
PZ		 646 }
647 val &= ~VIDEO_DIP_PORT_MASK;
648 val |= port;
649 }
650
822974ae 651 val |= VIDEO_DIP_ENABLE;
0be6f0c8
VS		 652 val &= ~(VIDEO_DIP_ENABLE_AVI |
653 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
822974ae 654
f278d972 655 I915_WRITE(reg, val);
9d9740f0 656 POSTING_READ(reg);
f278d972 657
6553b123 658 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
ac240288 659 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
f1781e9b 660 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
687f4d06
PZ		 661}
662
ac240288 663static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
6d67415f 664{
ac240288 665 struct drm_connector *connector = conn_state->connector;
6d67415f
VS		 666
667 /*
668 * HDMI cloning is only supported on g4x which doesn't
669 * support deep color or GCP infoframes anyway so no
670 * need to worry about multiple HDMI sinks here.
671 */
6d67415f 672
ac240288 673 return connector->display_info.bpc > 8;
6d67415f
VS		 674}
675
12aa3290
VS		 676/*
677 * Determine if default_phase=1 can be indicated in the GCP infoframe.
678 *
679 * From HDMI specification 1.4a:
680 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
681 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
682 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
683 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
684 * phase of 0
685 */
686static bool gcp_default_phase_possible(int pipe_bpp,
687 const struct drm_display_mode *mode)
688{
689 unsigned int pixels_per_group;
690
691 switch (pipe_bpp) {
692 case 30:
693 /* 4 pixels in 5 clocks */
694 pixels_per_group = 4;
695 break;
696 case 36:
697 /* 2 pixels in 3 clocks */
698 pixels_per_group = 2;
699 break;
700 case 48:
701 /* 1 pixel in 2 clocks */
702 pixels_per_group = 1;
703 break;
704 default:
705 /* phase information not relevant for 8bpc */
706 return false;
707 }
708
709 return mode->crtc_hdisplay % pixels_per_group == 0 &&
710 mode->crtc_htotal % pixels_per_group == 0 &&
711 mode->crtc_hblank_start % pixels_per_group == 0 &&
712 mode->crtc_hblank_end % pixels_per_group == 0 &&
713 mode->crtc_hsync_start % pixels_per_group == 0 &&
714 mode->crtc_hsync_end % pixels_per_group == 0 &&
715 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
716 mode->crtc_htotal/2 % pixels_per_group == 0);
717}
718
790ea70c 719static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
ac240288
ML		 720 const struct intel_crtc_state *crtc_state,
721 const struct drm_connector_state *conn_state)
6d67415f 722{
790ea70c 723 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ac240288 724 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
f0f59a00
VS		 725 i915_reg_t reg;
726 u32 val = 0;
6d67415f
VS		 727
728 if (HAS_DDI(dev_priv))
ac240288 729 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
666a4537 730 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6d67415f 731 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
2d1fe073 732 else if (HAS_PCH_SPLIT(dev_priv))
6d67415f
VS		 733 reg = TVIDEO_DIP_GCP(crtc->pipe);
734 else
735 return false;
736
737 /* Indicate color depth whenever the sink supports deep color */
ac240288 738 if (hdmi_sink_is_deep_color(conn_state))
6d67415f
VS		 739 val |= GCP_COLOR_INDICATION;
740
12aa3290 741 /* Enable default_phase whenever the display mode is suitably aligned */
ac240288
ML		 742 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
743 &crtc_state->base.adjusted_mode))
12aa3290
VS		 744 val |= GCP_DEFAULT_PHASE_ENABLE;
745
6d67415f
VS		 746 I915_WRITE(reg, val);
747
748 return val != 0;
749}
750
790ea70c 751static void ibx_set_infoframes(struct intel_encoder *encoder,
6897b4b5 752 bool enable,
ac240288
ML		 753 const struct intel_crtc_state *crtc_state,
754 const struct drm_connector_state *conn_state)
687f4d06 755{
790ea70c 756 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ac240288 757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
790ea70c 758 struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base);
69fde0a6 759 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
f0f59a00 760 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
0c14c7f9 761 u32 val = I915_READ(reg);
790ea70c 762 u32 port = VIDEO_DIP_PORT(encoder->port);
0c14c7f9 763
afba0188
DV		 764 assert_hdmi_port_disabled(intel_hdmi);
765
0c14c7f9
PZ		 766 /* See the big comment in g4x_set_infoframes() */
767 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
768
6897b4b5 769 if (!enable) {
0c14c7f9
PZ		 770 if (!(val & VIDEO_DIP_ENABLE))
771 return;
0be6f0c8
VS		 772 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
773 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
774 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
0c14c7f9 775 I915_WRITE(reg, val);
9d9740f0 776 POSTING_READ(reg);
0c14c7f9
PZ		 777 return;
778 }
779
72b78c9d 780 if (port != (val & VIDEO_DIP_PORT_MASK)) {
0be6f0c8
VS		 781 WARN(val & VIDEO_DIP_ENABLE,
782 "DIP already enabled on port %c\n",
783 (val & VIDEO_DIP_PORT_MASK) >> 29);
72b78c9d
PZ		 784 val &= ~VIDEO_DIP_PORT_MASK;
785 val |= port;
786 }
787
822974ae 788 val |= VIDEO_DIP_ENABLE;
0be6f0c8
VS		 789 val &= ~(VIDEO_DIP_ENABLE_AVI |
790 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
791 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
822974ae 792
ac240288 793 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
6d67415f
VS		 794 val |= VIDEO_DIP_ENABLE_GCP;
795
f278d972 796 I915_WRITE(reg, val);
9d9740f0 797 POSTING_READ(reg);
f278d972 798
6553b123 799 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
ac240288 800 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
f1781e9b 801 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
687f4d06
PZ		 802}
803
790ea70c 804static void cpt_set_infoframes(struct intel_encoder *encoder,
6897b4b5 805 bool enable,
ac240288
ML		 806 const struct intel_crtc_state *crtc_state,
807 const struct drm_connector_state *conn_state)
687f4d06 808{
790ea70c 809 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ac240288 810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
790ea70c 811 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
f0f59a00 812 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
0c14c7f9
PZ		 813 u32 val = I915_READ(reg);
814
afba0188
DV		 815 assert_hdmi_port_disabled(intel_hdmi);
816
0c14c7f9
PZ		 817 /* See the big comment in g4x_set_infoframes() */
818 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
819
6897b4b5 820 if (!enable) {
0c14c7f9
PZ		 821 if (!(val & VIDEO_DIP_ENABLE))
822 return;
0be6f0c8
VS		 823 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
824 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
825 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
0c14c7f9 826 I915_WRITE(reg, val);
9d9740f0 827 POSTING_READ(reg);
0c14c7f9
PZ		 828 return;
829 }
830
822974ae
PZ		 831 /* Set both together, unset both together: see the spec. */
832 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
0dd87d20 833 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
0be6f0c8 834 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
822974ae 835
ac240288 836 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
6d67415f
VS		 837 val |= VIDEO_DIP_ENABLE_GCP;
838
822974ae 839 I915_WRITE(reg, val);
9d9740f0 840 POSTING_READ(reg);
822974ae 841
6553b123 842 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
ac240288 843 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
f1781e9b 844 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
687f4d06
PZ		 845}
846
790ea70c 847static void vlv_set_infoframes(struct intel_encoder *encoder,
6897b4b5 848 bool enable,
ac240288
ML		 849 const struct intel_crtc_state *crtc_state,
850 const struct drm_connector_state *conn_state)
687f4d06 851{
790ea70c 852 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ac240288 853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
790ea70c 854 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
f0f59a00 855 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
0c14c7f9 856 u32 val = I915_READ(reg);
790ea70c 857 u32 port = VIDEO_DIP_PORT(encoder->port);
0c14c7f9 858
afba0188
DV		 859 assert_hdmi_port_disabled(intel_hdmi);
860
0c14c7f9
PZ		 861 /* See the big comment in g4x_set_infoframes() */
862 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
863
6897b4b5 864 if (!enable) {
0c14c7f9
PZ		 865 if (!(val & VIDEO_DIP_ENABLE))
866 return;
0be6f0c8
VS		 867 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
868 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
869 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
0c14c7f9 870 I915_WRITE(reg, val);
9d9740f0 871 POSTING_READ(reg);
0c14c7f9
PZ		 872 return;
873 }
874
6a2b8021 875 if (port != (val & VIDEO_DIP_PORT_MASK)) {
0be6f0c8
VS		 876 WARN(val & VIDEO_DIP_ENABLE,
877 "DIP already enabled on port %c\n",
878 (val & VIDEO_DIP_PORT_MASK) >> 29);
6a2b8021
JB		 879 val &= ~VIDEO_DIP_PORT_MASK;
880 val |= port;
881 }
882
822974ae 883 val |= VIDEO_DIP_ENABLE;
0be6f0c8
VS		 884 val &= ~(VIDEO_DIP_ENABLE_AVI |
885 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
886 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
822974ae 887
ac240288 888 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
6d67415f
VS		 889 val |= VIDEO_DIP_ENABLE_GCP;
890
822974ae 891 I915_WRITE(reg, val);
9d9740f0 892 POSTING_READ(reg);
822974ae 893
6553b123 894 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
ac240288 895 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
f1781e9b 896 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
687f4d06
PZ		 897}
898
790ea70c 899static void hsw_set_infoframes(struct intel_encoder *encoder,
6897b4b5 900 bool enable,
ac240288
ML		 901 const struct intel_crtc_state *crtc_state,
902 const struct drm_connector_state *conn_state)
687f4d06 903{
790ea70c 904 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
ac240288 905 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
0dd87d20 906 u32 val = I915_READ(reg);
0c14c7f9 907
8fc0aa6e
ID		 908 assert_hdmi_transcoder_func_disabled(dev_priv,
909 crtc_state->cpu_transcoder);
afba0188 910
0be6f0c8
VS		 911 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
912 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
913 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
914
6897b4b5 915 if (!enable) {
0be6f0c8 916 I915_WRITE(reg, val);
9d9740f0 917 POSTING_READ(reg);
0c14c7f9
PZ		 918 return;
919 }
920
ac240288 921 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
6d67415f
VS		 922 val |= VIDEO_DIP_ENABLE_GCP_HSW;
923
0dd87d20 924 I915_WRITE(reg, val);
9d9740f0 925 POSTING_READ(reg);
0dd87d20 926
6553b123 927 intel_hdmi_set_avi_infoframe(encoder, crtc_state, conn_state);
ac240288 928 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
f1781e9b 929 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
687f4d06
PZ		 930}
931
b2ccb822
VS		 932void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
933{
934 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
935 struct i2c_adapter *adapter =
936 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
937
938 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
939 return;
940
941 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
942 enable ? "Enabling" : "Disabling");
943
944 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
945 adapter, enable);
946}
947
2320175f
SP		 948static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port,
949 unsigned int offset, void *buffer, size_t size)
950{
951 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
952 struct drm_i915_private *dev_priv =
953 intel_dig_port->base.base.dev->dev_private;
954 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
955 hdmi->ddc_bus);
956 int ret;
957 u8 start = offset & 0xff;
958 struct i2c_msg msgs[] = {
959 {
960 .addr = DRM_HDCP_DDC_ADDR,
961 .flags = 0,
962 .len = 1,
963 .buf = &start,
964 },
965 {
966 .addr = DRM_HDCP_DDC_ADDR,
967 .flags = I2C_M_RD,
968 .len = size,
969 .buf = buffer
970 }
971 };
972 ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
973 if (ret == ARRAY_SIZE(msgs))
974 return 0;
975 return ret >= 0 ? -EIO : ret;
976}
977
978static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port,
979 unsigned int offset, void *buffer, size_t size)
980{
981 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
982 struct drm_i915_private *dev_priv =
983 intel_dig_port->base.base.dev->dev_private;
984 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
985 hdmi->ddc_bus);
986 int ret;
987 u8 *write_buf;
988 struct i2c_msg msg;
989
990 write_buf = kzalloc(size + 1, GFP_KERNEL);
991 if (!write_buf)
992 return -ENOMEM;
993
994 write_buf[0] = offset & 0xff;
995 memcpy(&write_buf[1], buffer, size);
996
997 msg.addr = DRM_HDCP_DDC_ADDR;
998 msg.flags = 0,
999 msg.len = size + 1,
1000 msg.buf = write_buf;
1001
1002 ret = i2c_transfer(adapter, &msg, 1);
1003 if (ret == 1)
1b1b1162
RV		 1004 ret = 0;
1005 else if (ret >= 0)
1006 ret = -EIO;
1007
1008 kfree(write_buf);
1009 return ret;
2320175f
SP		 1010}
1011
1012static
1013int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
1014 u8 *an)
1015{
1016 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1017 struct drm_i915_private *dev_priv =
1018 intel_dig_port->base.base.dev->dev_private;
1019 struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv,
1020 hdmi->ddc_bus);
1021 int ret;
1022
1023 ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an,
1024 DRM_HDCP_AN_LEN);
1025 if (ret) {
3aae21fc 1026 DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret);
2320175f
SP		 1027 return ret;
1028 }
1029
1030 ret = intel_gmbus_output_aksv(adapter);
1031 if (ret < 0) {
3aae21fc 1032 DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret);
2320175f
SP		 1033 return ret;
1034 }
1035 return 0;
1036}
1037
1038static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
1039 u8 *bksv)
1040{
1041 int ret;
1042 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv,
1043 DRM_HDCP_KSV_LEN);
1044 if (ret)
3aae21fc 1045 DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret);
2320175f
SP		 1046 return ret;
1047}
1048
1049static
1050int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
1051 u8 *bstatus)
1052{
1053 int ret;
1054 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS,
1055 bstatus, DRM_HDCP_BSTATUS_LEN);
1056 if (ret)
3aae21fc 1057 DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret);
2320175f
SP		 1058 return ret;
1059}
1060
1061static
1062int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
1063 bool *repeater_present)
1064{
1065 int ret;
1066 u8 val;
1067
1068 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1069 if (ret) {
3aae21fc 1070 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
2320175f
SP		 1071 return ret;
1072 }
1073 *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1074 return 0;
1075}
1076
1077static
1078int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
1079 u8 *ri_prime)
1080{
1081 int ret;
1082 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME,
1083 ri_prime, DRM_HDCP_RI_LEN);
1084 if (ret)
3aae21fc 1085 DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret);
2320175f
SP		 1086 return ret;
1087}
1088
1089static
1090int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
1091 bool *ksv_ready)
1092{
1093 int ret;
1094 u8 val;
1095
1096 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1097 if (ret) {
3aae21fc 1098 DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret);
2320175f
SP		 1099 return ret;
1100 }
1101 *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1102 return 0;
1103}
1104
1105static
1106int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
1107 int num_downstream, u8 *ksv_fifo)
1108{
1109 int ret;
1110 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO,
1111 ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1112 if (ret) {
3aae21fc 1113 DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret);
2320175f
SP		 1114 return ret;
1115 }
1116 return 0;
1117}
1118
1119static
1120int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
1121 int i, u32 *part)
1122{
1123 int ret;
1124
1125 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1126 return -EINVAL;
1127
1128 ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i),
1129 part, DRM_HDCP_V_PRIME_PART_LEN);
1130 if (ret)
3aae21fc 1131 DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret);
2320175f
SP		 1132 return ret;
1133}
1134
7412826c
R		 1135static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1136{
1137 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1138 struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector);
1139 struct drm_crtc *crtc = connector->base.state->crtc;
1140 struct intel_crtc *intel_crtc = container_of(crtc,
1141 struct intel_crtc, base);
1142 u32 scanline;
1143 int ret;
1144
1145 for (;;) {
1146 scanline = I915_READ(PIPEDSL(intel_crtc->pipe));
1147 if (scanline > 100 && scanline < 200)
1148 break;
1149 usleep_range(25, 50);
1150 }
1151
1152 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false);
1153 if (ret) {
1154 DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret);
1155 return ret;
1156 }
1157 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true);
1158 if (ret) {
1159 DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret);
1160 return ret;
1161 }
1162
1163 return 0;
1164}
1165
2320175f
SP		 1166static
1167int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
1168 bool enable)
1169{
7412826c
R		 1170 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1171 struct intel_connector *connector = hdmi->attached_connector;
1172 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
2320175f
SP		 1173 int ret;
1174
1175 if (!enable)
1176 usleep_range(6, 60); /* Bspec says >= 6us */
1177
1178 ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable);
1179 if (ret) {
1180 DRM_ERROR("%s HDCP signalling failed (%d)\n",
1181 enable ? "Enable" : "Disable", ret);
1182 return ret;
1183 }
7412826c
R		 1184
1185 /*
1186 * WA: To fix incorrect positioning of the window of
1187 * opportunity and enc_en signalling in KABYLAKE.
1188 */
1189 if (IS_KABYLAKE(dev_priv) && enable)
1190 return kbl_repositioning_enc_en_signal(connector);
1191
2320175f
SP		 1192 return 0;
1193}
1194
1195static
1196bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
1197{
1198 struct drm_i915_private *dev_priv =
1199 intel_dig_port->base.base.dev->dev_private;
1200 enum port port = intel_dig_port->base.port;
1201 int ret;
1202 union {
1203 u32 reg;
1204 u8 shim[DRM_HDCP_RI_LEN];
1205 } ri;
1206
1207 ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim);
1208 if (ret)
1209 return false;
1210
1211 I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg);
1212
1213 /* Wait for Ri prime match */
1214 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) &
1215 (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1216 DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
1217 I915_READ(PORT_HDCP_STATUS(port)));
1218 return false;
1219 }
1220 return true;
1221}
1222
2d4254e5
R		 1223static struct hdcp2_hdmi_msg_data {
1224 u8 msg_id;
1225 u32 timeout;
1226 u32 timeout2;
1227 } hdcp2_msg_data[] = {
1228 {HDCP_2_2_AKE_INIT, 0, 0},
1229 {HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0},
1230 {HDCP_2_2_AKE_NO_STORED_KM, 0, 0},
1231 {HDCP_2_2_AKE_STORED_KM, 0, 0},
1232 {HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
1233 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS},
1234 {HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS,
1235 0},
1236 {HDCP_2_2_LC_INIT, 0, 0},
1237 {HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0},
1238 {HDCP_2_2_SKE_SEND_EKS, 0, 0},
1239 {HDCP_2_2_REP_SEND_RECVID_LIST,
1240 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0},
1241 {HDCP_2_2_REP_SEND_ACK, 0, 0},
1242 {HDCP_2_2_REP_STREAM_MANAGE, 0, 0},
1243 {HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS,
1244 0},
1245 };
1246
1247static
1248int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port,
1249 uint8_t *rx_status)
1250{
1251 return intel_hdmi_hdcp_read(intel_dig_port,
1252 HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1253 rx_status,
1254 HDCP_2_2_HDMI_RXSTATUS_LEN);
1255}
1256
1257static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1258{
1259 int i;
1260
1261 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++)
1262 if (hdcp2_msg_data[i].msg_id == msg_id &&
1263 (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired))
1264 return hdcp2_msg_data[i].timeout;
1265 else if (hdcp2_msg_data[i].msg_id == msg_id)
1266 return hdcp2_msg_data[i].timeout2;
1267
1268 return -EINVAL;
1269}
1270
1271static inline
1272int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port,
1273 u8 msg_id, bool *msg_ready,
1274 ssize_t *msg_sz)
1275{
1276 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1277 int ret;
1278
1279 ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status);
1280 if (ret < 0) {
1281 DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret);
1282 return ret;
1283 }
1284
1285 *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1286 rx_status[0]);
1287
1288 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1289 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1290 *msg_sz);
1291 else
1292 *msg_ready = *msg_sz;
1293
1294 return 0;
1295}
1296
1297static ssize_t
1298intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port,
1299 u8 msg_id, bool paired)
1300{
1301 bool msg_ready = false;
1302 int timeout, ret;
1303 ssize_t msg_sz = 0;
1304
1305 timeout = get_hdcp2_msg_timeout(msg_id, paired);
1306 if (timeout < 0)
1307 return timeout;
1308
1309 ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port,
1310 msg_id, &msg_ready,
1311 &msg_sz),
1312 !ret && msg_ready && msg_sz, timeout * 1000,
1313 1000, 5 * 1000);
1314 if (ret)
1315 DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n",
1316 msg_id, ret, timeout);
1317
1318 return ret ? ret : msg_sz;
1319}
1320
1321static
1322int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port,
1323 void *buf, size_t size)
1324{
1325 unsigned int offset;
1326
1327 offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1328 return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size);
1329}
1330
1331static
1332int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port,
1333 u8 msg_id, void *buf, size_t size)
1334{
1335 struct intel_hdmi *hdmi = &intel_dig_port->hdmi;
1336 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1337 unsigned int offset;
1338 ssize_t ret;
1339
1340 ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id,
1341 hdcp->is_paired);
1342 if (ret < 0)
1343 return ret;
1344
1345 /*
1346 * Available msg size should be equal to or lesser than the
1347 * available buffer.
1348 */
1349 if (ret > size) {
1350 DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n",
1351 ret, size);
1352 return -1;
1353 }
1354
1355 offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1356 ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret);
1357 if (ret)
1358 DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret);
1359
1360 return ret;
1361}
1362
1363static
1364int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port)
1365{
1366 u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1367 int ret;
1368
1369 ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status);
1370 if (ret)
1371 return ret;
1372
1373 /*
1374 * Re-auth request and Link Integrity Failures are represented by
1375 * same bit. i.e reauth_req.
1376 */
1377 if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1378 ret = HDCP_REAUTH_REQUEST;
1379 else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1380 ret = HDCP_TOPOLOGY_CHANGE;
1381
1382 return ret;
1383}
1384
1385static
1386int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port,
1387 bool *capable)
1388{
1389 u8 hdcp2_version;
1390 int ret;
1391
1392 *capable = false;
1393 ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1394 &hdcp2_version, sizeof(hdcp2_version));
1395 if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1396 *capable = true;
1397
1398 return ret;
1399}
1400
1401static inline
1402enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void)
1403{
1404 return HDCP_PROTOCOL_HDMI;
1405}
1406
2320175f
SP		 1407static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1408 .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1409 .read_bksv = intel_hdmi_hdcp_read_bksv,
1410 .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1411 .repeater_present = intel_hdmi_hdcp_repeater_present,
1412 .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1413 .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1414 .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1415 .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1416 .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1417 .check_link = intel_hdmi_hdcp_check_link,
2d4254e5
R		 1418 .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1419 .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1420 .check_2_2_link = intel_hdmi_hdcp2_check_link,
1421 .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1422 .protocol = HDCP_PROTOCOL_HDMI,
2320175f
SP		 1423};
1424
ac240288
ML		 1425static void intel_hdmi_prepare(struct intel_encoder *encoder,
1426 const struct intel_crtc_state *crtc_state)
7d57382e 1427{
c59423a3 1428 struct drm_device *dev = encoder->base.dev;
fac5e23e 1429 struct drm_i915_private *dev_priv = to_i915(dev);
ac240288 1430 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
c59423a3 1431 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
ac240288 1432 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
b242b7f7 1433 u32 hdmi_val;
7d57382e 1434
b2ccb822
VS		 1435 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1436
b242b7f7 1437 hdmi_val = SDVO_ENCODING_HDMI;
ac240288 1438 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
0f2a2a75 1439 hdmi_val |= HDMI_COLOR_RANGE_16_235;
b599c0bc 1440 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
b242b7f7 1441 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
b599c0bc 1442 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
b242b7f7 1443 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
7d57382e 1444
ac240288 1445 if (crtc_state->pipe_bpp > 24)
4f3a8bc7 1446 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
020f6704 1447 else
4f3a8bc7 1448 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
020f6704 1449
ac240288 1450 if (crtc_state->has_hdmi_sink)
dc0fa718 1451 hdmi_val |= HDMI_MODE_SELECT_HDMI;
2e3d6006 1452
6e266956 1453 if (HAS_PCH_CPT(dev_priv))
c59423a3 1454 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
920a14b2 1455 else if (IS_CHERRYVIEW(dev_priv))
44f37d1f 1456 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
dc0fa718 1457 else
c59423a3 1458 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
7d57382e 1459
b242b7f7
PZ		 1460 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
1461 POSTING_READ(intel_hdmi->hdmi_reg);
7d57382e
EA		 1462}
1463
85234cdc
DV		 1464static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1465 enum pipe *pipe)
7d57382e 1466{
76203467 1467 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
85234cdc 1468 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
0e6e0be4 1469 intel_wakeref_t wakeref;
5b092174 1470 bool ret;
85234cdc 1471
0e6e0be4
CW		 1472 wakeref = intel_display_power_get_if_enabled(dev_priv,
1473 encoder->power_domain);
1474 if (!wakeref)
6d129bea
ID		 1475 return false;
1476
76203467 1477 ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
5b092174 1478
0e6e0be4 1479 intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
5b092174
ID		 1480
1481 return ret;
85234cdc
DV		 1482}
1483
045ac3b5 1484static void intel_hdmi_get_config(struct intel_encoder *encoder,
5cec258b 1485 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 1486{
1487 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
8c875fca 1488 struct drm_device *dev = encoder->base.dev;
fac5e23e 1489 struct drm_i915_private *dev_priv = to_i915(dev);
045ac3b5 1490 u32 tmp, flags = 0;
18442d08 1491 int dotclock;
045ac3b5 1492
e1214b95
VS		 1493 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1494
045ac3b5
JB		 1495 tmp = I915_READ(intel_hdmi->hdmi_reg);
1496
1497 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1498 flags |= DRM_MODE_FLAG_PHSYNC;
1499 else
1500 flags |= DRM_MODE_FLAG_NHSYNC;
1501
1502 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1503 flags |= DRM_MODE_FLAG_PVSYNC;
1504 else
1505 flags |= DRM_MODE_FLAG_NVSYNC;
1506
6897b4b5
DV		 1507 if (tmp & HDMI_MODE_SELECT_HDMI)
1508 pipe_config->has_hdmi_sink = true;
1509
509efa2b 1510 if (intel_hdmi_infoframes_enabled(encoder, pipe_config))
e43823ec
JB		 1511 pipe_config->has_infoframe = true;
1512
c84db770 1513 if (tmp & SDVO_AUDIO_ENABLE)
9ed109a7
DV		 1514 pipe_config->has_audio = true;
1515
6e266956 1516 if (!HAS_PCH_SPLIT(dev_priv) &&
8c875fca
VS		 1517 tmp & HDMI_COLOR_RANGE_16_235)
1518 pipe_config->limited_color_range = true;
1519
2d112de7 1520 pipe_config->base.adjusted_mode.flags |= flags;
18442d08
VS		 1521
1522 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1523 dotclock = pipe_config->port_clock * 2 / 3;
1524 else
1525 dotclock = pipe_config->port_clock;
1526
be69a133
VS		 1527 if (pipe_config->pixel_multiplier)
1528 dotclock /= pipe_config->pixel_multiplier;
1529
2d112de7 1530 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
d4d6279a
ACO		 1531
1532 pipe_config->lane_count = 4;
045ac3b5
JB		 1533}
1534
df18e721 1535static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
5f88a9c6
VS		 1536 const struct intel_crtc_state *pipe_config,
1537 const struct drm_connector_state *conn_state)
d1b1589c 1538{
ac240288 1539 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
d1b1589c 1540
ac240288 1541 WARN_ON(!pipe_config->has_hdmi_sink);
d1b1589c
VS		 1542 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1543 pipe_name(crtc->pipe));
bbf35e9d 1544 intel_audio_codec_enable(encoder, pipe_config, conn_state);
d1b1589c
VS		 1545}
1546
fd6bbda9 1547static void g4x_enable_hdmi(struct intel_encoder *encoder,
5f88a9c6
VS		 1548 const struct intel_crtc_state *pipe_config,
1549 const struct drm_connector_state *conn_state)
7d57382e 1550{
5ab432ef 1551 struct drm_device *dev = encoder->base.dev;
fac5e23e 1552 struct drm_i915_private *dev_priv = to_i915(dev);
5ab432ef 1553 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
7d57382e
EA		 1554 u32 temp;
1555
b242b7f7 1556 temp = I915_READ(intel_hdmi->hdmi_reg);
d8a2d0e0 1557
bf868c7d 1558 temp |= SDVO_ENABLE;
df18e721 1559 if (pipe_config->has_audio)
bf868c7d 1560 temp |= SDVO_AUDIO_ENABLE;
7a87c289 1561
bf868c7d
VS		 1562 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1563 POSTING_READ(intel_hdmi->hdmi_reg);
1564
df18e721
ML		 1565 if (pipe_config->has_audio)
1566 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
bf868c7d
VS		 1567}
1568
fd6bbda9 1569static void ibx_enable_hdmi(struct intel_encoder *encoder,
5f88a9c6
VS		 1570 const struct intel_crtc_state *pipe_config,
1571 const struct drm_connector_state *conn_state)
bf868c7d
VS		 1572{
1573 struct drm_device *dev = encoder->base.dev;
fac5e23e 1574 struct drm_i915_private *dev_priv = to_i915(dev);
bf868c7d
VS		 1575 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1576 u32 temp;
1577
1578 temp = I915_READ(intel_hdmi->hdmi_reg);
d8a2d0e0 1579
bf868c7d 1580 temp |= SDVO_ENABLE;
ac240288 1581 if (pipe_config->has_audio)
bf868c7d 1582 temp |= SDVO_AUDIO_ENABLE;
5ab432ef 1583
bf868c7d
VS		 1584 /*
1585 * HW workaround, need to write this twice for issue
1586 * that may result in first write getting masked.
1587 */
1588 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1589 POSTING_READ(intel_hdmi->hdmi_reg);
b242b7f7
PZ		 1590 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1591 POSTING_READ(intel_hdmi->hdmi_reg);
5ab432ef 1592
bf868c7d
VS		 1593 /*
1594 * HW workaround, need to toggle enable bit off and on
1595 * for 12bpc with pixel repeat.
1596 *
1597 * FIXME: BSpec says this should be done at the end of
1598 * of the modeset sequence, so not sure if this isn't too soon.
5ab432ef 1599 */
df18e721
ML		 1600 if (pipe_config->pipe_bpp > 24 &&
1601 pipe_config->pixel_multiplier > 1) {
bf868c7d
VS		 1602 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1603 POSTING_READ(intel_hdmi->hdmi_reg);
1604
1605 /*
1606 * HW workaround, need to write this twice for issue
1607 * that may result in first write getting masked.
1608 */
1609 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1610 POSTING_READ(intel_hdmi->hdmi_reg);
b242b7f7
PZ		 1611 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1612 POSTING_READ(intel_hdmi->hdmi_reg);
7d57382e 1613 }
c1dec79a 1614
df18e721
ML		 1615 if (pipe_config->has_audio)
1616 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
d1b1589c
VS		 1617}
1618
fd6bbda9 1619static void cpt_enable_hdmi(struct intel_encoder *encoder,
5f88a9c6
VS		 1620 const struct intel_crtc_state *pipe_config,
1621 const struct drm_connector_state *conn_state)
d1b1589c
VS		 1622{
1623 struct drm_device *dev = encoder->base.dev;
fac5e23e 1624 struct drm_i915_private *dev_priv = to_i915(dev);
ac240288 1625 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
d1b1589c
VS		 1626 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1627 enum pipe pipe = crtc->pipe;
1628 u32 temp;
1629
1630 temp = I915_READ(intel_hdmi->hdmi_reg);
1631
1632 temp |= SDVO_ENABLE;
df18e721 1633 if (pipe_config->has_audio)
d1b1589c
VS		 1634 temp |= SDVO_AUDIO_ENABLE;
1635
1636 /*
1637 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1638 *
1639 * The procedure for 12bpc is as follows:
1640 * 1. disable HDMI clock gating
1641 * 2. enable HDMI with 8bpc
1642 * 3. enable HDMI with 12bpc
1643 * 4. enable HDMI clock gating
1644 */
1645
df18e721 1646 if (pipe_config->pipe_bpp > 24) {
d1b1589c
VS		 1647 I915_WRITE(TRANS_CHICKEN1(pipe),
1648 I915_READ(TRANS_CHICKEN1(pipe)) |
1649 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1650
1651 temp &= ~SDVO_COLOR_FORMAT_MASK;
1652 temp |= SDVO_COLOR_FORMAT_8bpc;
c1dec79a 1653 }
d1b1589c
VS		 1654
1655 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1656 POSTING_READ(intel_hdmi->hdmi_reg);
1657
df18e721 1658 if (pipe_config->pipe_bpp > 24) {
d1b1589c
VS		 1659 temp &= ~SDVO_COLOR_FORMAT_MASK;
1660 temp |= HDMI_COLOR_FORMAT_12bpc;
1661
1662 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1663 POSTING_READ(intel_hdmi->hdmi_reg);
1664
1665 I915_WRITE(TRANS_CHICKEN1(pipe),
1666 I915_READ(TRANS_CHICKEN1(pipe)) &
1667 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1668 }
1669
df18e721
ML		 1670 if (pipe_config->has_audio)
1671 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
b76cf76b 1672}
89b667f8 1673
fd6bbda9 1674static void vlv_enable_hdmi(struct intel_encoder *encoder,
5f88a9c6
VS		 1675 const struct intel_crtc_state *pipe_config,
1676 const struct drm_connector_state *conn_state)
b76cf76b 1677{
5ab432ef
DV		 1678}
1679
fd6bbda9 1680static void intel_disable_hdmi(struct intel_encoder *encoder,
5f88a9c6
VS		 1681 const struct intel_crtc_state *old_crtc_state,
1682 const struct drm_connector_state *old_conn_state)
5ab432ef
DV		 1683{
1684 struct drm_device *dev = encoder->base.dev;
fac5e23e 1685 struct drm_i915_private *dev_priv = to_i915(dev);
5ab432ef 1686 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
f99be1b3
VS		 1687 struct intel_digital_port *intel_dig_port =
1688 hdmi_to_dig_port(intel_hdmi);
ac240288 1689 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5ab432ef 1690 u32 temp;
5ab432ef 1691
b242b7f7 1692 temp = I915_READ(intel_hdmi->hdmi_reg);
5ab432ef 1693
1612c8bd 1694 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
b242b7f7
PZ		 1695 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1696 POSTING_READ(intel_hdmi->hdmi_reg);
1612c8bd
VS		 1697
1698 /*
1699 * HW workaround for IBX, we need to move the port
1700 * to transcoder A after disabling it to allow the
1701 * matching DP port to be enabled on transcoder A.
1702 */
6e266956 1703 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1704 /*
1705 * We get CPU/PCH FIFO underruns on the other pipe when
1706 * doing the workaround. Sweep them under the rug.
1707 */
1708 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1709 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1710
76203467
VS		 1711 temp &= ~SDVO_PIPE_SEL_MASK;
1712 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1612c8bd
VS		 1713 /*
1714 * HW workaround, need to write this twice for issue
1715 * that may result in first write getting masked.
1716 */
1717 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1718 POSTING_READ(intel_hdmi->hdmi_reg);
1719 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1720 POSTING_READ(intel_hdmi->hdmi_reg);
1721
1722 temp &= ~SDVO_ENABLE;
1723 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1724 POSTING_READ(intel_hdmi->hdmi_reg);
0c241d5b 1725
0f0f74bc 1726 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0c241d5b
VS		 1727 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1728 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1612c8bd 1729 }
6d67415f 1730
790ea70c
VS		 1731 intel_dig_port->set_infoframes(encoder,
1732 false,
f99be1b3 1733 old_crtc_state, old_conn_state);
b2ccb822
VS		 1734
1735 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
7d57382e
EA		 1736}
1737
fd6bbda9 1738static void g4x_disable_hdmi(struct intel_encoder *encoder,
5f88a9c6
VS		 1739 const struct intel_crtc_state *old_crtc_state,
1740 const struct drm_connector_state *old_conn_state)
a4790cec 1741{
df18e721 1742 if (old_crtc_state->has_audio)
8ec47de2
VS		 1743 intel_audio_codec_disable(encoder,
1744 old_crtc_state, old_conn_state);
a4790cec 1745
fd6bbda9 1746 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
a4790cec
VS		 1747}
1748
fd6bbda9 1749static void pch_disable_hdmi(struct intel_encoder *encoder,
5f88a9c6
VS		 1750 const struct intel_crtc_state *old_crtc_state,
1751 const struct drm_connector_state *old_conn_state)
a4790cec 1752{
df18e721 1753 if (old_crtc_state->has_audio)
8ec47de2
VS		 1754 intel_audio_codec_disable(encoder,
1755 old_crtc_state, old_conn_state);
a4790cec
VS		 1756}
1757
fd6bbda9 1758static void pch_post_disable_hdmi(struct intel_encoder *encoder,
5f88a9c6
VS		 1759 const struct intel_crtc_state *old_crtc_state,
1760 const struct drm_connector_state *old_conn_state)
a4790cec 1761{
fd6bbda9 1762 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
a4790cec
VS		 1763}
1764
d6038611 1765static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
7d148ef5 1766{
d6038611
VS		 1767 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1768 const struct ddi_vbt_port_info *info =
1769 &dev_priv->vbt.ddi_port_info[encoder->port];
1770 int max_tmds_clock;
1771
9672a69c 1772 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
d6038611
VS		 1773 max_tmds_clock = 594000;
1774 else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1775 max_tmds_clock = 300000;
1776 else if (INTEL_GEN(dev_priv) >= 5)
1777 max_tmds_clock = 225000;
7d148ef5 1778 else
d6038611
VS		 1779 max_tmds_clock = 165000;
1780
1781 if (info->max_tmds_clock)
1782 max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);
1783
1784 return max_tmds_clock;
7d148ef5
DV		 1785}
1786
b1ba124d 1787static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
7a5ca19f
ML		 1788 bool respect_downstream_limits,
1789 bool force_dvi)
b1ba124d 1790{
d6038611
VS		 1791 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1792 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
b1ba124d
VS		 1793
1794 if (respect_downstream_limits) {
8cadab0a
VS		 1795 struct intel_connector *connector = hdmi->attached_connector;
1796 const struct drm_display_info *info = &connector->base.display_info;
1797
b1ba124d
VS		 1798 if (hdmi->dp_dual_mode.max_tmds_clock)
1799 max_tmds_clock = min(max_tmds_clock,
1800 hdmi->dp_dual_mode.max_tmds_clock);
8cadab0a
VS		 1801
1802 if (info->max_tmds_clock)
1803 max_tmds_clock = min(max_tmds_clock,
1804 info->max_tmds_clock);
7a5ca19f 1805 else if (!hdmi->has_hdmi_sink || force_dvi)
b1ba124d
VS		 1806 max_tmds_clock = min(max_tmds_clock, 165000);
1807 }
1808
1809 return max_tmds_clock;
1810}
1811
e64e739e
VS		 1812static enum drm_mode_status
1813hdmi_port_clock_valid(struct intel_hdmi *hdmi,
7a5ca19f
ML		 1814 int clock, bool respect_downstream_limits,
1815 bool force_dvi)
e64e739e 1816{
e2d214ae 1817 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
e64e739e
VS		 1818
1819 if (clock < 25000)
1820 return MODE_CLOCK_LOW;
7a5ca19f 1821 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
e64e739e
VS		 1822 return MODE_CLOCK_HIGH;
1823
5e6ccc0b 1824 /* BXT DPLL can't generate 223-240 MHz */
cc3f90f0 1825 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
5e6ccc0b
VS		 1826 return MODE_CLOCK_RANGE;
1827
1828 /* CHV DPLL can't generate 216-240 MHz */
e2d214ae 1829 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
e64e739e
VS		 1830 return MODE_CLOCK_RANGE;
1831
1832 return MODE_OK;
1833}
1834
c19de8eb
DL		 1835static enum drm_mode_status
1836intel_hdmi_mode_valid(struct drm_connector *connector,
1837 struct drm_display_mode *mode)
7d57382e 1838{
e64e739e
VS		 1839 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1840 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
49cff963 1841 struct drm_i915_private *dev_priv = to_i915(dev);
e64e739e
VS		 1842 enum drm_mode_status status;
1843 int clock;
587bf496 1844 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
7a5ca19f
ML		 1845 bool force_dvi =
1846 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
e64e739e 1847
e4dd27aa
VS		 1848 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1849 return MODE_NO_DBLESCAN;
1850
e64e739e 1851 clock = mode->clock;
587bf496
MK		 1852
1853 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1854 clock *= 2;
1855
1856 if (clock > max_dotclk)
1857 return MODE_CLOCK_HIGH;
1858
697c4078
CT		 1859 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1860 clock *= 2;
1861
b22ca995
SS		 1862 if (drm_mode_is_420_only(&connector->display_info, mode))
1863 clock /= 2;
1864
e64e739e 1865 /* check if we can do 8bpc */
7a5ca19f 1866 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
7d57382e 1867
cd9e11a8
RS		 1868 if (hdmi->has_hdmi_sink && !force_dvi) {
1869 /* if we can't do 8bpc we may still be able to do 12bpc */
b2ae318a 1870 if (status != MODE_OK && !HAS_GMCH(dev_priv))
cd9e11a8
RS		 1871 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
1872 true, force_dvi);
1873
1874 /* if we can't do 8,12bpc we may still be able to do 10bpc */
1875 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
1876 status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
1877 true, force_dvi);
1878 }
7d57382e 1879
e64e739e 1880 return status;
7d57382e
EA		 1881}
1882
cd9e11a8
RS		 1883static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
1884 int bpc)
71800632 1885{
c750bdd3
VS		 1886 struct drm_i915_private *dev_priv =
1887 to_i915(crtc_state->base.crtc->dev);
1888 struct drm_atomic_state *state = crtc_state->base.state;
1889 struct drm_connector_state *connector_state;
1890 struct drm_connector *connector;
22dae8a0
RS		 1891 const struct drm_display_mode *adjusted_mode =
1892 &crtc_state->base.adjusted_mode;
c750bdd3 1893 int i;
71800632 1894
b2ae318a 1895 if (HAS_GMCH(dev_priv))
71800632
VS		 1896 return false;
1897
cd9e11a8
RS		 1898 if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
1899 return false;
1900
be33be5d
VS		 1901 if (crtc_state->pipe_bpp <= 8*3)
1902 return false;
1903
1904 if (!crtc_state->has_hdmi_sink)
1905 return false;
1906
71800632 1907 /*
cd9e11a8 1908 * HDMI deep color affects the clocks, so it's only possible
71800632
VS		 1909 * when not cloning with other encoder types.
1910 */
c750bdd3
VS		 1911 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1912 return false;
1913
fe5f6b1f 1914 for_each_new_connector_in_state(state, connector, connector_state, i) {
c750bdd3
VS		 1915 const struct drm_display_info *info = &connector->display_info;
1916
1917 if (connector_state->crtc != crtc_state->base.crtc)
1918 continue;
1919
33b7f3ee 1920 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
60436fd4
SS		 1921 const struct drm_hdmi_info *hdmi = &info->hdmi;
1922
cd9e11a8
RS		 1923 if (bpc == 12 && !(hdmi->y420_dc_modes &
1924 DRM_EDID_YCBCR420_DC_36))
1925 return false;
1926 else if (bpc == 10 && !(hdmi->y420_dc_modes &
1927 DRM_EDID_YCBCR420_DC_30))
60436fd4
SS		 1928 return false;
1929 } else {
cd9e11a8
RS		 1930 if (bpc == 12 && !(info->edid_hdmi_dc_modes &
1931 DRM_EDID_HDMI_DC_36))
1932 return false;
1933 else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
1934 DRM_EDID_HDMI_DC_30))
60436fd4
SS		 1935 return false;
1936 }
c750bdd3
VS		 1937 }
1938
2abf3c0d 1939 /* Display WA #1139: glk */
cd9e11a8 1940 if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
22dae8a0
RS		 1941 adjusted_mode->htotal > 5460)
1942 return false;
1943
1944 /* Display Wa_1405510057:icl */
1945 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1946 bpc == 10 && IS_ICELAKE(dev_priv) &&
1947 (adjusted_mode->crtc_hblank_end -
1948 adjusted_mode->crtc_hblank_start) % 8 == 2)
46649d8b
ACO		 1949 return false;
1950
c750bdd3 1951 return true;
71800632
VS		 1952}
1953
60436fd4
SS		 1954static bool
1955intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1956 struct intel_crtc_state *config,
cd9e11a8
RS		 1957 int *clock_12bpc, int *clock_10bpc,
1958 int *clock_8bpc)
60436fd4 1959{
e5c05931
SS		 1960 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1961
60436fd4
SS		 1962 if (!connector->ycbcr_420_allowed) {
1963 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1964 return false;
1965 }
1966
1967 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1968 config->port_clock /= 2;
1969 *clock_12bpc /= 2;
cd9e11a8 1970 *clock_10bpc /= 2;
60436fd4 1971 *clock_8bpc /= 2;
33b7f3ee 1972 config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
e5c05931
SS		 1973
1974 /* YCBCR 420 output conversion needs a scaler */
1975 if (skl_update_scaler_crtc(config)) {
1976 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1977 return false;
1978 }
1979
1980 intel_pch_panel_fitting(intel_crtc, config,
1981 DRM_MODE_SCALE_FULLSCREEN);
1982
60436fd4
SS		 1983 return true;
1984}
1985
204474a6
LP		 1986int intel_hdmi_compute_config(struct intel_encoder *encoder,
1987 struct intel_crtc_state *pipe_config,
1988 struct drm_connector_state *conn_state)
7d57382e 1989{
5bfe2ac0 1990 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
4f8036a2 1991 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2d112de7 1992 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
60436fd4
SS		 1993 struct drm_connector *connector = conn_state->connector;
1994 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
7a5ca19f
ML		 1995 struct intel_digital_connector_state *intel_conn_state =
1996 to_intel_digital_connector_state(conn_state);
e64e739e 1997 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
cd9e11a8 1998 int clock_10bpc = clock_8bpc * 5 / 4;
e64e739e 1999 int clock_12bpc = clock_8bpc * 3 / 2;
e29c22c0 2000 int desired_bpp;
7a5ca19f 2001 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
3685a8f3 2002
e4dd27aa 2003 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
204474a6 2004 return -EINVAL;
e4dd27aa 2005
d9facae6 2006 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
7a5ca19f 2007 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
6897b4b5 2008
e43823ec
JB		 2009 if (pipe_config->has_hdmi_sink)
2010 pipe_config->has_infoframe = true;
2011
7a5ca19f 2012 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
55bc60db 2013 /* See CEA-861-E - 5.1 Default Encoding Parameters */
0f2a2a75
VS		 2014 pipe_config->limited_color_range =
2015 pipe_config->has_hdmi_sink &&
c8127cf0
VS		 2016 drm_default_rgb_quant_range(adjusted_mode) ==
2017 HDMI_QUANTIZATION_RANGE_LIMITED;
0f2a2a75
VS		 2018 } else {
2019 pipe_config->limited_color_range =
7a5ca19f 2020 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
55bc60db
VS		 2021 }
2022
697c4078
CT		 2023 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
2024 pipe_config->pixel_multiplier = 2;
e64e739e 2025 clock_8bpc *= 2;
cd9e11a8 2026 clock_10bpc *= 2;
3320e37f 2027 clock_12bpc *= 2;
697c4078
CT		 2028 }
2029
60436fd4
SS		 2030 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
2031 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
cd9e11a8
RS		 2032 &clock_12bpc, &clock_10bpc,
2033 &clock_8bpc)) {
60436fd4 2034 DRM_ERROR("Can't support YCBCR420 output\n");
204474a6 2035 return -EINVAL;
60436fd4
SS		 2036 }
2037 }
2038
4f8036a2 2039 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
5bfe2ac0
DV		 2040 pipe_config->has_pch_encoder = true;
2041
7a5ca19f
ML		 2042 if (pipe_config->has_hdmi_sink) {
2043 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2044 pipe_config->has_audio = intel_hdmi->has_audio;
2045 else
2046 pipe_config->has_audio =
2047 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2048 }
9ed109a7 2049
4e53c2e0 2050 /*
cd9e11a8
RS		 2051 * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need
2052 * to check that the higher clock still fits within limits.
4e53c2e0 2053 */
cd9e11a8
RS		 2054 if (hdmi_deep_color_possible(pipe_config, 12) &&
2055 hdmi_port_clock_valid(intel_hdmi, clock_12bpc,
2056 true, force_dvi) == MODE_OK) {
e29c22c0
DV		 2057 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
2058 desired_bpp = 12*3;
325b9d04
DV		 2059
2060 /* Need to adjust the port link by 1.5x for 12bpc. */
ff9a6750 2061 pipe_config->port_clock = clock_12bpc;
cd9e11a8
RS		 2062 } else if (hdmi_deep_color_possible(pipe_config, 10) &&
2063 hdmi_port_clock_valid(intel_hdmi, clock_10bpc,
2064 true, force_dvi) == MODE_OK) {
2065 DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n");
2066 desired_bpp = 10 * 3;
2067
2068 /* Need to adjust the port link by 1.25x for 10bpc. */
2069 pipe_config->port_clock = clock_10bpc;
4e53c2e0 2070 } else {
e29c22c0
DV		 2071 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
2072 desired_bpp = 8*3;
e64e739e
VS		 2073
2074 pipe_config->port_clock = clock_8bpc;
e29c22c0
DV		 2075 }
2076
2077 if (!pipe_config->bw_constrained) {
b64b7a60 2078 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
e29c22c0 2079 pipe_config->pipe_bpp = desired_bpp;
4e53c2e0
DV		 2080 }
2081
e64e739e 2082 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
7a5ca19f 2083 false, force_dvi) != MODE_OK) {
e64e739e 2084 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
204474a6 2085 return -EINVAL;
325b9d04
DV		 2086 }
2087
28b468a0 2088 /* Set user selected PAR to incoming mode's member */
0e9f25d0 2089 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
28b468a0 2090
d4d6279a
ACO		 2091 pipe_config->lane_count = 4;
2092
9672a69c
RV		 2093 if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2094 IS_GEMINILAKE(dev_priv))) {
15953637
SS		 2095 if (scdc->scrambling.low_rates)
2096 pipe_config->hdmi_scrambling = true;
2097
2098 if (pipe_config->port_clock > 340000) {
2099 pipe_config->hdmi_scrambling = true;
2100 pipe_config->hdmi_high_tmds_clock_ratio = true;
2101 }
2102 }
2103
204474a6 2104 return 0;
7d57382e
EA		 2105}
2106
953ece69
CW		 2107static void
2108intel_hdmi_unset_edid(struct drm_connector *connector)
9dff6af8 2109{
df0e9248 2110 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
9dff6af8 2111
953ece69
CW		 2112 intel_hdmi->has_hdmi_sink = false;
2113 intel_hdmi->has_audio = false;
953ece69 2114
b1ba124d
VS		 2115 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2116 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2117
953ece69
CW		 2118 kfree(to_intel_connector(connector)->detect_edid);
2119 to_intel_connector(connector)->detect_edid = NULL;
2120}
2121
b1ba124d 2122static void
d6199256 2123intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
b1ba124d
VS		 2124{
2125 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2126 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
8f4f2797 2127 enum port port = hdmi_to_dig_port(hdmi)->base.port;
b1ba124d
VS		 2128 struct i2c_adapter *adapter =
2129 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2130 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2131
d6199256
VS		 2132 /*
2133 * Type 1 DVI adaptors are not required to implement any
2134 * registers, so we can't always detect their presence.
2135 * Ideally we should be able to check the state of the
2136 * CONFIG1 pin, but no such luck on our hardware.
2137 *
2138 * The only method left to us is to check the VBT to see
2139 * if the port is a dual mode capable DP port. But let's
2140 * only do that when we sucesfully read the EDID, to avoid
2141 * confusing log messages about DP dual mode adaptors when
2142 * there's nothing connected to the port.
2143 */
2144 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
30190629
AJ		 2145 /* An overridden EDID imply that we want this port for testing.
2146 * Make sure not to set limits for that port.
2147 */
2148 if (has_edid && !connector->override_edid &&
d6199256
VS		 2149 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2150 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
2151 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2152 } else {
2153 type = DRM_DP_DUAL_MODE_NONE;
2154 }
2155 }
2156
2157 if (type == DRM_DP_DUAL_MODE_NONE)
b1ba124d
VS		 2158 return;
2159
2160 hdmi->dp_dual_mode.type = type;
2161 hdmi->dp_dual_mode.max_tmds_clock =
2162 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2163
2164 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2165 drm_dp_get_dual_mode_type_name(type),
2166 hdmi->dp_dual_mode.max_tmds_clock);
2167}
2168
953ece69 2169static bool
23f889bd 2170intel_hdmi_set_edid(struct drm_connector *connector)
953ece69
CW		 2171{
2172 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2173 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
0e6e0be4 2174 intel_wakeref_t wakeref;
23f889bd 2175 struct edid *edid;
953ece69 2176 bool connected = false;
cfb926e1 2177 struct i2c_adapter *i2c;
164c8598 2178
0e6e0be4 2179 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
671dedd2 2180
cfb926e1
SB		 2181 i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2182
2183 edid = drm_get_edid(connector, i2c);
2184
2185 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2186 DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2187 intel_gmbus_force_bit(i2c, true);
2188 edid = drm_get_edid(connector, i2c);
2189 intel_gmbus_force_bit(i2c, false);
2190 }
2ded9e27 2191
23f889bd 2192 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
b1ba124d 2193
0e6e0be4 2194 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
30ad48b7 2195
953ece69
CW		 2196 to_intel_connector(connector)->detect_edid = edid;
2197 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
953ece69 2198 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
7a5ca19f 2199 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
953ece69
CW		 2200
2201 connected = true;
55b7d6e8
CW		 2202 }
2203
9c229127
NA		 2204 cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2205
953ece69
CW		 2206 return connected;
2207}
2208
8166fcea
DV		 2209static enum drm_connector_status
2210intel_hdmi_detect(struct drm_connector *connector, bool force)
953ece69 2211{
39d1e234 2212 enum drm_connector_status status = connector_status_disconnected;
8166fcea 2213 struct drm_i915_private *dev_priv = to_i915(connector->dev);
9c229127 2214 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
39d1e234 2215 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
0e6e0be4 2216 intel_wakeref_t wakeref;
953ece69 2217
8166fcea
DV		 2218 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2219 connector->base.id, connector->name);
2220
0e6e0be4 2221 wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
29bb94bb 2222
39d1e234
PZ		 2223 if (IS_ICELAKE(dev_priv) &&
2224 !intel_digital_port_connected(encoder))
2225 goto out;
2226
8166fcea 2227 intel_hdmi_unset_edid(connector);
0b5e88dc 2228
7e732cac 2229 if (intel_hdmi_set_edid(connector))
953ece69 2230 status = connector_status_connected;
671dedd2 2231
39d1e234 2232out:
0e6e0be4 2233 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
29bb94bb 2234
9c229127
NA		 2235 if (status != connector_status_connected)
2236 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2237
2ded9e27 2238 return status;
7d57382e
EA		 2239}
2240
953ece69
CW		 2241static void
2242intel_hdmi_force(struct drm_connector *connector)
7d57382e 2243{
953ece69
CW		 2244 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2245 connector->base.id, connector->name);
7d57382e 2246
953ece69 2247 intel_hdmi_unset_edid(connector);
671dedd2 2248
953ece69
CW		 2249 if (connector->status != connector_status_connected)
2250 return;
671dedd2 2251
23f889bd 2252 intel_hdmi_set_edid(connector);
953ece69 2253}
671dedd2 2254
953ece69
CW		 2255static int intel_hdmi_get_modes(struct drm_connector *connector)
2256{
2257 struct edid *edid;
2258
2259 edid = to_intel_connector(connector)->detect_edid;
2260 if (edid == NULL)
2261 return 0;
671dedd2 2262
953ece69 2263 return intel_connector_update_modes(connector, edid);
7d57382e
EA		 2264}
2265
fd6bbda9 2266static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2267 const struct intel_crtc_state *pipe_config,
2268 const struct drm_connector_state *conn_state)
13732ba7 2269{
f99be1b3
VS		 2270 struct intel_digital_port *intel_dig_port =
2271 enc_to_dig_port(&encoder->base);
13732ba7 2272
ac240288 2273 intel_hdmi_prepare(encoder, pipe_config);
4cde8a21 2274
790ea70c 2275 intel_dig_port->set_infoframes(encoder,
f99be1b3
VS		 2276 pipe_config->has_infoframe,
2277 pipe_config, conn_state);
13732ba7
JB		 2278}
2279
fd6bbda9 2280static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2281 const struct intel_crtc_state *pipe_config,
2282 const struct drm_connector_state *conn_state)
89b667f8
JB		 2283{
2284 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2e1029c6 2285 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5f68c275 2286
2e1029c6 2287 vlv_phy_pre_encoder_enable(encoder, pipe_config);
b76cf76b 2288
53d98725
ACO		 2289 /* HDMI 1.0V-2dB */
2290 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2291 0x2b247878);
2292
790ea70c 2293 dport->set_infoframes(encoder,
f99be1b3
VS		 2294 pipe_config->has_infoframe,
2295 pipe_config, conn_state);
13732ba7 2296
fd6bbda9 2297 g4x_enable_hdmi(encoder, pipe_config, conn_state);
b76cf76b 2298
9b6de0a1 2299 vlv_wait_port_ready(dev_priv, dport, 0x0);
89b667f8
JB		 2300}
2301
fd6bbda9 2302static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2303 const struct intel_crtc_state *pipe_config,
2304 const struct drm_connector_state *conn_state)
89b667f8 2305{
ac240288 2306 intel_hdmi_prepare(encoder, pipe_config);
4cde8a21 2307
2e1029c6 2308 vlv_phy_pre_pll_enable(encoder, pipe_config);
89b667f8
JB		 2309}
2310
fd6bbda9 2311static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2312 const struct intel_crtc_state *pipe_config,
2313 const struct drm_connector_state *conn_state)
9197c88b 2314{
ac240288 2315 intel_hdmi_prepare(encoder, pipe_config);
625695f8 2316
2e1029c6 2317 chv_phy_pre_pll_enable(encoder, pipe_config);
9197c88b
VS		 2318}
2319
fd6bbda9 2320static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 2321 const struct intel_crtc_state *old_crtc_state,
2322 const struct drm_connector_state *old_conn_state)
d6db995f 2323{
2e1029c6 2324 chv_phy_post_pll_disable(encoder, old_crtc_state);
d6db995f
VS		 2325}
2326
fd6bbda9 2327static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 2328 const struct intel_crtc_state *old_crtc_state,
2329 const struct drm_connector_state *old_conn_state)
89b667f8 2330{
89b667f8 2331 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2e1029c6 2332 vlv_phy_reset_lanes(encoder, old_crtc_state);
89b667f8
JB		 2333}
2334
fd6bbda9 2335static void chv_hdmi_post_disable(struct intel_encoder *encoder,
5f88a9c6
VS		 2336 const struct intel_crtc_state *old_crtc_state,
2337 const struct drm_connector_state *old_conn_state)
580d3811 2338{
580d3811 2339 struct drm_device *dev = encoder->base.dev;
fac5e23e 2340 struct drm_i915_private *dev_priv = to_i915(dev);
580d3811 2341
a580516d 2342 mutex_lock(&dev_priv->sb_lock);
580d3811 2343
a8f327fb 2344 /* Assert data lane reset */
2e1029c6 2345 chv_data_lane_soft_reset(encoder, old_crtc_state, true);
580d3811 2346
a580516d 2347 mutex_unlock(&dev_priv->sb_lock);
580d3811
VS		 2348}
2349
fd6bbda9 2350static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
5f88a9c6
VS		 2351 const struct intel_crtc_state *pipe_config,
2352 const struct drm_connector_state *conn_state)
e4a1d846
CML		 2353{
2354 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2355 struct drm_device *dev = encoder->base.dev;
fac5e23e 2356 struct drm_i915_private *dev_priv = to_i915(dev);
2e523e98 2357
2e1029c6 2358 chv_phy_pre_encoder_enable(encoder, pipe_config);
a02ef3c7 2359
e4a1d846
CML		 2360 /* FIXME: Program the support xxx V-dB */
2361 /* Use 800mV-0dB */
b7fa22d8 2362 chv_set_phy_signal_level(encoder, 128, 102, false);
e4a1d846 2363
790ea70c 2364 dport->set_infoframes(encoder,
f99be1b3
VS		 2365 pipe_config->has_infoframe,
2366 pipe_config, conn_state);
b4eb1564 2367
fd6bbda9 2368 g4x_enable_hdmi(encoder, pipe_config, conn_state);
e4a1d846 2369
9b6de0a1 2370 vlv_wait_port_ready(dev_priv, dport, 0x0);
b0b33846
VS		 2371
2372 /* Second common lane will stay alive on its own now */
e7d2a717 2373 chv_phy_release_cl2_override(encoder);
e4a1d846
CML		 2374}
2375
bdc93fe0
R		 2376static int
2377intel_hdmi_connector_register(struct drm_connector *connector)
2378{
2379 int ret;
2380
2381 ret = intel_connector_register(connector);
2382 if (ret)
2383 return ret;
2384
2385 i915_debugfs_connector_add(connector);
2386
2387 return ret;
2388}
2389
7d57382e
EA		 2390static void intel_hdmi_destroy(struct drm_connector *connector)
2391{
9c229127
NA		 2392 if (intel_attached_hdmi(connector)->cec_notifier)
2393 cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier);
d4b26e4f
JN		 2394
2395 intel_connector_destroy(connector);
7d57382e
EA		 2396}
2397
7d57382e 2398static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
7d57382e 2399 .detect = intel_hdmi_detect,
953ece69 2400 .force = intel_hdmi_force,
7d57382e 2401 .fill_modes = drm_helper_probe_single_connector_modes,
7a5ca19f
ML		 2402 .atomic_get_property = intel_digital_connector_atomic_get_property,
2403 .atomic_set_property = intel_digital_connector_atomic_set_property,
bdc93fe0 2404 .late_register = intel_hdmi_connector_register,
c191eca1 2405 .early_unregister = intel_connector_unregister,
7d57382e 2406 .destroy = intel_hdmi_destroy,
c6f95f27 2407 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7a5ca19f 2408 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7d57382e
EA		 2409};
2410
2411static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2412 .get_modes = intel_hdmi_get_modes,
2413 .mode_valid = intel_hdmi_mode_valid,
7a5ca19f 2414 .atomic_check = intel_digital_connector_atomic_check,
7d57382e
EA		 2415};
2416
7d57382e 2417static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
ea5b213a 2418 .destroy = intel_encoder_destroy,
7d57382e
EA		 2419};
2420
55b7d6e8
CW		 2421static void
2422intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2423{
f1a12172
RS		 2424 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2425
3f43c48d 2426 intel_attach_force_audio_property(connector);
e953fd7b 2427 intel_attach_broadcast_rgb_property(connector);
94a11ddc 2428 intel_attach_aspect_ratio_property(connector);
6553b123 2429 drm_connector_attach_content_type_property(connector);
0e9f25d0 2430 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
f1a12172 2431
b2ae318a 2432 if (!HAS_GMCH(dev_priv))
f1a12172 2433 drm_connector_attach_max_bpc_property(connector, 8, 12);
55b7d6e8
CW		 2434}
2435
15953637
SS		 2436/*
2437 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2438 * @encoder: intel_encoder
2439 * @connector: drm_connector
2440 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2441 * or reset the high tmds clock ratio for scrambling
2442 * @scrambling: bool to Indicate if the function needs to set or reset
2443 * sink scrambling
2444 *
2445 * This function handles scrambling on HDMI 2.0 capable sinks.
2446 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2447 * it enables scrambling. This should be called before enabling the HDMI
2448 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2449 * detect a scrambled clock within 100 ms.
277ab5ab
VS		 2450 *
2451 * Returns:
2452 * True on success, false on failure.
15953637 2453 */
277ab5ab 2454bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
15953637
SS		 2455 struct drm_connector *connector,
2456 bool high_tmds_clock_ratio,
2457 bool scrambling)
2458{
277ab5ab 2459 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
15953637 2460 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
15953637 2461 struct drm_scrambling *sink_scrambling =
277ab5ab
VS		 2462 &connector->display_info.hdmi.scdc.scrambling;
2463 struct i2c_adapter *adapter =
2464 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
15953637
SS		 2465
2466 if (!sink_scrambling->supported)
277ab5ab 2467 return true;
15953637 2468
277ab5ab
VS		 2469 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2470 connector->base.id, connector->name,
2471 yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
15953637 2472
277ab5ab
VS		 2473 /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2474 return drm_scdc_set_high_tmds_clock_ratio(adapter,
2475 high_tmds_clock_ratio) &&
2476 drm_scdc_set_scrambling(adapter, scrambling);
15953637
SS		 2477}
2478
cec3bb01 2479static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
e4ab73a1 2480{
e4ab73a1
VS		 2481 u8 ddc_pin;
2482
cec3bb01
AS		 2483 switch (port) {
2484 case PORT_B:
2485 ddc_pin = GMBUS_PIN_DPB;
2486 break;
2487 case PORT_C:
2488 ddc_pin = GMBUS_PIN_DPC;
2489 break;
2490 case PORT_D:
2491 ddc_pin = GMBUS_PIN_DPD_CHV;
2492 break;
2493 default:
2494 MISSING_CASE(port);
2495 ddc_pin = GMBUS_PIN_DPB;
2496 break;
e4ab73a1 2497 }
cec3bb01
AS		 2498 return ddc_pin;
2499}
2500
2501static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2502{
2503 u8 ddc_pin;
e4ab73a1
VS		 2504
2505 switch (port) {
2506 case PORT_B:
cec3bb01 2507 ddc_pin = GMBUS_PIN_1_BXT;
e4ab73a1
VS		 2508 break;
2509 case PORT_C:
cec3bb01
AS		 2510 ddc_pin = GMBUS_PIN_2_BXT;
2511 break;
2512 default:
2513 MISSING_CASE(port);
2514 ddc_pin = GMBUS_PIN_1_BXT;
2515 break;
2516 }
2517 return ddc_pin;
2518}
2519
2520static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2521 enum port port)
2522{
2523 u8 ddc_pin;
2524
2525 switch (port) {
2526 case PORT_B:
2527 ddc_pin = GMBUS_PIN_1_BXT;
2528 break;
2529 case PORT_C:
2530 ddc_pin = GMBUS_PIN_2_BXT;
e4ab73a1
VS		 2531 break;
2532 case PORT_D:
cec3bb01
AS		 2533 ddc_pin = GMBUS_PIN_4_CNP;
2534 break;
3a2a59cc
RV		 2535 case PORT_F:
2536 ddc_pin = GMBUS_PIN_3_BXT;
2537 break;
cec3bb01
AS		 2538 default:
2539 MISSING_CASE(port);
2540 ddc_pin = GMBUS_PIN_1_BXT;
2541 break;
2542 }
2543 return ddc_pin;
2544}
2545
5c749c52
AS		 2546static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2547{
2548 u8 ddc_pin;
2549
2550 switch (port) {
2551 case PORT_A:
2552 ddc_pin = GMBUS_PIN_1_BXT;
2553 break;
2554 case PORT_B:
2555 ddc_pin = GMBUS_PIN_2_BXT;
2556 break;
2557 case PORT_C:
2558 ddc_pin = GMBUS_PIN_9_TC1_ICP;
2559 break;
2560 case PORT_D:
2561 ddc_pin = GMBUS_PIN_10_TC2_ICP;
2562 break;
2563 case PORT_E:
2564 ddc_pin = GMBUS_PIN_11_TC3_ICP;
2565 break;
2566 case PORT_F:
2567 ddc_pin = GMBUS_PIN_12_TC4_ICP;
2568 break;
2569 default:
2570 MISSING_CASE(port);
2571 ddc_pin = GMBUS_PIN_2_BXT;
2572 break;
2573 }
2574 return ddc_pin;
2575}
2576
cec3bb01
AS		 2577static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2578 enum port port)
2579{
2580 u8 ddc_pin;
2581
2582 switch (port) {
2583 case PORT_B:
2584 ddc_pin = GMBUS_PIN_DPB;
2585 break;
2586 case PORT_C:
2587 ddc_pin = GMBUS_PIN_DPC;
2588 break;
2589 case PORT_D:
2590 ddc_pin = GMBUS_PIN_DPD;
e4ab73a1
VS		 2591 break;
2592 default:
2593 MISSING_CASE(port);
2594 ddc_pin = GMBUS_PIN_DPB;
2595 break;
2596 }
cec3bb01
AS		 2597 return ddc_pin;
2598}
2599
2600static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2601 enum port port)
2602{
2603 const struct ddi_vbt_port_info *info =
2604 &dev_priv->vbt.ddi_port_info[port];
2605 u8 ddc_pin;
2606
2607 if (info->alternate_ddc_pin) {
2608 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2609 info->alternate_ddc_pin, port_name(port));
2610 return info->alternate_ddc_pin;
2611 }
2612
e0f83eb5
RV		 2613 if (HAS_PCH_ICP(dev_priv))
2614 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
cec3bb01
AS		 2615 else if (HAS_PCH_CNP(dev_priv))
2616 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
e0f83eb5
RV		 2617 else if (IS_GEN9_LP(dev_priv))
2618 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2619 else if (IS_CHERRYVIEW(dev_priv))
2620 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
cec3bb01
AS		 2621 else
2622 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
e4ab73a1
VS		 2623
2624 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2625 ddc_pin, port_name(port));
2626
2627 return ddc_pin;
2628}
2629
385e4de0
VS		 2630void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
2631{
2632 struct drm_i915_private *dev_priv =
2633 to_i915(intel_dig_port->base.base.dev);
2634
2635 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2636 intel_dig_port->write_infoframe = vlv_write_infoframe;
2637 intel_dig_port->set_infoframes = vlv_set_infoframes;
509efa2b 2638 intel_dig_port->infoframes_enabled = vlv_infoframes_enabled;
385e4de0
VS		 2639 } else if (IS_G4X(dev_priv)) {
2640 intel_dig_port->write_infoframe = g4x_write_infoframe;
2641 intel_dig_port->set_infoframes = g4x_set_infoframes;
509efa2b 2642 intel_dig_port->infoframes_enabled = g4x_infoframes_enabled;
385e4de0 2643 } else if (HAS_DDI(dev_priv)) {
06c812d7 2644 if (intel_dig_port->lspcon.active) {
509efa2b 2645 intel_dig_port->write_infoframe = lspcon_write_infoframe;
06c812d7 2646 intel_dig_port->set_infoframes = lspcon_set_infoframes;
509efa2b 2647 intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled;
06c812d7 2648 } else {
06c812d7 2649 intel_dig_port->write_infoframe = hsw_write_infoframe;
509efa2b
VS		 2650 intel_dig_port->set_infoframes = hsw_set_infoframes;
2651 intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
06c812d7 2652 }
385e4de0
VS		 2653 } else if (HAS_PCH_IBX(dev_priv)) {
2654 intel_dig_port->write_infoframe = ibx_write_infoframe;
2655 intel_dig_port->set_infoframes = ibx_set_infoframes;
509efa2b 2656 intel_dig_port->infoframes_enabled = ibx_infoframes_enabled;
385e4de0
VS		 2657 } else {
2658 intel_dig_port->write_infoframe = cpt_write_infoframe;
2659 intel_dig_port->set_infoframes = cpt_set_infoframes;
509efa2b 2660 intel_dig_port->infoframes_enabled = cpt_infoframes_enabled;
385e4de0
VS		 2661 }
2662}
2663
00c09d70
PZ		 2664void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2665 struct intel_connector *intel_connector)
7d57382e 2666{
b9cb234c
PZ		 2667 struct drm_connector *connector = &intel_connector->base;
2668 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2669 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2670 struct drm_device *dev = intel_encoder->base.dev;
fac5e23e 2671 struct drm_i915_private *dev_priv = to_i915(dev);
8f4f2797 2672 enum port port = intel_encoder->port;
373a3cf7 2673
22f35042
VS		 2674 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2675 port_name(port));
2676
ccb1a831
VS		 2677 if (WARN(intel_dig_port->max_lanes < 4,
2678 "Not enough lanes (%d) for HDMI on port %c\n",
2679 intel_dig_port->max_lanes, port_name(port)))
2680 return;
2681
7d57382e 2682 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
8d91104a 2683 DRM_MODE_CONNECTOR_HDMIA);
7d57382e
EA		 2684 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2685
c3febcc4 2686 connector->interlace_allowed = 1;
7d57382e 2687 connector->doublescan_allowed = 0;
573e74ad 2688 connector->stereo_allowed = 1;
66a9278e 2689
9672a69c 2690 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
eadc2e51
SS		 2691 connector->ycbcr_420_allowed = true;
2692
e4ab73a1
VS		 2693 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2694
f761bef2 2695 if (WARN_ON(port == PORT_A))
e4ab73a1 2696 return;
cf53902f 2697 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
7d57382e 2698
4f8036a2 2699 if (HAS_DDI(dev_priv))
bcbc889b
PZ		 2700 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2701 else
2702 intel_connector->get_hw_state = intel_connector_get_hw_state;
b9cb234c
PZ		 2703
2704 intel_hdmi_add_properties(intel_hdmi, connector);
2705
04707f97
R		 2706 intel_connector_attach_encoder(intel_connector, intel_encoder);
2707 intel_hdmi->attached_connector = intel_connector;
2708
fdddd08c 2709 if (is_hdcp_supported(dev_priv, port)) {
2320175f
SP		 2710 int ret = intel_hdcp_init(intel_connector,
2711 &intel_hdmi_hdcp_shim);
2712 if (ret)
2713 DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
2714 }
2715
b9cb234c
PZ		 2716 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2717 * 0xd. Failure to do so will result in spurious interrupts being
2718 * generated on the port when a cable is not attached.
2719 */
1c0f1b3d 2720 if (IS_G45(dev_priv)) {
b9cb234c
PZ		 2721 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2722 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2723 }
9c229127
NA		 2724
2725 intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev,
2726 port_identifier(port));
2727 if (!intel_hdmi->cec_notifier)
2728 DRM_DEBUG_KMS("CEC notifier get failed\n");
b9cb234c
PZ		 2729}
2730
c39055b0 2731void intel_hdmi_init(struct drm_i915_private *dev_priv,
f0f59a00 2732 i915_reg_t hdmi_reg, enum port port)
b9cb234c
PZ		 2733{
2734 struct intel_digital_port *intel_dig_port;
2735 struct intel_encoder *intel_encoder;
b9cb234c
PZ		 2736 struct intel_connector *intel_connector;
2737
b14c5679 2738 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
b9cb234c
PZ		 2739 if (!intel_dig_port)
2740 return;
2741
08d9bc92 2742 intel_connector = intel_connector_alloc();
b9cb234c
PZ		 2743 if (!intel_connector) {
2744 kfree(intel_dig_port);
2745 return;
2746 }
2747
2748 intel_encoder = &intel_dig_port->base;
b9cb234c 2749
c39055b0
ACO		 2750 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2751 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2752 "HDMI %c", port_name(port));
00c09d70 2753
dba14b27 2754 intel_encoder->hotplug = intel_encoder_hotplug;
5bfe2ac0 2755 intel_encoder->compute_config = intel_hdmi_compute_config;
6e266956 2756 if (HAS_PCH_SPLIT(dev_priv)) {
a4790cec
VS		 2757 intel_encoder->disable = pch_disable_hdmi;
2758 intel_encoder->post_disable = pch_post_disable_hdmi;
2759 } else {
2760 intel_encoder->disable = g4x_disable_hdmi;
2761 }
00c09d70 2762 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
045ac3b5 2763 intel_encoder->get_config = intel_hdmi_get_config;
920a14b2 2764 if (IS_CHERRYVIEW(dev_priv)) {
9197c88b 2765 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
e4a1d846
CML		 2766 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2767 intel_encoder->enable = vlv_enable_hdmi;
580d3811 2768 intel_encoder->post_disable = chv_hdmi_post_disable;
d6db995f 2769 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
11a914c2 2770 } else if (IS_VALLEYVIEW(dev_priv)) {
9514ac6e
CML		 2771 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2772 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
b76cf76b 2773 intel_encoder->enable = vlv_enable_hdmi;
9514ac6e 2774 intel_encoder->post_disable = vlv_hdmi_post_disable;
b76cf76b 2775 } else {
13732ba7 2776 intel_encoder->pre_enable = intel_hdmi_pre_enable;
6e266956 2777 if (HAS_PCH_CPT(dev_priv))
d1b1589c 2778 intel_encoder->enable = cpt_enable_hdmi;
6e266956 2779 else if (HAS_PCH_IBX(dev_priv))
bf868c7d 2780 intel_encoder->enable = ibx_enable_hdmi;
d1b1589c 2781 else
bf868c7d 2782 intel_encoder->enable = g4x_enable_hdmi;
89b667f8 2783 }
5ab432ef 2784
b9cb234c 2785 intel_encoder->type = INTEL_OUTPUT_HDMI;
79f255a0 2786 intel_encoder->power_domain = intel_port_to_power_domain(port);
03cdc1d4 2787 intel_encoder->port = port;
920a14b2 2788 if (IS_CHERRYVIEW(dev_priv)) {
882ec384
VS		 2789 if (port == PORT_D)
2790 intel_encoder->crtc_mask = 1 << 2;
2791 else
2792 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2793 } else {
2794 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2795 }
301ea74a 2796 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
c6f1495d
VS		 2797 /*
2798 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2799 * to work on real hardware. And since g4x can send infoframes to
2800 * only one port anyway, nothing is lost by allowing it.
2801 */
9beb5fea 2802 if (IS_G4X(dev_priv))
c6f1495d 2803 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
7d57382e 2804
b242b7f7 2805 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
f0f59a00 2806 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
ccb1a831 2807 intel_dig_port->max_lanes = 4;
55b7d6e8 2808
385e4de0
VS		 2809 intel_infoframe_init(intel_dig_port);
2810
39053089 2811 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
b9cb234c 2812 intel_hdmi_init_connector(intel_dig_port, intel_connector);
7d57382e 2813}
Linux 6.x block layer and io_uring tree(s)