[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_hdmi.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include "drmP.h"
#include "drm.h"
#include "drm_crtc.h"
#include "drm_edid.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

struct intel_hdmi {
	struct intel_encoder base;
	u32 sdvox_reg;
	int ddc_bus;
	uint32_t color_range;
	bool has_hdmi_sink;
	bool has_audio;
	int force_audio;
	void (*write_infoframe)(struct drm_encoder *encoder,
				struct dip_infoframe *frame);
};

static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_hdmi, base.base);
}

static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_hdmi, base);
}

void intel_dip_infoframe_csum(struct dip_infoframe *frame)
{
	uint8_t *data = (uint8_t *)frame;
	uint8_t sum = 0;
	unsigned i;

	frame->checksum = 0;
	frame->ecc = 0;

	/* Header isn't part of the checksum */
	for (i = 5; i < frame->len; i++)
		sum += data[i];

	frame->checksum = 0x100 - sum;
}

static u32 intel_infoframe_index(struct dip_infoframe *frame)
{
	u32 flags = 0;

	switch (frame->type) {
	case DIP_TYPE_AVI:
		flags |= VIDEO_DIP_SELECT_AVI;
		break;
	case DIP_TYPE_SPD:
		flags |= VIDEO_DIP_SELECT_SPD;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		break;
	}

	return flags;
}

static u32 intel_infoframe_flags(struct dip_infoframe *frame)
{
	u32 flags = 0;

	switch (frame->type) {
	case DIP_TYPE_AVI:
		flags |= VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_FREQ_VSYNC;
		break;
	case DIP_TYPE_SPD:
		flags |= VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_FREQ_2VSYNC;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
		break;
	}

	return flags;
}

static void i9xx_write_infoframe(struct drm_encoder *encoder,
				 struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;


	/* XXX first guess at handling video port, is this corrent? */
	if (intel_hdmi->sdvox_reg == SDVOB)
		port = VIDEO_DIP_PORT_B;
	else if (intel_hdmi->sdvox_reg == SDVOC)
		port = VIDEO_DIP_PORT_C;
	else
		return;

	flags = intel_infoframe_index(frame);

	val &= ~VIDEO_DIP_SELECT_MASK;

	I915_WRITE(VIDEO_DIP_CTL, val | port | flags);

	for (i = 0; i < len; i += 4) {
		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}

	flags |= intel_infoframe_flags(frame);

	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE | val | port | flags);
}

static void ironlake_write_infoframe(struct drm_encoder *encoder,
				     struct dip_infoframe *frame)
{
	uint32_t *data = (uint32_t *)frame;
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	unsigned i, len = DIP_HEADER_SIZE + frame->len;
	u32 flags, val = I915_READ(reg);

	intel_wait_for_vblank(dev, intel_crtc->pipe);

	flags = intel_infoframe_index(frame);

	val &= ~VIDEO_DIP_SELECT_MASK;

	I915_WRITE(reg, val | flags);

	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}

	flags |= intel_infoframe_flags(frame);

	I915_WRITE(reg, VIDEO_DIP_ENABLE | val | flags);
}
static void intel_set_infoframe(struct drm_encoder *encoder,
				struct dip_infoframe *frame)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);

	if (!intel_hdmi->has_hdmi_sink)
		return;

	intel_dip_infoframe_csum(frame);
	intel_hdmi->write_infoframe(encoder, frame);
}

static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
{
	struct dip_infoframe avi_if = {
		.type = DIP_TYPE_AVI,
		.ver = DIP_VERSION_AVI,
		.len = DIP_LEN_AVI,
	};

	intel_set_infoframe(encoder, &avi_if);
}

static void intel_hdmi_mode_set(struct drm_encoder *encoder,
				struct drm_display_mode *mode,
				struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = encoder->crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 sdvox;

	sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE;
	if (!HAS_PCH_SPLIT(dev))
		sdvox |= intel_hdmi->color_range;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		sdvox |= SDVO_HSYNC_ACTIVE_HIGH;

	if (intel_crtc->bpp > 24)
		sdvox |= COLOR_FORMAT_12bpc;
	else
		sdvox |= COLOR_FORMAT_8bpc;

	/* Required on CPT */
	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
		sdvox |= HDMI_MODE_SELECT;

	if (intel_hdmi->has_audio) {
		sdvox |= SDVO_AUDIO_ENABLE;
		sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC;
	}

	if (intel_crtc->pipe == 1) {
		if (HAS_PCH_CPT(dev))
			sdvox |= PORT_TRANS_B_SEL_CPT;
		else
			sdvox |= SDVO_PIPE_B_SELECT;
	}

	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
	POSTING_READ(intel_hdmi->sdvox_reg);

	intel_hdmi_set_avi_infoframe(encoder);
}

static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 temp;

	temp = I915_READ(intel_hdmi->sdvox_reg);

	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}

	if (mode != DRM_MODE_DPMS_ON) {
		temp &= ~SDVO_ENABLE;
	} else {
		temp |= SDVO_ENABLE;
	}

	I915_WRITE(intel_hdmi->sdvox_reg, temp);
	POSTING_READ(intel_hdmi->sdvox_reg);

	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
		I915_WRITE(intel_hdmi->sdvox_reg, temp);
		POSTING_READ(intel_hdmi->sdvox_reg);
	}
}

static int intel_hdmi_mode_valid(struct drm_connector *connector,
				 struct drm_display_mode *mode)
{
	if (mode->clock > 165000)
		return MODE_CLOCK_HIGH;
	if (mode->clock < 20000)
		return MODE_CLOCK_LOW;

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	return MODE_OK;
}

static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
				  struct drm_display_mode *mode,
				  struct drm_display_mode *adjusted_mode)
{
	return true;
}

static enum drm_connector_status
intel_hdmi_detect(struct drm_connector *connector, bool force)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	enum drm_connector_status status = connector_status_disconnected;

	intel_hdmi->has_hdmi_sink = false;
	intel_hdmi->has_audio = false;
	edid = drm_get_edid(connector,
			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);

	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
			status = connector_status_connected;
			intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
		}
		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	if (status == connector_status_connected) {
		if (intel_hdmi->force_audio)
			intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
	}

	return status;
}

static int intel_hdmi_get_modes(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	/* We should parse the EDID data and find out if it's an HDMI sink so
	 * we can send audio to it.
	 */

	return intel_ddc_get_modes(connector,
				   &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
}

static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	struct edid *edid;
	bool has_audio = false;

	edid = drm_get_edid(connector,
			    &dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL)
			has_audio = drm_detect_monitor_audio(edid);

		connector->display_info.raw_edid = NULL;
		kfree(edid);
	}

	return has_audio;
}

static int
intel_hdmi_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	int ret;

	ret = drm_connector_property_set_value(connector, property, val);
	if (ret)
		return ret;

	if (property == dev_priv->force_audio_property) {
		int i = val;
		bool has_audio;

		if (i == intel_hdmi->force_audio)
			return 0;

		intel_hdmi->force_audio = i;

		if (i == 0)
			has_audio = intel_hdmi_detect_audio(connector);
		else
			has_audio = i > 0;

		if (has_audio == intel_hdmi->has_audio)
			return 0;

		intel_hdmi->has_audio = has_audio;
		goto done;
	}

	if (property == dev_priv->broadcast_rgb_property) {
		if (val == !!intel_hdmi->color_range)
			return 0;

		intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
		goto done;
	}

	return -EINVAL;

done:
	if (intel_hdmi->base.base.crtc) {
		struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
		drm_crtc_helper_set_mode(crtc, &crtc->mode,
					 crtc->x, crtc->y,
					 crtc->fb);
	}

	return 0;
}

static void intel_hdmi_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	.dpms = intel_hdmi_dpms,
	.mode_fixup = intel_hdmi_mode_fixup,
	.prepare = intel_encoder_prepare,
	.mode_set = intel_hdmi_mode_set,
	.commit = intel_encoder_commit,
};

static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
	.dpms = drm_helper_connector_dpms,
	.detect = intel_hdmi_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.set_property = intel_hdmi_set_property,
	.destroy = intel_hdmi_destroy,
};

static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
	.best_encoder = intel_best_encoder,
};

static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
	.destroy = intel_encoder_destroy,
};

static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
	intel_attach_force_audio_property(connector);
	intel_attach_broadcast_rgb_property(connector);
}

void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_connector *connector;
	struct intel_encoder *intel_encoder;
	struct intel_connector *intel_connector;
	struct intel_hdmi *intel_hdmi;

	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
	if (!intel_hdmi)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_hdmi);
		return;
	}

	intel_encoder = &intel_hdmi->base;
	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

	connector = &intel_connector->base;
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
			   DRM_MODE_CONNECTOR_HDMIA);
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

	intel_encoder->type = INTEL_OUTPUT_HDMI;

	connector->polled = DRM_CONNECTOR_POLL_HPD;
	connector->interlace_allowed = 0;
	connector->doublescan_allowed = 0;
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1);

	/* Set up the DDC bus. */
	if (sdvox_reg == SDVOB) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == SDVOC) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMIB) {
		intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
		dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMIC) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
		dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS;
	} else if (sdvox_reg == HDMID) {
		intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
		intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
		dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS;
	}

	intel_hdmi->sdvox_reg = sdvox_reg;

	if (!HAS_PCH_SPLIT(dev))
		intel_hdmi->write_infoframe = i9xx_write_infoframe;
	else
		intel_hdmi->write_infoframe = ironlake_write_infoframe;

	drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);

	intel_hdmi_add_properties(intel_hdmi, connector);

	intel_connector_attach_encoder(intel_connector, intel_encoder);
	drm_sysfs_connector_add(connector);

	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}
Commit	Line	Data
7d57382e EA	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2009 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	* Jesse Barnes <jesse.barnes@intel.com>
	27	*/
	28
	29	#include <linux/i2c.h>
5a0e3ad6	30	#include <linux/slab.h>
7d57382e EA	31	#include <linux/delay.h>
	32	#include "drmP.h"
	33	#include "drm.h"
	34	#include "drm_crtc.h"
aa93d632	35	#include "drm_edid.h"
7d57382e EA	36	#include "intel_drv.h"
	37	#include "i915_drm.h"
	38	#include "i915_drv.h"
	39
ea5b213a CW	40	struct intel_hdmi {
ea5b213a CW	41	struct intel_encoder base;
7d57382e	42	u32 sdvox_reg;
f899fc64	43	int ddc_bus;
e953fd7b	44	uint32_t color_range;
9dff6af8	45	bool has_hdmi_sink;
2e3d6006	46	bool has_audio;
55b7d6e8	47	int force_audio;
45187ace JB	48	void (write_infoframe)(struct drm_encoder encoder,
45187ace JB	49	struct dip_infoframe *frame);
7d57382e EA	50	};
7d57382e EA	51
ea5b213a CW	52	static struct intel_hdmi enc_to_intel_hdmi(struct drm_encoder encoder)
ea5b213a CW	53	{
4ef69c7a	54	return container_of(encoder, struct intel_hdmi, base.base);
ea5b213a CW	55	}
ea5b213a CW	56
df0e9248 CW	57	static struct intel_hdmi intel_attached_hdmi(struct drm_connector connector)
	58	{
	59	return container_of(intel_attached_encoder(connector),
	60	struct intel_hdmi, base);
	61	}
	62
45187ace	63	void intel_dip_infoframe_csum(struct dip_infoframe *frame)
3c17fe4b	64	{
45187ace	65	uint8_t data = (uint8_t )frame;
3c17fe4b DH	66	uint8_t sum = 0;
	67	unsigned i;
	68
45187ace JB	69	frame->checksum = 0;
45187ace JB	70	frame->ecc = 0;
3c17fe4b	71
45187ace JB	72	/* Header isn't part of the checksum */
45187ace JB	73	for (i = 5; i < frame->len; i++)
3c17fe4b DH	74	sum += data[i];
3c17fe4b DH	75
45187ace	76	frame->checksum = 0x100 - sum;
3c17fe4b DH	77	}
3c17fe4b DH	78
45187ace	79	static u32 intel_infoframe_index(struct dip_infoframe *frame)
3c17fe4b	80	{
45187ace JB	81	u32 flags = 0;
	82
	83	switch (frame->type) {
	84	case DIP_TYPE_AVI:
	85	flags \|= VIDEO_DIP_SELECT_AVI;
	86	break;
	87	case DIP_TYPE_SPD:
	88	flags \|= VIDEO_DIP_SELECT_SPD;
	89	break;
	90	default:
	91	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
	92	break;
	93	}
	94
	95	return flags;
	96	}
	97
	98	static u32 intel_infoframe_flags(struct dip_infoframe *frame)
	99	{
	100	u32 flags = 0;
	101
	102	switch (frame->type) {
	103	case DIP_TYPE_AVI:
	104	flags \|= VIDEO_DIP_ENABLE_AVI \| VIDEO_DIP_FREQ_VSYNC;
	105	break;
	106	case DIP_TYPE_SPD:
	107	flags \|= VIDEO_DIP_ENABLE_SPD \| VIDEO_DIP_FREQ_2VSYNC;
	108	break;
	109	default:
	110	DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type);
	111	break;
	112	}
	113
	114	return flags;
	115	}
	116
	117	static void i9xx_write_infoframe(struct drm_encoder *encoder,
	118	struct dip_infoframe *frame)
	119	{
	120	uint32_t data = (uint32_t )frame;
3c17fe4b DH	121	struct drm_device *dev = encoder->dev;
	122	struct drm_i915_private *dev_priv = dev->dev_private;
	123	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
45187ace JB	124	u32 port, flags, val = I915_READ(VIDEO_DIP_CTL);
45187ace JB	125	unsigned i, len = DIP_HEADER_SIZE + frame->len;
3c17fe4b	126
3c17fe4b DH	127
	128	/* XXX first guess at handling video port, is this corrent? */
	129	if (intel_hdmi->sdvox_reg == SDVOB)
	130	port = VIDEO_DIP_PORT_B;
	131	else if (intel_hdmi->sdvox_reg == SDVOC)
	132	port = VIDEO_DIP_PORT_C;
	133	else
	134	return;
	135
45187ace JB	136	flags = intel_infoframe_index(frame);
	137
	138	val &= ~VIDEO_DIP_SELECT_MASK;
	139
	140	I915_WRITE(VIDEO_DIP_CTL, val \| port \| flags);
3c17fe4b	141
45187ace	142	for (i = 0; i < len; i += 4) {
3c17fe4b DH	143	I915_WRITE(VIDEO_DIP_DATA, *data);
	144	data++;
	145	}
	146
45187ace JB	147	flags \|= intel_infoframe_flags(frame);
	148
	149	I915_WRITE(VIDEO_DIP_CTL, VIDEO_DIP_ENABLE \| val \| port \| flags);
3c17fe4b DH	150	}
3c17fe4b DH	151
45187ace JB	152	static void ironlake_write_infoframe(struct drm_encoder *encoder,
45187ace JB	153	struct dip_infoframe *frame)
b055c8f3	154	{
45187ace	155	uint32_t data = (uint32_t )frame;
b055c8f3 JB	156	struct drm_device *dev = encoder->dev;
b055c8f3 JB	157	struct drm_i915_private *dev_priv = dev->dev_private;
b055c8f3 JB	158	struct drm_crtc *crtc = encoder->crtc;
	159	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	160	int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
45187ace JB	161	unsigned i, len = DIP_HEADER_SIZE + frame->len;
45187ace JB	162	u32 flags, val = I915_READ(reg);
b055c8f3 JB	163
	164	intel_wait_for_vblank(dev, intel_crtc->pipe);
	165
45187ace	166	flags = intel_infoframe_index(frame);
b055c8f3	167
45187ace JB	168	val &= ~VIDEO_DIP_SELECT_MASK;
	169
	170	I915_WRITE(reg, val \| flags);
	171
	172	for (i = 0; i < len; i += 4) {
b055c8f3 JB	173	I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
	174	data++;
	175	}
	176
45187ace JB	177	flags \|= intel_infoframe_flags(frame);
	178
	179	I915_WRITE(reg, VIDEO_DIP_ENABLE \| val \| flags);
	180	}
	181	static void intel_set_infoframe(struct drm_encoder *encoder,
	182	struct dip_infoframe *frame)
	183	{
	184	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	185
	186	if (!intel_hdmi->has_hdmi_sink)
	187	return;
	188
	189	intel_dip_infoframe_csum(frame);
	190	intel_hdmi->write_infoframe(encoder, frame);
	191	}
	192
	193	static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
	194	{
	195	struct dip_infoframe avi_if = {
	196	.type = DIP_TYPE_AVI,
	197	.ver = DIP_VERSION_AVI,
	198	.len = DIP_LEN_AVI,
	199	};
	200
	201	intel_set_infoframe(encoder, &avi_if);
b055c8f3 JB	202	}
b055c8f3 JB	203
7d57382e EA	204	static void intel_hdmi_mode_set(struct drm_encoder *encoder,
	205	struct drm_display_mode *mode,
	206	struct drm_display_mode *adjusted_mode)
	207	{
	208	struct drm_device *dev = encoder->dev;
	209	struct drm_i915_private *dev_priv = dev->dev_private;
	210	struct drm_crtc *crtc = encoder->crtc;
	211	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a	212	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
7d57382e EA	213	u32 sdvox;
7d57382e EA	214
b599c0bc	215	sdvox = SDVO_ENCODING_HDMI \| SDVO_BORDER_ENABLE;
5d4fac97 JB	216	if (!HAS_PCH_SPLIT(dev))
5d4fac97 JB	217	sdvox \|= intel_hdmi->color_range;
b599c0bc AJ	218	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	219	sdvox \|= SDVO_VSYNC_ACTIVE_HIGH;
	220	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	221	sdvox \|= SDVO_HSYNC_ACTIVE_HIGH;
7d57382e	222
020f6704 JB	223	if (intel_crtc->bpp > 24)
	224	sdvox \|= COLOR_FORMAT_12bpc;
	225	else
	226	sdvox \|= COLOR_FORMAT_8bpc;
	227
2e3d6006 ZW	228	/* Required on CPT */
	229	if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev))
	230	sdvox \|= HDMI_MODE_SELECT;
	231
3c17fe4b	232	if (intel_hdmi->has_audio) {
7d57382e	233	sdvox \|= SDVO_AUDIO_ENABLE;
3c17fe4b DH	234	sdvox \|= SDVO_NULL_PACKETS_DURING_VSYNC;
3c17fe4b DH	235	}
7d57382e	236
0f229062 ZW	237	if (intel_crtc->pipe == 1) {
	238	if (HAS_PCH_CPT(dev))
	239	sdvox \|= PORT_TRANS_B_SEL_CPT;
	240	else
	241	sdvox \|= SDVO_PIPE_B_SELECT;
	242	}
7d57382e	243
ea5b213a CW	244	I915_WRITE(intel_hdmi->sdvox_reg, sdvox);
ea5b213a CW	245	POSTING_READ(intel_hdmi->sdvox_reg);
3c17fe4b	246
45187ace	247	intel_hdmi_set_avi_infoframe(encoder);
7d57382e EA	248	}
	249
	250	static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode)
	251	{
	252	struct drm_device *dev = encoder->dev;
	253	struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a	254	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
7d57382e EA	255	u32 temp;
7d57382e EA	256
ea5b213a	257	temp = I915_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	258
	259	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	260	* we do this anyway which shows more stable in testing.
	261	*/
c619eed4	262	if (HAS_PCH_SPLIT(dev)) {
ea5b213a CW	263	I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE);
ea5b213a CW	264	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	265	}
	266
	267	if (mode != DRM_MODE_DPMS_ON) {
	268	temp &= ~SDVO_ENABLE;
7d57382e	269	} else {
d8a2d0e0	270	temp \|= SDVO_ENABLE;
7d57382e	271	}
d8a2d0e0	272
ea5b213a CW	273	I915_WRITE(intel_hdmi->sdvox_reg, temp);
ea5b213a CW	274	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0 ZW	275
	276	/* HW workaround, need to write this twice for issue that may result
	277	* in first write getting masked.
	278	*/
c619eed4	279	if (HAS_PCH_SPLIT(dev)) {
ea5b213a CW	280	I915_WRITE(intel_hdmi->sdvox_reg, temp);
ea5b213a CW	281	POSTING_READ(intel_hdmi->sdvox_reg);
d8a2d0e0	282	}
7d57382e EA	283	}
7d57382e EA	284
7d57382e EA	285	static int intel_hdmi_mode_valid(struct drm_connector *connector,
	286	struct drm_display_mode *mode)
	287	{
	288	if (mode->clock > 165000)
	289	return MODE_CLOCK_HIGH;
	290	if (mode->clock < 20000)
5cbba41d	291	return MODE_CLOCK_LOW;
7d57382e EA	292
	293	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	294	return MODE_NO_DBLESCAN;
	295
	296	return MODE_OK;
	297	}
	298
	299	static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder,
	300	struct drm_display_mode *mode,
	301	struct drm_display_mode *adjusted_mode)
	302	{
	303	return true;
	304	}
	305
aa93d632	306	static enum drm_connector_status
930a9e28	307	intel_hdmi_detect(struct drm_connector *connector, bool force)
9dff6af8	308	{
df0e9248	309	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
f899fc64 CW	310	struct drm_i915_private *dev_priv = connector->dev->dev_private;
f899fc64 CW	311	struct edid *edid;
aa93d632	312	enum drm_connector_status status = connector_status_disconnected;
9dff6af8	313
ea5b213a	314	intel_hdmi->has_hdmi_sink = false;
2e3d6006	315	intel_hdmi->has_audio = false;
f899fc64 CW	316	edid = drm_get_edid(connector,
f899fc64 CW	317	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
2ded9e27	318
aa93d632	319	if (edid) {
be9f1c4f	320	if (edid->input & DRM_EDID_INPUT_DIGITAL) {
aa93d632	321	status = connector_status_connected;
ea5b213a	322	intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2e3d6006	323	intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
aa93d632	324	}
674e2d08	325	connector->display_info.raw_edid = NULL;
aa93d632	326	kfree(edid);
9dff6af8	327	}
30ad48b7	328
55b7d6e8 CW	329	if (status == connector_status_connected) {
	330	if (intel_hdmi->force_audio)
	331	intel_hdmi->has_audio = intel_hdmi->force_audio > 0;
	332	}
	333
2ded9e27	334	return status;
7d57382e EA	335	}
	336
	337	static int intel_hdmi_get_modes(struct drm_connector *connector)
	338	{
df0e9248	339	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
f899fc64	340	struct drm_i915_private *dev_priv = connector->dev->dev_private;
7d57382e EA	341
	342	/* We should parse the EDID data and find out if it's an HDMI sink so
	343	* we can send audio to it.
	344	*/
	345
f899fc64 CW	346	return intel_ddc_get_modes(connector,
f899fc64 CW	347	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
7d57382e EA	348	}
7d57382e EA	349
1aad7ac0 CW	350	static bool
	351	intel_hdmi_detect_audio(struct drm_connector *connector)
	352	{
	353	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
	354	struct drm_i915_private *dev_priv = connector->dev->dev_private;
	355	struct edid *edid;
	356	bool has_audio = false;
	357
	358	edid = drm_get_edid(connector,
	359	&dev_priv->gmbus[intel_hdmi->ddc_bus].adapter);
	360	if (edid) {
	361	if (edid->input & DRM_EDID_INPUT_DIGITAL)
	362	has_audio = drm_detect_monitor_audio(edid);
	363
	364	connector->display_info.raw_edid = NULL;
	365	kfree(edid);
	366	}
	367
	368	return has_audio;
	369	}
	370
55b7d6e8 CW	371	static int
	372	intel_hdmi_set_property(struct drm_connector *connector,
	373	struct drm_property *property,
	374	uint64_t val)
	375	{
	376	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
e953fd7b	377	struct drm_i915_private *dev_priv = connector->dev->dev_private;
55b7d6e8 CW	378	int ret;
	379
	380	ret = drm_connector_property_set_value(connector, property, val);
	381	if (ret)
	382	return ret;
	383
3f43c48d	384	if (property == dev_priv->force_audio_property) {
1aad7ac0 CW	385	int i = val;
	386	bool has_audio;
	387
	388	if (i == intel_hdmi->force_audio)
55b7d6e8 CW	389	return 0;
55b7d6e8 CW	390
1aad7ac0	391	intel_hdmi->force_audio = i;
55b7d6e8	392
1aad7ac0 CW	393	if (i == 0)
	394	has_audio = intel_hdmi_detect_audio(connector);
	395	else
	396	has_audio = i > 0;
	397
	398	if (has_audio == intel_hdmi->has_audio)
55b7d6e8 CW	399	return 0;
55b7d6e8 CW	400
1aad7ac0	401	intel_hdmi->has_audio = has_audio;
55b7d6e8 CW	402	goto done;
	403	}
	404
e953fd7b CW	405	if (property == dev_priv->broadcast_rgb_property) {
	406	if (val == !!intel_hdmi->color_range)
	407	return 0;
	408
	409	intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
	410	goto done;
	411	}
	412
55b7d6e8 CW	413	return -EINVAL;
	414
	415	done:
	416	if (intel_hdmi->base.base.crtc) {
	417	struct drm_crtc *crtc = intel_hdmi->base.base.crtc;
	418	drm_crtc_helper_set_mode(crtc, &crtc->mode,
	419	crtc->x, crtc->y,
	420	crtc->fb);
	421	}
	422
	423	return 0;
	424	}
	425
7d57382e EA	426	static void intel_hdmi_destroy(struct drm_connector *connector)
7d57382e EA	427	{
7d57382e EA	428	drm_sysfs_connector_remove(connector);
7d57382e EA	429	drm_connector_cleanup(connector);
674e2d08	430	kfree(connector);
7d57382e EA	431	}
	432
	433	static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = {
	434	.dpms = intel_hdmi_dpms,
	435	.mode_fixup = intel_hdmi_mode_fixup,
	436	.prepare = intel_encoder_prepare,
	437	.mode_set = intel_hdmi_mode_set,
	438	.commit = intel_encoder_commit,
	439	};
	440
	441	static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
c9fb15f6	442	.dpms = drm_helper_connector_dpms,
7d57382e EA	443	.detect = intel_hdmi_detect,
7d57382e EA	444	.fill_modes = drm_helper_probe_single_connector_modes,
55b7d6e8	445	.set_property = intel_hdmi_set_property,
7d57382e EA	446	.destroy = intel_hdmi_destroy,
	447	};
	448
	449	static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	450	.get_modes = intel_hdmi_get_modes,
	451	.mode_valid = intel_hdmi_mode_valid,
df0e9248	452	.best_encoder = intel_best_encoder,
7d57382e EA	453	};
7d57382e EA	454
7d57382e	455	static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
ea5b213a	456	.destroy = intel_encoder_destroy,
7d57382e EA	457	};
7d57382e EA	458
55b7d6e8 CW	459	static void
	460	intel_hdmi_add_properties(struct intel_hdmi intel_hdmi, struct drm_connector connector)
	461	{
3f43c48d	462	intel_attach_force_audio_property(connector);
e953fd7b	463	intel_attach_broadcast_rgb_property(connector);
55b7d6e8 CW	464	}
55b7d6e8 CW	465
7d57382e EA	466	void intel_hdmi_init(struct drm_device *dev, int sdvox_reg)
	467	{
	468	struct drm_i915_private *dev_priv = dev->dev_private;
	469	struct drm_connector *connector;
21d40d37	470	struct intel_encoder *intel_encoder;
674e2d08	471	struct intel_connector *intel_connector;
ea5b213a	472	struct intel_hdmi *intel_hdmi;
7d57382e	473
ea5b213a CW	474	intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL);
ea5b213a CW	475	if (!intel_hdmi)
7d57382e	476	return;
674e2d08 ZW	477
	478	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	479	if (!intel_connector) {
ea5b213a	480	kfree(intel_hdmi);
674e2d08 ZW	481	return;
	482	}
	483
ea5b213a	484	intel_encoder = &intel_hdmi->base;
373a3cf7 CW	485	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
	486	DRM_MODE_ENCODER_TMDS);
	487
674e2d08	488	connector = &intel_connector->base;
7d57382e	489	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
8d91104a	490	DRM_MODE_CONNECTOR_HDMIA);
7d57382e EA	491	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
7d57382e EA	492
21d40d37	493	intel_encoder->type = INTEL_OUTPUT_HDMI;
7d57382e	494
eb1f8e4f	495	connector->polled = DRM_CONNECTOR_POLL_HPD;
7d57382e EA	496	connector->interlace_allowed = 0;
7d57382e EA	497	connector->doublescan_allowed = 0;
21d40d37	498	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
7d57382e EA	499
7d57382e EA	500	/* Set up the DDC bus. */
f8aed700	501	if (sdvox_reg == SDVOB) {
21d40d37	502	intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT);
f899fc64	503	intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
b01f2c3a	504	dev_priv->hotplug_supported_mask \|= HDMIB_HOTPLUG_INT_STATUS;
f8aed700	505	} else if (sdvox_reg == SDVOC) {
21d40d37	506	intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT);
f899fc64	507	intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
b01f2c3a	508	dev_priv->hotplug_supported_mask \|= HDMIC_HOTPLUG_INT_STATUS;
f8aed700	509	} else if (sdvox_reg == HDMIB) {
21d40d37	510	intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT);
f899fc64	511	intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
b01f2c3a	512	dev_priv->hotplug_supported_mask \|= HDMIB_HOTPLUG_INT_STATUS;
f8aed700	513	} else if (sdvox_reg == HDMIC) {
21d40d37	514	intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT);
f899fc64	515	intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
b01f2c3a	516	dev_priv->hotplug_supported_mask \|= HDMIC_HOTPLUG_INT_STATUS;
f8aed700	517	} else if (sdvox_reg == HDMID) {
21d40d37	518	intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT);
f899fc64	519	intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
b01f2c3a	520	dev_priv->hotplug_supported_mask \|= HDMID_HOTPLUG_INT_STATUS;
f8aed700	521	}
7d57382e	522
ea5b213a	523	intel_hdmi->sdvox_reg = sdvox_reg;
7d57382e	524
45187ace JB	525	if (!HAS_PCH_SPLIT(dev))
	526	intel_hdmi->write_infoframe = i9xx_write_infoframe;
	527	else
	528	intel_hdmi->write_infoframe = ironlake_write_infoframe;
	529
4ef69c7a	530	drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs);
7d57382e	531
55b7d6e8 CW	532	intel_hdmi_add_properties(intel_hdmi, connector);
55b7d6e8 CW	533
df0e9248	534	intel_connector_attach_encoder(intel_connector, intel_encoder);
7d57382e EA	535	drm_sysfs_connector_add(connector);
	536
	537	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	538	* 0xd. Failure to do so will result in spurious interrupts being
	539	* generated on the port when a cable is not attached.
	540	*/
	541	if (IS_G4X(dev) && !IS_GM45(dev)) {
	542	u32 temp = I915_READ(PEG_BAND_GAP_DATA);
	543	I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) \| 0xd);
	544	}
7d57382e	545	}