Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
7d57382e | 29 | #include <linux/delay.h> |
178f736a | 30 | #include <linux/hdmi.h> |
331c201a JN |
31 | #include <linux/i2c.h> |
32 | #include <linux/slab.h> | |
33 | ||
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
2320175f | 37 | #include <drm/drm_hdcp.h> |
15953637 | 38 | #include <drm/drm_scdc_helper.h> |
760285e7 | 39 | #include <drm/i915_drm.h> |
46d196ec | 40 | #include <drm/intel_lpe_audio.h> |
331c201a | 41 | |
7d57382e | 42 | #include "i915_drv.h" |
331c201a | 43 | #include "intel_audio.h" |
ec7f29ff | 44 | #include "intel_connector.h" |
fdc24cf3 | 45 | #include "intel_ddi.h" |
331c201a | 46 | #include "intel_drv.h" |
408bd917 | 47 | #include "intel_hdcp.h" |
f3e18947 | 48 | #include "intel_lspcon.h" |
596fee14 | 49 | #include "intel_sdvo.h" |
7d57382e | 50 | |
30add22d PZ |
51 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
52 | { | |
da63a9f2 | 53 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
54 | } |
55 | ||
afba0188 DV |
56 | static void |
57 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
58 | { | |
30add22d | 59 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 60 | struct drm_i915_private *dev_priv = to_i915(dev); |
faa087c4 | 61 | u32 enabled_bits; |
afba0188 | 62 | |
4f8036a2 | 63 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 64 | |
b242b7f7 | 65 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
66 | "HDMI port enabled, expecting disabled\n"); |
67 | } | |
68 | ||
8fc0aa6e ID |
69 | static void |
70 | assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, | |
71 | enum transcoder cpu_transcoder) | |
72 | { | |
73 | WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & | |
74 | TRANS_DDI_FUNC_ENABLE, | |
75 | "HDMI transcoder function enabled, expecting disabled\n"); | |
76 | } | |
77 | ||
f5bbfca3 | 78 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 79 | { |
da63a9f2 PZ |
80 | struct intel_digital_port *intel_dig_port = |
81 | container_of(encoder, struct intel_digital_port, base.base); | |
82 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
83 | } |
84 | ||
df0e9248 CW |
85 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
86 | { | |
da63a9f2 | 87 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
88 | } |
89 | ||
1d776538 | 90 | static u32 g4x_infoframe_index(unsigned int type) |
3c17fe4b | 91 | { |
178f736a | 92 | switch (type) { |
5cb3c1a1 VS |
93 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
94 | return VIDEO_DIP_SELECT_GAMUT; | |
178f736a | 95 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 96 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 97 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 98 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
99 | case HDMI_INFOFRAME_TYPE_VENDOR: |
100 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 101 | default: |
ffc85dab | 102 | MISSING_CASE(type); |
ed517fbb | 103 | return 0; |
45187ace | 104 | } |
45187ace JB |
105 | } |
106 | ||
1d776538 | 107 | static u32 g4x_infoframe_enable(unsigned int type) |
45187ace | 108 | { |
178f736a | 109 | switch (type) { |
5cb3c1a1 VS |
110 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
111 | return VIDEO_DIP_ENABLE_GCP; | |
112 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
113 | return VIDEO_DIP_ENABLE_GAMUT; | |
509efa2b VS |
114 | case DP_SDP_VSC: |
115 | return 0; | |
178f736a | 116 | case HDMI_INFOFRAME_TYPE_AVI: |
ed517fbb | 117 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 118 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 119 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
120 | case HDMI_INFOFRAME_TYPE_VENDOR: |
121 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 122 | default: |
ffc85dab | 123 | MISSING_CASE(type); |
ed517fbb | 124 | return 0; |
fa193ff7 | 125 | } |
fa193ff7 PZ |
126 | } |
127 | ||
1d776538 | 128 | static u32 hsw_infoframe_enable(unsigned int type) |
2da8af54 | 129 | { |
178f736a | 130 | switch (type) { |
5cb3c1a1 VS |
131 | case HDMI_PACKET_TYPE_GENERAL_CONTROL: |
132 | return VIDEO_DIP_ENABLE_GCP_HSW; | |
133 | case HDMI_PACKET_TYPE_GAMUT_METADATA: | |
134 | return VIDEO_DIP_ENABLE_GMP_HSW; | |
1d776538 VS |
135 | case DP_SDP_VSC: |
136 | return VIDEO_DIP_ENABLE_VSC_HSW; | |
4c614831 MN |
137 | case DP_SDP_PPS: |
138 | return VDIP_ENABLE_PPS; | |
178f736a | 139 | case HDMI_INFOFRAME_TYPE_AVI: |
2da8af54 | 140 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 141 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 142 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
143 | case HDMI_INFOFRAME_TYPE_VENDOR: |
144 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 145 | default: |
ffc85dab | 146 | MISSING_CASE(type); |
2da8af54 PZ |
147 | return 0; |
148 | } | |
149 | } | |
150 | ||
f0f59a00 VS |
151 | static i915_reg_t |
152 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
153 | enum transcoder cpu_transcoder, | |
1d776538 | 154 | unsigned int type, |
f0f59a00 | 155 | int i) |
2da8af54 | 156 | { |
178f736a | 157 | switch (type) { |
5cb3c1a1 VS |
158 | case HDMI_PACKET_TYPE_GAMUT_METADATA: |
159 | return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); | |
1d776538 VS |
160 | case DP_SDP_VSC: |
161 | return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); | |
4c614831 MN |
162 | case DP_SDP_PPS: |
163 | return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); | |
178f736a | 164 | case HDMI_INFOFRAME_TYPE_AVI: |
436c6d4a | 165 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 166 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 167 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 168 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 169 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 170 | default: |
ffc85dab | 171 | MISSING_CASE(type); |
f0f59a00 | 172 | return INVALID_MMIO_REG; |
2da8af54 PZ |
173 | } |
174 | } | |
175 | ||
4c614831 MN |
176 | static int hsw_dip_data_size(unsigned int type) |
177 | { | |
178 | switch (type) { | |
179 | case DP_SDP_VSC: | |
180 | return VIDEO_DIP_VSC_DATA_SIZE; | |
181 | case DP_SDP_PPS: | |
182 | return VIDEO_DIP_PPS_DATA_SIZE; | |
183 | default: | |
184 | return VIDEO_DIP_DATA_SIZE; | |
185 | } | |
186 | } | |
187 | ||
790ea70c | 188 | static void g4x_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 189 | const struct intel_crtc_state *crtc_state, |
1d776538 | 190 | unsigned int type, |
fff63867 | 191 | const void *frame, ssize_t len) |
45187ace | 192 | { |
faa087c4 | 193 | const u32 *data = frame; |
790ea70c | 194 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
22509ec8 | 195 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 196 | int i; |
3c17fe4b | 197 | |
822974ae PZ |
198 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
199 | ||
1d4f85ac | 200 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 201 | val |= g4x_infoframe_index(type); |
22509ec8 | 202 | |
178f736a | 203 | val &= ~g4x_infoframe_enable(type); |
45187ace | 204 | |
22509ec8 | 205 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 206 | |
9d9740f0 | 207 | mmiowb(); |
45187ace | 208 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
209 | I915_WRITE(VIDEO_DIP_DATA, *data); |
210 | data++; | |
211 | } | |
adf00b26 PZ |
212 | /* Write every possible data byte to force correct ECC calculation. */ |
213 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
214 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 215 | mmiowb(); |
3c17fe4b | 216 | |
178f736a | 217 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 218 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 219 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 220 | |
22509ec8 | 221 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 222 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
223 | } |
224 | ||
f2a10d61 VS |
225 | static void g4x_read_infoframe(struct intel_encoder *encoder, |
226 | const struct intel_crtc_state *crtc_state, | |
227 | unsigned int type, | |
228 | void *frame, ssize_t len) | |
229 | { | |
230 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
231 | u32 val, *data = frame; | |
232 | int i; | |
233 | ||
234 | val = I915_READ(VIDEO_DIP_CTL); | |
235 | ||
236 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
237 | val |= g4x_infoframe_index(type); | |
238 | ||
239 | I915_WRITE(VIDEO_DIP_CTL, val); | |
240 | ||
241 | for (i = 0; i < len; i += 4) | |
242 | *data++ = I915_READ(VIDEO_DIP_DATA); | |
243 | } | |
244 | ||
509efa2b | 245 | static u32 g4x_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 246 | const struct intel_crtc_state *pipe_config) |
e43823ec | 247 | { |
790ea70c | 248 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
e43823ec JB |
249 | u32 val = I915_READ(VIDEO_DIP_CTL); |
250 | ||
ec1dc603 | 251 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 252 | return 0; |
89a35ecd | 253 | |
790ea70c | 254 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 255 | return 0; |
ec1dc603 VS |
256 | |
257 | return val & (VIDEO_DIP_ENABLE_AVI | | |
258 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
259 | } |
260 | ||
790ea70c | 261 | static void ibx_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 262 | const struct intel_crtc_state *crtc_state, |
1d776538 | 263 | unsigned int type, |
fff63867 | 264 | const void *frame, ssize_t len) |
fdf1250a | 265 | { |
faa087c4 | 266 | const u32 *data = frame; |
790ea70c | 267 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 268 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 269 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 270 | u32 val = I915_READ(reg); |
f0f59a00 | 271 | int i; |
fdf1250a | 272 | |
822974ae PZ |
273 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
274 | ||
fdf1250a | 275 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 276 | val |= g4x_infoframe_index(type); |
fdf1250a | 277 | |
178f736a | 278 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
279 | |
280 | I915_WRITE(reg, val); | |
281 | ||
9d9740f0 | 282 | mmiowb(); |
fdf1250a PZ |
283 | for (i = 0; i < len; i += 4) { |
284 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
285 | data++; | |
286 | } | |
adf00b26 PZ |
287 | /* Write every possible data byte to force correct ECC calculation. */ |
288 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
289 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 290 | mmiowb(); |
fdf1250a | 291 | |
178f736a | 292 | val |= g4x_infoframe_enable(type); |
fdf1250a | 293 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 294 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
295 | |
296 | I915_WRITE(reg, val); | |
9d9740f0 | 297 | POSTING_READ(reg); |
fdf1250a PZ |
298 | } |
299 | ||
f2a10d61 VS |
300 | static void ibx_read_infoframe(struct intel_encoder *encoder, |
301 | const struct intel_crtc_state *crtc_state, | |
302 | unsigned int type, | |
303 | void *frame, ssize_t len) | |
304 | { | |
305 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
306 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
307 | u32 val, *data = frame; | |
308 | int i; | |
309 | ||
310 | val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); | |
311 | ||
312 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
313 | val |= g4x_infoframe_index(type); | |
314 | ||
315 | I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); | |
316 | ||
317 | for (i = 0; i < len; i += 4) | |
318 | *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); | |
319 | } | |
320 | ||
509efa2b | 321 | static u32 ibx_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 322 | const struct intel_crtc_state *pipe_config) |
e43823ec | 323 | { |
790ea70c | 324 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
325 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
326 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
327 | u32 val = I915_READ(reg); |
328 | ||
ec1dc603 | 329 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 330 | return 0; |
ec1dc603 | 331 | |
790ea70c | 332 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 333 | return 0; |
052f62f7 | 334 | |
ec1dc603 VS |
335 | return val & (VIDEO_DIP_ENABLE_AVI | |
336 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
337 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
338 | } |
339 | ||
790ea70c | 340 | static void cpt_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 341 | const struct intel_crtc_state *crtc_state, |
1d776538 | 342 | unsigned int type, |
fff63867 | 343 | const void *frame, ssize_t len) |
b055c8f3 | 344 | { |
faa087c4 | 345 | const u32 *data = frame; |
790ea70c | 346 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 347 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 348 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 349 | u32 val = I915_READ(reg); |
f0f59a00 | 350 | int i; |
b055c8f3 | 351 | |
822974ae PZ |
352 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
353 | ||
64a8fc01 | 354 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 355 | val |= g4x_infoframe_index(type); |
45187ace | 356 | |
ecb97851 PZ |
357 | /* The DIP control register spec says that we need to update the AVI |
358 | * infoframe without clearing its enable bit */ | |
178f736a DL |
359 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
360 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 361 | |
22509ec8 | 362 | I915_WRITE(reg, val); |
45187ace | 363 | |
9d9740f0 | 364 | mmiowb(); |
45187ace | 365 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
366 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
367 | data++; | |
368 | } | |
adf00b26 PZ |
369 | /* Write every possible data byte to force correct ECC calculation. */ |
370 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
371 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 372 | mmiowb(); |
b055c8f3 | 373 | |
178f736a | 374 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 375 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 376 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 377 | |
22509ec8 | 378 | I915_WRITE(reg, val); |
9d9740f0 | 379 | POSTING_READ(reg); |
45187ace | 380 | } |
90b107c8 | 381 | |
f2a10d61 VS |
382 | static void cpt_read_infoframe(struct intel_encoder *encoder, |
383 | const struct intel_crtc_state *crtc_state, | |
384 | unsigned int type, | |
385 | void *frame, ssize_t len) | |
386 | { | |
387 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
388 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
389 | u32 val, *data = frame; | |
390 | int i; | |
391 | ||
392 | val = I915_READ(TVIDEO_DIP_CTL(crtc->pipe)); | |
393 | ||
394 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
395 | val |= g4x_infoframe_index(type); | |
396 | ||
397 | I915_WRITE(TVIDEO_DIP_CTL(crtc->pipe), val); | |
398 | ||
399 | for (i = 0; i < len; i += 4) | |
400 | *data++ = I915_READ(TVIDEO_DIP_DATA(crtc->pipe)); | |
401 | } | |
402 | ||
509efa2b | 403 | static u32 cpt_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 404 | const struct intel_crtc_state *pipe_config) |
e43823ec | 405 | { |
790ea70c | 406 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
407 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
408 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 409 | |
ec1dc603 | 410 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 411 | return 0; |
ec1dc603 VS |
412 | |
413 | return val & (VIDEO_DIP_ENABLE_AVI | | |
414 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
415 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
416 | } |
417 | ||
790ea70c | 418 | static void vlv_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 419 | const struct intel_crtc_state *crtc_state, |
1d776538 | 420 | unsigned int type, |
fff63867 | 421 | const void *frame, ssize_t len) |
90b107c8 | 422 | { |
faa087c4 | 423 | const u32 *data = frame; |
790ea70c | 424 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 425 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 426 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 427 | u32 val = I915_READ(reg); |
f0f59a00 | 428 | int i; |
90b107c8 | 429 | |
822974ae PZ |
430 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
431 | ||
90b107c8 | 432 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 433 | val |= g4x_infoframe_index(type); |
22509ec8 | 434 | |
178f736a | 435 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 436 | |
22509ec8 | 437 | I915_WRITE(reg, val); |
90b107c8 | 438 | |
9d9740f0 | 439 | mmiowb(); |
90b107c8 SK |
440 | for (i = 0; i < len; i += 4) { |
441 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
442 | data++; | |
443 | } | |
adf00b26 PZ |
444 | /* Write every possible data byte to force correct ECC calculation. */ |
445 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
446 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 447 | mmiowb(); |
90b107c8 | 448 | |
178f736a | 449 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 450 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 451 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 452 | |
22509ec8 | 453 | I915_WRITE(reg, val); |
9d9740f0 | 454 | POSTING_READ(reg); |
90b107c8 SK |
455 | } |
456 | ||
f2a10d61 VS |
457 | static void vlv_read_infoframe(struct intel_encoder *encoder, |
458 | const struct intel_crtc_state *crtc_state, | |
459 | unsigned int type, | |
460 | void *frame, ssize_t len) | |
461 | { | |
462 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
463 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
464 | u32 val, *data = frame; | |
465 | int i; | |
466 | ||
467 | val = I915_READ(VLV_TVIDEO_DIP_CTL(crtc->pipe)); | |
468 | ||
469 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
470 | val |= g4x_infoframe_index(type); | |
471 | ||
472 | I915_WRITE(VLV_TVIDEO_DIP_CTL(crtc->pipe), val); | |
473 | ||
474 | for (i = 0; i < len; i += 4) | |
475 | *data++ = I915_READ(VLV_TVIDEO_DIP_DATA(crtc->pipe)); | |
476 | } | |
477 | ||
509efa2b | 478 | static u32 vlv_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 479 | const struct intel_crtc_state *pipe_config) |
e43823ec | 480 | { |
790ea70c | 481 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf VS |
482 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
483 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 484 | |
ec1dc603 | 485 | if ((val & VIDEO_DIP_ENABLE) == 0) |
509efa2b | 486 | return 0; |
ec1dc603 | 487 | |
790ea70c | 488 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) |
509efa2b | 489 | return 0; |
535afa2e | 490 | |
ec1dc603 VS |
491 | return val & (VIDEO_DIP_ENABLE_AVI | |
492 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
493 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
494 | } |
495 | ||
790ea70c | 496 | static void hsw_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 497 | const struct intel_crtc_state *crtc_state, |
1d776538 | 498 | unsigned int type, |
fff63867 | 499 | const void *frame, ssize_t len) |
8c5f5f7c | 500 | { |
faa087c4 | 501 | const u32 *data = frame; |
790ea70c | 502 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 503 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 | 504 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
4c614831 | 505 | int data_size; |
178f736a | 506 | int i; |
2da8af54 | 507 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 508 | |
4c614831 MN |
509 | data_size = hsw_dip_data_size(type); |
510 | ||
178f736a | 511 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
512 | I915_WRITE(ctl_reg, val); |
513 | ||
9d9740f0 | 514 | mmiowb(); |
2da8af54 | 515 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
516 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
517 | type, i >> 2), *data); | |
2da8af54 PZ |
518 | data++; |
519 | } | |
adf00b26 | 520 | /* Write every possible data byte to force correct ECC calculation. */ |
1d776538 | 521 | for (; i < data_size; i += 4) |
436c6d4a VS |
522 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
523 | type, i >> 2), 0); | |
9d9740f0 | 524 | mmiowb(); |
8c5f5f7c | 525 | |
178f736a | 526 | val |= hsw_infoframe_enable(type); |
2da8af54 | 527 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 528 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
529 | } |
530 | ||
f2a10d61 VS |
531 | static void hsw_read_infoframe(struct intel_encoder *encoder, |
532 | const struct intel_crtc_state *crtc_state, | |
533 | unsigned int type, | |
534 | void *frame, ssize_t len) | |
535 | { | |
536 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
537 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; | |
538 | u32 val, *data = frame; | |
539 | int i; | |
540 | ||
541 | val = I915_READ(HSW_TVIDEO_DIP_CTL(cpu_transcoder)); | |
542 | ||
543 | for (i = 0; i < len; i += 4) | |
544 | *data++ = I915_READ(hsw_dip_data_reg(dev_priv, cpu_transcoder, | |
545 | type, i >> 2)); | |
546 | } | |
547 | ||
509efa2b | 548 | static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, |
cda0aaaf | 549 | const struct intel_crtc_state *pipe_config) |
e43823ec | 550 | { |
790ea70c | 551 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
cda0aaaf | 552 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); |
e43823ec | 553 | |
ec1dc603 VS |
554 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
555 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
556 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
557 | } |
558 | ||
509efa2b VS |
559 | static const u8 infoframe_type_to_idx[] = { |
560 | HDMI_PACKET_TYPE_GENERAL_CONTROL, | |
561 | HDMI_PACKET_TYPE_GAMUT_METADATA, | |
562 | DP_SDP_VSC, | |
563 | HDMI_INFOFRAME_TYPE_AVI, | |
564 | HDMI_INFOFRAME_TYPE_SPD, | |
565 | HDMI_INFOFRAME_TYPE_VENDOR, | |
566 | }; | |
567 | ||
fbf08556 VS |
568 | u32 intel_hdmi_infoframe_enable(unsigned int type) |
569 | { | |
570 | int i; | |
571 | ||
572 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
573 | if (infoframe_type_to_idx[i] == type) | |
574 | return BIT(i); | |
575 | } | |
576 | ||
577 | return 0; | |
578 | } | |
579 | ||
509efa2b VS |
580 | u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder, |
581 | const struct intel_crtc_state *crtc_state) | |
582 | { | |
583 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
584 | struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); | |
585 | u32 val, ret = 0; | |
586 | int i; | |
587 | ||
588 | val = dig_port->infoframes_enabled(encoder, crtc_state); | |
589 | ||
590 | /* map from hardware bits to dip idx */ | |
591 | for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) { | |
592 | unsigned int type = infoframe_type_to_idx[i]; | |
593 | ||
594 | if (HAS_DDI(dev_priv)) { | |
595 | if (val & hsw_infoframe_enable(type)) | |
596 | ret |= BIT(i); | |
597 | } else { | |
598 | if (val & g4x_infoframe_enable(type)) | |
599 | ret |= BIT(i); | |
600 | } | |
601 | } | |
602 | ||
603 | return ret; | |
604 | } | |
605 | ||
5adaea79 DL |
606 | /* |
607 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
608 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
609 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
610 | * used for both technologies. | |
611 | * | |
612 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
613 | * DW1: DB3 | DB2 | DB1 | DB0 | |
614 | * DW2: DB7 | DB6 | DB5 | DB4 | |
615 | * DW3: ... | |
616 | * | |
617 | * (HB is Header Byte, DB is Data Byte) | |
618 | * | |
619 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
620 | * trick them by giving an offset into the buffer and moving back the header | |
621 | * bytes by one. | |
622 | */ | |
790ea70c | 623 | static void intel_write_infoframe(struct intel_encoder *encoder, |
ac240288 | 624 | const struct intel_crtc_state *crtc_state, |
fbf08556 VS |
625 | enum hdmi_infoframe_type type, |
626 | const union hdmi_infoframe *frame) | |
45187ace | 627 | { |
790ea70c | 628 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
faa087c4 | 629 | u8 buffer[VIDEO_DIP_DATA_SIZE]; |
5adaea79 | 630 | ssize_t len; |
45187ace | 631 | |
fbf08556 VS |
632 | if ((crtc_state->infoframes.enable & |
633 | intel_hdmi_infoframe_enable(type)) == 0) | |
634 | return; | |
635 | ||
636 | if (WARN_ON(frame->any.type != type)) | |
637 | return; | |
638 | ||
5adaea79 | 639 | /* see comment above for the reason for this offset */ |
fbf08556 VS |
640 | len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); |
641 | if (WARN_ON(len < 0)) | |
5adaea79 DL |
642 | return; |
643 | ||
644 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
121f0ff5 | 645 | memmove(&buffer[0], &buffer[1], 3); |
5adaea79 DL |
646 | buffer[3] = 0; |
647 | len++; | |
45187ace | 648 | |
fbf08556 | 649 | intel_dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); |
45187ace JB |
650 | } |
651 | ||
f2a10d61 VS |
652 | void intel_read_infoframe(struct intel_encoder *encoder, |
653 | const struct intel_crtc_state *crtc_state, | |
654 | enum hdmi_infoframe_type type, | |
655 | union hdmi_infoframe *frame) | |
656 | { | |
657 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
658 | u8 buffer[VIDEO_DIP_DATA_SIZE]; | |
659 | int ret; | |
660 | ||
661 | if ((crtc_state->infoframes.enable & | |
662 | intel_hdmi_infoframe_enable(type)) == 0) | |
663 | return; | |
664 | ||
665 | intel_dig_port->read_infoframe(encoder, crtc_state, | |
666 | type, buffer, sizeof(buffer)); | |
667 | ||
668 | /* Fill the 'hole' (see big comment above) at position 3 */ | |
669 | memmove(&buffer[1], &buffer[0], 3); | |
670 | ||
671 | /* see comment above for the reason for this offset */ | |
672 | ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); | |
673 | if (ret) { | |
674 | DRM_DEBUG_KMS("Failed to unpack infoframe type 0x%02x\n", type); | |
675 | return; | |
676 | } | |
677 | ||
678 | if (frame->any.type != type) | |
679 | DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n", | |
680 | frame->any.type, type); | |
681 | } | |
682 | ||
fbf08556 VS |
683 | static bool |
684 | intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, | |
685 | struct intel_crtc_state *crtc_state, | |
686 | struct drm_connector_state *conn_state) | |
45187ace | 687 | { |
fbf08556 | 688 | struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; |
779c4c28 VS |
689 | const struct drm_display_mode *adjusted_mode = |
690 | &crtc_state->base.adjusted_mode; | |
fbf08556 | 691 | struct drm_connector *connector = conn_state->connector; |
5adaea79 | 692 | int ret; |
45187ace | 693 | |
fbf08556 VS |
694 | if (!crtc_state->has_infoframe) |
695 | return true; | |
696 | ||
697 | crtc_state->infoframes.enable |= | |
698 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); | |
699 | ||
700 | ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, | |
13d0add3 | 701 | adjusted_mode); |
fbf08556 VS |
702 | if (ret) |
703 | return false; | |
c846b619 | 704 | |
33b7f3ee | 705 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) |
fbf08556 | 706 | frame->colorspace = HDMI_COLORSPACE_YUV420; |
8c79f844 | 707 | else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) |
fbf08556 | 708 | frame->colorspace = HDMI_COLORSPACE_YUV444; |
2d8bd2bf | 709 | else |
fbf08556 | 710 | frame->colorspace = HDMI_COLORSPACE_RGB; |
2d8bd2bf | 711 | |
0e2f54f8 | 712 | drm_hdmi_avi_infoframe_colorspace(frame, conn_state); |
2f146b78 | 713 | |
fbf08556 | 714 | drm_hdmi_avi_infoframe_quant_range(frame, connector, |
13d0add3 | 715 | adjusted_mode, |
a2ce26f8 VS |
716 | crtc_state->limited_color_range ? |
717 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
1581b2df | 718 | HDMI_QUANTIZATION_RANGE_FULL); |
abedc077 | 719 | |
fbf08556 | 720 | drm_hdmi_avi_infoframe_content_type(frame, conn_state); |
6553b123 | 721 | |
2d8bd2bf | 722 | /* TODO: handle pixel repetition for YCBCR420 outputs */ |
fbf08556 VS |
723 | |
724 | ret = hdmi_avi_infoframe_check(frame); | |
725 | if (WARN_ON(ret)) | |
726 | return false; | |
727 | ||
728 | return true; | |
b055c8f3 JB |
729 | } |
730 | ||
fbf08556 VS |
731 | static bool |
732 | intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder, | |
733 | struct intel_crtc_state *crtc_state, | |
734 | struct drm_connector_state *conn_state) | |
c0864cb3 | 735 | { |
fbf08556 | 736 | struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; |
5adaea79 DL |
737 | int ret; |
738 | ||
fbf08556 VS |
739 | if (!crtc_state->has_infoframe) |
740 | return true; | |
c0864cb3 | 741 | |
fbf08556 VS |
742 | crtc_state->infoframes.enable |= |
743 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD); | |
c0864cb3 | 744 | |
fbf08556 VS |
745 | ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"); |
746 | if (WARN_ON(ret)) | |
747 | return false; | |
748 | ||
749 | frame->sdi = HDMI_SPD_SDI_PC; | |
750 | ||
751 | ret = hdmi_spd_infoframe_check(frame); | |
752 | if (WARN_ON(ret)) | |
753 | return false; | |
754 | ||
755 | return true; | |
c0864cb3 JB |
756 | } |
757 | ||
fbf08556 VS |
758 | static bool |
759 | intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder, | |
760 | struct intel_crtc_state *crtc_state, | |
761 | struct drm_connector_state *conn_state) | |
762 | { | |
763 | struct hdmi_vendor_infoframe *frame = | |
764 | &crtc_state->infoframes.hdmi.vendor.hdmi; | |
765 | const struct drm_display_info *info = | |
766 | &conn_state->connector->display_info; | |
c8bb75af LD |
767 | int ret; |
768 | ||
fbf08556 VS |
769 | if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) |
770 | return true; | |
771 | ||
772 | crtc_state->infoframes.enable |= | |
773 | intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR); | |
774 | ||
775 | ret = drm_hdmi_vendor_infoframe_from_display_mode(frame, | |
f1781e9b | 776 | conn_state->connector, |
ac240288 | 777 | &crtc_state->base.adjusted_mode); |
fbf08556 VS |
778 | if (WARN_ON(ret)) |
779 | return false; | |
c8bb75af | 780 | |
fbf08556 VS |
781 | ret = hdmi_vendor_infoframe_check(frame); |
782 | if (WARN_ON(ret)) | |
783 | return false; | |
784 | ||
785 | return true; | |
c8bb75af LD |
786 | } |
787 | ||
790ea70c | 788 | static void g4x_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 789 | bool enable, |
ac240288 ML |
790 | const struct intel_crtc_state *crtc_state, |
791 | const struct drm_connector_state *conn_state) | |
687f4d06 | 792 | { |
790ea70c VS |
793 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
794 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); | |
69fde0a6 | 795 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 796 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 797 | u32 val = I915_READ(reg); |
790ea70c | 798 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 799 | |
afba0188 DV |
800 | assert_hdmi_port_disabled(intel_hdmi); |
801 | ||
0c14c7f9 PZ |
802 | /* If the registers were not initialized yet, they might be zeroes, |
803 | * which means we're selecting the AVI DIP and we're setting its | |
804 | * frequency to once. This seems to really confuse the HW and make | |
805 | * things stop working (the register spec says the AVI always needs to | |
806 | * be sent every VSync). So here we avoid writing to the register more | |
807 | * than we need and also explicitly select the AVI DIP and explicitly | |
808 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
809 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
810 | * either. */ | |
811 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
812 | ||
6897b4b5 | 813 | if (!enable) { |
0c14c7f9 PZ |
814 | if (!(val & VIDEO_DIP_ENABLE)) |
815 | return; | |
0be6f0c8 VS |
816 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
817 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
818 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
819 | return; | |
820 | } | |
821 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
822 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 823 | I915_WRITE(reg, val); |
9d9740f0 | 824 | POSTING_READ(reg); |
0c14c7f9 PZ |
825 | return; |
826 | } | |
827 | ||
72b78c9d PZ |
828 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
829 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
830 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
831 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
832 | return; | |
72b78c9d PZ |
833 | } |
834 | val &= ~VIDEO_DIP_PORT_MASK; | |
835 | val |= port; | |
836 | } | |
837 | ||
822974ae | 838 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
839 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
840 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 841 | |
f278d972 | 842 | I915_WRITE(reg, val); |
9d9740f0 | 843 | POSTING_READ(reg); |
f278d972 | 844 | |
fbf08556 VS |
845 | intel_write_infoframe(encoder, crtc_state, |
846 | HDMI_INFOFRAME_TYPE_AVI, | |
847 | &crtc_state->infoframes.avi); | |
848 | intel_write_infoframe(encoder, crtc_state, | |
849 | HDMI_INFOFRAME_TYPE_SPD, | |
850 | &crtc_state->infoframes.spd); | |
851 | intel_write_infoframe(encoder, crtc_state, | |
852 | HDMI_INFOFRAME_TYPE_VENDOR, | |
853 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
854 | } |
855 | ||
ac240288 | 856 | static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state) |
6d67415f | 857 | { |
ac240288 | 858 | struct drm_connector *connector = conn_state->connector; |
6d67415f VS |
859 | |
860 | /* | |
861 | * HDMI cloning is only supported on g4x which doesn't | |
862 | * support deep color or GCP infoframes anyway so no | |
863 | * need to worry about multiple HDMI sinks here. | |
864 | */ | |
6d67415f | 865 | |
ac240288 | 866 | return connector->display_info.bpc > 8; |
6d67415f VS |
867 | } |
868 | ||
12aa3290 VS |
869 | /* |
870 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
871 | * | |
872 | * From HDMI specification 1.4a: | |
873 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
874 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
875 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
876 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
877 | * phase of 0 | |
878 | */ | |
879 | static bool gcp_default_phase_possible(int pipe_bpp, | |
880 | const struct drm_display_mode *mode) | |
881 | { | |
882 | unsigned int pixels_per_group; | |
883 | ||
884 | switch (pipe_bpp) { | |
885 | case 30: | |
886 | /* 4 pixels in 5 clocks */ | |
887 | pixels_per_group = 4; | |
888 | break; | |
889 | case 36: | |
890 | /* 2 pixels in 3 clocks */ | |
891 | pixels_per_group = 2; | |
892 | break; | |
893 | case 48: | |
894 | /* 1 pixel in 2 clocks */ | |
895 | pixels_per_group = 1; | |
896 | break; | |
897 | default: | |
898 | /* phase information not relevant for 8bpc */ | |
899 | return false; | |
900 | } | |
901 | ||
902 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
903 | mode->crtc_htotal % pixels_per_group == 0 && | |
904 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
905 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
906 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
907 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
908 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
909 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
910 | } | |
911 | ||
790ea70c | 912 | static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, |
ac240288 ML |
913 | const struct intel_crtc_state *crtc_state, |
914 | const struct drm_connector_state *conn_state) | |
6d67415f | 915 | { |
790ea70c | 916 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 917 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 918 | i915_reg_t reg; |
fbf08556 VS |
919 | |
920 | if ((crtc_state->infoframes.enable & | |
921 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
922 | return false; | |
6d67415f VS |
923 | |
924 | if (HAS_DDI(dev_priv)) | |
ac240288 | 925 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 926 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 927 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 928 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
929 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
930 | else | |
931 | return false; | |
932 | ||
fbf08556 VS |
933 | I915_WRITE(reg, crtc_state->infoframes.gcp); |
934 | ||
935 | return true; | |
936 | } | |
937 | ||
f2a10d61 VS |
938 | void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, |
939 | struct intel_crtc_state *crtc_state) | |
940 | { | |
941 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
942 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
943 | i915_reg_t reg; | |
944 | ||
945 | if ((crtc_state->infoframes.enable & | |
946 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0) | |
947 | return; | |
948 | ||
949 | if (HAS_DDI(dev_priv)) | |
950 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); | |
951 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
952 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); | |
953 | else if (HAS_PCH_SPLIT(dev_priv)) | |
954 | reg = TVIDEO_DIP_GCP(crtc->pipe); | |
955 | else | |
956 | return; | |
957 | ||
958 | crtc_state->infoframes.gcp = I915_READ(reg); | |
959 | } | |
960 | ||
fbf08556 VS |
961 | static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder, |
962 | struct intel_crtc_state *crtc_state, | |
963 | struct drm_connector_state *conn_state) | |
964 | { | |
965 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
966 | ||
967 | if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) | |
968 | return; | |
969 | ||
970 | crtc_state->infoframes.enable |= | |
971 | intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL); | |
972 | ||
6d67415f | 973 | /* Indicate color depth whenever the sink supports deep color */ |
ac240288 | 974 | if (hdmi_sink_is_deep_color(conn_state)) |
fbf08556 | 975 | crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; |
6d67415f | 976 | |
12aa3290 | 977 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
978 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
979 | &crtc_state->base.adjusted_mode)) | |
fbf08556 | 980 | crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; |
6d67415f VS |
981 | } |
982 | ||
790ea70c | 983 | static void ibx_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 984 | bool enable, |
ac240288 ML |
985 | const struct intel_crtc_state *crtc_state, |
986 | const struct drm_connector_state *conn_state) | |
687f4d06 | 987 | { |
790ea70c | 988 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 989 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 990 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&encoder->base); |
69fde0a6 | 991 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
f0f59a00 | 992 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 993 | u32 val = I915_READ(reg); |
790ea70c | 994 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 995 | |
afba0188 DV |
996 | assert_hdmi_port_disabled(intel_hdmi); |
997 | ||
0c14c7f9 PZ |
998 | /* See the big comment in g4x_set_infoframes() */ |
999 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1000 | ||
6897b4b5 | 1001 | if (!enable) { |
0c14c7f9 PZ |
1002 | if (!(val & VIDEO_DIP_ENABLE)) |
1003 | return; | |
0be6f0c8 VS |
1004 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1005 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1006 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1007 | I915_WRITE(reg, val); |
9d9740f0 | 1008 | POSTING_READ(reg); |
0c14c7f9 PZ |
1009 | return; |
1010 | } | |
1011 | ||
72b78c9d | 1012 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
1013 | WARN(val & VIDEO_DIP_ENABLE, |
1014 | "DIP already enabled on port %c\n", | |
1015 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
1016 | val &= ~VIDEO_DIP_PORT_MASK; |
1017 | val |= port; | |
1018 | } | |
1019 | ||
822974ae | 1020 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1021 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1022 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1023 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1024 | |
ac240288 | 1025 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1026 | val |= VIDEO_DIP_ENABLE_GCP; |
1027 | ||
f278d972 | 1028 | I915_WRITE(reg, val); |
9d9740f0 | 1029 | POSTING_READ(reg); |
f278d972 | 1030 | |
fbf08556 VS |
1031 | intel_write_infoframe(encoder, crtc_state, |
1032 | HDMI_INFOFRAME_TYPE_AVI, | |
1033 | &crtc_state->infoframes.avi); | |
1034 | intel_write_infoframe(encoder, crtc_state, | |
1035 | HDMI_INFOFRAME_TYPE_SPD, | |
1036 | &crtc_state->infoframes.spd); | |
1037 | intel_write_infoframe(encoder, crtc_state, | |
1038 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1039 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1040 | } |
1041 | ||
790ea70c | 1042 | static void cpt_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1043 | bool enable, |
ac240288 ML |
1044 | const struct intel_crtc_state *crtc_state, |
1045 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1046 | { |
790ea70c | 1047 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1048 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1049 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 1050 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
1051 | u32 val = I915_READ(reg); |
1052 | ||
afba0188 DV |
1053 | assert_hdmi_port_disabled(intel_hdmi); |
1054 | ||
0c14c7f9 PZ |
1055 | /* See the big comment in g4x_set_infoframes() */ |
1056 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1057 | ||
6897b4b5 | 1058 | if (!enable) { |
0c14c7f9 PZ |
1059 | if (!(val & VIDEO_DIP_ENABLE)) |
1060 | return; | |
0be6f0c8 VS |
1061 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1062 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1063 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1064 | I915_WRITE(reg, val); |
9d9740f0 | 1065 | POSTING_READ(reg); |
0c14c7f9 PZ |
1066 | return; |
1067 | } | |
1068 | ||
822974ae PZ |
1069 | /* Set both together, unset both together: see the spec. */ |
1070 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 1071 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 1072 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 1073 | |
ac240288 | 1074 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1075 | val |= VIDEO_DIP_ENABLE_GCP; |
1076 | ||
822974ae | 1077 | I915_WRITE(reg, val); |
9d9740f0 | 1078 | POSTING_READ(reg); |
822974ae | 1079 | |
fbf08556 VS |
1080 | intel_write_infoframe(encoder, crtc_state, |
1081 | HDMI_INFOFRAME_TYPE_AVI, | |
1082 | &crtc_state->infoframes.avi); | |
1083 | intel_write_infoframe(encoder, crtc_state, | |
1084 | HDMI_INFOFRAME_TYPE_SPD, | |
1085 | &crtc_state->infoframes.spd); | |
1086 | intel_write_infoframe(encoder, crtc_state, | |
1087 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1088 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1089 | } |
1090 | ||
790ea70c | 1091 | static void vlv_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1092 | bool enable, |
ac240288 ML |
1093 | const struct intel_crtc_state *crtc_state, |
1094 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1095 | { |
790ea70c | 1096 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1097 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
790ea70c | 1098 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f0f59a00 | 1099 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 1100 | u32 val = I915_READ(reg); |
790ea70c | 1101 | u32 port = VIDEO_DIP_PORT(encoder->port); |
0c14c7f9 | 1102 | |
afba0188 DV |
1103 | assert_hdmi_port_disabled(intel_hdmi); |
1104 | ||
0c14c7f9 PZ |
1105 | /* See the big comment in g4x_set_infoframes() */ |
1106 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
1107 | ||
6897b4b5 | 1108 | if (!enable) { |
0c14c7f9 PZ |
1109 | if (!(val & VIDEO_DIP_ENABLE)) |
1110 | return; | |
0be6f0c8 VS |
1111 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
1112 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1113 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 1114 | I915_WRITE(reg, val); |
9d9740f0 | 1115 | POSTING_READ(reg); |
0c14c7f9 PZ |
1116 | return; |
1117 | } | |
1118 | ||
6a2b8021 | 1119 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
1120 | WARN(val & VIDEO_DIP_ENABLE, |
1121 | "DIP already enabled on port %c\n", | |
1122 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
1123 | val &= ~VIDEO_DIP_PORT_MASK; |
1124 | val |= port; | |
1125 | } | |
1126 | ||
822974ae | 1127 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
1128 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
1129 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
1130 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 1131 | |
ac240288 | 1132 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1133 | val |= VIDEO_DIP_ENABLE_GCP; |
1134 | ||
822974ae | 1135 | I915_WRITE(reg, val); |
9d9740f0 | 1136 | POSTING_READ(reg); |
822974ae | 1137 | |
fbf08556 VS |
1138 | intel_write_infoframe(encoder, crtc_state, |
1139 | HDMI_INFOFRAME_TYPE_AVI, | |
1140 | &crtc_state->infoframes.avi); | |
1141 | intel_write_infoframe(encoder, crtc_state, | |
1142 | HDMI_INFOFRAME_TYPE_SPD, | |
1143 | &crtc_state->infoframes.spd); | |
1144 | intel_write_infoframe(encoder, crtc_state, | |
1145 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1146 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1147 | } |
1148 | ||
790ea70c | 1149 | static void hsw_set_infoframes(struct intel_encoder *encoder, |
6897b4b5 | 1150 | bool enable, |
ac240288 ML |
1151 | const struct intel_crtc_state *crtc_state, |
1152 | const struct drm_connector_state *conn_state) | |
687f4d06 | 1153 | { |
790ea70c | 1154 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
ac240288 | 1155 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 1156 | u32 val = I915_READ(reg); |
0c14c7f9 | 1157 | |
8fc0aa6e ID |
1158 | assert_hdmi_transcoder_func_disabled(dev_priv, |
1159 | crtc_state->cpu_transcoder); | |
afba0188 | 1160 | |
0be6f0c8 VS |
1161 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
1162 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
1163 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
1164 | ||
6897b4b5 | 1165 | if (!enable) { |
0be6f0c8 | 1166 | I915_WRITE(reg, val); |
9d9740f0 | 1167 | POSTING_READ(reg); |
0c14c7f9 PZ |
1168 | return; |
1169 | } | |
1170 | ||
ac240288 | 1171 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
1172 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
1173 | ||
0dd87d20 | 1174 | I915_WRITE(reg, val); |
9d9740f0 | 1175 | POSTING_READ(reg); |
0dd87d20 | 1176 | |
fbf08556 VS |
1177 | intel_write_infoframe(encoder, crtc_state, |
1178 | HDMI_INFOFRAME_TYPE_AVI, | |
1179 | &crtc_state->infoframes.avi); | |
1180 | intel_write_infoframe(encoder, crtc_state, | |
1181 | HDMI_INFOFRAME_TYPE_SPD, | |
1182 | &crtc_state->infoframes.spd); | |
1183 | intel_write_infoframe(encoder, crtc_state, | |
1184 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1185 | &crtc_state->infoframes.hdmi); | |
687f4d06 PZ |
1186 | } |
1187 | ||
b2ccb822 VS |
1188 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
1189 | { | |
1190 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
1191 | struct i2c_adapter *adapter = | |
1192 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1193 | ||
1194 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
1195 | return; | |
1196 | ||
1197 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
1198 | enable ? "Enabling" : "Disabling"); | |
1199 | ||
1200 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
1201 | adapter, enable); | |
1202 | } | |
1203 | ||
2320175f SP |
1204 | static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, |
1205 | unsigned int offset, void *buffer, size_t size) | |
1206 | { | |
1207 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1208 | struct drm_i915_private *dev_priv = | |
1209 | intel_dig_port->base.base.dev->dev_private; | |
1210 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1211 | hdmi->ddc_bus); | |
1212 | int ret; | |
1213 | u8 start = offset & 0xff; | |
1214 | struct i2c_msg msgs[] = { | |
1215 | { | |
1216 | .addr = DRM_HDCP_DDC_ADDR, | |
1217 | .flags = 0, | |
1218 | .len = 1, | |
1219 | .buf = &start, | |
1220 | }, | |
1221 | { | |
1222 | .addr = DRM_HDCP_DDC_ADDR, | |
1223 | .flags = I2C_M_RD, | |
1224 | .len = size, | |
1225 | .buf = buffer | |
1226 | } | |
1227 | }; | |
1228 | ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); | |
1229 | if (ret == ARRAY_SIZE(msgs)) | |
1230 | return 0; | |
1231 | return ret >= 0 ? -EIO : ret; | |
1232 | } | |
1233 | ||
1234 | static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, | |
1235 | unsigned int offset, void *buffer, size_t size) | |
1236 | { | |
1237 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1238 | struct drm_i915_private *dev_priv = | |
1239 | intel_dig_port->base.base.dev->dev_private; | |
1240 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1241 | hdmi->ddc_bus); | |
1242 | int ret; | |
1243 | u8 *write_buf; | |
1244 | struct i2c_msg msg; | |
1245 | ||
1246 | write_buf = kzalloc(size + 1, GFP_KERNEL); | |
1247 | if (!write_buf) | |
1248 | return -ENOMEM; | |
1249 | ||
1250 | write_buf[0] = offset & 0xff; | |
1251 | memcpy(&write_buf[1], buffer, size); | |
1252 | ||
1253 | msg.addr = DRM_HDCP_DDC_ADDR; | |
1254 | msg.flags = 0, | |
1255 | msg.len = size + 1, | |
1256 | msg.buf = write_buf; | |
1257 | ||
1258 | ret = i2c_transfer(adapter, &msg, 1); | |
1259 | if (ret == 1) | |
1b1b1162 RV |
1260 | ret = 0; |
1261 | else if (ret >= 0) | |
1262 | ret = -EIO; | |
1263 | ||
1264 | kfree(write_buf); | |
1265 | return ret; | |
2320175f SP |
1266 | } |
1267 | ||
1268 | static | |
1269 | int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
1270 | u8 *an) | |
1271 | { | |
1272 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1273 | struct drm_i915_private *dev_priv = | |
1274 | intel_dig_port->base.base.dev->dev_private; | |
1275 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
1276 | hdmi->ddc_bus); | |
1277 | int ret; | |
1278 | ||
1279 | ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, | |
1280 | DRM_HDCP_AN_LEN); | |
1281 | if (ret) { | |
3aae21fc | 1282 | DRM_DEBUG_KMS("Write An over DDC failed (%d)\n", ret); |
2320175f SP |
1283 | return ret; |
1284 | } | |
1285 | ||
1286 | ret = intel_gmbus_output_aksv(adapter); | |
1287 | if (ret < 0) { | |
3aae21fc | 1288 | DRM_DEBUG_KMS("Failed to output aksv (%d)\n", ret); |
2320175f SP |
1289 | return ret; |
1290 | } | |
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
1295 | u8 *bksv) | |
1296 | { | |
1297 | int ret; | |
1298 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, | |
1299 | DRM_HDCP_KSV_LEN); | |
1300 | if (ret) | |
3aae21fc | 1301 | DRM_DEBUG_KMS("Read Bksv over DDC failed (%d)\n", ret); |
2320175f SP |
1302 | return ret; |
1303 | } | |
1304 | ||
1305 | static | |
1306 | int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
1307 | u8 *bstatus) | |
1308 | { | |
1309 | int ret; | |
1310 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, | |
1311 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
1312 | if (ret) | |
3aae21fc | 1313 | DRM_DEBUG_KMS("Read bstatus over DDC failed (%d)\n", ret); |
2320175f SP |
1314 | return ret; |
1315 | } | |
1316 | ||
1317 | static | |
1318 | int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
1319 | bool *repeater_present) | |
1320 | { | |
1321 | int ret; | |
1322 | u8 val; | |
1323 | ||
1324 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1325 | if (ret) { | |
3aae21fc | 1326 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1327 | return ret; |
1328 | } | |
1329 | *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; | |
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | static | |
1334 | int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
1335 | u8 *ri_prime) | |
1336 | { | |
1337 | int ret; | |
1338 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, | |
1339 | ri_prime, DRM_HDCP_RI_LEN); | |
1340 | if (ret) | |
3aae21fc | 1341 | DRM_DEBUG_KMS("Read Ri' over DDC failed (%d)\n", ret); |
2320175f SP |
1342 | return ret; |
1343 | } | |
1344 | ||
1345 | static | |
1346 | int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
1347 | bool *ksv_ready) | |
1348 | { | |
1349 | int ret; | |
1350 | u8 val; | |
1351 | ||
1352 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1353 | if (ret) { | |
3aae21fc | 1354 | DRM_DEBUG_KMS("Read bcaps over DDC failed (%d)\n", ret); |
2320175f SP |
1355 | return ret; |
1356 | } | |
1357 | *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; | |
1358 | return 0; | |
1359 | } | |
1360 | ||
1361 | static | |
1362 | int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
1363 | int num_downstream, u8 *ksv_fifo) | |
1364 | { | |
1365 | int ret; | |
1366 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, | |
1367 | ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); | |
1368 | if (ret) { | |
3aae21fc | 1369 | DRM_DEBUG_KMS("Read ksv fifo over DDC failed (%d)\n", ret); |
2320175f SP |
1370 | return ret; |
1371 | } | |
1372 | return 0; | |
1373 | } | |
1374 | ||
1375 | static | |
1376 | int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
1377 | int i, u32 *part) | |
1378 | { | |
1379 | int ret; | |
1380 | ||
1381 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
1382 | return -EINVAL; | |
1383 | ||
1384 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), | |
1385 | part, DRM_HDCP_V_PRIME_PART_LEN); | |
1386 | if (ret) | |
3aae21fc | 1387 | DRM_DEBUG_KMS("Read V'[%d] over DDC failed (%d)\n", i, ret); |
2320175f SP |
1388 | return ret; |
1389 | } | |
1390 | ||
7412826c R |
1391 | static int kbl_repositioning_enc_en_signal(struct intel_connector *connector) |
1392 | { | |
1393 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
1394 | struct intel_digital_port *intel_dig_port = conn_to_dig_port(connector); | |
1395 | struct drm_crtc *crtc = connector->base.state->crtc; | |
1396 | struct intel_crtc *intel_crtc = container_of(crtc, | |
1397 | struct intel_crtc, base); | |
1398 | u32 scanline; | |
1399 | int ret; | |
1400 | ||
1401 | for (;;) { | |
1402 | scanline = I915_READ(PIPEDSL(intel_crtc->pipe)); | |
1403 | if (scanline > 100 && scanline < 200) | |
1404 | break; | |
1405 | usleep_range(25, 50); | |
1406 | } | |
1407 | ||
1408 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, false); | |
1409 | if (ret) { | |
1410 | DRM_ERROR("Disable HDCP signalling failed (%d)\n", ret); | |
1411 | return ret; | |
1412 | } | |
1413 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, true); | |
1414 | if (ret) { | |
1415 | DRM_ERROR("Enable HDCP signalling failed (%d)\n", ret); | |
1416 | return ret; | |
1417 | } | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | ||
2320175f SP |
1422 | static |
1423 | int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
1424 | bool enable) | |
1425 | { | |
7412826c R |
1426 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; |
1427 | struct intel_connector *connector = hdmi->attached_connector; | |
1428 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); | |
2320175f SP |
1429 | int ret; |
1430 | ||
1431 | if (!enable) | |
1432 | usleep_range(6, 60); /* Bspec says >= 6us */ | |
1433 | ||
1434 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); | |
1435 | if (ret) { | |
1436 | DRM_ERROR("%s HDCP signalling failed (%d)\n", | |
1437 | enable ? "Enable" : "Disable", ret); | |
1438 | return ret; | |
1439 | } | |
7412826c R |
1440 | |
1441 | /* | |
1442 | * WA: To fix incorrect positioning of the window of | |
1443 | * opportunity and enc_en signalling in KABYLAKE. | |
1444 | */ | |
1445 | if (IS_KABYLAKE(dev_priv) && enable) | |
1446 | return kbl_repositioning_enc_en_signal(connector); | |
1447 | ||
2320175f SP |
1448 | return 0; |
1449 | } | |
1450 | ||
1451 | static | |
1452 | bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
1453 | { | |
1454 | struct drm_i915_private *dev_priv = | |
1455 | intel_dig_port->base.base.dev->dev_private; | |
1456 | enum port port = intel_dig_port->base.port; | |
1457 | int ret; | |
1458 | union { | |
1459 | u32 reg; | |
1460 | u8 shim[DRM_HDCP_RI_LEN]; | |
1461 | } ri; | |
1462 | ||
1463 | ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); | |
1464 | if (ret) | |
1465 | return false; | |
1466 | ||
1467 | I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); | |
1468 | ||
1469 | /* Wait for Ri prime match */ | |
1470 | if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & | |
1471 | (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { | |
1472 | DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", | |
1473 | I915_READ(PORT_HDCP_STATUS(port))); | |
1474 | return false; | |
1475 | } | |
1476 | return true; | |
1477 | } | |
1478 | ||
2d4254e5 R |
1479 | static struct hdcp2_hdmi_msg_data { |
1480 | u8 msg_id; | |
1481 | u32 timeout; | |
1482 | u32 timeout2; | |
1483 | } hdcp2_msg_data[] = { | |
1484 | {HDCP_2_2_AKE_INIT, 0, 0}, | |
1485 | {HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, 0}, | |
1486 | {HDCP_2_2_AKE_NO_STORED_KM, 0, 0}, | |
1487 | {HDCP_2_2_AKE_STORED_KM, 0, 0}, | |
1488 | {HDCP_2_2_AKE_SEND_HPRIME, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, | |
1489 | HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS}, | |
1490 | {HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, | |
1491 | 0}, | |
1492 | {HDCP_2_2_LC_INIT, 0, 0}, | |
1493 | {HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, 0}, | |
1494 | {HDCP_2_2_SKE_SEND_EKS, 0, 0}, | |
1495 | {HDCP_2_2_REP_SEND_RECVID_LIST, | |
1496 | HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0}, | |
1497 | {HDCP_2_2_REP_SEND_ACK, 0, 0}, | |
1498 | {HDCP_2_2_REP_STREAM_MANAGE, 0, 0}, | |
1499 | {HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, | |
1500 | 0}, | |
1501 | }; | |
1502 | ||
1503 | static | |
1504 | int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, | |
126d0a94 | 1505 | u8 *rx_status) |
2d4254e5 R |
1506 | { |
1507 | return intel_hdmi_hdcp_read(intel_dig_port, | |
1508 | HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET, | |
1509 | rx_status, | |
1510 | HDCP_2_2_HDMI_RXSTATUS_LEN); | |
1511 | } | |
1512 | ||
1513 | static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired) | |
1514 | { | |
1515 | int i; | |
1516 | ||
1517 | for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++) | |
1518 | if (hdcp2_msg_data[i].msg_id == msg_id && | |
1519 | (msg_id != HDCP_2_2_AKE_SEND_HPRIME || is_paired)) | |
1520 | return hdcp2_msg_data[i].timeout; | |
1521 | else if (hdcp2_msg_data[i].msg_id == msg_id) | |
1522 | return hdcp2_msg_data[i].timeout2; | |
1523 | ||
1524 | return -EINVAL; | |
1525 | } | |
1526 | ||
1527 | static inline | |
1528 | int hdcp2_detect_msg_availability(struct intel_digital_port *intel_digital_port, | |
1529 | u8 msg_id, bool *msg_ready, | |
1530 | ssize_t *msg_sz) | |
1531 | { | |
1532 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1533 | int ret; | |
1534 | ||
1535 | ret = intel_hdmi_hdcp2_read_rx_status(intel_digital_port, rx_status); | |
1536 | if (ret < 0) { | |
1537 | DRM_DEBUG_KMS("rx_status read failed. Err %d\n", ret); | |
1538 | return ret; | |
1539 | } | |
1540 | ||
1541 | *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) | | |
1542 | rx_status[0]); | |
1543 | ||
1544 | if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) | |
1545 | *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) && | |
1546 | *msg_sz); | |
1547 | else | |
1548 | *msg_ready = *msg_sz; | |
1549 | ||
1550 | return 0; | |
1551 | } | |
1552 | ||
1553 | static ssize_t | |
1554 | intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, | |
1555 | u8 msg_id, bool paired) | |
1556 | { | |
1557 | bool msg_ready = false; | |
1558 | int timeout, ret; | |
1559 | ssize_t msg_sz = 0; | |
1560 | ||
1561 | timeout = get_hdcp2_msg_timeout(msg_id, paired); | |
1562 | if (timeout < 0) | |
1563 | return timeout; | |
1564 | ||
1565 | ret = __wait_for(ret = hdcp2_detect_msg_availability(intel_dig_port, | |
1566 | msg_id, &msg_ready, | |
1567 | &msg_sz), | |
1568 | !ret && msg_ready && msg_sz, timeout * 1000, | |
1569 | 1000, 5 * 1000); | |
1570 | if (ret) | |
1571 | DRM_DEBUG_KMS("msg_id: %d, ret: %d, timeout: %d\n", | |
1572 | msg_id, ret, timeout); | |
1573 | ||
1574 | return ret ? ret : msg_sz; | |
1575 | } | |
1576 | ||
1577 | static | |
1578 | int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, | |
1579 | void *buf, size_t size) | |
1580 | { | |
1581 | unsigned int offset; | |
1582 | ||
1583 | offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET; | |
1584 | return intel_hdmi_hdcp_write(intel_dig_port, offset, buf, size); | |
1585 | } | |
1586 | ||
1587 | static | |
1588 | int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, | |
1589 | u8 msg_id, void *buf, size_t size) | |
1590 | { | |
1591 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
1592 | struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; | |
1593 | unsigned int offset; | |
1594 | ssize_t ret; | |
1595 | ||
1596 | ret = intel_hdmi_hdcp2_wait_for_msg(intel_dig_port, msg_id, | |
1597 | hdcp->is_paired); | |
1598 | if (ret < 0) | |
1599 | return ret; | |
1600 | ||
1601 | /* | |
1602 | * Available msg size should be equal to or lesser than the | |
1603 | * available buffer. | |
1604 | */ | |
1605 | if (ret > size) { | |
1606 | DRM_DEBUG_KMS("msg_sz(%zd) is more than exp size(%zu)\n", | |
1607 | ret, size); | |
1608 | return -1; | |
1609 | } | |
1610 | ||
1611 | offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET; | |
1612 | ret = intel_hdmi_hdcp_read(intel_dig_port, offset, buf, ret); | |
1613 | if (ret) | |
1614 | DRM_DEBUG_KMS("Failed to read msg_id: %d(%zd)\n", msg_id, ret); | |
1615 | ||
1616 | return ret; | |
1617 | } | |
1618 | ||
1619 | static | |
1620 | int intel_hdmi_hdcp2_check_link(struct intel_digital_port *intel_dig_port) | |
1621 | { | |
1622 | u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN]; | |
1623 | int ret; | |
1624 | ||
1625 | ret = intel_hdmi_hdcp2_read_rx_status(intel_dig_port, rx_status); | |
1626 | if (ret) | |
1627 | return ret; | |
1628 | ||
1629 | /* | |
1630 | * Re-auth request and Link Integrity Failures are represented by | |
1631 | * same bit. i.e reauth_req. | |
1632 | */ | |
1633 | if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1])) | |
1634 | ret = HDCP_REAUTH_REQUEST; | |
1635 | else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1])) | |
1636 | ret = HDCP_TOPOLOGY_CHANGE; | |
1637 | ||
1638 | return ret; | |
1639 | } | |
1640 | ||
1641 | static | |
1642 | int intel_hdmi_hdcp2_capable(struct intel_digital_port *intel_dig_port, | |
1643 | bool *capable) | |
1644 | { | |
1645 | u8 hdcp2_version; | |
1646 | int ret; | |
1647 | ||
1648 | *capable = false; | |
1649 | ret = intel_hdmi_hdcp_read(intel_dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET, | |
1650 | &hdcp2_version, sizeof(hdcp2_version)); | |
1651 | if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK) | |
1652 | *capable = true; | |
1653 | ||
1654 | return ret; | |
1655 | } | |
1656 | ||
1657 | static inline | |
1658 | enum hdcp_wired_protocol intel_hdmi_hdcp2_protocol(void) | |
1659 | { | |
1660 | return HDCP_PROTOCOL_HDMI; | |
1661 | } | |
1662 | ||
2320175f SP |
1663 | static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { |
1664 | .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, | |
1665 | .read_bksv = intel_hdmi_hdcp_read_bksv, | |
1666 | .read_bstatus = intel_hdmi_hdcp_read_bstatus, | |
1667 | .repeater_present = intel_hdmi_hdcp_repeater_present, | |
1668 | .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, | |
1669 | .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, | |
1670 | .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, | |
1671 | .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, | |
1672 | .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, | |
1673 | .check_link = intel_hdmi_hdcp_check_link, | |
2d4254e5 R |
1674 | .write_2_2_msg = intel_hdmi_hdcp2_write_msg, |
1675 | .read_2_2_msg = intel_hdmi_hdcp2_read_msg, | |
1676 | .check_2_2_link = intel_hdmi_hdcp2_check_link, | |
1677 | .hdcp_2_2_capable = intel_hdmi_hdcp2_capable, | |
1678 | .protocol = HDCP_PROTOCOL_HDMI, | |
2320175f SP |
1679 | }; |
1680 | ||
ac240288 ML |
1681 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
1682 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 1683 | { |
c59423a3 | 1684 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1685 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1686 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 1687 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 1688 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 1689 | u32 hdmi_val; |
7d57382e | 1690 | |
b2ccb822 VS |
1691 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
1692 | ||
b242b7f7 | 1693 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 1694 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 1695 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 1696 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 1697 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 1698 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 1699 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 1700 | |
ac240288 | 1701 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 1702 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 1703 | else |
4f3a8bc7 | 1704 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 1705 | |
ac240288 | 1706 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 1707 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 1708 | |
6e266956 | 1709 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 1710 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 1711 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1712 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 1713 | else |
c59423a3 | 1714 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 1715 | |
b242b7f7 PZ |
1716 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
1717 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
1718 | } |
1719 | ||
85234cdc DV |
1720 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
1721 | enum pipe *pipe) | |
7d57382e | 1722 | { |
76203467 | 1723 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
85234cdc | 1724 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
0e6e0be4 | 1725 | intel_wakeref_t wakeref; |
5b092174 | 1726 | bool ret; |
85234cdc | 1727 | |
0e6e0be4 CW |
1728 | wakeref = intel_display_power_get_if_enabled(dev_priv, |
1729 | encoder->power_domain); | |
1730 | if (!wakeref) | |
6d129bea ID |
1731 | return false; |
1732 | ||
76203467 | 1733 | ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe); |
5b092174 | 1734 | |
0e6e0be4 | 1735 | intel_display_power_put(dev_priv, encoder->power_domain, wakeref); |
5b092174 ID |
1736 | |
1737 | return ret; | |
85234cdc DV |
1738 | } |
1739 | ||
045ac3b5 | 1740 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 1741 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
1742 | { |
1743 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca | 1744 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1745 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 1746 | u32 tmp, flags = 0; |
18442d08 | 1747 | int dotclock; |
045ac3b5 | 1748 | |
e1214b95 VS |
1749 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); |
1750 | ||
045ac3b5 JB |
1751 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
1752 | ||
1753 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
1754 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1755 | else | |
1756 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1757 | ||
1758 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
1759 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1760 | else | |
1761 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1762 | ||
6897b4b5 DV |
1763 | if (tmp & HDMI_MODE_SELECT_HDMI) |
1764 | pipe_config->has_hdmi_sink = true; | |
1765 | ||
e5e70d4a VS |
1766 | pipe_config->infoframes.enable |= |
1767 | intel_hdmi_infoframes_enabled(encoder, pipe_config); | |
1768 | ||
1769 | if (pipe_config->infoframes.enable) | |
e43823ec JB |
1770 | pipe_config->has_infoframe = true; |
1771 | ||
c84db770 | 1772 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
1773 | pipe_config->has_audio = true; |
1774 | ||
6e266956 | 1775 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
1776 | tmp & HDMI_COLOR_RANGE_16_235) |
1777 | pipe_config->limited_color_range = true; | |
1778 | ||
2d112de7 | 1779 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
1780 | |
1781 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
1782 | dotclock = pipe_config->port_clock * 2 / 3; | |
1783 | else | |
1784 | dotclock = pipe_config->port_clock; | |
1785 | ||
be69a133 VS |
1786 | if (pipe_config->pixel_multiplier) |
1787 | dotclock /= pipe_config->pixel_multiplier; | |
1788 | ||
2d112de7 | 1789 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
1790 | |
1791 | pipe_config->lane_count = 4; | |
f2a10d61 VS |
1792 | |
1793 | intel_hdmi_read_gcp_infoframe(encoder, pipe_config); | |
1794 | ||
1795 | intel_read_infoframe(encoder, pipe_config, | |
1796 | HDMI_INFOFRAME_TYPE_AVI, | |
1797 | &pipe_config->infoframes.avi); | |
1798 | intel_read_infoframe(encoder, pipe_config, | |
1799 | HDMI_INFOFRAME_TYPE_SPD, | |
1800 | &pipe_config->infoframes.spd); | |
1801 | intel_read_infoframe(encoder, pipe_config, | |
1802 | HDMI_INFOFRAME_TYPE_VENDOR, | |
1803 | &pipe_config->infoframes.hdmi); | |
045ac3b5 JB |
1804 | } |
1805 | ||
df18e721 | 1806 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
5f88a9c6 VS |
1807 | const struct intel_crtc_state *pipe_config, |
1808 | const struct drm_connector_state *conn_state) | |
d1b1589c | 1809 | { |
ac240288 | 1810 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 1811 | |
ac240288 | 1812 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
1813 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
1814 | pipe_name(crtc->pipe)); | |
bbf35e9d | 1815 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
1816 | } |
1817 | ||
fd6bbda9 | 1818 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1819 | const struct intel_crtc_state *pipe_config, |
1820 | const struct drm_connector_state *conn_state) | |
7d57382e | 1821 | { |
5ab432ef | 1822 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1823 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1824 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1825 | u32 temp; |
1826 | ||
b242b7f7 | 1827 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1828 | |
bf868c7d | 1829 | temp |= SDVO_ENABLE; |
df18e721 | 1830 | if (pipe_config->has_audio) |
bf868c7d | 1831 | temp |= SDVO_AUDIO_ENABLE; |
7a87c289 | 1832 | |
bf868c7d VS |
1833 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1834 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1835 | ||
df18e721 ML |
1836 | if (pipe_config->has_audio) |
1837 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1838 | } |
1839 | ||
fd6bbda9 | 1840 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1841 | const struct intel_crtc_state *pipe_config, |
1842 | const struct drm_connector_state *conn_state) | |
bf868c7d VS |
1843 | { |
1844 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1845 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1846 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1847 | u32 temp; | |
1848 | ||
1849 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1850 | |
bf868c7d | 1851 | temp |= SDVO_ENABLE; |
ac240288 | 1852 | if (pipe_config->has_audio) |
bf868c7d | 1853 | temp |= SDVO_AUDIO_ENABLE; |
5ab432ef | 1854 | |
bf868c7d VS |
1855 | /* |
1856 | * HW workaround, need to write this twice for issue | |
1857 | * that may result in first write getting masked. | |
1858 | */ | |
1859 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1860 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1861 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1862 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1863 | |
bf868c7d VS |
1864 | /* |
1865 | * HW workaround, need to toggle enable bit off and on | |
1866 | * for 12bpc with pixel repeat. | |
1867 | * | |
1868 | * FIXME: BSpec says this should be done at the end of | |
1869 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1870 | */ |
df18e721 ML |
1871 | if (pipe_config->pipe_bpp > 24 && |
1872 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1873 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1874 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1875 | ||
1876 | /* | |
1877 | * HW workaround, need to write this twice for issue | |
1878 | * that may result in first write getting masked. | |
1879 | */ | |
1880 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1881 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1882 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1883 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1884 | } |
c1dec79a | 1885 | |
df18e721 ML |
1886 | if (pipe_config->has_audio) |
1887 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1888 | } |
1889 | ||
fd6bbda9 | 1890 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1891 | const struct intel_crtc_state *pipe_config, |
1892 | const struct drm_connector_state *conn_state) | |
d1b1589c VS |
1893 | { |
1894 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1895 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1896 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1897 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1898 | enum pipe pipe = crtc->pipe; | |
1899 | u32 temp; | |
1900 | ||
1901 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1902 | ||
1903 | temp |= SDVO_ENABLE; | |
df18e721 | 1904 | if (pipe_config->has_audio) |
d1b1589c VS |
1905 | temp |= SDVO_AUDIO_ENABLE; |
1906 | ||
1907 | /* | |
1908 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1909 | * | |
1910 | * The procedure for 12bpc is as follows: | |
1911 | * 1. disable HDMI clock gating | |
1912 | * 2. enable HDMI with 8bpc | |
1913 | * 3. enable HDMI with 12bpc | |
1914 | * 4. enable HDMI clock gating | |
1915 | */ | |
1916 | ||
df18e721 | 1917 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1918 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1919 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1920 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1921 | ||
1922 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1923 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1924 | } |
d1b1589c VS |
1925 | |
1926 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1927 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1928 | ||
df18e721 | 1929 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1930 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1931 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1932 | ||
1933 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1934 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1935 | ||
1936 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1937 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1938 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1939 | } | |
1940 | ||
df18e721 ML |
1941 | if (pipe_config->has_audio) |
1942 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1943 | } |
89b667f8 | 1944 | |
fd6bbda9 | 1945 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1946 | const struct intel_crtc_state *pipe_config, |
1947 | const struct drm_connector_state *conn_state) | |
b76cf76b | 1948 | { |
5ab432ef DV |
1949 | } |
1950 | ||
fd6bbda9 | 1951 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1952 | const struct intel_crtc_state *old_crtc_state, |
1953 | const struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
1954 | { |
1955 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1956 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1957 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f99be1b3 VS |
1958 | struct intel_digital_port *intel_dig_port = |
1959 | hdmi_to_dig_port(intel_hdmi); | |
ac240288 | 1960 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 1961 | u32 temp; |
5ab432ef | 1962 | |
b242b7f7 | 1963 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1964 | |
1612c8bd | 1965 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1966 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1967 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1968 | |
1969 | /* | |
1970 | * HW workaround for IBX, we need to move the port | |
1971 | * to transcoder A after disabling it to allow the | |
1972 | * matching DP port to be enabled on transcoder A. | |
1973 | */ | |
6e266956 | 1974 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
1975 | /* |
1976 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1977 | * doing the workaround. Sweep them under the rug. | |
1978 | */ | |
1979 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1980 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1981 | ||
76203467 VS |
1982 | temp &= ~SDVO_PIPE_SEL_MASK; |
1983 | temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); | |
1612c8bd VS |
1984 | /* |
1985 | * HW workaround, need to write this twice for issue | |
1986 | * that may result in first write getting masked. | |
1987 | */ | |
1988 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1989 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1990 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1991 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1992 | ||
1993 | temp &= ~SDVO_ENABLE; | |
1994 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1995 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 1996 | |
0f0f74bc | 1997 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
1998 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
1999 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 2000 | } |
6d67415f | 2001 | |
790ea70c VS |
2002 | intel_dig_port->set_infoframes(encoder, |
2003 | false, | |
f99be1b3 | 2004 | old_crtc_state, old_conn_state); |
b2ccb822 VS |
2005 | |
2006 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
2007 | } |
2008 | ||
fd6bbda9 | 2009 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2010 | const struct intel_crtc_state *old_crtc_state, |
2011 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2012 | { |
df18e721 | 2013 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2014 | intel_audio_codec_disable(encoder, |
2015 | old_crtc_state, old_conn_state); | |
a4790cec | 2016 | |
fd6bbda9 | 2017 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2018 | } |
2019 | ||
fd6bbda9 | 2020 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2021 | const struct intel_crtc_state *old_crtc_state, |
2022 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2023 | { |
df18e721 | 2024 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
2025 | intel_audio_codec_disable(encoder, |
2026 | old_crtc_state, old_conn_state); | |
a4790cec VS |
2027 | } |
2028 | ||
fd6bbda9 | 2029 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
2030 | const struct intel_crtc_state *old_crtc_state, |
2031 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 2032 | { |
fd6bbda9 | 2033 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
2034 | } |
2035 | ||
d6038611 | 2036 | static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) |
7d148ef5 | 2037 | { |
d6038611 VS |
2038 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2039 | const struct ddi_vbt_port_info *info = | |
2040 | &dev_priv->vbt.ddi_port_info[encoder->port]; | |
2041 | int max_tmds_clock; | |
2042 | ||
9672a69c | 2043 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
d6038611 VS |
2044 | max_tmds_clock = 594000; |
2045 | else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) | |
2046 | max_tmds_clock = 300000; | |
2047 | else if (INTEL_GEN(dev_priv) >= 5) | |
2048 | max_tmds_clock = 225000; | |
7d148ef5 | 2049 | else |
d6038611 VS |
2050 | max_tmds_clock = 165000; |
2051 | ||
2052 | if (info->max_tmds_clock) | |
2053 | max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); | |
2054 | ||
2055 | return max_tmds_clock; | |
7d148ef5 DV |
2056 | } |
2057 | ||
b1ba124d | 2058 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f ML |
2059 | bool respect_downstream_limits, |
2060 | bool force_dvi) | |
b1ba124d | 2061 | { |
d6038611 VS |
2062 | struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; |
2063 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); | |
b1ba124d VS |
2064 | |
2065 | if (respect_downstream_limits) { | |
8cadab0a VS |
2066 | struct intel_connector *connector = hdmi->attached_connector; |
2067 | const struct drm_display_info *info = &connector->base.display_info; | |
2068 | ||
b1ba124d VS |
2069 | if (hdmi->dp_dual_mode.max_tmds_clock) |
2070 | max_tmds_clock = min(max_tmds_clock, | |
2071 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
2072 | |
2073 | if (info->max_tmds_clock) | |
2074 | max_tmds_clock = min(max_tmds_clock, | |
2075 | info->max_tmds_clock); | |
7a5ca19f | 2076 | else if (!hdmi->has_hdmi_sink || force_dvi) |
b1ba124d VS |
2077 | max_tmds_clock = min(max_tmds_clock, 165000); |
2078 | } | |
2079 | ||
2080 | return max_tmds_clock; | |
2081 | } | |
2082 | ||
e64e739e VS |
2083 | static enum drm_mode_status |
2084 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f ML |
2085 | int clock, bool respect_downstream_limits, |
2086 | bool force_dvi) | |
e64e739e | 2087 | { |
e2d214ae | 2088 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
2089 | |
2090 | if (clock < 25000) | |
2091 | return MODE_CLOCK_LOW; | |
7a5ca19f | 2092 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) |
e64e739e VS |
2093 | return MODE_CLOCK_HIGH; |
2094 | ||
5e6ccc0b | 2095 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 2096 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
2097 | return MODE_CLOCK_RANGE; |
2098 | ||
2099 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 2100 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
2101 | return MODE_CLOCK_RANGE; |
2102 | ||
2103 | return MODE_OK; | |
2104 | } | |
2105 | ||
c19de8eb DL |
2106 | static enum drm_mode_status |
2107 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
2108 | struct drm_display_mode *mode) | |
7d57382e | 2109 | { |
e64e739e VS |
2110 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
2111 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 2112 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
2113 | enum drm_mode_status status; |
2114 | int clock; | |
587bf496 | 2115 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
7a5ca19f ML |
2116 | bool force_dvi = |
2117 | READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; | |
e64e739e | 2118 | |
e4dd27aa VS |
2119 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
2120 | return MODE_NO_DBLESCAN; | |
2121 | ||
e64e739e | 2122 | clock = mode->clock; |
587bf496 MK |
2123 | |
2124 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
2125 | clock *= 2; | |
2126 | ||
2127 | if (clock > max_dotclk) | |
2128 | return MODE_CLOCK_HIGH; | |
2129 | ||
697c4078 CT |
2130 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
2131 | clock *= 2; | |
2132 | ||
b22ca995 SS |
2133 | if (drm_mode_is_420_only(&connector->display_info, mode)) |
2134 | clock /= 2; | |
2135 | ||
e64e739e | 2136 | /* check if we can do 8bpc */ |
7a5ca19f | 2137 | status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); |
7d57382e | 2138 | |
cd9e11a8 RS |
2139 | if (hdmi->has_hdmi_sink && !force_dvi) { |
2140 | /* if we can't do 8bpc we may still be able to do 12bpc */ | |
b2ae318a | 2141 | if (status != MODE_OK && !HAS_GMCH(dev_priv)) |
cd9e11a8 RS |
2142 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, |
2143 | true, force_dvi); | |
2144 | ||
2145 | /* if we can't do 8,12bpc we may still be able to do 10bpc */ | |
2146 | if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11) | |
2147 | status = hdmi_port_clock_valid(hdmi, clock * 5 / 4, | |
2148 | true, force_dvi); | |
2149 | } | |
7d57382e | 2150 | |
e64e739e | 2151 | return status; |
7d57382e EA |
2152 | } |
2153 | ||
cd9e11a8 RS |
2154 | static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state, |
2155 | int bpc) | |
71800632 | 2156 | { |
c750bdd3 VS |
2157 | struct drm_i915_private *dev_priv = |
2158 | to_i915(crtc_state->base.crtc->dev); | |
2159 | struct drm_atomic_state *state = crtc_state->base.state; | |
2160 | struct drm_connector_state *connector_state; | |
2161 | struct drm_connector *connector; | |
22dae8a0 RS |
2162 | const struct drm_display_mode *adjusted_mode = |
2163 | &crtc_state->base.adjusted_mode; | |
c750bdd3 | 2164 | int i; |
71800632 | 2165 | |
b2ae318a | 2166 | if (HAS_GMCH(dev_priv)) |
71800632 VS |
2167 | return false; |
2168 | ||
cd9e11a8 RS |
2169 | if (bpc == 10 && INTEL_GEN(dev_priv) < 11) |
2170 | return false; | |
2171 | ||
be33be5d VS |
2172 | if (crtc_state->pipe_bpp <= 8*3) |
2173 | return false; | |
2174 | ||
2175 | if (!crtc_state->has_hdmi_sink) | |
2176 | return false; | |
2177 | ||
71800632 | 2178 | /* |
cd9e11a8 | 2179 | * HDMI deep color affects the clocks, so it's only possible |
71800632 VS |
2180 | * when not cloning with other encoder types. |
2181 | */ | |
c750bdd3 VS |
2182 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
2183 | return false; | |
2184 | ||
fe5f6b1f | 2185 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
c750bdd3 VS |
2186 | const struct drm_display_info *info = &connector->display_info; |
2187 | ||
2188 | if (connector_state->crtc != crtc_state->base.crtc) | |
2189 | continue; | |
2190 | ||
33b7f3ee | 2191 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { |
60436fd4 SS |
2192 | const struct drm_hdmi_info *hdmi = &info->hdmi; |
2193 | ||
cd9e11a8 RS |
2194 | if (bpc == 12 && !(hdmi->y420_dc_modes & |
2195 | DRM_EDID_YCBCR420_DC_36)) | |
2196 | return false; | |
2197 | else if (bpc == 10 && !(hdmi->y420_dc_modes & | |
2198 | DRM_EDID_YCBCR420_DC_30)) | |
60436fd4 SS |
2199 | return false; |
2200 | } else { | |
cd9e11a8 RS |
2201 | if (bpc == 12 && !(info->edid_hdmi_dc_modes & |
2202 | DRM_EDID_HDMI_DC_36)) | |
2203 | return false; | |
2204 | else if (bpc == 10 && !(info->edid_hdmi_dc_modes & | |
2205 | DRM_EDID_HDMI_DC_30)) | |
60436fd4 SS |
2206 | return false; |
2207 | } | |
c750bdd3 VS |
2208 | } |
2209 | ||
2abf3c0d | 2210 | /* Display WA #1139: glk */ |
cd9e11a8 | 2211 | if (bpc == 12 && IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && |
22dae8a0 RS |
2212 | adjusted_mode->htotal > 5460) |
2213 | return false; | |
2214 | ||
2215 | /* Display Wa_1405510057:icl */ | |
2216 | if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 && | |
2dd24a9c | 2217 | bpc == 10 && INTEL_GEN(dev_priv) >= 11 && |
22dae8a0 RS |
2218 | (adjusted_mode->crtc_hblank_end - |
2219 | adjusted_mode->crtc_hblank_start) % 8 == 2) | |
46649d8b ACO |
2220 | return false; |
2221 | ||
c750bdd3 | 2222 | return true; |
71800632 VS |
2223 | } |
2224 | ||
60436fd4 SS |
2225 | static bool |
2226 | intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |
2227 | struct intel_crtc_state *config, | |
cd9e11a8 RS |
2228 | int *clock_12bpc, int *clock_10bpc, |
2229 | int *clock_8bpc) | |
60436fd4 | 2230 | { |
e5c05931 SS |
2231 | struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); |
2232 | ||
60436fd4 SS |
2233 | if (!connector->ycbcr_420_allowed) { |
2234 | DRM_ERROR("Platform doesn't support YCBCR420 output\n"); | |
2235 | return false; | |
2236 | } | |
2237 | ||
2238 | /* YCBCR420 TMDS rate requirement is half the pixel clock */ | |
2239 | config->port_clock /= 2; | |
2240 | *clock_12bpc /= 2; | |
cd9e11a8 | 2241 | *clock_10bpc /= 2; |
60436fd4 | 2242 | *clock_8bpc /= 2; |
33b7f3ee | 2243 | config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; |
e5c05931 SS |
2244 | |
2245 | /* YCBCR 420 output conversion needs a scaler */ | |
2246 | if (skl_update_scaler_crtc(config)) { | |
2247 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
2248 | return false; | |
2249 | } | |
2250 | ||
2251 | intel_pch_panel_fitting(intel_crtc, config, | |
2252 | DRM_MODE_SCALE_FULLSCREEN); | |
2253 | ||
60436fd4 SS |
2254 | return true; |
2255 | } | |
2256 | ||
204474a6 LP |
2257 | int intel_hdmi_compute_config(struct intel_encoder *encoder, |
2258 | struct intel_crtc_state *pipe_config, | |
2259 | struct drm_connector_state *conn_state) | |
7d57382e | 2260 | { |
5bfe2ac0 | 2261 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 2262 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 2263 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
60436fd4 SS |
2264 | struct drm_connector *connector = conn_state->connector; |
2265 | struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; | |
7a5ca19f ML |
2266 | struct intel_digital_connector_state *intel_conn_state = |
2267 | to_intel_digital_connector_state(conn_state); | |
e64e739e | 2268 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
cd9e11a8 | 2269 | int clock_10bpc = clock_8bpc * 5 / 4; |
e64e739e | 2270 | int clock_12bpc = clock_8bpc * 3 / 2; |
e29c22c0 | 2271 | int desired_bpp; |
7a5ca19f | 2272 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
3685a8f3 | 2273 | |
e4dd27aa | 2274 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
204474a6 | 2275 | return -EINVAL; |
e4dd27aa | 2276 | |
d9facae6 | 2277 | pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; |
7a5ca19f | 2278 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
6897b4b5 | 2279 | |
e43823ec JB |
2280 | if (pipe_config->has_hdmi_sink) |
2281 | pipe_config->has_infoframe = true; | |
2282 | ||
7a5ca19f | 2283 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db | 2284 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
0f2a2a75 VS |
2285 | pipe_config->limited_color_range = |
2286 | pipe_config->has_hdmi_sink && | |
c8127cf0 VS |
2287 | drm_default_rgb_quant_range(adjusted_mode) == |
2288 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
2289 | } else { |
2290 | pipe_config->limited_color_range = | |
7a5ca19f | 2291 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
2292 | } |
2293 | ||
697c4078 CT |
2294 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
2295 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 2296 | clock_8bpc *= 2; |
cd9e11a8 | 2297 | clock_10bpc *= 2; |
3320e37f | 2298 | clock_12bpc *= 2; |
697c4078 CT |
2299 | } |
2300 | ||
60436fd4 SS |
2301 | if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { |
2302 | if (!intel_hdmi_ycbcr420_config(connector, pipe_config, | |
cd9e11a8 RS |
2303 | &clock_12bpc, &clock_10bpc, |
2304 | &clock_8bpc)) { | |
60436fd4 | 2305 | DRM_ERROR("Can't support YCBCR420 output\n"); |
204474a6 | 2306 | return -EINVAL; |
60436fd4 SS |
2307 | } |
2308 | } | |
2309 | ||
4f8036a2 | 2310 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
2311 | pipe_config->has_pch_encoder = true; |
2312 | ||
7a5ca19f ML |
2313 | if (pipe_config->has_hdmi_sink) { |
2314 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
2315 | pipe_config->has_audio = intel_hdmi->has_audio; | |
2316 | else | |
2317 | pipe_config->has_audio = | |
2318 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
2319 | } | |
9ed109a7 | 2320 | |
4e53c2e0 | 2321 | /* |
cd9e11a8 RS |
2322 | * Note that g4x/vlv don't support 12bpc hdmi outputs. We also need |
2323 | * to check that the higher clock still fits within limits. | |
4e53c2e0 | 2324 | */ |
cd9e11a8 RS |
2325 | if (hdmi_deep_color_possible(pipe_config, 12) && |
2326 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, | |
2327 | true, force_dvi) == MODE_OK) { | |
e29c22c0 DV |
2328 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
2329 | desired_bpp = 12*3; | |
325b9d04 DV |
2330 | |
2331 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 2332 | pipe_config->port_clock = clock_12bpc; |
cd9e11a8 RS |
2333 | } else if (hdmi_deep_color_possible(pipe_config, 10) && |
2334 | hdmi_port_clock_valid(intel_hdmi, clock_10bpc, | |
2335 | true, force_dvi) == MODE_OK) { | |
2336 | DRM_DEBUG_KMS("picking bpc to 10 for HDMI output\n"); | |
2337 | desired_bpp = 10 * 3; | |
2338 | ||
2339 | /* Need to adjust the port link by 1.25x for 10bpc. */ | |
2340 | pipe_config->port_clock = clock_10bpc; | |
4e53c2e0 | 2341 | } else { |
e29c22c0 DV |
2342 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
2343 | desired_bpp = 8*3; | |
e64e739e VS |
2344 | |
2345 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
2346 | } |
2347 | ||
2348 | if (!pipe_config->bw_constrained) { | |
b64b7a60 | 2349 | DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp); |
e29c22c0 | 2350 | pipe_config->pipe_bpp = desired_bpp; |
4e53c2e0 DV |
2351 | } |
2352 | ||
e64e739e | 2353 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
7a5ca19f | 2354 | false, force_dvi) != MODE_OK) { |
e64e739e | 2355 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
204474a6 | 2356 | return -EINVAL; |
325b9d04 DV |
2357 | } |
2358 | ||
28b468a0 | 2359 | /* Set user selected PAR to incoming mode's member */ |
0e9f25d0 | 2360 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
28b468a0 | 2361 | |
d4d6279a ACO |
2362 | pipe_config->lane_count = 4; |
2363 | ||
9672a69c RV |
2364 | if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || |
2365 | IS_GEMINILAKE(dev_priv))) { | |
15953637 SS |
2366 | if (scdc->scrambling.low_rates) |
2367 | pipe_config->hdmi_scrambling = true; | |
2368 | ||
2369 | if (pipe_config->port_clock > 340000) { | |
2370 | pipe_config->hdmi_scrambling = true; | |
2371 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
2372 | } | |
2373 | } | |
2374 | ||
fbf08556 VS |
2375 | intel_hdmi_compute_gcp_infoframe(encoder, pipe_config, conn_state); |
2376 | ||
2377 | if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) { | |
2378 | DRM_DEBUG_KMS("bad AVI infoframe\n"); | |
2379 | return -EINVAL; | |
2380 | } | |
2381 | ||
2382 | if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) { | |
2383 | DRM_DEBUG_KMS("bad SPD infoframe\n"); | |
2384 | return -EINVAL; | |
2385 | } | |
2386 | ||
2387 | if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) { | |
2388 | DRM_DEBUG_KMS("bad HDMI infoframe\n"); | |
2389 | return -EINVAL; | |
2390 | } | |
2391 | ||
204474a6 | 2392 | return 0; |
7d57382e EA |
2393 | } |
2394 | ||
953ece69 CW |
2395 | static void |
2396 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 2397 | { |
df0e9248 | 2398 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 2399 | |
953ece69 CW |
2400 | intel_hdmi->has_hdmi_sink = false; |
2401 | intel_hdmi->has_audio = false; | |
953ece69 | 2402 | |
b1ba124d VS |
2403 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
2404 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
2405 | ||
953ece69 CW |
2406 | kfree(to_intel_connector(connector)->detect_edid); |
2407 | to_intel_connector(connector)->detect_edid = NULL; | |
2408 | } | |
2409 | ||
b1ba124d | 2410 | static void |
d6199256 | 2411 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
2412 | { |
2413 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2414 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
8f4f2797 | 2415 | enum port port = hdmi_to_dig_port(hdmi)->base.port; |
b1ba124d VS |
2416 | struct i2c_adapter *adapter = |
2417 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
2418 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
2419 | ||
d6199256 VS |
2420 | /* |
2421 | * Type 1 DVI adaptors are not required to implement any | |
2422 | * registers, so we can't always detect their presence. | |
2423 | * Ideally we should be able to check the state of the | |
2424 | * CONFIG1 pin, but no such luck on our hardware. | |
2425 | * | |
2426 | * The only method left to us is to check the VBT to see | |
2427 | * if the port is a dual mode capable DP port. But let's | |
2428 | * only do that when we sucesfully read the EDID, to avoid | |
2429 | * confusing log messages about DP dual mode adaptors when | |
2430 | * there's nothing connected to the port. | |
2431 | */ | |
2432 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
30190629 AJ |
2433 | /* An overridden EDID imply that we want this port for testing. |
2434 | * Make sure not to set limits for that port. | |
2435 | */ | |
2436 | if (has_edid && !connector->override_edid && | |
d6199256 VS |
2437 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { |
2438 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
2439 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
2440 | } else { | |
2441 | type = DRM_DP_DUAL_MODE_NONE; | |
2442 | } | |
2443 | } | |
2444 | ||
2445 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
2446 | return; |
2447 | ||
2448 | hdmi->dp_dual_mode.type = type; | |
2449 | hdmi->dp_dual_mode.max_tmds_clock = | |
2450 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
2451 | ||
2452 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
2453 | drm_dp_get_dual_mode_type_name(type), | |
2454 | hdmi->dp_dual_mode.max_tmds_clock); | |
2455 | } | |
2456 | ||
953ece69 | 2457 | static bool |
23f889bd | 2458 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
2459 | { |
2460 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
2461 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
0e6e0be4 | 2462 | intel_wakeref_t wakeref; |
23f889bd | 2463 | struct edid *edid; |
953ece69 | 2464 | bool connected = false; |
cfb926e1 | 2465 | struct i2c_adapter *i2c; |
164c8598 | 2466 | |
0e6e0be4 | 2467 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 2468 | |
cfb926e1 SB |
2469 | i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); |
2470 | ||
2471 | edid = drm_get_edid(connector, i2c); | |
2472 | ||
2473 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
2474 | DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
2475 | intel_gmbus_force_bit(i2c, true); | |
2476 | edid = drm_get_edid(connector, i2c); | |
2477 | intel_gmbus_force_bit(i2c, false); | |
2478 | } | |
2ded9e27 | 2479 | |
23f889bd | 2480 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 2481 | |
0e6e0be4 | 2482 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
30ad48b7 | 2483 | |
953ece69 CW |
2484 | to_intel_connector(connector)->detect_edid = edid; |
2485 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
953ece69 | 2486 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
7a5ca19f | 2487 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
2488 | |
2489 | connected = true; | |
55b7d6e8 CW |
2490 | } |
2491 | ||
9c229127 NA |
2492 | cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid); |
2493 | ||
953ece69 CW |
2494 | return connected; |
2495 | } | |
2496 | ||
8166fcea DV |
2497 | static enum drm_connector_status |
2498 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 2499 | { |
39d1e234 | 2500 | enum drm_connector_status status = connector_status_disconnected; |
8166fcea | 2501 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
9c229127 | 2502 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
39d1e234 | 2503 | struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; |
0e6e0be4 | 2504 | intel_wakeref_t wakeref; |
953ece69 | 2505 | |
8166fcea DV |
2506 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2507 | connector->base.id, connector->name); | |
2508 | ||
0e6e0be4 | 2509 | wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
29bb94bb | 2510 | |
2dd24a9c | 2511 | if (INTEL_GEN(dev_priv) >= 11 && |
39d1e234 PZ |
2512 | !intel_digital_port_connected(encoder)) |
2513 | goto out; | |
2514 | ||
8166fcea | 2515 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 2516 | |
7e732cac | 2517 | if (intel_hdmi_set_edid(connector)) |
953ece69 | 2518 | status = connector_status_connected; |
671dedd2 | 2519 | |
39d1e234 | 2520 | out: |
0e6e0be4 | 2521 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref); |
29bb94bb | 2522 | |
9c229127 NA |
2523 | if (status != connector_status_connected) |
2524 | cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); | |
2525 | ||
2ded9e27 | 2526 | return status; |
7d57382e EA |
2527 | } |
2528 | ||
953ece69 CW |
2529 | static void |
2530 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 2531 | { |
953ece69 CW |
2532 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
2533 | connector->base.id, connector->name); | |
7d57382e | 2534 | |
953ece69 | 2535 | intel_hdmi_unset_edid(connector); |
671dedd2 | 2536 | |
953ece69 CW |
2537 | if (connector->status != connector_status_connected) |
2538 | return; | |
671dedd2 | 2539 | |
23f889bd | 2540 | intel_hdmi_set_edid(connector); |
953ece69 | 2541 | } |
671dedd2 | 2542 | |
953ece69 CW |
2543 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
2544 | { | |
2545 | struct edid *edid; | |
2546 | ||
2547 | edid = to_intel_connector(connector)->detect_edid; | |
2548 | if (edid == NULL) | |
2549 | return 0; | |
671dedd2 | 2550 | |
953ece69 | 2551 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
2552 | } |
2553 | ||
fd6bbda9 | 2554 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2555 | const struct intel_crtc_state *pipe_config, |
2556 | const struct drm_connector_state *conn_state) | |
13732ba7 | 2557 | { |
f99be1b3 VS |
2558 | struct intel_digital_port *intel_dig_port = |
2559 | enc_to_dig_port(&encoder->base); | |
13732ba7 | 2560 | |
ac240288 | 2561 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2562 | |
790ea70c | 2563 | intel_dig_port->set_infoframes(encoder, |
f99be1b3 VS |
2564 | pipe_config->has_infoframe, |
2565 | pipe_config, conn_state); | |
13732ba7 JB |
2566 | } |
2567 | ||
fd6bbda9 | 2568 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2569 | const struct intel_crtc_state *pipe_config, |
2570 | const struct drm_connector_state *conn_state) | |
89b667f8 JB |
2571 | { |
2572 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2e1029c6 | 2573 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5f68c275 | 2574 | |
2e1029c6 | 2575 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
b76cf76b | 2576 | |
53d98725 ACO |
2577 | /* HDMI 1.0V-2dB */ |
2578 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
2579 | 0x2b247878); | |
2580 | ||
790ea70c | 2581 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2582 | pipe_config->has_infoframe, |
2583 | pipe_config, conn_state); | |
13732ba7 | 2584 | |
fd6bbda9 | 2585 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 2586 | |
9b6de0a1 | 2587 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
2588 | } |
2589 | ||
fd6bbda9 | 2590 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2591 | const struct intel_crtc_state *pipe_config, |
2592 | const struct drm_connector_state *conn_state) | |
89b667f8 | 2593 | { |
ac240288 | 2594 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 2595 | |
2e1029c6 | 2596 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
89b667f8 JB |
2597 | } |
2598 | ||
fd6bbda9 | 2599 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2600 | const struct intel_crtc_state *pipe_config, |
2601 | const struct drm_connector_state *conn_state) | |
9197c88b | 2602 | { |
ac240288 | 2603 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 2604 | |
2e1029c6 | 2605 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
2606 | } |
2607 | ||
fd6bbda9 | 2608 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2609 | const struct intel_crtc_state *old_crtc_state, |
2610 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 2611 | { |
2e1029c6 | 2612 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
2613 | } |
2614 | ||
fd6bbda9 | 2615 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2616 | const struct intel_crtc_state *old_crtc_state, |
2617 | const struct drm_connector_state *old_conn_state) | |
89b667f8 | 2618 | { |
89b667f8 | 2619 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
2e1029c6 | 2620 | vlv_phy_reset_lanes(encoder, old_crtc_state); |
89b667f8 JB |
2621 | } |
2622 | ||
fd6bbda9 | 2623 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2624 | const struct intel_crtc_state *old_crtc_state, |
2625 | const struct drm_connector_state *old_conn_state) | |
580d3811 | 2626 | { |
580d3811 | 2627 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 2628 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 2629 | |
a580516d | 2630 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 2631 | |
a8f327fb | 2632 | /* Assert data lane reset */ |
2e1029c6 | 2633 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 2634 | |
a580516d | 2635 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2636 | } |
2637 | ||
fd6bbda9 | 2638 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2639 | const struct intel_crtc_state *pipe_config, |
2640 | const struct drm_connector_state *conn_state) | |
e4a1d846 CML |
2641 | { |
2642 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2643 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2644 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 2645 | |
2e1029c6 | 2646 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
a02ef3c7 | 2647 | |
e4a1d846 CML |
2648 | /* FIXME: Program the support xxx V-dB */ |
2649 | /* Use 800mV-0dB */ | |
b7fa22d8 | 2650 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 2651 | |
790ea70c | 2652 | dport->set_infoframes(encoder, |
f99be1b3 VS |
2653 | pipe_config->has_infoframe, |
2654 | pipe_config, conn_state); | |
b4eb1564 | 2655 | |
fd6bbda9 | 2656 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 2657 | |
9b6de0a1 | 2658 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
2659 | |
2660 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2661 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2662 | } |
2663 | ||
bdc93fe0 R |
2664 | static int |
2665 | intel_hdmi_connector_register(struct drm_connector *connector) | |
2666 | { | |
2667 | int ret; | |
2668 | ||
2669 | ret = intel_connector_register(connector); | |
2670 | if (ret) | |
2671 | return ret; | |
2672 | ||
2673 | i915_debugfs_connector_add(connector); | |
2674 | ||
2675 | return ret; | |
2676 | } | |
2677 | ||
7d57382e EA |
2678 | static void intel_hdmi_destroy(struct drm_connector *connector) |
2679 | { | |
9c229127 NA |
2680 | if (intel_attached_hdmi(connector)->cec_notifier) |
2681 | cec_notifier_put(intel_attached_hdmi(connector)->cec_notifier); | |
d4b26e4f JN |
2682 | |
2683 | intel_connector_destroy(connector); | |
7d57382e EA |
2684 | } |
2685 | ||
7d57382e | 2686 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
7d57382e | 2687 | .detect = intel_hdmi_detect, |
953ece69 | 2688 | .force = intel_hdmi_force, |
7d57382e | 2689 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
2690 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
2691 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
bdc93fe0 | 2692 | .late_register = intel_hdmi_connector_register, |
c191eca1 | 2693 | .early_unregister = intel_connector_unregister, |
7d57382e | 2694 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 2695 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 2696 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
2697 | }; |
2698 | ||
2699 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
2700 | .get_modes = intel_hdmi_get_modes, | |
2701 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 2702 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
2703 | }; |
2704 | ||
7d57382e | 2705 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 2706 | .destroy = intel_encoder_destroy, |
7d57382e EA |
2707 | }; |
2708 | ||
55b7d6e8 CW |
2709 | static void |
2710 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
2711 | { | |
f1a12172 | 2712 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
2f146b78 US |
2713 | struct intel_digital_port *intel_dig_port = |
2714 | hdmi_to_dig_port(intel_hdmi); | |
f1a12172 | 2715 | |
3f43c48d | 2716 | intel_attach_force_audio_property(connector); |
e953fd7b | 2717 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 2718 | intel_attach_aspect_ratio_property(connector); |
2f146b78 US |
2719 | |
2720 | /* | |
2721 | * Attach Colorspace property for Non LSPCON based device | |
2722 | * ToDo: This needs to be extended for LSPCON implementation | |
2723 | * as well. Will be implemented separately. | |
2724 | */ | |
2725 | if (!intel_dig_port->lspcon.active) | |
2726 | intel_attach_colorspace_property(connector); | |
2727 | ||
6553b123 | 2728 | drm_connector_attach_content_type_property(connector); |
0e9f25d0 | 2729 | connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
f1a12172 | 2730 | |
b2ae318a | 2731 | if (!HAS_GMCH(dev_priv)) |
f1a12172 | 2732 | drm_connector_attach_max_bpc_property(connector, 8, 12); |
55b7d6e8 CW |
2733 | } |
2734 | ||
15953637 SS |
2735 | /* |
2736 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
2737 | * @encoder: intel_encoder | |
2738 | * @connector: drm_connector | |
2739 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
2740 | * or reset the high tmds clock ratio for scrambling | |
2741 | * @scrambling: bool to Indicate if the function needs to set or reset | |
2742 | * sink scrambling | |
2743 | * | |
2744 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
2745 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
2746 | * it enables scrambling. This should be called before enabling the HDMI | |
2747 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
2748 | * detect a scrambled clock within 100 ms. | |
277ab5ab VS |
2749 | * |
2750 | * Returns: | |
2751 | * True on success, false on failure. | |
15953637 | 2752 | */ |
277ab5ab | 2753 | bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, |
15953637 SS |
2754 | struct drm_connector *connector, |
2755 | bool high_tmds_clock_ratio, | |
2756 | bool scrambling) | |
2757 | { | |
277ab5ab | 2758 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
15953637 | 2759 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
15953637 | 2760 | struct drm_scrambling *sink_scrambling = |
277ab5ab VS |
2761 | &connector->display_info.hdmi.scdc.scrambling; |
2762 | struct i2c_adapter *adapter = | |
2763 | intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); | |
15953637 SS |
2764 | |
2765 | if (!sink_scrambling->supported) | |
277ab5ab | 2766 | return true; |
15953637 | 2767 | |
277ab5ab VS |
2768 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", |
2769 | connector->base.id, connector->name, | |
2770 | yesno(scrambling), high_tmds_clock_ratio ? 40 : 10); | |
15953637 | 2771 | |
277ab5ab VS |
2772 | /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */ |
2773 | return drm_scdc_set_high_tmds_clock_ratio(adapter, | |
2774 | high_tmds_clock_ratio) && | |
2775 | drm_scdc_set_scrambling(adapter, scrambling); | |
15953637 SS |
2776 | } |
2777 | ||
cec3bb01 | 2778 | static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
e4ab73a1 | 2779 | { |
e4ab73a1 VS |
2780 | u8 ddc_pin; |
2781 | ||
cec3bb01 AS |
2782 | switch (port) { |
2783 | case PORT_B: | |
2784 | ddc_pin = GMBUS_PIN_DPB; | |
2785 | break; | |
2786 | case PORT_C: | |
2787 | ddc_pin = GMBUS_PIN_DPC; | |
2788 | break; | |
2789 | case PORT_D: | |
2790 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
2791 | break; | |
2792 | default: | |
2793 | MISSING_CASE(port); | |
2794 | ddc_pin = GMBUS_PIN_DPB; | |
2795 | break; | |
e4ab73a1 | 2796 | } |
cec3bb01 AS |
2797 | return ddc_pin; |
2798 | } | |
2799 | ||
2800 | static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) | |
2801 | { | |
2802 | u8 ddc_pin; | |
e4ab73a1 VS |
2803 | |
2804 | switch (port) { | |
2805 | case PORT_B: | |
cec3bb01 | 2806 | ddc_pin = GMBUS_PIN_1_BXT; |
e4ab73a1 VS |
2807 | break; |
2808 | case PORT_C: | |
cec3bb01 AS |
2809 | ddc_pin = GMBUS_PIN_2_BXT; |
2810 | break; | |
2811 | default: | |
2812 | MISSING_CASE(port); | |
2813 | ddc_pin = GMBUS_PIN_1_BXT; | |
2814 | break; | |
2815 | } | |
2816 | return ddc_pin; | |
2817 | } | |
2818 | ||
2819 | static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
2820 | enum port port) | |
2821 | { | |
2822 | u8 ddc_pin; | |
2823 | ||
2824 | switch (port) { | |
2825 | case PORT_B: | |
2826 | ddc_pin = GMBUS_PIN_1_BXT; | |
2827 | break; | |
2828 | case PORT_C: | |
2829 | ddc_pin = GMBUS_PIN_2_BXT; | |
e4ab73a1 VS |
2830 | break; |
2831 | case PORT_D: | |
cec3bb01 AS |
2832 | ddc_pin = GMBUS_PIN_4_CNP; |
2833 | break; | |
3a2a59cc RV |
2834 | case PORT_F: |
2835 | ddc_pin = GMBUS_PIN_3_BXT; | |
2836 | break; | |
cec3bb01 AS |
2837 | default: |
2838 | MISSING_CASE(port); | |
2839 | ddc_pin = GMBUS_PIN_1_BXT; | |
2840 | break; | |
2841 | } | |
2842 | return ddc_pin; | |
2843 | } | |
2844 | ||
5c749c52 AS |
2845 | static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
2846 | { | |
2847 | u8 ddc_pin; | |
2848 | ||
2849 | switch (port) { | |
2850 | case PORT_A: | |
2851 | ddc_pin = GMBUS_PIN_1_BXT; | |
2852 | break; | |
2853 | case PORT_B: | |
2854 | ddc_pin = GMBUS_PIN_2_BXT; | |
2855 | break; | |
2856 | case PORT_C: | |
2857 | ddc_pin = GMBUS_PIN_9_TC1_ICP; | |
2858 | break; | |
2859 | case PORT_D: | |
2860 | ddc_pin = GMBUS_PIN_10_TC2_ICP; | |
2861 | break; | |
2862 | case PORT_E: | |
2863 | ddc_pin = GMBUS_PIN_11_TC3_ICP; | |
2864 | break; | |
2865 | case PORT_F: | |
2866 | ddc_pin = GMBUS_PIN_12_TC4_ICP; | |
2867 | break; | |
2868 | default: | |
2869 | MISSING_CASE(port); | |
2870 | ddc_pin = GMBUS_PIN_2_BXT; | |
2871 | break; | |
2872 | } | |
2873 | return ddc_pin; | |
2874 | } | |
2875 | ||
cec3bb01 AS |
2876 | static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, |
2877 | enum port port) | |
2878 | { | |
2879 | u8 ddc_pin; | |
2880 | ||
2881 | switch (port) { | |
2882 | case PORT_B: | |
2883 | ddc_pin = GMBUS_PIN_DPB; | |
2884 | break; | |
2885 | case PORT_C: | |
2886 | ddc_pin = GMBUS_PIN_DPC; | |
2887 | break; | |
2888 | case PORT_D: | |
2889 | ddc_pin = GMBUS_PIN_DPD; | |
e4ab73a1 VS |
2890 | break; |
2891 | default: | |
2892 | MISSING_CASE(port); | |
2893 | ddc_pin = GMBUS_PIN_DPB; | |
2894 | break; | |
2895 | } | |
cec3bb01 AS |
2896 | return ddc_pin; |
2897 | } | |
2898 | ||
2899 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, | |
2900 | enum port port) | |
2901 | { | |
2902 | const struct ddi_vbt_port_info *info = | |
2903 | &dev_priv->vbt.ddi_port_info[port]; | |
2904 | u8 ddc_pin; | |
2905 | ||
2906 | if (info->alternate_ddc_pin) { | |
2907 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
2908 | info->alternate_ddc_pin, port_name(port)); | |
2909 | return info->alternate_ddc_pin; | |
2910 | } | |
2911 | ||
e0f83eb5 RV |
2912 | if (HAS_PCH_ICP(dev_priv)) |
2913 | ddc_pin = icl_port_to_ddc_pin(dev_priv, port); | |
cec3bb01 AS |
2914 | else if (HAS_PCH_CNP(dev_priv)) |
2915 | ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); | |
e0f83eb5 RV |
2916 | else if (IS_GEN9_LP(dev_priv)) |
2917 | ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); | |
2918 | else if (IS_CHERRYVIEW(dev_priv)) | |
2919 | ddc_pin = chv_port_to_ddc_pin(dev_priv, port); | |
cec3bb01 AS |
2920 | else |
2921 | ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); | |
e4ab73a1 VS |
2922 | |
2923 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
2924 | ddc_pin, port_name(port)); | |
2925 | ||
2926 | return ddc_pin; | |
2927 | } | |
2928 | ||
385e4de0 VS |
2929 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port) |
2930 | { | |
2931 | struct drm_i915_private *dev_priv = | |
2932 | to_i915(intel_dig_port->base.base.dev); | |
2933 | ||
2934 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
2935 | intel_dig_port->write_infoframe = vlv_write_infoframe; | |
f2a10d61 | 2936 | intel_dig_port->read_infoframe = vlv_read_infoframe; |
385e4de0 | 2937 | intel_dig_port->set_infoframes = vlv_set_infoframes; |
509efa2b | 2938 | intel_dig_port->infoframes_enabled = vlv_infoframes_enabled; |
385e4de0 VS |
2939 | } else if (IS_G4X(dev_priv)) { |
2940 | intel_dig_port->write_infoframe = g4x_write_infoframe; | |
f2a10d61 | 2941 | intel_dig_port->read_infoframe = g4x_read_infoframe; |
385e4de0 | 2942 | intel_dig_port->set_infoframes = g4x_set_infoframes; |
509efa2b | 2943 | intel_dig_port->infoframes_enabled = g4x_infoframes_enabled; |
385e4de0 | 2944 | } else if (HAS_DDI(dev_priv)) { |
06c812d7 | 2945 | if (intel_dig_port->lspcon.active) { |
509efa2b | 2946 | intel_dig_port->write_infoframe = lspcon_write_infoframe; |
f2a10d61 | 2947 | intel_dig_port->read_infoframe = lspcon_read_infoframe; |
06c812d7 | 2948 | intel_dig_port->set_infoframes = lspcon_set_infoframes; |
509efa2b | 2949 | intel_dig_port->infoframes_enabled = lspcon_infoframes_enabled; |
06c812d7 | 2950 | } else { |
06c812d7 | 2951 | intel_dig_port->write_infoframe = hsw_write_infoframe; |
f2a10d61 | 2952 | intel_dig_port->read_infoframe = hsw_read_infoframe; |
509efa2b VS |
2953 | intel_dig_port->set_infoframes = hsw_set_infoframes; |
2954 | intel_dig_port->infoframes_enabled = hsw_infoframes_enabled; | |
06c812d7 | 2955 | } |
385e4de0 VS |
2956 | } else if (HAS_PCH_IBX(dev_priv)) { |
2957 | intel_dig_port->write_infoframe = ibx_write_infoframe; | |
f2a10d61 | 2958 | intel_dig_port->read_infoframe = ibx_read_infoframe; |
385e4de0 | 2959 | intel_dig_port->set_infoframes = ibx_set_infoframes; |
509efa2b | 2960 | intel_dig_port->infoframes_enabled = ibx_infoframes_enabled; |
385e4de0 VS |
2961 | } else { |
2962 | intel_dig_port->write_infoframe = cpt_write_infoframe; | |
f2a10d61 | 2963 | intel_dig_port->read_infoframe = cpt_read_infoframe; |
385e4de0 | 2964 | intel_dig_port->set_infoframes = cpt_set_infoframes; |
509efa2b | 2965 | intel_dig_port->infoframes_enabled = cpt_infoframes_enabled; |
385e4de0 VS |
2966 | } |
2967 | } | |
2968 | ||
00c09d70 PZ |
2969 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2970 | struct intel_connector *intel_connector) | |
7d57382e | 2971 | { |
b9cb234c PZ |
2972 | struct drm_connector *connector = &intel_connector->base; |
2973 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
2974 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2975 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 2976 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 2977 | enum port port = intel_encoder->port; |
373a3cf7 | 2978 | |
22f35042 VS |
2979 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2980 | port_name(port)); | |
2981 | ||
ccb1a831 VS |
2982 | if (WARN(intel_dig_port->max_lanes < 4, |
2983 | "Not enough lanes (%d) for HDMI on port %c\n", | |
2984 | intel_dig_port->max_lanes, port_name(port))) | |
2985 | return; | |
2986 | ||
7d57382e | 2987 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 2988 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
2989 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2990 | ||
c3febcc4 | 2991 | connector->interlace_allowed = 1; |
7d57382e | 2992 | connector->doublescan_allowed = 0; |
573e74ad | 2993 | connector->stereo_allowed = 1; |
66a9278e | 2994 | |
9672a69c | 2995 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
eadc2e51 SS |
2996 | connector->ycbcr_420_allowed = true; |
2997 | ||
e4ab73a1 VS |
2998 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
2999 | ||
f761bef2 | 3000 | if (WARN_ON(port == PORT_A)) |
e4ab73a1 | 3001 | return; |
cf53902f | 3002 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
7d57382e | 3003 | |
4f8036a2 | 3004 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
3005 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
3006 | else | |
3007 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
3008 | |
3009 | intel_hdmi_add_properties(intel_hdmi, connector); | |
3010 | ||
04707f97 R |
3011 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
3012 | intel_hdmi->attached_connector = intel_connector; | |
3013 | ||
fdddd08c | 3014 | if (is_hdcp_supported(dev_priv, port)) { |
2320175f SP |
3015 | int ret = intel_hdcp_init(intel_connector, |
3016 | &intel_hdmi_hdcp_shim); | |
3017 | if (ret) | |
3018 | DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); | |
3019 | } | |
3020 | ||
b9cb234c PZ |
3021 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
3022 | * 0xd. Failure to do so will result in spurious interrupts being | |
3023 | * generated on the port when a cable is not attached. | |
3024 | */ | |
1c0f1b3d | 3025 | if (IS_G45(dev_priv)) { |
b9cb234c PZ |
3026 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
3027 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
3028 | } | |
9c229127 NA |
3029 | |
3030 | intel_hdmi->cec_notifier = cec_notifier_get_conn(dev->dev, | |
3031 | port_identifier(port)); | |
3032 | if (!intel_hdmi->cec_notifier) | |
3033 | DRM_DEBUG_KMS("CEC notifier get failed\n"); | |
b9cb234c PZ |
3034 | } |
3035 | ||
c39055b0 | 3036 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 3037 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
3038 | { |
3039 | struct intel_digital_port *intel_dig_port; | |
3040 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
3041 | struct intel_connector *intel_connector; |
3042 | ||
b14c5679 | 3043 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
3044 | if (!intel_dig_port) |
3045 | return; | |
3046 | ||
08d9bc92 | 3047 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
3048 | if (!intel_connector) { |
3049 | kfree(intel_dig_port); | |
3050 | return; | |
3051 | } | |
3052 | ||
3053 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 3054 | |
c39055b0 ACO |
3055 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
3056 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
3057 | "HDMI %c", port_name(port)); | |
00c09d70 | 3058 | |
dba14b27 | 3059 | intel_encoder->hotplug = intel_encoder_hotplug; |
5bfe2ac0 | 3060 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 3061 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
3062 | intel_encoder->disable = pch_disable_hdmi; |
3063 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
3064 | } else { | |
3065 | intel_encoder->disable = g4x_disable_hdmi; | |
3066 | } | |
00c09d70 | 3067 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 3068 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 3069 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 3070 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
3071 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
3072 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 3073 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 3074 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 3075 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
3076 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
3077 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 3078 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 3079 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 3080 | } else { |
13732ba7 | 3081 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 3082 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 3083 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 3084 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 3085 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 3086 | else |
bf868c7d | 3087 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 3088 | } |
5ab432ef | 3089 | |
b9cb234c | 3090 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 3091 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 3092 | intel_encoder->port = port; |
920a14b2 | 3093 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
3094 | if (port == PORT_D) |
3095 | intel_encoder->crtc_mask = 1 << 2; | |
3096 | else | |
3097 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
3098 | } else { | |
3099 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
3100 | } | |
301ea74a | 3101 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
3102 | /* |
3103 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
3104 | * to work on real hardware. And since g4x can send infoframes to | |
3105 | * only one port anyway, nothing is lost by allowing it. | |
3106 | */ | |
9beb5fea | 3107 | if (IS_G4X(dev_priv)) |
c6f1495d | 3108 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 3109 | |
b242b7f7 | 3110 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 3111 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 3112 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 3113 | |
385e4de0 VS |
3114 | intel_infoframe_init(intel_dig_port); |
3115 | ||
39053089 | 3116 | intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); |
b9cb234c | 3117 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 3118 | } |