Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
7d57382e | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
7d57382e EA |
39 | #include "i915_drv.h" |
40 | ||
30add22d PZ |
41 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
42 | { | |
da63a9f2 | 43 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
44 | } |
45 | ||
afba0188 DV |
46 | static void |
47 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
48 | { | |
30add22d | 49 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
50 | struct drm_i915_private *dev_priv = dev->dev_private; |
51 | uint32_t enabled_bits; | |
52 | ||
affa9354 | 53 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 54 | |
b242b7f7 | 55 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
56 | "HDMI port enabled, expecting disabled\n"); |
57 | } | |
58 | ||
f5bbfca3 | 59 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 60 | { |
da63a9f2 PZ |
61 | struct intel_digital_port *intel_dig_port = |
62 | container_of(encoder, struct intel_digital_port, base.base); | |
63 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
64 | } |
65 | ||
df0e9248 CW |
66 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
67 | { | |
da63a9f2 | 68 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
69 | } |
70 | ||
178f736a | 71 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 72 | { |
178f736a DL |
73 | switch (type) { |
74 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 75 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 76 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 77 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
78 | case HDMI_INFOFRAME_TYPE_VENDOR: |
79 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 80 | default: |
ffc85dab | 81 | MISSING_CASE(type); |
ed517fbb | 82 | return 0; |
45187ace | 83 | } |
45187ace JB |
84 | } |
85 | ||
178f736a | 86 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 87 | { |
178f736a DL |
88 | switch (type) { |
89 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 90 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 91 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 92 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
93 | case HDMI_INFOFRAME_TYPE_VENDOR: |
94 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 95 | default: |
ffc85dab | 96 | MISSING_CASE(type); |
ed517fbb | 97 | return 0; |
fa193ff7 | 98 | } |
fa193ff7 PZ |
99 | } |
100 | ||
178f736a | 101 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 102 | { |
178f736a DL |
103 | switch (type) { |
104 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 105 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 106 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 107 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
108 | case HDMI_INFOFRAME_TYPE_VENDOR: |
109 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 110 | default: |
ffc85dab | 111 | MISSING_CASE(type); |
2da8af54 PZ |
112 | return 0; |
113 | } | |
114 | } | |
115 | ||
f0f59a00 VS |
116 | static i915_reg_t |
117 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
118 | enum transcoder cpu_transcoder, | |
119 | enum hdmi_infoframe_type type, | |
120 | int i) | |
2da8af54 | 121 | { |
178f736a DL |
122 | switch (type) { |
123 | case HDMI_INFOFRAME_TYPE_AVI: | |
436c6d4a | 124 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 125 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 126 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 127 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 128 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 129 | default: |
ffc85dab | 130 | MISSING_CASE(type); |
f0f59a00 | 131 | return INVALID_MMIO_REG; |
2da8af54 PZ |
132 | } |
133 | } | |
134 | ||
a3da1df7 | 135 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 136 | enum hdmi_infoframe_type type, |
fff63867 | 137 | const void *frame, ssize_t len) |
45187ace | 138 | { |
fff63867 | 139 | const uint32_t *data = frame; |
3c17fe4b DH |
140 | struct drm_device *dev = encoder->dev; |
141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 142 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 143 | int i; |
3c17fe4b | 144 | |
822974ae PZ |
145 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
146 | ||
1d4f85ac | 147 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 148 | val |= g4x_infoframe_index(type); |
22509ec8 | 149 | |
178f736a | 150 | val &= ~g4x_infoframe_enable(type); |
45187ace | 151 | |
22509ec8 | 152 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 153 | |
9d9740f0 | 154 | mmiowb(); |
45187ace | 155 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
156 | I915_WRITE(VIDEO_DIP_DATA, *data); |
157 | data++; | |
158 | } | |
adf00b26 PZ |
159 | /* Write every possible data byte to force correct ECC calculation. */ |
160 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
161 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 162 | mmiowb(); |
3c17fe4b | 163 | |
178f736a | 164 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 165 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 166 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 167 | |
22509ec8 | 168 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 169 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
170 | } |
171 | ||
cda0aaaf VS |
172 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder, |
173 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 174 | { |
cda0aaaf | 175 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
89a35ecd | 176 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
177 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178 | ||
ec1dc603 VS |
179 | if ((val & VIDEO_DIP_ENABLE) == 0) |
180 | return false; | |
89a35ecd | 181 | |
ec1dc603 VS |
182 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) |
183 | return false; | |
184 | ||
185 | return val & (VIDEO_DIP_ENABLE_AVI | | |
186 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
187 | } |
188 | ||
fdf1250a | 189 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 190 | enum hdmi_infoframe_type type, |
fff63867 | 191 | const void *frame, ssize_t len) |
fdf1250a | 192 | { |
fff63867 | 193 | const uint32_t *data = frame; |
fdf1250a PZ |
194 | struct drm_device *dev = encoder->dev; |
195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 196 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
f0f59a00 | 197 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 198 | u32 val = I915_READ(reg); |
f0f59a00 | 199 | int i; |
fdf1250a | 200 | |
822974ae PZ |
201 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
202 | ||
fdf1250a | 203 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 204 | val |= g4x_infoframe_index(type); |
fdf1250a | 205 | |
178f736a | 206 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
207 | |
208 | I915_WRITE(reg, val); | |
209 | ||
9d9740f0 | 210 | mmiowb(); |
fdf1250a PZ |
211 | for (i = 0; i < len; i += 4) { |
212 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
213 | data++; | |
214 | } | |
adf00b26 PZ |
215 | /* Write every possible data byte to force correct ECC calculation. */ |
216 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
217 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 218 | mmiowb(); |
fdf1250a | 219 | |
178f736a | 220 | val |= g4x_infoframe_enable(type); |
fdf1250a | 221 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 222 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
223 | |
224 | I915_WRITE(reg, val); | |
9d9740f0 | 225 | POSTING_READ(reg); |
fdf1250a PZ |
226 | } |
227 | ||
cda0aaaf VS |
228 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder, |
229 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 230 | { |
cda0aaaf | 231 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
052f62f7 | 232 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
233 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
234 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
235 | u32 val = I915_READ(reg); |
236 | ||
ec1dc603 VS |
237 | if ((val & VIDEO_DIP_ENABLE) == 0) |
238 | return false; | |
239 | ||
240 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
241 | return false; | |
052f62f7 | 242 | |
ec1dc603 VS |
243 | return val & (VIDEO_DIP_ENABLE_AVI | |
244 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
245 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
246 | } |
247 | ||
fdf1250a | 248 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
178f736a | 249 | enum hdmi_infoframe_type type, |
fff63867 | 250 | const void *frame, ssize_t len) |
b055c8f3 | 251 | { |
fff63867 | 252 | const uint32_t *data = frame; |
b055c8f3 JB |
253 | struct drm_device *dev = encoder->dev; |
254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 255 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
f0f59a00 | 256 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 257 | u32 val = I915_READ(reg); |
f0f59a00 | 258 | int i; |
b055c8f3 | 259 | |
822974ae PZ |
260 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
261 | ||
64a8fc01 | 262 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 263 | val |= g4x_infoframe_index(type); |
45187ace | 264 | |
ecb97851 PZ |
265 | /* The DIP control register spec says that we need to update the AVI |
266 | * infoframe without clearing its enable bit */ | |
178f736a DL |
267 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
268 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 269 | |
22509ec8 | 270 | I915_WRITE(reg, val); |
45187ace | 271 | |
9d9740f0 | 272 | mmiowb(); |
45187ace | 273 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
274 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
275 | data++; | |
276 | } | |
adf00b26 PZ |
277 | /* Write every possible data byte to force correct ECC calculation. */ |
278 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
279 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 280 | mmiowb(); |
b055c8f3 | 281 | |
178f736a | 282 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 283 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 284 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 285 | |
22509ec8 | 286 | I915_WRITE(reg, val); |
9d9740f0 | 287 | POSTING_READ(reg); |
45187ace | 288 | } |
90b107c8 | 289 | |
cda0aaaf VS |
290 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder, |
291 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 292 | { |
cda0aaaf VS |
293 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
294 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; | |
295 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 296 | |
ec1dc603 VS |
297 | if ((val & VIDEO_DIP_ENABLE) == 0) |
298 | return false; | |
299 | ||
300 | return val & (VIDEO_DIP_ENABLE_AVI | | |
301 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
302 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
303 | } |
304 | ||
90b107c8 | 305 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
178f736a | 306 | enum hdmi_infoframe_type type, |
fff63867 | 307 | const void *frame, ssize_t len) |
90b107c8 | 308 | { |
fff63867 | 309 | const uint32_t *data = frame; |
90b107c8 SK |
310 | struct drm_device *dev = encoder->dev; |
311 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 312 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
f0f59a00 | 313 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 314 | u32 val = I915_READ(reg); |
f0f59a00 | 315 | int i; |
90b107c8 | 316 | |
822974ae PZ |
317 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
318 | ||
90b107c8 | 319 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 320 | val |= g4x_infoframe_index(type); |
22509ec8 | 321 | |
178f736a | 322 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 323 | |
22509ec8 | 324 | I915_WRITE(reg, val); |
90b107c8 | 325 | |
9d9740f0 | 326 | mmiowb(); |
90b107c8 SK |
327 | for (i = 0; i < len; i += 4) { |
328 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
329 | data++; | |
330 | } | |
adf00b26 PZ |
331 | /* Write every possible data byte to force correct ECC calculation. */ |
332 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
333 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 334 | mmiowb(); |
90b107c8 | 335 | |
178f736a | 336 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 337 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 338 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 339 | |
22509ec8 | 340 | I915_WRITE(reg, val); |
9d9740f0 | 341 | POSTING_READ(reg); |
90b107c8 SK |
342 | } |
343 | ||
cda0aaaf VS |
344 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder, |
345 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 346 | { |
cda0aaaf | 347 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
535afa2e | 348 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
349 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
350 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 351 | |
ec1dc603 VS |
352 | if ((val & VIDEO_DIP_ENABLE) == 0) |
353 | return false; | |
354 | ||
355 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | |
356 | return false; | |
535afa2e | 357 | |
ec1dc603 VS |
358 | return val & (VIDEO_DIP_ENABLE_AVI | |
359 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
360 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
361 | } |
362 | ||
8c5f5f7c | 363 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 364 | enum hdmi_infoframe_type type, |
fff63867 | 365 | const void *frame, ssize_t len) |
8c5f5f7c | 366 | { |
fff63867 | 367 | const uint32_t *data = frame; |
2da8af54 PZ |
368 | struct drm_device *dev = encoder->dev; |
369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
370 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
436c6d4a | 371 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
f0f59a00 VS |
372 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
373 | i915_reg_t data_reg; | |
178f736a | 374 | int i; |
2da8af54 | 375 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 376 | |
436c6d4a | 377 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
2da8af54 | 378 | |
178f736a | 379 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
380 | I915_WRITE(ctl_reg, val); |
381 | ||
9d9740f0 | 382 | mmiowb(); |
2da8af54 | 383 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
384 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
385 | type, i >> 2), *data); | |
2da8af54 PZ |
386 | data++; |
387 | } | |
adf00b26 PZ |
388 | /* Write every possible data byte to force correct ECC calculation. */ |
389 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
436c6d4a VS |
390 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
391 | type, i >> 2), 0); | |
9d9740f0 | 392 | mmiowb(); |
8c5f5f7c | 393 | |
178f736a | 394 | val |= hsw_infoframe_enable(type); |
2da8af54 | 395 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 396 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
397 | } |
398 | ||
cda0aaaf VS |
399 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder, |
400 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 401 | { |
cda0aaaf VS |
402 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
403 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); | |
e43823ec | 404 | |
ec1dc603 VS |
405 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
406 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
407 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
408 | } |
409 | ||
5adaea79 DL |
410 | /* |
411 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
412 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
413 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
414 | * used for both technologies. | |
415 | * | |
416 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
417 | * DW1: DB3 | DB2 | DB1 | DB0 | |
418 | * DW2: DB7 | DB6 | DB5 | DB4 | |
419 | * DW3: ... | |
420 | * | |
421 | * (HB is Header Byte, DB is Data Byte) | |
422 | * | |
423 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
424 | * trick them by giving an offset into the buffer and moving back the header | |
425 | * bytes by one. | |
426 | */ | |
9198ee5b DL |
427 | static void intel_write_infoframe(struct drm_encoder *encoder, |
428 | union hdmi_infoframe *frame) | |
45187ace JB |
429 | { |
430 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
431 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
432 | ssize_t len; | |
45187ace | 433 | |
5adaea79 DL |
434 | /* see comment above for the reason for this offset */ |
435 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
436 | if (len < 0) | |
437 | return; | |
438 | ||
439 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
440 | buffer[0] = buffer[1]; | |
441 | buffer[1] = buffer[2]; | |
442 | buffer[2] = buffer[3]; | |
443 | buffer[3] = 0; | |
444 | len++; | |
45187ace | 445 | |
5adaea79 | 446 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
447 | } |
448 | ||
687f4d06 | 449 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
7c5f93b0 | 450 | const struct drm_display_mode *adjusted_mode) |
45187ace | 451 | { |
abedc077 | 452 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 453 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
454 | union hdmi_infoframe frame; |
455 | int ret; | |
45187ace | 456 | |
5adaea79 DL |
457 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
458 | adjusted_mode); | |
459 | if (ret < 0) { | |
460 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
461 | return; | |
462 | } | |
c846b619 | 463 | |
abedc077 | 464 | if (intel_hdmi->rgb_quant_range_selectable) { |
6e3c9717 | 465 | if (intel_crtc->config->limited_color_range) |
5adaea79 DL |
466 | frame.avi.quantization_range = |
467 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 468 | else |
5adaea79 DL |
469 | frame.avi.quantization_range = |
470 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
471 | } |
472 | ||
9198ee5b | 473 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
474 | } |
475 | ||
687f4d06 | 476 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 477 | { |
5adaea79 DL |
478 | union hdmi_infoframe frame; |
479 | int ret; | |
480 | ||
481 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
482 | if (ret < 0) { | |
483 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
484 | return; | |
485 | } | |
c0864cb3 | 486 | |
5adaea79 | 487 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 488 | |
9198ee5b | 489 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
490 | } |
491 | ||
c8bb75af LD |
492 | static void |
493 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
7c5f93b0 | 494 | const struct drm_display_mode *adjusted_mode) |
c8bb75af LD |
495 | { |
496 | union hdmi_infoframe frame; | |
497 | int ret; | |
498 | ||
499 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
500 | adjusted_mode); | |
501 | if (ret < 0) | |
502 | return; | |
503 | ||
504 | intel_write_infoframe(encoder, &frame); | |
505 | } | |
506 | ||
687f4d06 | 507 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 508 | bool enable, |
7c5f93b0 | 509 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 510 | { |
0c14c7f9 | 511 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
512 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
513 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 514 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 515 | u32 val = I915_READ(reg); |
822cdc52 | 516 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 517 | |
afba0188 DV |
518 | assert_hdmi_port_disabled(intel_hdmi); |
519 | ||
0c14c7f9 PZ |
520 | /* If the registers were not initialized yet, they might be zeroes, |
521 | * which means we're selecting the AVI DIP and we're setting its | |
522 | * frequency to once. This seems to really confuse the HW and make | |
523 | * things stop working (the register spec says the AVI always needs to | |
524 | * be sent every VSync). So here we avoid writing to the register more | |
525 | * than we need and also explicitly select the AVI DIP and explicitly | |
526 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
527 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
528 | * either. */ | |
529 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
530 | ||
6897b4b5 | 531 | if (!enable) { |
0c14c7f9 PZ |
532 | if (!(val & VIDEO_DIP_ENABLE)) |
533 | return; | |
0be6f0c8 VS |
534 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
535 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
536 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
537 | return; | |
538 | } | |
539 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
540 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 541 | I915_WRITE(reg, val); |
9d9740f0 | 542 | POSTING_READ(reg); |
0c14c7f9 PZ |
543 | return; |
544 | } | |
545 | ||
72b78c9d PZ |
546 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
547 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
548 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
549 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
550 | return; | |
72b78c9d PZ |
551 | } |
552 | val &= ~VIDEO_DIP_PORT_MASK; | |
553 | val |= port; | |
554 | } | |
555 | ||
822974ae | 556 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
557 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
558 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 559 | |
f278d972 | 560 | I915_WRITE(reg, val); |
9d9740f0 | 561 | POSTING_READ(reg); |
f278d972 | 562 | |
687f4d06 PZ |
563 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
564 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 565 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
566 | } |
567 | ||
6d67415f VS |
568 | static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder) |
569 | { | |
570 | struct drm_device *dev = encoder->dev; | |
571 | struct drm_connector *connector; | |
572 | ||
573 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); | |
574 | ||
575 | /* | |
576 | * HDMI cloning is only supported on g4x which doesn't | |
577 | * support deep color or GCP infoframes anyway so no | |
578 | * need to worry about multiple HDMI sinks here. | |
579 | */ | |
580 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) | |
581 | if (connector->encoder == encoder) | |
582 | return connector->display_info.bpc > 8; | |
583 | ||
584 | return false; | |
585 | } | |
586 | ||
12aa3290 VS |
587 | /* |
588 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
589 | * | |
590 | * From HDMI specification 1.4a: | |
591 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
592 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
593 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
594 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
595 | * phase of 0 | |
596 | */ | |
597 | static bool gcp_default_phase_possible(int pipe_bpp, | |
598 | const struct drm_display_mode *mode) | |
599 | { | |
600 | unsigned int pixels_per_group; | |
601 | ||
602 | switch (pipe_bpp) { | |
603 | case 30: | |
604 | /* 4 pixels in 5 clocks */ | |
605 | pixels_per_group = 4; | |
606 | break; | |
607 | case 36: | |
608 | /* 2 pixels in 3 clocks */ | |
609 | pixels_per_group = 2; | |
610 | break; | |
611 | case 48: | |
612 | /* 1 pixel in 2 clocks */ | |
613 | pixels_per_group = 1; | |
614 | break; | |
615 | default: | |
616 | /* phase information not relevant for 8bpc */ | |
617 | return false; | |
618 | } | |
619 | ||
620 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
621 | mode->crtc_htotal % pixels_per_group == 0 && | |
622 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
623 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
624 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
625 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
626 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
627 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
628 | } | |
629 | ||
6d67415f VS |
630 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder) |
631 | { | |
632 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
633 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); | |
f0f59a00 VS |
634 | i915_reg_t reg; |
635 | u32 val = 0; | |
6d67415f VS |
636 | |
637 | if (HAS_DDI(dev_priv)) | |
638 | reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder); | |
666a4537 | 639 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f VS |
640 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
641 | else if (HAS_PCH_SPLIT(dev_priv->dev)) | |
642 | reg = TVIDEO_DIP_GCP(crtc->pipe); | |
643 | else | |
644 | return false; | |
645 | ||
646 | /* Indicate color depth whenever the sink supports deep color */ | |
647 | if (hdmi_sink_is_deep_color(encoder)) | |
648 | val |= GCP_COLOR_INDICATION; | |
649 | ||
12aa3290 VS |
650 | /* Enable default_phase whenever the display mode is suitably aligned */ |
651 | if (gcp_default_phase_possible(crtc->config->pipe_bpp, | |
652 | &crtc->config->base.adjusted_mode)) | |
653 | val |= GCP_DEFAULT_PHASE_ENABLE; | |
654 | ||
6d67415f VS |
655 | I915_WRITE(reg, val); |
656 | ||
657 | return val != 0; | |
658 | } | |
659 | ||
687f4d06 | 660 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 661 | bool enable, |
7c5f93b0 | 662 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 663 | { |
0c14c7f9 PZ |
664 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
665 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
666 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
667 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 668 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 669 | u32 val = I915_READ(reg); |
822cdc52 | 670 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 671 | |
afba0188 DV |
672 | assert_hdmi_port_disabled(intel_hdmi); |
673 | ||
0c14c7f9 PZ |
674 | /* See the big comment in g4x_set_infoframes() */ |
675 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
676 | ||
6897b4b5 | 677 | if (!enable) { |
0c14c7f9 PZ |
678 | if (!(val & VIDEO_DIP_ENABLE)) |
679 | return; | |
0be6f0c8 VS |
680 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
681 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
682 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 683 | I915_WRITE(reg, val); |
9d9740f0 | 684 | POSTING_READ(reg); |
0c14c7f9 PZ |
685 | return; |
686 | } | |
687 | ||
72b78c9d | 688 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
689 | WARN(val & VIDEO_DIP_ENABLE, |
690 | "DIP already enabled on port %c\n", | |
691 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
692 | val &= ~VIDEO_DIP_PORT_MASK; |
693 | val |= port; | |
694 | } | |
695 | ||
822974ae | 696 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
697 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
698 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
699 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 700 | |
6d67415f VS |
701 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
702 | val |= VIDEO_DIP_ENABLE_GCP; | |
703 | ||
f278d972 | 704 | I915_WRITE(reg, val); |
9d9740f0 | 705 | POSTING_READ(reg); |
f278d972 | 706 | |
687f4d06 PZ |
707 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
708 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 709 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
710 | } |
711 | ||
712 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 713 | bool enable, |
7c5f93b0 | 714 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 715 | { |
0c14c7f9 PZ |
716 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
717 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
718 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
f0f59a00 | 719 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
720 | u32 val = I915_READ(reg); |
721 | ||
afba0188 DV |
722 | assert_hdmi_port_disabled(intel_hdmi); |
723 | ||
0c14c7f9 PZ |
724 | /* See the big comment in g4x_set_infoframes() */ |
725 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
726 | ||
6897b4b5 | 727 | if (!enable) { |
0c14c7f9 PZ |
728 | if (!(val & VIDEO_DIP_ENABLE)) |
729 | return; | |
0be6f0c8 VS |
730 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
731 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
732 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 733 | I915_WRITE(reg, val); |
9d9740f0 | 734 | POSTING_READ(reg); |
0c14c7f9 PZ |
735 | return; |
736 | } | |
737 | ||
822974ae PZ |
738 | /* Set both together, unset both together: see the spec. */ |
739 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 740 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 741 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 742 | |
6d67415f VS |
743 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
744 | val |= VIDEO_DIP_ENABLE_GCP; | |
745 | ||
822974ae | 746 | I915_WRITE(reg, val); |
9d9740f0 | 747 | POSTING_READ(reg); |
822974ae | 748 | |
687f4d06 PZ |
749 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
750 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 751 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
752 | } |
753 | ||
754 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 755 | bool enable, |
7c5f93b0 | 756 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 757 | { |
0c14c7f9 | 758 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 759 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
760 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
761 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
f0f59a00 | 762 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 763 | u32 val = I915_READ(reg); |
6a2b8021 | 764 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 765 | |
afba0188 DV |
766 | assert_hdmi_port_disabled(intel_hdmi); |
767 | ||
0c14c7f9 PZ |
768 | /* See the big comment in g4x_set_infoframes() */ |
769 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
770 | ||
6897b4b5 | 771 | if (!enable) { |
0c14c7f9 PZ |
772 | if (!(val & VIDEO_DIP_ENABLE)) |
773 | return; | |
0be6f0c8 VS |
774 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
775 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
776 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 777 | I915_WRITE(reg, val); |
9d9740f0 | 778 | POSTING_READ(reg); |
0c14c7f9 PZ |
779 | return; |
780 | } | |
781 | ||
6a2b8021 | 782 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
783 | WARN(val & VIDEO_DIP_ENABLE, |
784 | "DIP already enabled on port %c\n", | |
785 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
786 | val &= ~VIDEO_DIP_PORT_MASK; |
787 | val |= port; | |
788 | } | |
789 | ||
822974ae | 790 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
791 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
792 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
793 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 794 | |
6d67415f VS |
795 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
796 | val |= VIDEO_DIP_ENABLE_GCP; | |
797 | ||
822974ae | 798 | I915_WRITE(reg, val); |
9d9740f0 | 799 | POSTING_READ(reg); |
822974ae | 800 | |
687f4d06 PZ |
801 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
802 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 803 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
804 | } |
805 | ||
806 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 807 | bool enable, |
7c5f93b0 | 808 | const struct drm_display_mode *adjusted_mode) |
687f4d06 | 809 | { |
0c14c7f9 PZ |
810 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
811 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
812 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
f0f59a00 | 813 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder); |
0dd87d20 | 814 | u32 val = I915_READ(reg); |
0c14c7f9 | 815 | |
afba0188 DV |
816 | assert_hdmi_port_disabled(intel_hdmi); |
817 | ||
0be6f0c8 VS |
818 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
819 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
820 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
821 | ||
6897b4b5 | 822 | if (!enable) { |
0be6f0c8 | 823 | I915_WRITE(reg, val); |
9d9740f0 | 824 | POSTING_READ(reg); |
0c14c7f9 PZ |
825 | return; |
826 | } | |
827 | ||
6d67415f VS |
828 | if (intel_hdmi_set_gcp_infoframe(encoder)) |
829 | val |= VIDEO_DIP_ENABLE_GCP_HSW; | |
830 | ||
0dd87d20 | 831 | I915_WRITE(reg, val); |
9d9740f0 | 832 | POSTING_READ(reg); |
0dd87d20 | 833 | |
687f4d06 PZ |
834 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
835 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 836 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
837 | } |
838 | ||
4cde8a21 | 839 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 840 | { |
c59423a3 | 841 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 842 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
843 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
844 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
7c5f93b0 | 845 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
b242b7f7 | 846 | u32 hdmi_val; |
7d57382e | 847 | |
b242b7f7 | 848 | hdmi_val = SDVO_ENCODING_HDMI; |
0f2a2a75 VS |
849 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
850 | hdmi_val |= HDMI_COLOR_RANGE_16_235; | |
b599c0bc | 851 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 852 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 853 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 854 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 855 | |
6e3c9717 | 856 | if (crtc->config->pipe_bpp > 24) |
4f3a8bc7 | 857 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 858 | else |
4f3a8bc7 | 859 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 860 | |
6e3c9717 | 861 | if (crtc->config->has_hdmi_sink) |
dc0fa718 | 862 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 863 | |
75770564 | 864 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 865 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
866 | else if (IS_CHERRYVIEW(dev)) |
867 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 868 | else |
c59423a3 | 869 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 870 | |
b242b7f7 PZ |
871 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
872 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
873 | } |
874 | ||
85234cdc DV |
875 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
876 | enum pipe *pipe) | |
7d57382e | 877 | { |
85234cdc | 878 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 879 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 880 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 881 | enum intel_display_power_domain power_domain; |
85234cdc DV |
882 | u32 tmp; |
883 | ||
6d129bea | 884 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 885 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
886 | return false; |
887 | ||
b242b7f7 | 888 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
889 | |
890 | if (!(tmp & SDVO_ENABLE)) | |
891 | return false; | |
892 | ||
893 | if (HAS_PCH_CPT(dev)) | |
894 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
895 | else if (IS_CHERRYVIEW(dev)) |
896 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
897 | else |
898 | *pipe = PORT_TO_PIPE(tmp); | |
899 | ||
900 | return true; | |
901 | } | |
902 | ||
045ac3b5 | 903 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 904 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
905 | { |
906 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
8c875fca VS |
907 | struct drm_device *dev = encoder->base.dev; |
908 | struct drm_i915_private *dev_priv = dev->dev_private; | |
045ac3b5 | 909 | u32 tmp, flags = 0; |
18442d08 | 910 | int dotclock; |
045ac3b5 JB |
911 | |
912 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
913 | ||
914 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
915 | flags |= DRM_MODE_FLAG_PHSYNC; | |
916 | else | |
917 | flags |= DRM_MODE_FLAG_NHSYNC; | |
918 | ||
919 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
920 | flags |= DRM_MODE_FLAG_PVSYNC; | |
921 | else | |
922 | flags |= DRM_MODE_FLAG_NVSYNC; | |
923 | ||
6897b4b5 DV |
924 | if (tmp & HDMI_MODE_SELECT_HDMI) |
925 | pipe_config->has_hdmi_sink = true; | |
926 | ||
cda0aaaf | 927 | if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config)) |
e43823ec JB |
928 | pipe_config->has_infoframe = true; |
929 | ||
c84db770 | 930 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
931 | pipe_config->has_audio = true; |
932 | ||
8c875fca VS |
933 | if (!HAS_PCH_SPLIT(dev) && |
934 | tmp & HDMI_COLOR_RANGE_16_235) | |
935 | pipe_config->limited_color_range = true; | |
936 | ||
2d112de7 | 937 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
938 | |
939 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
940 | dotclock = pipe_config->port_clock * 2 / 3; | |
941 | else | |
942 | dotclock = pipe_config->port_clock; | |
943 | ||
be69a133 VS |
944 | if (pipe_config->pixel_multiplier) |
945 | dotclock /= pipe_config->pixel_multiplier; | |
946 | ||
18442d08 VS |
947 | if (HAS_PCH_SPLIT(dev_priv->dev)) |
948 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
949 | ||
2d112de7 | 950 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
951 | } |
952 | ||
d1b1589c VS |
953 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder) |
954 | { | |
955 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
956 | ||
957 | WARN_ON(!crtc->config->has_hdmi_sink); | |
958 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", | |
959 | pipe_name(crtc->pipe)); | |
960 | intel_audio_codec_enable(encoder); | |
961 | } | |
962 | ||
bf868c7d | 963 | static void g4x_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 964 | { |
5ab432ef | 965 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 966 | struct drm_i915_private *dev_priv = dev->dev_private; |
bf868c7d | 967 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 968 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
969 | u32 temp; |
970 | ||
b242b7f7 | 971 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 972 | |
bf868c7d VS |
973 | temp |= SDVO_ENABLE; |
974 | if (crtc->config->has_audio) | |
975 | temp |= SDVO_AUDIO_ENABLE; | |
7a87c289 | 976 | |
bf868c7d VS |
977 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
978 | POSTING_READ(intel_hdmi->hdmi_reg); | |
979 | ||
980 | if (crtc->config->has_audio) | |
981 | intel_enable_hdmi_audio(encoder); | |
982 | } | |
983 | ||
984 | static void ibx_enable_hdmi(struct intel_encoder *encoder) | |
985 | { | |
986 | struct drm_device *dev = encoder->base.dev; | |
987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
988 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
989 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
990 | u32 temp; | |
991 | ||
992 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 993 | |
bf868c7d VS |
994 | temp |= SDVO_ENABLE; |
995 | if (crtc->config->has_audio) | |
996 | temp |= SDVO_AUDIO_ENABLE; | |
5ab432ef | 997 | |
bf868c7d VS |
998 | /* |
999 | * HW workaround, need to write this twice for issue | |
1000 | * that may result in first write getting masked. | |
1001 | */ | |
1002 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1003 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1004 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1005 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1006 | |
bf868c7d VS |
1007 | /* |
1008 | * HW workaround, need to toggle enable bit off and on | |
1009 | * for 12bpc with pixel repeat. | |
1010 | * | |
1011 | * FIXME: BSpec says this should be done at the end of | |
1012 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1013 | */ |
bf868c7d VS |
1014 | if (crtc->config->pipe_bpp > 24 && |
1015 | crtc->config->pixel_multiplier > 1) { | |
1016 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); | |
1017 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1018 | ||
1019 | /* | |
1020 | * HW workaround, need to write this twice for issue | |
1021 | * that may result in first write getting masked. | |
1022 | */ | |
1023 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1024 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1025 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1026 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1027 | } |
c1dec79a | 1028 | |
bf868c7d | 1029 | if (crtc->config->has_audio) |
d1b1589c VS |
1030 | intel_enable_hdmi_audio(encoder); |
1031 | } | |
1032 | ||
1033 | static void cpt_enable_hdmi(struct intel_encoder *encoder) | |
1034 | { | |
1035 | struct drm_device *dev = encoder->base.dev; | |
1036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1037 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1038 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1039 | enum pipe pipe = crtc->pipe; | |
1040 | u32 temp; | |
1041 | ||
1042 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1043 | ||
1044 | temp |= SDVO_ENABLE; | |
1045 | if (crtc->config->has_audio) | |
1046 | temp |= SDVO_AUDIO_ENABLE; | |
1047 | ||
1048 | /* | |
1049 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1050 | * | |
1051 | * The procedure for 12bpc is as follows: | |
1052 | * 1. disable HDMI clock gating | |
1053 | * 2. enable HDMI with 8bpc | |
1054 | * 3. enable HDMI with 12bpc | |
1055 | * 4. enable HDMI clock gating | |
1056 | */ | |
1057 | ||
1058 | if (crtc->config->pipe_bpp > 24) { | |
1059 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1060 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1061 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1062 | ||
1063 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1064 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1065 | } |
d1b1589c VS |
1066 | |
1067 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1068 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1069 | ||
1070 | if (crtc->config->pipe_bpp > 24) { | |
1071 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1072 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1073 | ||
1074 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1075 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1076 | ||
1077 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1078 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1079 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1080 | } | |
1081 | ||
1082 | if (crtc->config->has_audio) | |
1083 | intel_enable_hdmi_audio(encoder); | |
b76cf76b | 1084 | } |
89b667f8 | 1085 | |
b76cf76b JN |
1086 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
1087 | { | |
5ab432ef DV |
1088 | } |
1089 | ||
1090 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
1091 | { | |
1092 | struct drm_device *dev = encoder->base.dev; | |
1093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1094 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
495a5bb8 | 1095 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 1096 | u32 temp; |
5ab432ef | 1097 | |
b242b7f7 | 1098 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1099 | |
1612c8bd | 1100 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1101 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1102 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1103 | |
1104 | /* | |
1105 | * HW workaround for IBX, we need to move the port | |
1106 | * to transcoder A after disabling it to allow the | |
1107 | * matching DP port to be enabled on transcoder A. | |
1108 | */ | |
1109 | if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) { | |
0c241d5b VS |
1110 | /* |
1111 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1112 | * doing the workaround. Sweep them under the rug. | |
1113 | */ | |
1114 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1115 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1116 | ||
1612c8bd VS |
1117 | temp &= ~SDVO_PIPE_B_SELECT; |
1118 | temp |= SDVO_ENABLE; | |
1119 | /* | |
1120 | * HW workaround, need to write this twice for issue | |
1121 | * that may result in first write getting masked. | |
1122 | */ | |
1123 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1124 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1125 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1126 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1127 | ||
1128 | temp &= ~SDVO_ENABLE; | |
1129 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1130 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b VS |
1131 | |
1132 | intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A); | |
1133 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1134 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 1135 | } |
6d67415f | 1136 | |
0be6f0c8 | 1137 | intel_hdmi->set_infoframes(&encoder->base, false, NULL); |
7d57382e EA |
1138 | } |
1139 | ||
a4790cec VS |
1140 | static void g4x_disable_hdmi(struct intel_encoder *encoder) |
1141 | { | |
1142 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1143 | ||
1144 | if (crtc->config->has_audio) | |
1145 | intel_audio_codec_disable(encoder); | |
1146 | ||
1147 | intel_disable_hdmi(encoder); | |
1148 | } | |
1149 | ||
1150 | static void pch_disable_hdmi(struct intel_encoder *encoder) | |
1151 | { | |
1152 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1153 | ||
1154 | if (crtc->config->has_audio) | |
1155 | intel_audio_codec_disable(encoder); | |
1156 | } | |
1157 | ||
1158 | static void pch_post_disable_hdmi(struct intel_encoder *encoder) | |
1159 | { | |
1160 | intel_disable_hdmi(encoder); | |
1161 | } | |
1162 | ||
e64e739e | 1163 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
1164 | { |
1165 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1166 | ||
40478455 | 1167 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 1168 | return 165000; |
e3c33578 | 1169 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
1170 | return 300000; |
1171 | else | |
1172 | return 225000; | |
1173 | } | |
1174 | ||
e64e739e VS |
1175 | static enum drm_mode_status |
1176 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
1177 | int clock, bool respect_dvi_limit) | |
1178 | { | |
1179 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1180 | ||
1181 | if (clock < 25000) | |
1182 | return MODE_CLOCK_LOW; | |
1183 | if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit)) | |
1184 | return MODE_CLOCK_HIGH; | |
1185 | ||
5e6ccc0b VS |
1186 | /* BXT DPLL can't generate 223-240 MHz */ |
1187 | if (IS_BROXTON(dev) && clock > 223333 && clock < 240000) | |
1188 | return MODE_CLOCK_RANGE; | |
1189 | ||
1190 | /* CHV DPLL can't generate 216-240 MHz */ | |
1191 | if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000) | |
e64e739e VS |
1192 | return MODE_CLOCK_RANGE; |
1193 | ||
1194 | return MODE_OK; | |
1195 | } | |
1196 | ||
c19de8eb DL |
1197 | static enum drm_mode_status |
1198 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1199 | struct drm_display_mode *mode) | |
7d57382e | 1200 | { |
e64e739e VS |
1201 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1202 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
1203 | enum drm_mode_status status; | |
1204 | int clock; | |
587bf496 | 1205 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
e64e739e VS |
1206 | |
1207 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1208 | return MODE_NO_DBLESCAN; | |
697c4078 | 1209 | |
e64e739e | 1210 | clock = mode->clock; |
587bf496 MK |
1211 | |
1212 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
1213 | clock *= 2; | |
1214 | ||
1215 | if (clock > max_dotclk) | |
1216 | return MODE_CLOCK_HIGH; | |
1217 | ||
697c4078 CT |
1218 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1219 | clock *= 2; | |
1220 | ||
e64e739e VS |
1221 | /* check if we can do 8bpc */ |
1222 | status = hdmi_port_clock_valid(hdmi, clock, true); | |
7d57382e | 1223 | |
e64e739e VS |
1224 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
1225 | if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK) | |
1226 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true); | |
7d57382e | 1227 | |
e64e739e | 1228 | return status; |
7d57382e EA |
1229 | } |
1230 | ||
77f06c86 | 1231 | static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state) |
71800632 | 1232 | { |
77f06c86 ACO |
1233 | struct drm_device *dev = crtc_state->base.crtc->dev; |
1234 | struct drm_atomic_state *state; | |
71800632 | 1235 | struct intel_encoder *encoder; |
da3ced29 | 1236 | struct drm_connector *connector; |
77f06c86 | 1237 | struct drm_connector_state *connector_state; |
71800632 | 1238 | int count = 0, count_hdmi = 0; |
77f06c86 | 1239 | int i; |
71800632 | 1240 | |
f227ae9e | 1241 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
1242 | return false; |
1243 | ||
77f06c86 ACO |
1244 | state = crtc_state->base.state; |
1245 | ||
da3ced29 | 1246 | for_each_connector_in_state(state, connector, connector_state, i) { |
77f06c86 ACO |
1247 | if (connector_state->crtc != crtc_state->base.crtc) |
1248 | continue; | |
1249 | ||
1250 | encoder = to_intel_encoder(connector_state->best_encoder); | |
1251 | ||
71800632 VS |
1252 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; |
1253 | count++; | |
1254 | } | |
1255 | ||
1256 | /* | |
1257 | * HDMI 12bpc affects the clocks, so it's only possible | |
1258 | * when not cloning with other encoder types. | |
1259 | */ | |
1260 | return count_hdmi > 0 && count_hdmi == count; | |
1261 | } | |
1262 | ||
5bfe2ac0 | 1263 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
5cec258b | 1264 | struct intel_crtc_state *pipe_config) |
7d57382e | 1265 | { |
5bfe2ac0 DV |
1266 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1267 | struct drm_device *dev = encoder->base.dev; | |
2d112de7 | 1268 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
e64e739e VS |
1269 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1270 | int clock_12bpc = clock_8bpc * 3 / 2; | |
e29c22c0 | 1271 | int desired_bpp; |
3685a8f3 | 1272 | |
6897b4b5 DV |
1273 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
1274 | ||
e43823ec JB |
1275 | if (pipe_config->has_hdmi_sink) |
1276 | pipe_config->has_infoframe = true; | |
1277 | ||
55bc60db VS |
1278 | if (intel_hdmi->color_range_auto) { |
1279 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
0f2a2a75 VS |
1280 | pipe_config->limited_color_range = |
1281 | pipe_config->has_hdmi_sink && | |
1282 | drm_match_cea_mode(adjusted_mode) > 1; | |
1283 | } else { | |
1284 | pipe_config->limited_color_range = | |
1285 | intel_hdmi->limited_color_range; | |
55bc60db VS |
1286 | } |
1287 | ||
697c4078 CT |
1288 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1289 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1290 | clock_8bpc *= 2; |
3320e37f | 1291 | clock_12bpc *= 2; |
697c4078 CT |
1292 | } |
1293 | ||
5bfe2ac0 DV |
1294 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
1295 | pipe_config->has_pch_encoder = true; | |
1296 | ||
9ed109a7 DV |
1297 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
1298 | pipe_config->has_audio = true; | |
1299 | ||
4e53c2e0 DV |
1300 | /* |
1301 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1302 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1303 | * outputs. We also need to check that the higher clock still fits |
1304 | * within limits. | |
4e53c2e0 | 1305 | */ |
6897b4b5 | 1306 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
e64e739e | 1307 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK && |
7a0baa62 | 1308 | hdmi_12bpc_possible(pipe_config)) { |
e29c22c0 DV |
1309 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1310 | desired_bpp = 12*3; | |
325b9d04 DV |
1311 | |
1312 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1313 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1314 | } else { |
e29c22c0 DV |
1315 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1316 | desired_bpp = 8*3; | |
e64e739e VS |
1317 | |
1318 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1319 | } |
1320 | ||
1321 | if (!pipe_config->bw_constrained) { | |
1322 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
1323 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
1324 | } |
1325 | ||
e64e739e VS |
1326 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
1327 | false) != MODE_OK) { | |
1328 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); | |
325b9d04 DV |
1329 | return false; |
1330 | } | |
1331 | ||
28b468a0 VS |
1332 | /* Set user selected PAR to incoming mode's member */ |
1333 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
1334 | ||
7d57382e EA |
1335 | return true; |
1336 | } | |
1337 | ||
953ece69 CW |
1338 | static void |
1339 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1340 | { |
df0e9248 | 1341 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1342 | |
953ece69 CW |
1343 | intel_hdmi->has_hdmi_sink = false; |
1344 | intel_hdmi->has_audio = false; | |
1345 | intel_hdmi->rgb_quant_range_selectable = false; | |
1346 | ||
1347 | kfree(to_intel_connector(connector)->detect_edid); | |
1348 | to_intel_connector(connector)->detect_edid = NULL; | |
1349 | } | |
1350 | ||
1351 | static bool | |
237ed86c | 1352 | intel_hdmi_set_edid(struct drm_connector *connector, bool force) |
953ece69 CW |
1353 | { |
1354 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1355 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
237ed86c | 1356 | struct edid *edid = NULL; |
953ece69 | 1357 | bool connected = false; |
164c8598 | 1358 | |
69172f21 ID |
1359 | if (force) { |
1360 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); | |
671dedd2 | 1361 | |
237ed86c SJ |
1362 | edid = drm_get_edid(connector, |
1363 | intel_gmbus_get_adapter(dev_priv, | |
1364 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 1365 | |
69172f21 ID |
1366 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1367 | } | |
30ad48b7 | 1368 | |
953ece69 CW |
1369 | to_intel_connector(connector)->detect_edid = edid; |
1370 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1371 | intel_hdmi->rgb_quant_range_selectable = | |
1372 | drm_rgb_quant_range_selectable(edid); | |
1373 | ||
1374 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
b1d7e4b4 WF |
1375 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1376 | intel_hdmi->has_audio = | |
953ece69 CW |
1377 | intel_hdmi->force_audio == HDMI_AUDIO_ON; |
1378 | ||
1379 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) | |
1380 | intel_hdmi->has_hdmi_sink = | |
1381 | drm_detect_hdmi_monitor(edid); | |
1382 | ||
1383 | connected = true; | |
55b7d6e8 CW |
1384 | } |
1385 | ||
953ece69 CW |
1386 | return connected; |
1387 | } | |
1388 | ||
8166fcea DV |
1389 | static enum drm_connector_status |
1390 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 1391 | { |
8166fcea DV |
1392 | enum drm_connector_status status; |
1393 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
1394 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
237ed86c | 1395 | bool live_status = false; |
61fb3980 | 1396 | unsigned int try; |
953ece69 | 1397 | |
8166fcea DV |
1398 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1399 | connector->base.id, connector->name); | |
1400 | ||
29bb94bb ID |
1401 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1402 | ||
f8d03ea0 | 1403 | for (try = 0; !live_status && try < 9; try++) { |
61fb3980 GW |
1404 | if (try) |
1405 | msleep(10); | |
237ed86c SJ |
1406 | live_status = intel_digital_port_connected(dev_priv, |
1407 | hdmi_to_dig_port(intel_hdmi)); | |
237ed86c SJ |
1408 | } |
1409 | ||
1410 | if (!live_status) | |
1411 | DRM_DEBUG_KMS("Live status not up!"); | |
1412 | ||
8166fcea | 1413 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 1414 | |
8166fcea | 1415 | if (intel_hdmi_set_edid(connector, live_status)) { |
953ece69 CW |
1416 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
1417 | ||
1418 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | |
1419 | status = connector_status_connected; | |
8166fcea | 1420 | } else |
953ece69 | 1421 | status = connector_status_disconnected; |
671dedd2 | 1422 | |
29bb94bb ID |
1423 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1424 | ||
2ded9e27 | 1425 | return status; |
7d57382e EA |
1426 | } |
1427 | ||
953ece69 CW |
1428 | static void |
1429 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1430 | { |
953ece69 | 1431 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
7d57382e | 1432 | |
953ece69 CW |
1433 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1434 | connector->base.id, connector->name); | |
7d57382e | 1435 | |
953ece69 | 1436 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1437 | |
953ece69 CW |
1438 | if (connector->status != connector_status_connected) |
1439 | return; | |
671dedd2 | 1440 | |
237ed86c | 1441 | intel_hdmi_set_edid(connector, true); |
953ece69 CW |
1442 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; |
1443 | } | |
671dedd2 | 1444 | |
953ece69 CW |
1445 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1446 | { | |
1447 | struct edid *edid; | |
1448 | ||
1449 | edid = to_intel_connector(connector)->detect_edid; | |
1450 | if (edid == NULL) | |
1451 | return 0; | |
671dedd2 | 1452 | |
953ece69 | 1453 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1454 | } |
1455 | ||
1aad7ac0 CW |
1456 | static bool |
1457 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1458 | { | |
1aad7ac0 | 1459 | bool has_audio = false; |
953ece69 | 1460 | struct edid *edid; |
1aad7ac0 | 1461 | |
953ece69 CW |
1462 | edid = to_intel_connector(connector)->detect_edid; |
1463 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1464 | has_audio = drm_detect_monitor_audio(edid); | |
671dedd2 | 1465 | |
1aad7ac0 CW |
1466 | return has_audio; |
1467 | } | |
1468 | ||
55b7d6e8 CW |
1469 | static int |
1470 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1471 | struct drm_property *property, |
1472 | uint64_t val) | |
55b7d6e8 CW |
1473 | { |
1474 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1475 | struct intel_digital_port *intel_dig_port = |
1476 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1477 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1478 | int ret; |
1479 | ||
662595df | 1480 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1481 | if (ret) |
1482 | return ret; | |
1483 | ||
3f43c48d | 1484 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1485 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1486 | bool has_audio; |
1487 | ||
1488 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1489 | return 0; |
1490 | ||
1aad7ac0 | 1491 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1492 | |
b1d7e4b4 | 1493 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1494 | has_audio = intel_hdmi_detect_audio(connector); |
1495 | else | |
b1d7e4b4 | 1496 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1497 | |
b1d7e4b4 WF |
1498 | if (i == HDMI_AUDIO_OFF_DVI) |
1499 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1500 | |
1aad7ac0 | 1501 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1502 | goto done; |
1503 | } | |
1504 | ||
e953fd7b | 1505 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 | 1506 | bool old_auto = intel_hdmi->color_range_auto; |
0f2a2a75 | 1507 | bool old_range = intel_hdmi->limited_color_range; |
ae4edb80 | 1508 | |
55bc60db VS |
1509 | switch (val) { |
1510 | case INTEL_BROADCAST_RGB_AUTO: | |
1511 | intel_hdmi->color_range_auto = true; | |
1512 | break; | |
1513 | case INTEL_BROADCAST_RGB_FULL: | |
1514 | intel_hdmi->color_range_auto = false; | |
0f2a2a75 | 1515 | intel_hdmi->limited_color_range = false; |
55bc60db VS |
1516 | break; |
1517 | case INTEL_BROADCAST_RGB_LIMITED: | |
1518 | intel_hdmi->color_range_auto = false; | |
0f2a2a75 | 1519 | intel_hdmi->limited_color_range = true; |
55bc60db VS |
1520 | break; |
1521 | default: | |
1522 | return -EINVAL; | |
1523 | } | |
ae4edb80 DV |
1524 | |
1525 | if (old_auto == intel_hdmi->color_range_auto && | |
0f2a2a75 | 1526 | old_range == intel_hdmi->limited_color_range) |
ae4edb80 DV |
1527 | return 0; |
1528 | ||
e953fd7b CW |
1529 | goto done; |
1530 | } | |
1531 | ||
94a11ddc VK |
1532 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1533 | switch (val) { | |
1534 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1535 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1536 | break; | |
1537 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1538 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1539 | break; | |
1540 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1541 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1542 | break; | |
1543 | default: | |
1544 | return -EINVAL; | |
1545 | } | |
1546 | goto done; | |
1547 | } | |
1548 | ||
55b7d6e8 CW |
1549 | return -EINVAL; |
1550 | ||
1551 | done: | |
c0c36b94 CW |
1552 | if (intel_dig_port->base.base.crtc) |
1553 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1554 | |
1555 | return 0; | |
1556 | } | |
1557 | ||
13732ba7 JB |
1558 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1559 | { | |
1560 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1561 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
7c5f93b0 | 1562 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
13732ba7 | 1563 | |
4cde8a21 DV |
1564 | intel_hdmi_prepare(encoder); |
1565 | ||
6897b4b5 | 1566 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1567 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1568 | adjusted_mode); |
13732ba7 JB |
1569 | } |
1570 | ||
9514ac6e | 1571 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1572 | { |
1573 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1574 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1575 | struct drm_device *dev = encoder->base.dev; |
1576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1577 | struct intel_crtc *intel_crtc = | |
1578 | to_intel_crtc(encoder->base.crtc); | |
7c5f93b0 | 1579 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
e4607fcf | 1580 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1581 | int pipe = intel_crtc->pipe; |
1582 | u32 val; | |
1583 | ||
89b667f8 | 1584 | /* Enable clock channels for this port */ |
a580516d | 1585 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1586 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1587 | val = 0; |
1588 | if (pipe) | |
1589 | val |= (1<<21); | |
1590 | else | |
1591 | val &= ~(1<<21); | |
1592 | val |= 0x001000c4; | |
ab3c759a | 1593 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1594 | |
1595 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1596 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1597 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1598 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1599 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1600 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1601 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1602 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1603 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1604 | |
1605 | /* Program lane clock */ | |
ab3c759a CML |
1606 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1607 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
a580516d | 1608 | mutex_unlock(&dev_priv->sb_lock); |
b76cf76b | 1609 | |
6897b4b5 | 1610 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1611 | intel_crtc->config->has_hdmi_sink, |
6897b4b5 | 1612 | adjusted_mode); |
13732ba7 | 1613 | |
bf868c7d | 1614 | g4x_enable_hdmi(encoder); |
b76cf76b | 1615 | |
9b6de0a1 | 1616 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1617 | } |
1618 | ||
9514ac6e | 1619 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1620 | { |
1621 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1622 | struct drm_device *dev = encoder->base.dev; | |
1623 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1624 | struct intel_crtc *intel_crtc = |
1625 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1626 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1627 | int pipe = intel_crtc->pipe; |
89b667f8 | 1628 | |
4cde8a21 DV |
1629 | intel_hdmi_prepare(encoder); |
1630 | ||
89b667f8 | 1631 | /* Program Tx lane resets to default */ |
a580516d | 1632 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 1633 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1634 | DPIO_PCS_TX_LANE2_RESET | |
1635 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1636 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1637 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1638 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1639 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1640 | DPIO_PCS_CLK_SOFT_RESET); | |
1641 | ||
1642 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1643 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1644 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1645 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1646 | ||
1647 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1648 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
a580516d | 1649 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1650 | } |
1651 | ||
a8f327fb VS |
1652 | static void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
1653 | bool reset) | |
1654 | { | |
1655 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1656 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); | |
1657 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); | |
1658 | enum pipe pipe = crtc->pipe; | |
1659 | uint32_t val; | |
1660 | ||
1661 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1662 | if (reset) | |
1663 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1664 | else | |
1665 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
1666 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1667 | ||
1668 | if (crtc->config->lane_count > 2) { | |
1669 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
1670 | if (reset) | |
1671 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1672 | else | |
1673 | val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; | |
1674 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); | |
1675 | } | |
1676 | ||
1677 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); | |
1678 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1679 | if (reset) | |
1680 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
1681 | else | |
1682 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
1683 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); | |
1684 | ||
1685 | if (crtc->config->lane_count > 2) { | |
1686 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1687 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1688 | if (reset) | |
1689 | val &= ~DPIO_PCS_CLK_SOFT_RESET; | |
1690 | else | |
1691 | val |= DPIO_PCS_CLK_SOFT_RESET; | |
1692 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1693 | } | |
1694 | } | |
1695 | ||
9197c88b VS |
1696 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1697 | { | |
1698 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1699 | struct drm_device *dev = encoder->base.dev; | |
1700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1701 | struct intel_crtc *intel_crtc = | |
1702 | to_intel_crtc(encoder->base.crtc); | |
1703 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1704 | enum pipe pipe = intel_crtc->pipe; | |
1705 | u32 val; | |
1706 | ||
625695f8 VS |
1707 | intel_hdmi_prepare(encoder); |
1708 | ||
b0b33846 VS |
1709 | /* |
1710 | * Must trick the second common lane into life. | |
1711 | * Otherwise we can't even access the PLL. | |
1712 | */ | |
1713 | if (ch == DPIO_CH0 && pipe == PIPE_B) | |
1714 | dport->release_cl2_override = | |
1715 | !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); | |
1716 | ||
e0fce78f VS |
1717 | chv_phy_powergate_lanes(encoder, true, 0x0); |
1718 | ||
a580516d | 1719 | mutex_lock(&dev_priv->sb_lock); |
9197c88b | 1720 | |
a8f327fb VS |
1721 | /* Assert data lane reset */ |
1722 | chv_data_lane_soft_reset(encoder, true); | |
1723 | ||
b9e5ac3c VS |
1724 | /* program left/right clock distribution */ |
1725 | if (pipe != PIPE_B) { | |
1726 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1727 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1728 | if (ch == DPIO_CH0) | |
1729 | val |= CHV_BUFLEFTENA1_FORCE; | |
1730 | if (ch == DPIO_CH1) | |
1731 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1732 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1733 | } else { | |
1734 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1735 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1736 | if (ch == DPIO_CH0) | |
1737 | val |= CHV_BUFLEFTENA2_FORCE; | |
1738 | if (ch == DPIO_CH1) | |
1739 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1740 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1741 | } | |
1742 | ||
9197c88b VS |
1743 | /* program clock channel usage */ |
1744 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1745 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1746 | if (pipe != PIPE_B) | |
1747 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1748 | else | |
1749 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1750 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1751 | ||
1752 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1753 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1754 | if (pipe != PIPE_B) | |
1755 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1756 | else | |
1757 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1758 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1759 | ||
1760 | /* | |
1761 | * This a a bit weird since generally CL | |
1762 | * matches the pipe, but here we need to | |
1763 | * pick the CL based on the port. | |
1764 | */ | |
1765 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1766 | if (pipe != PIPE_B) | |
1767 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1768 | else | |
1769 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1770 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1771 | ||
a580516d | 1772 | mutex_unlock(&dev_priv->sb_lock); |
9197c88b VS |
1773 | } |
1774 | ||
d6db995f VS |
1775 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder) |
1776 | { | |
1777 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1778 | enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
1779 | u32 val; | |
1780 | ||
1781 | mutex_lock(&dev_priv->sb_lock); | |
1782 | ||
1783 | /* disable left/right clock distribution */ | |
1784 | if (pipe != PIPE_B) { | |
1785 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1786 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1787 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1788 | } else { | |
1789 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1790 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1791 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1792 | } | |
1793 | ||
1794 | mutex_unlock(&dev_priv->sb_lock); | |
e0fce78f | 1795 | |
b0b33846 VS |
1796 | /* |
1797 | * Leave the power down bit cleared for at least one | |
1798 | * lane so that chv_powergate_phy_ch() will power | |
1799 | * on something when the channel is otherwise unused. | |
1800 | * When the port is off and the override is removed | |
1801 | * the lanes power down anyway, so otherwise it doesn't | |
1802 | * really matter what the state of power down bits is | |
1803 | * after this. | |
1804 | */ | |
e0fce78f | 1805 | chv_phy_powergate_lanes(encoder, false, 0x0); |
d6db995f VS |
1806 | } |
1807 | ||
9514ac6e | 1808 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1809 | { |
1810 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1811 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1812 | struct intel_crtc *intel_crtc = |
1813 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1814 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1815 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1816 | |
1817 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
a580516d | 1818 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a CML |
1819 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1820 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
a580516d | 1821 | mutex_unlock(&dev_priv->sb_lock); |
89b667f8 JB |
1822 | } |
1823 | ||
580d3811 VS |
1824 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1825 | { | |
580d3811 VS |
1826 | struct drm_device *dev = encoder->base.dev; |
1827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
580d3811 | 1828 | |
a580516d | 1829 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 1830 | |
a8f327fb VS |
1831 | /* Assert data lane reset */ |
1832 | chv_data_lane_soft_reset(encoder, true); | |
580d3811 | 1833 | |
a580516d | 1834 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
1835 | } |
1836 | ||
e4a1d846 CML |
1837 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1838 | { | |
1839 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
b4eb1564 | 1840 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
e4a1d846 CML |
1841 | struct drm_device *dev = encoder->base.dev; |
1842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1843 | struct intel_crtc *intel_crtc = | |
1844 | to_intel_crtc(encoder->base.crtc); | |
7c5f93b0 | 1845 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
e4a1d846 CML |
1846 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
1847 | int pipe = intel_crtc->pipe; | |
2e523e98 | 1848 | int data, i, stagger; |
e4a1d846 CML |
1849 | u32 val; |
1850 | ||
a580516d | 1851 | mutex_lock(&dev_priv->sb_lock); |
949c1d43 | 1852 | |
570e2a74 VS |
1853 | /* allow hardware to manage TX FIFO reset source */ |
1854 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1855 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1856 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1857 | ||
1858 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1859 | val &= ~DPIO_LANEDESKEW_STRAP_OVRD; | |
1860 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1861 | ||
949c1d43 | 1862 | /* Program Tx latency optimal setting */ |
e4a1d846 | 1863 | for (i = 0; i < 4; i++) { |
e4a1d846 CML |
1864 | /* Set the upar bit */ |
1865 | data = (i == 1) ? 0x0 : 0x1; | |
1866 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1867 | data << DPIO_UPAR_SHIFT); | |
1868 | } | |
1869 | ||
1870 | /* Data lane stagger programming */ | |
2e523e98 VS |
1871 | if (intel_crtc->config->port_clock > 270000) |
1872 | stagger = 0x18; | |
1873 | else if (intel_crtc->config->port_clock > 135000) | |
1874 | stagger = 0xd; | |
1875 | else if (intel_crtc->config->port_clock > 67500) | |
1876 | stagger = 0x7; | |
1877 | else if (intel_crtc->config->port_clock > 33750) | |
1878 | stagger = 0x4; | |
1879 | else | |
1880 | stagger = 0x2; | |
1881 | ||
1882 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); | |
1883 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1884 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); | |
1885 | ||
1886 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); | |
1887 | val |= DPIO_TX2_STAGGER_MASK(0x1f); | |
1888 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); | |
1889 | ||
1890 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), | |
1891 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1892 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1893 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1894 | DPIO_TX1_STAGGER_MULT(6) | | |
1895 | DPIO_TX2_STAGGER_MULT(0)); | |
1896 | ||
1897 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), | |
1898 | DPIO_LANESTAGGER_STRAP(stagger) | | |
1899 | DPIO_LANESTAGGER_STRAP_OVRD | | |
1900 | DPIO_TX1_STAGGER_MASK(0x1f) | | |
1901 | DPIO_TX1_STAGGER_MULT(7) | | |
1902 | DPIO_TX2_STAGGER_MULT(5)); | |
e4a1d846 | 1903 | |
a8f327fb VS |
1904 | /* Deassert data lane reset */ |
1905 | chv_data_lane_soft_reset(encoder, false); | |
1906 | ||
e4a1d846 | 1907 | /* Clear calc init */ |
1966e59e VS |
1908 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1909 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1910 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1911 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e VS |
1912 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); |
1913 | ||
1914 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1915 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
a02ef3c7 VS |
1916 | val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); |
1917 | val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; | |
1966e59e | 1918 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); |
e4a1d846 | 1919 | |
a02ef3c7 VS |
1920 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); |
1921 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1922 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1923 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); | |
1924 | ||
1925 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); | |
1926 | val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); | |
1927 | val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; | |
1928 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); | |
1929 | ||
e4a1d846 CML |
1930 | /* FIXME: Program the support xxx V-dB */ |
1931 | /* Use 800mV-0dB */ | |
f72df8db VS |
1932 | for (i = 0; i < 4; i++) { |
1933 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1934 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1935 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1936 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1937 | } | |
e4a1d846 | 1938 | |
f72df8db VS |
1939 | for (i = 0; i < 4; i++) { |
1940 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
67fa24b4 | 1941 | |
1fb44505 VS |
1942 | val &= ~DPIO_SWING_MARGIN000_MASK; |
1943 | val |= 102 << DPIO_SWING_MARGIN000_SHIFT; | |
67fa24b4 VS |
1944 | |
1945 | /* | |
1946 | * Supposedly this value shouldn't matter when unique transition | |
1947 | * scale is disabled, but in fact it does matter. Let's just | |
1948 | * always program the same value and hope it's OK. | |
1949 | */ | |
1950 | val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); | |
1951 | val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; | |
1952 | ||
f72df8db VS |
1953 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); |
1954 | } | |
e4a1d846 | 1955 | |
67fa24b4 VS |
1956 | /* |
1957 | * The document said it needs to set bit 27 for ch0 and bit 26 | |
1958 | * for ch1. Might be a typo in the doc. | |
1959 | * For now, for this unique transition scale selection, set bit | |
1960 | * 27 for ch0 and ch1. | |
1961 | */ | |
f72df8db VS |
1962 | for (i = 0; i < 4; i++) { |
1963 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1964 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1965 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1966 | } | |
e4a1d846 | 1967 | |
e4a1d846 | 1968 | /* Start swing calculation */ |
1966e59e VS |
1969 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1970 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1971 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1972 | ||
1973 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1974 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1975 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 | 1976 | |
a580516d | 1977 | mutex_unlock(&dev_priv->sb_lock); |
e4a1d846 | 1978 | |
b4eb1564 | 1979 | intel_hdmi->set_infoframes(&encoder->base, |
6e3c9717 | 1980 | intel_crtc->config->has_hdmi_sink, |
b4eb1564 CT |
1981 | adjusted_mode); |
1982 | ||
bf868c7d | 1983 | g4x_enable_hdmi(encoder); |
e4a1d846 | 1984 | |
9b6de0a1 | 1985 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
1986 | |
1987 | /* Second common lane will stay alive on its own now */ | |
1988 | if (dport->release_cl2_override) { | |
1989 | chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); | |
1990 | dport->release_cl2_override = false; | |
1991 | } | |
e4a1d846 CML |
1992 | } |
1993 | ||
7d57382e EA |
1994 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1995 | { | |
10e972d3 | 1996 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 1997 | drm_connector_cleanup(connector); |
674e2d08 | 1998 | kfree(connector); |
7d57382e EA |
1999 | } |
2000 | ||
7d57382e | 2001 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
4d688a2a | 2002 | .dpms = drm_atomic_helper_connector_dpms, |
7d57382e | 2003 | .detect = intel_hdmi_detect, |
953ece69 | 2004 | .force = intel_hdmi_force, |
7d57382e | 2005 | .fill_modes = drm_helper_probe_single_connector_modes, |
55b7d6e8 | 2006 | .set_property = intel_hdmi_set_property, |
2545e4a6 | 2007 | .atomic_get_property = intel_connector_atomic_get_property, |
7d57382e | 2008 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 2009 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 2010 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
7d57382e EA |
2011 | }; |
2012 | ||
2013 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
2014 | .get_modes = intel_hdmi_get_modes, | |
2015 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 2016 | .best_encoder = intel_best_encoder, |
7d57382e EA |
2017 | }; |
2018 | ||
7d57382e | 2019 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 2020 | .destroy = intel_encoder_destroy, |
7d57382e EA |
2021 | }; |
2022 | ||
55b7d6e8 CW |
2023 | static void |
2024 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
2025 | { | |
3f43c48d | 2026 | intel_attach_force_audio_property(connector); |
e953fd7b | 2027 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 2028 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
2029 | intel_attach_aspect_ratio_property(connector); |
2030 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
2031 | } |
2032 | ||
00c09d70 PZ |
2033 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2034 | struct intel_connector *intel_connector) | |
7d57382e | 2035 | { |
b9cb234c PZ |
2036 | struct drm_connector *connector = &intel_connector->base; |
2037 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
2038 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2039 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 2040 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 2041 | enum port port = intel_dig_port->port; |
11c1b657 | 2042 | uint8_t alternate_ddc_pin; |
373a3cf7 | 2043 | |
ccb1a831 VS |
2044 | if (WARN(intel_dig_port->max_lanes < 4, |
2045 | "Not enough lanes (%d) for HDMI on port %c\n", | |
2046 | intel_dig_port->max_lanes, port_name(port))) | |
2047 | return; | |
2048 | ||
7d57382e | 2049 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 2050 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
2051 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2052 | ||
c3febcc4 | 2053 | connector->interlace_allowed = 1; |
7d57382e | 2054 | connector->doublescan_allowed = 0; |
573e74ad | 2055 | connector->stereo_allowed = 1; |
66a9278e | 2056 | |
08d644ad DV |
2057 | switch (port) { |
2058 | case PORT_B: | |
4c272834 JN |
2059 | if (IS_BROXTON(dev_priv)) |
2060 | intel_hdmi->ddc_bus = GMBUS_PIN_1_BXT; | |
2061 | else | |
2062 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; | |
cf1d5883 SJ |
2063 | /* |
2064 | * On BXT A0/A1, sw needs to activate DDIA HPD logic and | |
2065 | * interrupts to check the external panel connection. | |
2066 | */ | |
e87a005d | 2067 | if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) |
cf1d5883 SJ |
2068 | intel_encoder->hpd_pin = HPD_PORT_A; |
2069 | else | |
2070 | intel_encoder->hpd_pin = HPD_PORT_B; | |
08d644ad DV |
2071 | break; |
2072 | case PORT_C: | |
4c272834 JN |
2073 | if (IS_BROXTON(dev_priv)) |
2074 | intel_hdmi->ddc_bus = GMBUS_PIN_2_BXT; | |
2075 | else | |
2076 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; | |
1d843f9d | 2077 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
2078 | break; |
2079 | case PORT_D: | |
4c272834 JN |
2080 | if (WARN_ON(IS_BROXTON(dev_priv))) |
2081 | intel_hdmi->ddc_bus = GMBUS_PIN_DISABLED; | |
2082 | else if (IS_CHERRYVIEW(dev_priv)) | |
988c7015 | 2083 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD_CHV; |
c0c35329 | 2084 | else |
988c7015 | 2085 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; |
1d843f9d | 2086 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad | 2087 | break; |
11c1b657 XZ |
2088 | case PORT_E: |
2089 | /* On SKL PORT E doesn't have seperate GMBUS pin | |
2090 | * We rely on VBT to set a proper alternate GMBUS pin. */ | |
2091 | alternate_ddc_pin = | |
2092 | dev_priv->vbt.ddi_port_info[PORT_E].alternate_ddc_pin; | |
2093 | switch (alternate_ddc_pin) { | |
2094 | case DDC_PIN_B: | |
2095 | intel_hdmi->ddc_bus = GMBUS_PIN_DPB; | |
2096 | break; | |
2097 | case DDC_PIN_C: | |
2098 | intel_hdmi->ddc_bus = GMBUS_PIN_DPC; | |
2099 | break; | |
2100 | case DDC_PIN_D: | |
2101 | intel_hdmi->ddc_bus = GMBUS_PIN_DPD; | |
2102 | break; | |
2103 | default: | |
2104 | MISSING_CASE(alternate_ddc_pin); | |
2105 | } | |
2106 | intel_encoder->hpd_pin = HPD_PORT_E; | |
2107 | break; | |
08d644ad | 2108 | case PORT_A: |
1d843f9d | 2109 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
2110 | /* Internal port only for eDP. */ |
2111 | default: | |
6e4c1677 | 2112 | BUG(); |
f8aed700 | 2113 | } |
7d57382e | 2114 | |
666a4537 | 2115 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
90b107c8 | 2116 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 2117 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
e43823ec | 2118 | intel_hdmi->infoframe_enabled = vlv_infoframe_enabled; |
b98856a8 | 2119 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
2120 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
2121 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
e43823ec | 2122 | intel_hdmi->infoframe_enabled = g4x_infoframe_enabled; |
22b8bf17 | 2123 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 2124 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 2125 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
e43823ec | 2126 | intel_hdmi->infoframe_enabled = hsw_infoframe_enabled; |
fdf1250a PZ |
2127 | } else if (HAS_PCH_IBX(dev)) { |
2128 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 2129 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
e43823ec | 2130 | intel_hdmi->infoframe_enabled = ibx_infoframe_enabled; |
fdf1250a PZ |
2131 | } else { |
2132 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 2133 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
e43823ec | 2134 | intel_hdmi->infoframe_enabled = cpt_infoframe_enabled; |
64a8fc01 | 2135 | } |
45187ace | 2136 | |
affa9354 | 2137 | if (HAS_DDI(dev)) |
bcbc889b PZ |
2138 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2139 | else | |
2140 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 2141 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
2142 | |
2143 | intel_hdmi_add_properties(intel_hdmi, connector); | |
2144 | ||
2145 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 2146 | drm_connector_register(connector); |
d8b4c43a | 2147 | intel_hdmi->attached_connector = intel_connector; |
b9cb234c PZ |
2148 | |
2149 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
2150 | * 0xd. Failure to do so will result in spurious interrupts being | |
2151 | * generated on the port when a cable is not attached. | |
2152 | */ | |
2153 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
2154 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
2155 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2156 | } | |
2157 | } | |
2158 | ||
f0f59a00 VS |
2159 | void intel_hdmi_init(struct drm_device *dev, |
2160 | i915_reg_t hdmi_reg, enum port port) | |
b9cb234c | 2161 | { |
0bdf5a05 | 2162 | struct drm_i915_private *dev_priv = dev->dev_private; |
b9cb234c PZ |
2163 | struct intel_digital_port *intel_dig_port; |
2164 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
2165 | struct intel_connector *intel_connector; |
2166 | ||
b14c5679 | 2167 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
2168 | if (!intel_dig_port) |
2169 | return; | |
2170 | ||
08d9bc92 | 2171 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
2172 | if (!intel_connector) { |
2173 | kfree(intel_dig_port); | |
2174 | return; | |
2175 | } | |
2176 | ||
2177 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
2178 | |
2179 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
13a3d91f | 2180 | DRM_MODE_ENCODER_TMDS, NULL); |
00c09d70 | 2181 | |
5bfe2ac0 | 2182 | intel_encoder->compute_config = intel_hdmi_compute_config; |
a4790cec VS |
2183 | if (HAS_PCH_SPLIT(dev)) { |
2184 | intel_encoder->disable = pch_disable_hdmi; | |
2185 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
2186 | } else { | |
2187 | intel_encoder->disable = g4x_disable_hdmi; | |
2188 | } | |
00c09d70 | 2189 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 2190 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 2191 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 2192 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
2193 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2194 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 2195 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 2196 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
e4a1d846 | 2197 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
2198 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2199 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 2200 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 2201 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 2202 | } else { |
13732ba7 | 2203 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
d1b1589c VS |
2204 | if (HAS_PCH_CPT(dev)) |
2205 | intel_encoder->enable = cpt_enable_hdmi; | |
bf868c7d VS |
2206 | else if (HAS_PCH_IBX(dev)) |
2207 | intel_encoder->enable = ibx_enable_hdmi; | |
d1b1589c | 2208 | else |
bf868c7d | 2209 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 2210 | } |
5ab432ef | 2211 | |
b9cb234c | 2212 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
2213 | if (IS_CHERRYVIEW(dev)) { |
2214 | if (port == PORT_D) | |
2215 | intel_encoder->crtc_mask = 1 << 2; | |
2216 | else | |
2217 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
2218 | } else { | |
2219 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
2220 | } | |
301ea74a | 2221 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
2222 | /* |
2223 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
2224 | * to work on real hardware. And since g4x can send infoframes to | |
2225 | * only one port anyway, nothing is lost by allowing it. | |
2226 | */ | |
2227 | if (IS_G4X(dev)) | |
2228 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 2229 | |
174edf1f | 2230 | intel_dig_port->port = port; |
0bdf5a05 | 2231 | dev_priv->dig_port_map[port] = intel_encoder; |
b242b7f7 | 2232 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 2233 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 2234 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 2235 | |
b9cb234c | 2236 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2237 | } |