Commit | Line | Data |
---|---|---|
7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
45187ace | 70 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 71 | { |
45187ace | 72 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
73 | uint8_t sum = 0; |
74 | unsigned i; | |
75 | ||
45187ace JB |
76 | frame->checksum = 0; |
77 | frame->ecc = 0; | |
3c17fe4b | 78 | |
64a8fc01 | 79 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
80 | sum += data[i]; |
81 | ||
45187ace | 82 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
83 | } |
84 | ||
178f736a | 85 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 86 | { |
178f736a DL |
87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 89 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 91 | return VIDEO_DIP_SELECT_SPD; |
45187ace | 92 | default: |
178f736a | 93 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 94 | return 0; |
45187ace | 95 | } |
45187ace JB |
96 | } |
97 | ||
178f736a | 98 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 99 | { |
178f736a DL |
100 | switch (type) { |
101 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 102 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 103 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 104 | return VIDEO_DIP_ENABLE_SPD; |
fa193ff7 | 105 | default: |
178f736a | 106 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 107 | return 0; |
fa193ff7 | 108 | } |
fa193ff7 PZ |
109 | } |
110 | ||
178f736a | 111 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 112 | { |
178f736a DL |
113 | switch (type) { |
114 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 115 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 116 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 PZ |
117 | return VIDEO_DIP_ENABLE_SPD_HSW; |
118 | default: | |
178f736a | 119 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
120 | return 0; |
121 | } | |
122 | } | |
123 | ||
178f736a | 124 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
7d9bcebe | 125 | enum transcoder cpu_transcoder) |
2da8af54 | 126 | { |
178f736a DL |
127 | switch (type) { |
128 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 129 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 130 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 131 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
2da8af54 | 132 | default: |
178f736a | 133 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
134 | return 0; |
135 | } | |
136 | } | |
137 | ||
a3da1df7 | 138 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a DL |
139 | enum hdmi_infoframe_type type, |
140 | const uint8_t *frame, ssize_t len) | |
45187ace JB |
141 | { |
142 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
143 | struct drm_device *dev = encoder->dev; |
144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 145 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 146 | int i; |
3c17fe4b | 147 | |
822974ae PZ |
148 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
149 | ||
1d4f85ac | 150 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 151 | val |= g4x_infoframe_index(type); |
22509ec8 | 152 | |
178f736a | 153 | val &= ~g4x_infoframe_enable(type); |
45187ace | 154 | |
22509ec8 | 155 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 156 | |
9d9740f0 | 157 | mmiowb(); |
45187ace | 158 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
159 | I915_WRITE(VIDEO_DIP_DATA, *data); |
160 | data++; | |
161 | } | |
adf00b26 PZ |
162 | /* Write every possible data byte to force correct ECC calculation. */ |
163 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
164 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 165 | mmiowb(); |
3c17fe4b | 166 | |
178f736a | 167 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 168 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 169 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 170 | |
22509ec8 | 171 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 172 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
173 | } |
174 | ||
fdf1250a | 175 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a DL |
176 | enum hdmi_infoframe_type type, |
177 | const uint8_t *frame, ssize_t len) | |
fdf1250a PZ |
178 | { |
179 | uint32_t *data = (uint32_t *)frame; | |
180 | struct drm_device *dev = encoder->dev; | |
181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 182 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 183 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
184 | u32 val = I915_READ(reg); |
185 | ||
822974ae PZ |
186 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
187 | ||
fdf1250a | 188 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 189 | val |= g4x_infoframe_index(type); |
fdf1250a | 190 | |
178f736a | 191 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
192 | |
193 | I915_WRITE(reg, val); | |
194 | ||
9d9740f0 | 195 | mmiowb(); |
fdf1250a PZ |
196 | for (i = 0; i < len; i += 4) { |
197 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
198 | data++; | |
199 | } | |
adf00b26 PZ |
200 | /* Write every possible data byte to force correct ECC calculation. */ |
201 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
202 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 203 | mmiowb(); |
fdf1250a | 204 | |
178f736a | 205 | val |= g4x_infoframe_enable(type); |
fdf1250a | 206 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 207 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
208 | |
209 | I915_WRITE(reg, val); | |
9d9740f0 | 210 | POSTING_READ(reg); |
fdf1250a PZ |
211 | } |
212 | ||
213 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
178f736a DL |
214 | enum hdmi_infoframe_type type, |
215 | const uint8_t *frame, ssize_t len) | |
b055c8f3 | 216 | { |
45187ace | 217 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
218 | struct drm_device *dev = encoder->dev; |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 220 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 221 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 222 | u32 val = I915_READ(reg); |
b055c8f3 | 223 | |
822974ae PZ |
224 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
225 | ||
64a8fc01 | 226 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 227 | val |= g4x_infoframe_index(type); |
45187ace | 228 | |
ecb97851 PZ |
229 | /* The DIP control register spec says that we need to update the AVI |
230 | * infoframe without clearing its enable bit */ | |
178f736a DL |
231 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
232 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 233 | |
22509ec8 | 234 | I915_WRITE(reg, val); |
45187ace | 235 | |
9d9740f0 | 236 | mmiowb(); |
45187ace | 237 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
238 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
239 | data++; | |
240 | } | |
adf00b26 PZ |
241 | /* Write every possible data byte to force correct ECC calculation. */ |
242 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
243 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 244 | mmiowb(); |
b055c8f3 | 245 | |
178f736a | 246 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 247 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 248 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 249 | |
22509ec8 | 250 | I915_WRITE(reg, val); |
9d9740f0 | 251 | POSTING_READ(reg); |
45187ace | 252 | } |
90b107c8 SK |
253 | |
254 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
178f736a DL |
255 | enum hdmi_infoframe_type type, |
256 | const uint8_t *frame, ssize_t len) | |
90b107c8 SK |
257 | { |
258 | uint32_t *data = (uint32_t *)frame; | |
259 | struct drm_device *dev = encoder->dev; | |
260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 261 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 262 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 263 | u32 val = I915_READ(reg); |
90b107c8 | 264 | |
822974ae PZ |
265 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
266 | ||
90b107c8 | 267 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 268 | val |= g4x_infoframe_index(type); |
22509ec8 | 269 | |
178f736a | 270 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 271 | |
22509ec8 | 272 | I915_WRITE(reg, val); |
90b107c8 | 273 | |
9d9740f0 | 274 | mmiowb(); |
90b107c8 SK |
275 | for (i = 0; i < len; i += 4) { |
276 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
277 | data++; | |
278 | } | |
adf00b26 PZ |
279 | /* Write every possible data byte to force correct ECC calculation. */ |
280 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
281 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 282 | mmiowb(); |
90b107c8 | 283 | |
178f736a | 284 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 285 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 286 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 287 | |
22509ec8 | 288 | I915_WRITE(reg, val); |
9d9740f0 | 289 | POSTING_READ(reg); |
90b107c8 SK |
290 | } |
291 | ||
8c5f5f7c | 292 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a DL |
293 | enum hdmi_infoframe_type type, |
294 | const uint8_t *frame, ssize_t len) | |
8c5f5f7c | 295 | { |
2da8af54 PZ |
296 | uint32_t *data = (uint32_t *)frame; |
297 | struct drm_device *dev = encoder->dev; | |
298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
299 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f | 300 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
178f736a DL |
301 | u32 data_reg; |
302 | int i; | |
2da8af54 | 303 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 304 | |
178f736a DL |
305 | data_reg = hsw_infoframe_data_reg(type, |
306 | intel_crtc->config.cpu_transcoder); | |
2da8af54 PZ |
307 | if (data_reg == 0) |
308 | return; | |
309 | ||
178f736a | 310 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
311 | I915_WRITE(ctl_reg, val); |
312 | ||
9d9740f0 | 313 | mmiowb(); |
2da8af54 PZ |
314 | for (i = 0; i < len; i += 4) { |
315 | I915_WRITE(data_reg + i, *data); | |
316 | data++; | |
317 | } | |
adf00b26 PZ |
318 | /* Write every possible data byte to force correct ECC calculation. */ |
319 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
320 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 321 | mmiowb(); |
8c5f5f7c | 322 | |
178f736a | 323 | val |= hsw_infoframe_enable(type); |
2da8af54 | 324 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 325 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
326 | } |
327 | ||
45187ace JB |
328 | static void intel_set_infoframe(struct drm_encoder *encoder, |
329 | struct dip_infoframe *frame) | |
330 | { | |
331 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
332 | ||
45187ace | 333 | intel_dip_infoframe_csum(frame); |
178f736a DL |
334 | intel_hdmi->write_infoframe(encoder, frame->type, (uint8_t *)frame, |
335 | DIP_HEADER_SIZE + frame->len); | |
45187ace JB |
336 | } |
337 | ||
687f4d06 | 338 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 339 | struct drm_display_mode *adjusted_mode) |
45187ace | 340 | { |
abedc077 | 341 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 342 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
45187ace JB |
343 | struct dip_infoframe avi_if = { |
344 | .type = DIP_TYPE_AVI, | |
345 | .ver = DIP_VERSION_AVI, | |
346 | .len = DIP_LEN_AVI, | |
347 | }; | |
348 | ||
c846b619 PZ |
349 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
350 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
351 | ||
abedc077 | 352 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 353 | if (intel_crtc->config.limited_color_range) |
abedc077 VS |
354 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; |
355 | else | |
356 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; | |
357 | } | |
358 | ||
18316c8c | 359 | avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode); |
9a69b885 | 360 | |
45187ace | 361 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
362 | } |
363 | ||
687f4d06 | 364 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 JB |
365 | { |
366 | struct dip_infoframe spd_if; | |
367 | ||
368 | memset(&spd_if, 0, sizeof(spd_if)); | |
369 | spd_if.type = DIP_TYPE_SPD; | |
370 | spd_if.ver = DIP_VERSION_SPD; | |
371 | spd_if.len = DIP_LEN_SPD; | |
372 | strcpy(spd_if.body.spd.vn, "Intel"); | |
373 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
374 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
375 | ||
376 | intel_set_infoframe(encoder, &spd_if); | |
377 | } | |
378 | ||
687f4d06 PZ |
379 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
380 | struct drm_display_mode *adjusted_mode) | |
381 | { | |
0c14c7f9 | 382 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
383 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
384 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
385 | u32 reg = VIDEO_DIP_CTL; |
386 | u32 val = I915_READ(reg); | |
72b78c9d | 387 | u32 port; |
0c14c7f9 | 388 | |
afba0188 DV |
389 | assert_hdmi_port_disabled(intel_hdmi); |
390 | ||
0c14c7f9 PZ |
391 | /* If the registers were not initialized yet, they might be zeroes, |
392 | * which means we're selecting the AVI DIP and we're setting its | |
393 | * frequency to once. This seems to really confuse the HW and make | |
394 | * things stop working (the register spec says the AVI always needs to | |
395 | * be sent every VSync). So here we avoid writing to the register more | |
396 | * than we need and also explicitly select the AVI DIP and explicitly | |
397 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
398 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
399 | * either. */ | |
400 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
401 | ||
402 | if (!intel_hdmi->has_hdmi_sink) { | |
403 | if (!(val & VIDEO_DIP_ENABLE)) | |
404 | return; | |
405 | val &= ~VIDEO_DIP_ENABLE; | |
406 | I915_WRITE(reg, val); | |
9d9740f0 | 407 | POSTING_READ(reg); |
0c14c7f9 PZ |
408 | return; |
409 | } | |
410 | ||
69fde0a6 VS |
411 | switch (intel_dig_port->port) { |
412 | case PORT_B: | |
72b78c9d | 413 | port = VIDEO_DIP_PORT_B; |
f278d972 | 414 | break; |
69fde0a6 | 415 | case PORT_C: |
72b78c9d | 416 | port = VIDEO_DIP_PORT_C; |
f278d972 PZ |
417 | break; |
418 | default: | |
57df2ae9 | 419 | BUG(); |
f278d972 PZ |
420 | return; |
421 | } | |
422 | ||
72b78c9d PZ |
423 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
424 | if (val & VIDEO_DIP_ENABLE) { | |
425 | val &= ~VIDEO_DIP_ENABLE; | |
426 | I915_WRITE(reg, val); | |
9d9740f0 | 427 | POSTING_READ(reg); |
72b78c9d PZ |
428 | } |
429 | val &= ~VIDEO_DIP_PORT_MASK; | |
430 | val |= port; | |
431 | } | |
432 | ||
822974ae | 433 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 434 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 435 | |
f278d972 | 436 | I915_WRITE(reg, val); |
9d9740f0 | 437 | POSTING_READ(reg); |
f278d972 | 438 | |
687f4d06 PZ |
439 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
440 | intel_hdmi_set_spd_infoframe(encoder); | |
441 | } | |
442 | ||
443 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
444 | struct drm_display_mode *adjusted_mode) | |
445 | { | |
0c14c7f9 PZ |
446 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
447 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
448 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
449 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
450 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
451 | u32 val = I915_READ(reg); | |
72b78c9d | 452 | u32 port; |
0c14c7f9 | 453 | |
afba0188 DV |
454 | assert_hdmi_port_disabled(intel_hdmi); |
455 | ||
0c14c7f9 PZ |
456 | /* See the big comment in g4x_set_infoframes() */ |
457 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
458 | ||
459 | if (!intel_hdmi->has_hdmi_sink) { | |
460 | if (!(val & VIDEO_DIP_ENABLE)) | |
461 | return; | |
462 | val &= ~VIDEO_DIP_ENABLE; | |
463 | I915_WRITE(reg, val); | |
9d9740f0 | 464 | POSTING_READ(reg); |
0c14c7f9 PZ |
465 | return; |
466 | } | |
467 | ||
69fde0a6 VS |
468 | switch (intel_dig_port->port) { |
469 | case PORT_B: | |
72b78c9d | 470 | port = VIDEO_DIP_PORT_B; |
f278d972 | 471 | break; |
69fde0a6 | 472 | case PORT_C: |
72b78c9d | 473 | port = VIDEO_DIP_PORT_C; |
f278d972 | 474 | break; |
69fde0a6 | 475 | case PORT_D: |
72b78c9d | 476 | port = VIDEO_DIP_PORT_D; |
f278d972 PZ |
477 | break; |
478 | default: | |
57df2ae9 | 479 | BUG(); |
f278d972 PZ |
480 | return; |
481 | } | |
482 | ||
72b78c9d PZ |
483 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
484 | if (val & VIDEO_DIP_ENABLE) { | |
485 | val &= ~VIDEO_DIP_ENABLE; | |
486 | I915_WRITE(reg, val); | |
9d9740f0 | 487 | POSTING_READ(reg); |
72b78c9d PZ |
488 | } |
489 | val &= ~VIDEO_DIP_PORT_MASK; | |
490 | val |= port; | |
491 | } | |
492 | ||
822974ae | 493 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
494 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
495 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 496 | |
f278d972 | 497 | I915_WRITE(reg, val); |
9d9740f0 | 498 | POSTING_READ(reg); |
f278d972 | 499 | |
687f4d06 PZ |
500 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
501 | intel_hdmi_set_spd_infoframe(encoder); | |
502 | } | |
503 | ||
504 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
505 | struct drm_display_mode *adjusted_mode) | |
506 | { | |
0c14c7f9 PZ |
507 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
508 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
509 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
510 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
511 | u32 val = I915_READ(reg); | |
512 | ||
afba0188 DV |
513 | assert_hdmi_port_disabled(intel_hdmi); |
514 | ||
0c14c7f9 PZ |
515 | /* See the big comment in g4x_set_infoframes() */ |
516 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
517 | ||
518 | if (!intel_hdmi->has_hdmi_sink) { | |
519 | if (!(val & VIDEO_DIP_ENABLE)) | |
520 | return; | |
521 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
522 | I915_WRITE(reg, val); | |
9d9740f0 | 523 | POSTING_READ(reg); |
0c14c7f9 PZ |
524 | return; |
525 | } | |
526 | ||
822974ae PZ |
527 | /* Set both together, unset both together: see the spec. */ |
528 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
529 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
530 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
531 | |
532 | I915_WRITE(reg, val); | |
9d9740f0 | 533 | POSTING_READ(reg); |
822974ae | 534 | |
687f4d06 PZ |
535 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
536 | intel_hdmi_set_spd_infoframe(encoder); | |
537 | } | |
538 | ||
539 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
540 | struct drm_display_mode *adjusted_mode) | |
541 | { | |
0c14c7f9 PZ |
542 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
543 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
544 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
545 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
546 | u32 val = I915_READ(reg); | |
547 | ||
afba0188 DV |
548 | assert_hdmi_port_disabled(intel_hdmi); |
549 | ||
0c14c7f9 PZ |
550 | /* See the big comment in g4x_set_infoframes() */ |
551 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
552 | ||
553 | if (!intel_hdmi->has_hdmi_sink) { | |
554 | if (!(val & VIDEO_DIP_ENABLE)) | |
555 | return; | |
556 | val &= ~VIDEO_DIP_ENABLE; | |
557 | I915_WRITE(reg, val); | |
9d9740f0 | 558 | POSTING_READ(reg); |
0c14c7f9 PZ |
559 | return; |
560 | } | |
561 | ||
822974ae | 562 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
563 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
564 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
565 | |
566 | I915_WRITE(reg, val); | |
9d9740f0 | 567 | POSTING_READ(reg); |
822974ae | 568 | |
687f4d06 PZ |
569 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
570 | intel_hdmi_set_spd_infoframe(encoder); | |
571 | } | |
572 | ||
573 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
574 | struct drm_display_mode *adjusted_mode) | |
575 | { | |
0c14c7f9 PZ |
576 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
577 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
578 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 579 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 580 | u32 val = I915_READ(reg); |
0c14c7f9 | 581 | |
afba0188 DV |
582 | assert_hdmi_port_disabled(intel_hdmi); |
583 | ||
0c14c7f9 PZ |
584 | if (!intel_hdmi->has_hdmi_sink) { |
585 | I915_WRITE(reg, 0); | |
9d9740f0 | 586 | POSTING_READ(reg); |
0c14c7f9 PZ |
587 | return; |
588 | } | |
589 | ||
0dd87d20 PZ |
590 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
591 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
592 | ||
593 | I915_WRITE(reg, val); | |
9d9740f0 | 594 | POSTING_READ(reg); |
0dd87d20 | 595 | |
687f4d06 PZ |
596 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
597 | intel_hdmi_set_spd_infoframe(encoder); | |
598 | } | |
599 | ||
c59423a3 | 600 | static void intel_hdmi_mode_set(struct intel_encoder *encoder) |
7d57382e | 601 | { |
c59423a3 | 602 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 603 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
604 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
605 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
606 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
b242b7f7 | 607 | u32 hdmi_val; |
7d57382e | 608 | |
b242b7f7 | 609 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 610 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 611 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 612 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 613 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 614 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 615 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 616 | |
c59423a3 | 617 | if (crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 618 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 619 | else |
4f3a8bc7 | 620 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 621 | |
2e3d6006 ZW |
622 | /* Required on CPT */ |
623 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
dc0fa718 | 624 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 625 | |
3c17fe4b | 626 | if (intel_hdmi->has_audio) { |
e0dac65e | 627 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
c59423a3 | 628 | pipe_name(crtc->pipe)); |
b242b7f7 | 629 | hdmi_val |= SDVO_AUDIO_ENABLE; |
dc0fa718 | 630 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
c59423a3 | 631 | intel_write_eld(&encoder->base, adjusted_mode); |
3c17fe4b | 632 | } |
7d57382e | 633 | |
75770564 | 634 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 635 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
dc0fa718 | 636 | else |
c59423a3 | 637 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 638 | |
b242b7f7 PZ |
639 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
640 | POSTING_READ(intel_hdmi->hdmi_reg); | |
3c17fe4b | 641 | |
c59423a3 | 642 | intel_hdmi->set_infoframes(&encoder->base, adjusted_mode); |
7d57382e EA |
643 | } |
644 | ||
85234cdc DV |
645 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
646 | enum pipe *pipe) | |
7d57382e | 647 | { |
85234cdc | 648 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 649 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc DV |
650 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
651 | u32 tmp; | |
652 | ||
b242b7f7 | 653 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
654 | |
655 | if (!(tmp & SDVO_ENABLE)) | |
656 | return false; | |
657 | ||
658 | if (HAS_PCH_CPT(dev)) | |
659 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
660 | else | |
661 | *pipe = PORT_TO_PIPE(tmp); | |
662 | ||
663 | return true; | |
664 | } | |
665 | ||
045ac3b5 JB |
666 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
667 | struct intel_crtc_config *pipe_config) | |
668 | { | |
669 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
670 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
671 | u32 tmp, flags = 0; | |
672 | ||
673 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
674 | ||
675 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
676 | flags |= DRM_MODE_FLAG_PHSYNC; | |
677 | else | |
678 | flags |= DRM_MODE_FLAG_NHSYNC; | |
679 | ||
680 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
681 | flags |= DRM_MODE_FLAG_PVSYNC; | |
682 | else | |
683 | flags |= DRM_MODE_FLAG_NVSYNC; | |
684 | ||
685 | pipe_config->adjusted_mode.flags |= flags; | |
686 | } | |
687 | ||
5ab432ef | 688 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 689 | { |
5ab432ef | 690 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 691 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 692 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 693 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 694 | u32 temp; |
2deed761 WF |
695 | u32 enable_bits = SDVO_ENABLE; |
696 | ||
697 | if (intel_hdmi->has_audio) | |
698 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 699 | |
b242b7f7 | 700 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 701 | |
7a87c289 | 702 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
703 | * before disabling it, so restore the transcoder select bit here. */ |
704 | if (HAS_PCH_IBX(dev)) | |
705 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 706 | |
d8a2d0e0 ZW |
707 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
708 | * we do this anyway which shows more stable in testing. | |
709 | */ | |
c619eed4 | 710 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
711 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
712 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
713 | } |
714 | ||
5ab432ef DV |
715 | temp |= enable_bits; |
716 | ||
b242b7f7 PZ |
717 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
718 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
719 | |
720 | /* HW workaround, need to write this twice for issue that may result | |
721 | * in first write getting masked. | |
722 | */ | |
723 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
724 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
725 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 726 | } |
b76cf76b | 727 | } |
89b667f8 | 728 | |
b76cf76b JN |
729 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
730 | { | |
5ab432ef DV |
731 | } |
732 | ||
733 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
734 | { | |
735 | struct drm_device *dev = encoder->base.dev; | |
736 | struct drm_i915_private *dev_priv = dev->dev_private; | |
737 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
738 | u32 temp; | |
3cce574f | 739 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 740 | |
b242b7f7 | 741 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
742 | |
743 | /* HW workaround for IBX, we need to move the port to transcoder A | |
744 | * before disabling it. */ | |
745 | if (HAS_PCH_IBX(dev)) { | |
746 | struct drm_crtc *crtc = encoder->base.crtc; | |
747 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
748 | ||
749 | if (temp & SDVO_PIPE_B_SELECT) { | |
750 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
751 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
752 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
753 | |
754 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
755 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
756 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
757 | |
758 | /* Transcoder selection bits only update | |
759 | * effectively on vblank. */ | |
760 | if (crtc) | |
761 | intel_wait_for_vblank(dev, pipe); | |
762 | else | |
763 | msleep(50); | |
764 | } | |
7d57382e | 765 | } |
d8a2d0e0 | 766 | |
5ab432ef DV |
767 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
768 | * we do this anyway which shows more stable in testing. | |
769 | */ | |
770 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
771 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
772 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
773 | } |
774 | ||
775 | temp &= ~enable_bits; | |
d8a2d0e0 | 776 | |
b242b7f7 PZ |
777 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
778 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
779 | |
780 | /* HW workaround, need to write this twice for issue that may result | |
781 | * in first write getting masked. | |
782 | */ | |
c619eed4 | 783 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
784 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
785 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 786 | } |
7d57382e EA |
787 | } |
788 | ||
7d57382e EA |
789 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
790 | struct drm_display_mode *mode) | |
791 | { | |
792 | if (mode->clock > 165000) | |
793 | return MODE_CLOCK_HIGH; | |
794 | if (mode->clock < 20000) | |
5cbba41d | 795 | return MODE_CLOCK_LOW; |
7d57382e EA |
796 | |
797 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
798 | return MODE_NO_DBLESCAN; | |
799 | ||
800 | return MODE_OK; | |
801 | } | |
802 | ||
5bfe2ac0 DV |
803 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
804 | struct intel_crtc_config *pipe_config) | |
7d57382e | 805 | { |
5bfe2ac0 DV |
806 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
807 | struct drm_device *dev = encoder->base.dev; | |
808 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
325b9d04 | 809 | int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2; |
e29c22c0 | 810 | int desired_bpp; |
3685a8f3 | 811 | |
55bc60db VS |
812 | if (intel_hdmi->color_range_auto) { |
813 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
814 | if (intel_hdmi->has_hdmi_sink && | |
18316c8c | 815 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 816 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
817 | else |
818 | intel_hdmi->color_range = 0; | |
819 | } | |
820 | ||
3685a8f3 | 821 | if (intel_hdmi->color_range) |
50f3b016 | 822 | pipe_config->limited_color_range = true; |
3685a8f3 | 823 | |
5bfe2ac0 DV |
824 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
825 | pipe_config->has_pch_encoder = true; | |
826 | ||
4e53c2e0 DV |
827 | /* |
828 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
829 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
830 | * outputs. We also need to check that the higher clock still fits |
831 | * within limits. | |
4e53c2e0 | 832 | */ |
325b9d04 DV |
833 | if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= 225000 |
834 | && HAS_PCH_SPLIT(dev)) { | |
e29c22c0 DV |
835 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
836 | desired_bpp = 12*3; | |
325b9d04 DV |
837 | |
838 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 839 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 840 | } else { |
e29c22c0 DV |
841 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
842 | desired_bpp = 8*3; | |
843 | } | |
844 | ||
845 | if (!pipe_config->bw_constrained) { | |
846 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
847 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
848 | } |
849 | ||
325b9d04 DV |
850 | if (adjusted_mode->clock > 225000) { |
851 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); | |
852 | return false; | |
853 | } | |
854 | ||
7d57382e EA |
855 | return true; |
856 | } | |
857 | ||
aa93d632 | 858 | static enum drm_connector_status |
930a9e28 | 859 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 860 | { |
b0ea7d37 | 861 | struct drm_device *dev = connector->dev; |
df0e9248 | 862 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
863 | struct intel_digital_port *intel_dig_port = |
864 | hdmi_to_dig_port(intel_hdmi); | |
865 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 866 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 867 | struct edid *edid; |
aa93d632 | 868 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 869 | |
164c8598 CW |
870 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
871 | connector->base.id, drm_get_connector_name(connector)); | |
872 | ||
ea5b213a | 873 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 874 | intel_hdmi->has_audio = false; |
abedc077 | 875 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 876 | edid = drm_get_edid(connector, |
3bd7d909 DK |
877 | intel_gmbus_get_adapter(dev_priv, |
878 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 879 | |
aa93d632 | 880 | if (edid) { |
be9f1c4f | 881 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 882 | status = connector_status_connected; |
b1d7e4b4 WF |
883 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
884 | intel_hdmi->has_hdmi_sink = | |
885 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 886 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
887 | intel_hdmi->rgb_quant_range_selectable = |
888 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 889 | } |
aa93d632 | 890 | kfree(edid); |
9dff6af8 | 891 | } |
30ad48b7 | 892 | |
55b7d6e8 | 893 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
894 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
895 | intel_hdmi->has_audio = | |
896 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 897 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
898 | } |
899 | ||
2ded9e27 | 900 | return status; |
7d57382e EA |
901 | } |
902 | ||
903 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
904 | { | |
df0e9248 | 905 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 906 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
907 | |
908 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
909 | * we can send audio to it. | |
910 | */ | |
911 | ||
f899fc64 | 912 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
913 | intel_gmbus_get_adapter(dev_priv, |
914 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
915 | } |
916 | ||
1aad7ac0 CW |
917 | static bool |
918 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
919 | { | |
920 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
921 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
922 | struct edid *edid; | |
923 | bool has_audio = false; | |
924 | ||
925 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
926 | intel_gmbus_get_adapter(dev_priv, |
927 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
928 | if (edid) { |
929 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
930 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
931 | kfree(edid); |
932 | } | |
933 | ||
934 | return has_audio; | |
935 | } | |
936 | ||
55b7d6e8 CW |
937 | static int |
938 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
939 | struct drm_property *property, |
940 | uint64_t val) | |
55b7d6e8 CW |
941 | { |
942 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
943 | struct intel_digital_port *intel_dig_port = |
944 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 945 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
946 | int ret; |
947 | ||
662595df | 948 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
949 | if (ret) |
950 | return ret; | |
951 | ||
3f43c48d | 952 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 953 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
954 | bool has_audio; |
955 | ||
956 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
957 | return 0; |
958 | ||
1aad7ac0 | 959 | intel_hdmi->force_audio = i; |
55b7d6e8 | 960 | |
b1d7e4b4 | 961 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
962 | has_audio = intel_hdmi_detect_audio(connector); |
963 | else | |
b1d7e4b4 | 964 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 965 | |
b1d7e4b4 WF |
966 | if (i == HDMI_AUDIO_OFF_DVI) |
967 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 968 | |
1aad7ac0 | 969 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
970 | goto done; |
971 | } | |
972 | ||
e953fd7b | 973 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
974 | bool old_auto = intel_hdmi->color_range_auto; |
975 | uint32_t old_range = intel_hdmi->color_range; | |
976 | ||
55bc60db VS |
977 | switch (val) { |
978 | case INTEL_BROADCAST_RGB_AUTO: | |
979 | intel_hdmi->color_range_auto = true; | |
980 | break; | |
981 | case INTEL_BROADCAST_RGB_FULL: | |
982 | intel_hdmi->color_range_auto = false; | |
983 | intel_hdmi->color_range = 0; | |
984 | break; | |
985 | case INTEL_BROADCAST_RGB_LIMITED: | |
986 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 987 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
988 | break; |
989 | default: | |
990 | return -EINVAL; | |
991 | } | |
ae4edb80 DV |
992 | |
993 | if (old_auto == intel_hdmi->color_range_auto && | |
994 | old_range == intel_hdmi->color_range) | |
995 | return 0; | |
996 | ||
e953fd7b CW |
997 | goto done; |
998 | } | |
999 | ||
55b7d6e8 CW |
1000 | return -EINVAL; |
1001 | ||
1002 | done: | |
c0c36b94 CW |
1003 | if (intel_dig_port->base.base.crtc) |
1004 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1005 | |
1006 | return 0; | |
1007 | } | |
1008 | ||
89b667f8 JB |
1009 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1010 | { | |
1011 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1012 | struct drm_device *dev = encoder->base.dev; | |
1013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1014 | struct intel_crtc *intel_crtc = | |
1015 | to_intel_crtc(encoder->base.crtc); | |
1016 | int port = vlv_dport_to_channel(dport); | |
1017 | int pipe = intel_crtc->pipe; | |
1018 | u32 val; | |
1019 | ||
1020 | if (!IS_VALLEYVIEW(dev)) | |
1021 | return; | |
1022 | ||
89b667f8 | 1023 | /* Enable clock channels for this port */ |
0980a60f | 1024 | mutex_lock(&dev_priv->dpio_lock); |
ae99258f | 1025 | val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port)); |
89b667f8 JB |
1026 | val = 0; |
1027 | if (pipe) | |
1028 | val |= (1<<21); | |
1029 | else | |
1030 | val &= ~(1<<21); | |
1031 | val |= 0x001000c4; | |
ae99258f | 1032 | vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val); |
89b667f8 JB |
1033 | |
1034 | /* HDMI 1.0V-2dB */ | |
ae99258f JN |
1035 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0); |
1036 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), | |
89b667f8 | 1037 | 0x2b245f5f); |
ae99258f | 1038 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port), |
89b667f8 | 1039 | 0x5578b83a); |
ae99258f | 1040 | vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), |
89b667f8 | 1041 | 0x0c782040); |
ae99258f | 1042 | vlv_dpio_write(dev_priv, DPIO_TX3_SWING_CTL4(port), |
89b667f8 | 1043 | 0x2b247878); |
ae99258f JN |
1044 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000); |
1045 | vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), | |
89b667f8 | 1046 | 0x00002000); |
ae99258f | 1047 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), |
89b667f8 JB |
1048 | DPIO_TX_OCALINIT_EN); |
1049 | ||
1050 | /* Program lane clock */ | |
ae99258f | 1051 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port), |
89b667f8 | 1052 | 0x00760018); |
ae99258f | 1053 | vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port), |
89b667f8 | 1054 | 0x00400888); |
0980a60f | 1055 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b JN |
1056 | |
1057 | intel_enable_hdmi(encoder); | |
1058 | ||
1059 | vlv_wait_port_ready(dev_priv, port); | |
89b667f8 JB |
1060 | } |
1061 | ||
1062 | static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder) | |
1063 | { | |
1064 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1065 | struct drm_device *dev = encoder->base.dev; | |
1066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1067 | int port = vlv_dport_to_channel(dport); | |
1068 | ||
1069 | if (!IS_VALLEYVIEW(dev)) | |
1070 | return; | |
1071 | ||
89b667f8 | 1072 | /* Program Tx lane resets to default */ |
0980a60f | 1073 | mutex_lock(&dev_priv->dpio_lock); |
ae99258f | 1074 | vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), |
89b667f8 JB |
1075 | DPIO_PCS_TX_LANE2_RESET | |
1076 | DPIO_PCS_TX_LANE1_RESET); | |
ae99258f | 1077 | vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), |
89b667f8 JB |
1078 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1079 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1080 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1081 | DPIO_PCS_CLK_SOFT_RESET); | |
1082 | ||
1083 | /* Fix up inter-pair skew failure */ | |
ae99258f JN |
1084 | vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00); |
1085 | vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500); | |
1086 | vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000); | |
89b667f8 | 1087 | |
ae99258f | 1088 | vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), |
89b667f8 | 1089 | 0x00002000); |
ae99258f | 1090 | vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), |
89b667f8 | 1091 | DPIO_TX_OCALINIT_EN); |
0980a60f | 1092 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1093 | } |
1094 | ||
1095 | static void intel_hdmi_post_disable(struct intel_encoder *encoder) | |
1096 | { | |
1097 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1098 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1099 | int port = vlv_dport_to_channel(dport); | |
1100 | ||
1101 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1102 | mutex_lock(&dev_priv->dpio_lock); | |
ae99258f JN |
1103 | vlv_dpio_write(dev_priv, DPIO_PCS_TX(port), 0x00000000); |
1104 | vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port), 0x00e00060); | |
89b667f8 JB |
1105 | mutex_unlock(&dev_priv->dpio_lock); |
1106 | } | |
1107 | ||
7d57382e EA |
1108 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1109 | { | |
7d57382e EA |
1110 | drm_sysfs_connector_remove(connector); |
1111 | drm_connector_cleanup(connector); | |
674e2d08 | 1112 | kfree(connector); |
7d57382e EA |
1113 | } |
1114 | ||
7d57382e | 1115 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1116 | .dpms = intel_connector_dpms, |
7d57382e EA |
1117 | .detect = intel_hdmi_detect, |
1118 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 1119 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1120 | .destroy = intel_hdmi_destroy, |
1121 | }; | |
1122 | ||
1123 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1124 | .get_modes = intel_hdmi_get_modes, | |
1125 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1126 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1127 | }; |
1128 | ||
7d57382e | 1129 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1130 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1131 | }; |
1132 | ||
55b7d6e8 CW |
1133 | static void |
1134 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1135 | { | |
3f43c48d | 1136 | intel_attach_force_audio_property(connector); |
e953fd7b | 1137 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1138 | intel_hdmi->color_range_auto = true; |
55b7d6e8 CW |
1139 | } |
1140 | ||
00c09d70 PZ |
1141 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1142 | struct intel_connector *intel_connector) | |
7d57382e | 1143 | { |
b9cb234c PZ |
1144 | struct drm_connector *connector = &intel_connector->base; |
1145 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1146 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1147 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1148 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1149 | enum port port = intel_dig_port->port; |
373a3cf7 | 1150 | |
7d57382e | 1151 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1152 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1153 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1154 | ||
c3febcc4 | 1155 | connector->interlace_allowed = 1; |
7d57382e | 1156 | connector->doublescan_allowed = 0; |
66a9278e | 1157 | |
08d644ad DV |
1158 | switch (port) { |
1159 | case PORT_B: | |
f899fc64 | 1160 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1161 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1162 | break; |
1163 | case PORT_C: | |
7ceae0a5 | 1164 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1165 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1166 | break; |
1167 | case PORT_D: | |
7ceae0a5 | 1168 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
1d843f9d | 1169 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1170 | break; |
1171 | case PORT_A: | |
1d843f9d | 1172 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1173 | /* Internal port only for eDP. */ |
1174 | default: | |
6e4c1677 | 1175 | BUG(); |
f8aed700 | 1176 | } |
7d57382e | 1177 | |
7637bfdb | 1178 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1179 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1180 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
7637bfdb JB |
1181 | } else if (!HAS_PCH_SPLIT(dev)) { |
1182 | intel_hdmi->write_infoframe = g4x_write_infoframe; | |
1183 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
22b8bf17 | 1184 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1185 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1186 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1187 | } else if (HAS_PCH_IBX(dev)) { |
1188 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1189 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1190 | } else { |
1191 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1192 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1193 | } |
45187ace | 1194 | |
affa9354 | 1195 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1196 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1197 | else | |
1198 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
1199 | |
1200 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1201 | ||
1202 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
1203 | drm_sysfs_connector_add(connector); | |
1204 | ||
1205 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1206 | * 0xd. Failure to do so will result in spurious interrupts being | |
1207 | * generated on the port when a cable is not attached. | |
1208 | */ | |
1209 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1210 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1211 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1212 | } | |
1213 | } | |
1214 | ||
b242b7f7 | 1215 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1216 | { |
1217 | struct intel_digital_port *intel_dig_port; | |
1218 | struct intel_encoder *intel_encoder; | |
1219 | struct drm_encoder *encoder; | |
1220 | struct intel_connector *intel_connector; | |
1221 | ||
1222 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); | |
1223 | if (!intel_dig_port) | |
1224 | return; | |
1225 | ||
1226 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
1227 | if (!intel_connector) { | |
1228 | kfree(intel_dig_port); | |
1229 | return; | |
1230 | } | |
1231 | ||
1232 | intel_encoder = &intel_dig_port->base; | |
1233 | encoder = &intel_encoder->base; | |
1234 | ||
1235 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1236 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1237 | |
5bfe2ac0 | 1238 | intel_encoder->compute_config = intel_hdmi_compute_config; |
c59423a3 | 1239 | intel_encoder->mode_set = intel_hdmi_mode_set; |
00c09d70 PZ |
1240 | intel_encoder->disable = intel_disable_hdmi; |
1241 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1242 | intel_encoder->get_config = intel_hdmi_get_config; |
89b667f8 | 1243 | if (IS_VALLEYVIEW(dev)) { |
89b667f8 | 1244 | intel_encoder->pre_pll_enable = intel_hdmi_pre_pll_enable; |
b76cf76b JN |
1245 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
1246 | intel_encoder->enable = vlv_enable_hdmi; | |
89b667f8 | 1247 | intel_encoder->post_disable = intel_hdmi_post_disable; |
b76cf76b JN |
1248 | } else { |
1249 | intel_encoder->enable = intel_enable_hdmi; | |
89b667f8 | 1250 | } |
5ab432ef | 1251 | |
b9cb234c PZ |
1252 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
1253 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1254 | intel_encoder->cloneable = false; | |
7d57382e | 1255 | |
174edf1f | 1256 | intel_dig_port->port = port; |
b242b7f7 | 1257 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1258 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1259 | |
b9cb234c | 1260 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1261 | } |