Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e EA |
31 | #include <linux/delay.h> |
32 | #include "drmP.h" | |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
aa93d632 | 35 | #include "drm_edid.h" |
7d57382e EA |
36 | #include "intel_drv.h" |
37 | #include "i915_drm.h" | |
38 | #include "i915_drv.h" | |
39 | ||
ea5b213a CW |
40 | struct intel_hdmi { |
41 | struct intel_encoder base; | |
7d57382e | 42 | u32 sdvox_reg; |
f899fc64 | 43 | int ddc_bus; |
7ceae0a5 | 44 | int ddi_port; |
e953fd7b | 45 | uint32_t color_range; |
9dff6af8 | 46 | bool has_hdmi_sink; |
2e3d6006 | 47 | bool has_audio; |
b1d7e4b4 | 48 | enum hdmi_force_audio force_audio; |
45187ace JB |
49 | void (*write_infoframe)(struct drm_encoder *encoder, |
50 | struct dip_infoframe *frame); | |
7d57382e EA |
51 | }; |
52 | ||
ea5b213a CW |
53 | static struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
54 | { | |
4ef69c7a | 55 | return container_of(encoder, struct intel_hdmi, base.base); |
ea5b213a CW |
56 | } |
57 | ||
df0e9248 CW |
58 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
59 | { | |
60 | return container_of(intel_attached_encoder(connector), | |
61 | struct intel_hdmi, base); | |
62 | } | |
63 | ||
45187ace | 64 | void intel_dip_infoframe_csum(struct dip_infoframe *frame) |
3c17fe4b | 65 | { |
45187ace | 66 | uint8_t *data = (uint8_t *)frame; |
3c17fe4b DH |
67 | uint8_t sum = 0; |
68 | unsigned i; | |
69 | ||
45187ace JB |
70 | frame->checksum = 0; |
71 | frame->ecc = 0; | |
3c17fe4b | 72 | |
64a8fc01 | 73 | for (i = 0; i < frame->len + DIP_HEADER_SIZE; i++) |
3c17fe4b DH |
74 | sum += data[i]; |
75 | ||
45187ace | 76 | frame->checksum = 0x100 - sum; |
3c17fe4b DH |
77 | } |
78 | ||
bc2481f3 | 79 | static u32 g4x_infoframe_index(struct dip_infoframe *frame) |
3c17fe4b | 80 | { |
45187ace JB |
81 | u32 flags = 0; |
82 | ||
83 | switch (frame->type) { | |
84 | case DIP_TYPE_AVI: | |
85 | flags |= VIDEO_DIP_SELECT_AVI; | |
86 | break; | |
87 | case DIP_TYPE_SPD: | |
88 | flags |= VIDEO_DIP_SELECT_SPD; | |
89 | break; | |
90 | default: | |
91 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
92 | break; | |
93 | } | |
94 | ||
95 | return flags; | |
96 | } | |
97 | ||
bc2481f3 | 98 | static u32 g4x_infoframe_enable(struct dip_infoframe *frame) |
45187ace JB |
99 | { |
100 | u32 flags = 0; | |
101 | ||
102 | switch (frame->type) { | |
103 | case DIP_TYPE_AVI: | |
fa193ff7 | 104 | flags |= VIDEO_DIP_ENABLE_AVI; |
45187ace JB |
105 | break; |
106 | case DIP_TYPE_SPD: | |
fa193ff7 PZ |
107 | flags |= VIDEO_DIP_ENABLE_SPD; |
108 | break; | |
109 | default: | |
110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", frame->type); | |
111 | break; | |
112 | } | |
113 | ||
114 | return flags; | |
115 | } | |
116 | ||
a3da1df7 DV |
117 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
118 | struct dip_infoframe *frame) | |
45187ace JB |
119 | { |
120 | uint32_t *data = (uint32_t *)frame; | |
3c17fe4b DH |
121 | struct drm_device *dev = encoder->dev; |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
22509ec8 | 124 | u32 val = I915_READ(VIDEO_DIP_CTL); |
45187ace | 125 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
3c17fe4b | 126 | |
3c17fe4b DH |
127 | |
128 | /* XXX first guess at handling video port, is this corrent? */ | |
3e6e6395 | 129 | val &= ~VIDEO_DIP_PORT_MASK; |
3c17fe4b | 130 | if (intel_hdmi->sdvox_reg == SDVOB) |
22509ec8 | 131 | val |= VIDEO_DIP_PORT_B; |
3c17fe4b | 132 | else if (intel_hdmi->sdvox_reg == SDVOC) |
22509ec8 | 133 | val |= VIDEO_DIP_PORT_C; |
3c17fe4b DH |
134 | else |
135 | return; | |
136 | ||
1d4f85ac | 137 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 138 | val |= g4x_infoframe_index(frame); |
22509ec8 | 139 | |
bc2481f3 | 140 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 141 | val |= VIDEO_DIP_ENABLE; |
45187ace | 142 | |
22509ec8 | 143 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 144 | |
45187ace | 145 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
146 | I915_WRITE(VIDEO_DIP_DATA, *data); |
147 | data++; | |
148 | } | |
149 | ||
bc2481f3 | 150 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 151 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 152 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 153 | |
22509ec8 | 154 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b DH |
155 | } |
156 | ||
fdf1250a PZ |
157 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
158 | struct dip_infoframe *frame) | |
159 | { | |
160 | uint32_t *data = (uint32_t *)frame; | |
161 | struct drm_device *dev = encoder->dev; | |
162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
163 | struct drm_crtc *crtc = encoder->crtc; | |
164 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4e89ee17 | 165 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
fdf1250a PZ |
166 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
167 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
168 | u32 val = I915_READ(reg); | |
169 | ||
4e89ee17 PZ |
170 | val &= ~VIDEO_DIP_PORT_MASK; |
171 | switch (intel_hdmi->sdvox_reg) { | |
172 | case HDMIB: | |
173 | val |= VIDEO_DIP_PORT_B; | |
174 | break; | |
175 | case HDMIC: | |
176 | val |= VIDEO_DIP_PORT_C; | |
177 | break; | |
178 | case HDMID: | |
179 | val |= VIDEO_DIP_PORT_D; | |
180 | break; | |
181 | default: | |
182 | return; | |
183 | } | |
184 | ||
fdf1250a PZ |
185 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
186 | ||
187 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ | |
bc2481f3 | 188 | val |= g4x_infoframe_index(frame); |
fdf1250a | 189 | |
bc2481f3 | 190 | val &= ~g4x_infoframe_enable(frame); |
fdf1250a PZ |
191 | val |= VIDEO_DIP_ENABLE; |
192 | ||
193 | I915_WRITE(reg, val); | |
194 | ||
195 | for (i = 0; i < len; i += 4) { | |
196 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
197 | data++; | |
198 | } | |
199 | ||
bc2481f3 | 200 | val |= g4x_infoframe_enable(frame); |
fdf1250a | 201 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 202 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
203 | |
204 | I915_WRITE(reg, val); | |
205 | } | |
206 | ||
207 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
208 | struct dip_infoframe *frame) | |
b055c8f3 | 209 | { |
45187ace | 210 | uint32_t *data = (uint32_t *)frame; |
b055c8f3 JB |
211 | struct drm_device *dev = encoder->dev; |
212 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b055c8f3 JB |
213 | struct drm_crtc *crtc = encoder->crtc; |
214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
215 | int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
45187ace | 216 | unsigned i, len = DIP_HEADER_SIZE + frame->len; |
22509ec8 | 217 | u32 val = I915_READ(reg); |
b055c8f3 JB |
218 | |
219 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
220 | ||
64a8fc01 | 221 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 222 | val |= g4x_infoframe_index(frame); |
45187ace | 223 | |
ecb97851 PZ |
224 | /* The DIP control register spec says that we need to update the AVI |
225 | * infoframe without clearing its enable bit */ | |
226 | if (frame->type == DIP_TYPE_AVI) | |
227 | val |= VIDEO_DIP_ENABLE_AVI; | |
228 | else | |
bc2481f3 | 229 | val &= ~g4x_infoframe_enable(frame); |
ecb97851 | 230 | |
22509ec8 PZ |
231 | val |= VIDEO_DIP_ENABLE; |
232 | ||
233 | I915_WRITE(reg, val); | |
45187ace JB |
234 | |
235 | for (i = 0; i < len; i += 4) { | |
b055c8f3 JB |
236 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
237 | data++; | |
238 | } | |
239 | ||
bc2481f3 | 240 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 241 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 242 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 243 | |
22509ec8 | 244 | I915_WRITE(reg, val); |
45187ace | 245 | } |
90b107c8 SK |
246 | |
247 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
248 | struct dip_infoframe *frame) | |
249 | { | |
250 | uint32_t *data = (uint32_t *)frame; | |
251 | struct drm_device *dev = encoder->dev; | |
252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
253 | struct drm_crtc *crtc = encoder->crtc; | |
254 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
255 | int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
256 | unsigned i, len = DIP_HEADER_SIZE + frame->len; | |
22509ec8 | 257 | u32 val = I915_READ(reg); |
90b107c8 SK |
258 | |
259 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
260 | ||
90b107c8 | 261 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
bc2481f3 | 262 | val |= g4x_infoframe_index(frame); |
22509ec8 | 263 | |
bc2481f3 | 264 | val &= ~g4x_infoframe_enable(frame); |
22509ec8 | 265 | val |= VIDEO_DIP_ENABLE; |
90b107c8 | 266 | |
22509ec8 | 267 | I915_WRITE(reg, val); |
90b107c8 SK |
268 | |
269 | for (i = 0; i < len; i += 4) { | |
270 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
271 | data++; | |
272 | } | |
273 | ||
bc2481f3 | 274 | val |= g4x_infoframe_enable(frame); |
60c5ea2d | 275 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 276 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 277 | |
22509ec8 | 278 | I915_WRITE(reg, val); |
90b107c8 SK |
279 | } |
280 | ||
8c5f5f7c ED |
281 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
282 | struct dip_infoframe *frame) | |
283 | { | |
284 | /* Not implemented yet, so avoid doing anything at all. | |
285 | * This is the placeholder for Paulo Zanoni's infoframe writing patch | |
286 | */ | |
287 | DRM_DEBUG_DRIVER("Attempting to write infoframe on Haswell, this is not implemented yet.\n"); | |
288 | ||
289 | return; | |
290 | ||
291 | } | |
292 | ||
45187ace JB |
293 | static void intel_set_infoframe(struct drm_encoder *encoder, |
294 | struct dip_infoframe *frame) | |
295 | { | |
296 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
297 | ||
298 | if (!intel_hdmi->has_hdmi_sink) | |
299 | return; | |
300 | ||
301 | intel_dip_infoframe_csum(frame); | |
302 | intel_hdmi->write_infoframe(encoder, frame); | |
303 | } | |
304 | ||
c846b619 PZ |
305 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
306 | struct drm_display_mode *adjusted_mode) | |
45187ace JB |
307 | { |
308 | struct dip_infoframe avi_if = { | |
309 | .type = DIP_TYPE_AVI, | |
310 | .ver = DIP_VERSION_AVI, | |
311 | .len = DIP_LEN_AVI, | |
312 | }; | |
313 | ||
c846b619 PZ |
314 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
315 | avi_if.body.avi.YQ_CN_PR |= DIP_AVI_PR_2; | |
316 | ||
45187ace | 317 | intel_set_infoframe(encoder, &avi_if); |
b055c8f3 JB |
318 | } |
319 | ||
c0864cb3 JB |
320 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
321 | { | |
322 | struct dip_infoframe spd_if; | |
323 | ||
324 | memset(&spd_if, 0, sizeof(spd_if)); | |
325 | spd_if.type = DIP_TYPE_SPD; | |
326 | spd_if.ver = DIP_VERSION_SPD; | |
327 | spd_if.len = DIP_LEN_SPD; | |
328 | strcpy(spd_if.body.spd.vn, "Intel"); | |
329 | strcpy(spd_if.body.spd.pd, "Integrated gfx"); | |
330 | spd_if.body.spd.sdi = DIP_SPD_PC; | |
331 | ||
332 | intel_set_infoframe(encoder, &spd_if); | |
333 | } | |
334 | ||
7d57382e EA |
335 | static void intel_hdmi_mode_set(struct drm_encoder *encoder, |
336 | struct drm_display_mode *mode, | |
337 | struct drm_display_mode *adjusted_mode) | |
338 | { | |
339 | struct drm_device *dev = encoder->dev; | |
340 | struct drm_i915_private *dev_priv = dev->dev_private; | |
341 | struct drm_crtc *crtc = encoder->crtc; | |
342 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea5b213a | 343 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e EA |
344 | u32 sdvox; |
345 | ||
b599c0bc | 346 | sdvox = SDVO_ENCODING_HDMI | SDVO_BORDER_ENABLE; |
5d4fac97 JB |
347 | if (!HAS_PCH_SPLIT(dev)) |
348 | sdvox |= intel_hdmi->color_range; | |
b599c0bc AJ |
349 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
350 | sdvox |= SDVO_VSYNC_ACTIVE_HIGH; | |
351 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) | |
352 | sdvox |= SDVO_HSYNC_ACTIVE_HIGH; | |
7d57382e | 353 | |
020f6704 JB |
354 | if (intel_crtc->bpp > 24) |
355 | sdvox |= COLOR_FORMAT_12bpc; | |
356 | else | |
357 | sdvox |= COLOR_FORMAT_8bpc; | |
358 | ||
2e3d6006 ZW |
359 | /* Required on CPT */ |
360 | if (intel_hdmi->has_hdmi_sink && HAS_PCH_CPT(dev)) | |
361 | sdvox |= HDMI_MODE_SELECT; | |
362 | ||
3c17fe4b | 363 | if (intel_hdmi->has_audio) { |
e0dac65e WF |
364 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
365 | pipe_name(intel_crtc->pipe)); | |
7d57382e | 366 | sdvox |= SDVO_AUDIO_ENABLE; |
3c17fe4b | 367 | sdvox |= SDVO_NULL_PACKETS_DURING_VSYNC; |
e0dac65e | 368 | intel_write_eld(encoder, adjusted_mode); |
3c17fe4b | 369 | } |
7d57382e | 370 | |
75770564 JB |
371 | if (HAS_PCH_CPT(dev)) |
372 | sdvox |= PORT_TRANS_SEL_CPT(intel_crtc->pipe); | |
373 | else if (intel_crtc->pipe == 1) | |
374 | sdvox |= SDVO_PIPE_B_SELECT; | |
7d57382e | 375 | |
ea5b213a CW |
376 | I915_WRITE(intel_hdmi->sdvox_reg, sdvox); |
377 | POSTING_READ(intel_hdmi->sdvox_reg); | |
3c17fe4b | 378 | |
c846b619 | 379 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
c0864cb3 | 380 | intel_hdmi_set_spd_infoframe(encoder); |
7d57382e EA |
381 | } |
382 | ||
383 | static void intel_hdmi_dpms(struct drm_encoder *encoder, int mode) | |
384 | { | |
385 | struct drm_device *dev = encoder->dev; | |
386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 387 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
7d57382e | 388 | u32 temp; |
2deed761 WF |
389 | u32 enable_bits = SDVO_ENABLE; |
390 | ||
391 | if (intel_hdmi->has_audio) | |
392 | enable_bits |= SDVO_AUDIO_ENABLE; | |
7d57382e | 393 | |
ea5b213a | 394 | temp = I915_READ(intel_hdmi->sdvox_reg); |
d8a2d0e0 ZW |
395 | |
396 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but | |
397 | * we do this anyway which shows more stable in testing. | |
398 | */ | |
c619eed4 | 399 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
400 | I915_WRITE(intel_hdmi->sdvox_reg, temp & ~SDVO_ENABLE); |
401 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
402 | } |
403 | ||
404 | if (mode != DRM_MODE_DPMS_ON) { | |
2deed761 | 405 | temp &= ~enable_bits; |
7d57382e | 406 | } else { |
2deed761 | 407 | temp |= enable_bits; |
7d57382e | 408 | } |
d8a2d0e0 | 409 | |
ea5b213a CW |
410 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
411 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 ZW |
412 | |
413 | /* HW workaround, need to write this twice for issue that may result | |
414 | * in first write getting masked. | |
415 | */ | |
c619eed4 | 416 | if (HAS_PCH_SPLIT(dev)) { |
ea5b213a CW |
417 | I915_WRITE(intel_hdmi->sdvox_reg, temp); |
418 | POSTING_READ(intel_hdmi->sdvox_reg); | |
d8a2d0e0 | 419 | } |
7d57382e EA |
420 | } |
421 | ||
7d57382e EA |
422 | static int intel_hdmi_mode_valid(struct drm_connector *connector, |
423 | struct drm_display_mode *mode) | |
424 | { | |
425 | if (mode->clock > 165000) | |
426 | return MODE_CLOCK_HIGH; | |
427 | if (mode->clock < 20000) | |
5cbba41d | 428 | return MODE_CLOCK_LOW; |
7d57382e EA |
429 | |
430 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
431 | return MODE_NO_DBLESCAN; | |
432 | ||
433 | return MODE_OK; | |
434 | } | |
435 | ||
436 | static bool intel_hdmi_mode_fixup(struct drm_encoder *encoder, | |
437 | struct drm_display_mode *mode, | |
438 | struct drm_display_mode *adjusted_mode) | |
439 | { | |
440 | return true; | |
441 | } | |
442 | ||
aa93d632 | 443 | static enum drm_connector_status |
930a9e28 | 444 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 445 | { |
df0e9248 | 446 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 CW |
447 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
448 | struct edid *edid; | |
aa93d632 | 449 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 450 | |
ea5b213a | 451 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 452 | intel_hdmi->has_audio = false; |
f899fc64 | 453 | edid = drm_get_edid(connector, |
3bd7d909 DK |
454 | intel_gmbus_get_adapter(dev_priv, |
455 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 456 | |
aa93d632 | 457 | if (edid) { |
be9f1c4f | 458 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 459 | status = connector_status_connected; |
b1d7e4b4 WF |
460 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
461 | intel_hdmi->has_hdmi_sink = | |
462 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 463 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
aa93d632 | 464 | } |
674e2d08 | 465 | connector->display_info.raw_edid = NULL; |
aa93d632 | 466 | kfree(edid); |
9dff6af8 | 467 | } |
30ad48b7 | 468 | |
55b7d6e8 | 469 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
470 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
471 | intel_hdmi->has_audio = | |
472 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
55b7d6e8 CW |
473 | } |
474 | ||
2ded9e27 | 475 | return status; |
7d57382e EA |
476 | } |
477 | ||
478 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
479 | { | |
df0e9248 | 480 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
f899fc64 | 481 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
7d57382e EA |
482 | |
483 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
484 | * we can send audio to it. | |
485 | */ | |
486 | ||
f899fc64 | 487 | return intel_ddc_get_modes(connector, |
3bd7d909 DK |
488 | intel_gmbus_get_adapter(dev_priv, |
489 | intel_hdmi->ddc_bus)); | |
7d57382e EA |
490 | } |
491 | ||
1aad7ac0 CW |
492 | static bool |
493 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
494 | { | |
495 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
496 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
497 | struct edid *edid; | |
498 | bool has_audio = false; | |
499 | ||
500 | edid = drm_get_edid(connector, | |
3bd7d909 DK |
501 | intel_gmbus_get_adapter(dev_priv, |
502 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
503 | if (edid) { |
504 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
505 | has_audio = drm_detect_monitor_audio(edid); | |
506 | ||
507 | connector->display_info.raw_edid = NULL; | |
508 | kfree(edid); | |
509 | } | |
510 | ||
511 | return has_audio; | |
512 | } | |
513 | ||
55b7d6e8 CW |
514 | static int |
515 | intel_hdmi_set_property(struct drm_connector *connector, | |
516 | struct drm_property *property, | |
517 | uint64_t val) | |
518 | { | |
519 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
e953fd7b | 520 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
521 | int ret; |
522 | ||
523 | ret = drm_connector_property_set_value(connector, property, val); | |
524 | if (ret) | |
525 | return ret; | |
526 | ||
3f43c48d | 527 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 528 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
529 | bool has_audio; |
530 | ||
531 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
532 | return 0; |
533 | ||
1aad7ac0 | 534 | intel_hdmi->force_audio = i; |
55b7d6e8 | 535 | |
b1d7e4b4 | 536 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
537 | has_audio = intel_hdmi_detect_audio(connector); |
538 | else | |
b1d7e4b4 | 539 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 540 | |
b1d7e4b4 WF |
541 | if (i == HDMI_AUDIO_OFF_DVI) |
542 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 543 | |
1aad7ac0 | 544 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
545 | goto done; |
546 | } | |
547 | ||
e953fd7b CW |
548 | if (property == dev_priv->broadcast_rgb_property) { |
549 | if (val == !!intel_hdmi->color_range) | |
550 | return 0; | |
551 | ||
552 | intel_hdmi->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; | |
553 | goto done; | |
554 | } | |
555 | ||
55b7d6e8 CW |
556 | return -EINVAL; |
557 | ||
558 | done: | |
559 | if (intel_hdmi->base.base.crtc) { | |
560 | struct drm_crtc *crtc = intel_hdmi->base.base.crtc; | |
561 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
562 | crtc->x, crtc->y, | |
563 | crtc->fb); | |
564 | } | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
7d57382e EA |
569 | static void intel_hdmi_destroy(struct drm_connector *connector) |
570 | { | |
7d57382e EA |
571 | drm_sysfs_connector_remove(connector); |
572 | drm_connector_cleanup(connector); | |
674e2d08 | 573 | kfree(connector); |
7d57382e EA |
574 | } |
575 | ||
576 | static const struct drm_encoder_helper_funcs intel_hdmi_helper_funcs = { | |
577 | .dpms = intel_hdmi_dpms, | |
578 | .mode_fixup = intel_hdmi_mode_fixup, | |
579 | .prepare = intel_encoder_prepare, | |
580 | .mode_set = intel_hdmi_mode_set, | |
581 | .commit = intel_encoder_commit, | |
582 | }; | |
583 | ||
584 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { | |
c9fb15f6 | 585 | .dpms = drm_helper_connector_dpms, |
7d57382e EA |
586 | .detect = intel_hdmi_detect, |
587 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 588 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
589 | .destroy = intel_hdmi_destroy, |
590 | }; | |
591 | ||
592 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
593 | .get_modes = intel_hdmi_get_modes, | |
594 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 595 | .best_encoder = intel_best_encoder, |
7d57382e EA |
596 | }; |
597 | ||
7d57382e | 598 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 599 | .destroy = intel_encoder_destroy, |
7d57382e EA |
600 | }; |
601 | ||
55b7d6e8 CW |
602 | static void |
603 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
604 | { | |
3f43c48d | 605 | intel_attach_force_audio_property(connector); |
e953fd7b | 606 | intel_attach_broadcast_rgb_property(connector); |
55b7d6e8 CW |
607 | } |
608 | ||
7d57382e EA |
609 | void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) |
610 | { | |
611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
612 | struct drm_connector *connector; | |
21d40d37 | 613 | struct intel_encoder *intel_encoder; |
674e2d08 | 614 | struct intel_connector *intel_connector; |
ea5b213a | 615 | struct intel_hdmi *intel_hdmi; |
64a8fc01 | 616 | int i; |
7d57382e | 617 | |
ea5b213a CW |
618 | intel_hdmi = kzalloc(sizeof(struct intel_hdmi), GFP_KERNEL); |
619 | if (!intel_hdmi) | |
7d57382e | 620 | return; |
674e2d08 ZW |
621 | |
622 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); | |
623 | if (!intel_connector) { | |
ea5b213a | 624 | kfree(intel_hdmi); |
674e2d08 ZW |
625 | return; |
626 | } | |
627 | ||
ea5b213a | 628 | intel_encoder = &intel_hdmi->base; |
373a3cf7 CW |
629 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, |
630 | DRM_MODE_ENCODER_TMDS); | |
631 | ||
674e2d08 | 632 | connector = &intel_connector->base; |
7d57382e | 633 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 634 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
635 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
636 | ||
21d40d37 | 637 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
7d57382e | 638 | |
eb1f8e4f | 639 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
c3febcc4 | 640 | connector->interlace_allowed = 1; |
7d57382e | 641 | connector->doublescan_allowed = 0; |
27f8227b | 642 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
7d57382e EA |
643 | |
644 | /* Set up the DDC bus. */ | |
f8aed700 | 645 | if (sdvox_reg == SDVOB) { |
21d40d37 | 646 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); |
f899fc64 | 647 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 648 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 649 | } else if (sdvox_reg == SDVOC) { |
21d40d37 | 650 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); |
f899fc64 | 651 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 652 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 653 | } else if (sdvox_reg == HDMIB) { |
21d40d37 | 654 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); |
f899fc64 | 655 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
b01f2c3a | 656 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; |
f8aed700 | 657 | } else if (sdvox_reg == HDMIC) { |
21d40d37 | 658 | intel_encoder->clone_mask = (1 << INTEL_HDMIE_CLONE_BIT); |
f899fc64 | 659 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
b01f2c3a | 660 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; |
f8aed700 | 661 | } else if (sdvox_reg == HDMID) { |
21d40d37 | 662 | intel_encoder->clone_mask = (1 << INTEL_HDMIF_CLONE_BIT); |
f899fc64 | 663 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; |
b01f2c3a | 664 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; |
7ceae0a5 ED |
665 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_B)) { |
666 | DRM_DEBUG_DRIVER("LPT: detected output on DDI B\n"); | |
667 | intel_encoder->clone_mask = (1 << INTEL_HDMIB_CLONE_BIT); | |
668 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; | |
669 | intel_hdmi->ddi_port = PORT_B; | |
670 | dev_priv->hotplug_supported_mask |= HDMIB_HOTPLUG_INT_STATUS; | |
671 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_C)) { | |
672 | DRM_DEBUG_DRIVER("LPT: detected output on DDI C\n"); | |
673 | intel_encoder->clone_mask = (1 << INTEL_HDMIC_CLONE_BIT); | |
674 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; | |
675 | intel_hdmi->ddi_port = PORT_C; | |
676 | dev_priv->hotplug_supported_mask |= HDMIC_HOTPLUG_INT_STATUS; | |
677 | } else if (sdvox_reg == DDI_BUF_CTL(PORT_D)) { | |
678 | DRM_DEBUG_DRIVER("LPT: detected output on DDI D\n"); | |
679 | intel_encoder->clone_mask = (1 << INTEL_HDMID_CLONE_BIT); | |
680 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
681 | intel_hdmi->ddi_port = PORT_D; | |
682 | dev_priv->hotplug_supported_mask |= HDMID_HOTPLUG_INT_STATUS; | |
6e4c1677 ED |
683 | } else { |
684 | /* If we got an unknown sdvox_reg, things are pretty much broken | |
685 | * in a way that we should let the kernel know about it */ | |
686 | BUG(); | |
f8aed700 | 687 | } |
7d57382e | 688 | |
ea5b213a | 689 | intel_hdmi->sdvox_reg = sdvox_reg; |
7d57382e | 690 | |
64a8fc01 | 691 | if (!HAS_PCH_SPLIT(dev)) { |
a3da1df7 | 692 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
64a8fc01 | 693 | I915_WRITE(VIDEO_DIP_CTL, 0); |
90b107c8 SK |
694 | } else if (IS_VALLEYVIEW(dev)) { |
695 | intel_hdmi->write_infoframe = vlv_write_infoframe; | |
696 | for_each_pipe(i) | |
697 | I915_WRITE(VLV_TVIDEO_DIP_CTL(i), 0); | |
8c5f5f7c ED |
698 | } else if (IS_HASWELL(dev)) { |
699 | /* FIXME: Haswell has a new set of DIP frame registers, but we are | |
700 | * just doing the minimal required for HDMI to work at this stage. | |
701 | */ | |
702 | intel_hdmi->write_infoframe = hsw_write_infoframe; | |
703 | for_each_pipe(i) | |
704 | I915_WRITE(HSW_TVIDEO_DIP_CTL(i), 0); | |
fdf1250a PZ |
705 | } else if (HAS_PCH_IBX(dev)) { |
706 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
707 | for_each_pipe(i) | |
708 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
709 | } else { | |
710 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
64a8fc01 JB |
711 | for_each_pipe(i) |
712 | I915_WRITE(TVIDEO_DIP_CTL(i), 0); | |
713 | } | |
45187ace | 714 | |
4ef69c7a | 715 | drm_encoder_helper_add(&intel_encoder->base, &intel_hdmi_helper_funcs); |
7d57382e | 716 | |
55b7d6e8 CW |
717 | intel_hdmi_add_properties(intel_hdmi, connector); |
718 | ||
df0e9248 | 719 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
7d57382e EA |
720 | drm_sysfs_connector_add(connector); |
721 | ||
722 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
723 | * 0xd. Failure to do so will result in spurious interrupts being | |
724 | * generated on the port when a cable is not attached. | |
725 | */ | |
726 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
727 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
728 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
729 | } | |
7d57382e | 730 | } |