Commit | Line | Data |
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7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 | 33 | #include <drm/drmP.h> |
c6f95f27 | 34 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
35 | #include <drm/drm_crtc.h> |
36 | #include <drm/drm_edid.h> | |
2320175f | 37 | #include <drm/drm_hdcp.h> |
15953637 | 38 | #include <drm/drm_scdc_helper.h> |
7d57382e | 39 | #include "intel_drv.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
46d196ec | 41 | #include <drm/intel_lpe_audio.h> |
7d57382e EA |
42 | #include "i915_drv.h" |
43 | ||
30add22d PZ |
44 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
45 | { | |
da63a9f2 | 46 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
47 | } |
48 | ||
afba0188 DV |
49 | static void |
50 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
51 | { | |
30add22d | 52 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
fac5e23e | 53 | struct drm_i915_private *dev_priv = to_i915(dev); |
afba0188 DV |
54 | uint32_t enabled_bits; |
55 | ||
4f8036a2 | 56 | enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 57 | |
b242b7f7 | 58 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
59 | "HDMI port enabled, expecting disabled\n"); |
60 | } | |
61 | ||
f5bbfca3 | 62 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 63 | { |
da63a9f2 PZ |
64 | struct intel_digital_port *intel_dig_port = |
65 | container_of(encoder, struct intel_digital_port, base.base); | |
66 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
67 | } |
68 | ||
df0e9248 CW |
69 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
70 | { | |
da63a9f2 | 71 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
72 | } |
73 | ||
1d776538 | 74 | static u32 g4x_infoframe_index(unsigned int type) |
3c17fe4b | 75 | { |
178f736a DL |
76 | switch (type) { |
77 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 78 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 79 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 80 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
81 | case HDMI_INFOFRAME_TYPE_VENDOR: |
82 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 83 | default: |
ffc85dab | 84 | MISSING_CASE(type); |
ed517fbb | 85 | return 0; |
45187ace | 86 | } |
45187ace JB |
87 | } |
88 | ||
1d776538 | 89 | static u32 g4x_infoframe_enable(unsigned int type) |
45187ace | 90 | { |
178f736a DL |
91 | switch (type) { |
92 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 93 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 94 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 95 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
96 | case HDMI_INFOFRAME_TYPE_VENDOR: |
97 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 98 | default: |
ffc85dab | 99 | MISSING_CASE(type); |
ed517fbb | 100 | return 0; |
fa193ff7 | 101 | } |
fa193ff7 PZ |
102 | } |
103 | ||
1d776538 | 104 | static u32 hsw_infoframe_enable(unsigned int type) |
2da8af54 | 105 | { |
178f736a | 106 | switch (type) { |
1d776538 VS |
107 | case DP_SDP_VSC: |
108 | return VIDEO_DIP_ENABLE_VSC_HSW; | |
178f736a | 109 | case HDMI_INFOFRAME_TYPE_AVI: |
2da8af54 | 110 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 111 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 112 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
113 | case HDMI_INFOFRAME_TYPE_VENDOR: |
114 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 115 | default: |
ffc85dab | 116 | MISSING_CASE(type); |
2da8af54 PZ |
117 | return 0; |
118 | } | |
119 | } | |
120 | ||
f0f59a00 VS |
121 | static i915_reg_t |
122 | hsw_dip_data_reg(struct drm_i915_private *dev_priv, | |
123 | enum transcoder cpu_transcoder, | |
1d776538 | 124 | unsigned int type, |
f0f59a00 | 125 | int i) |
2da8af54 | 126 | { |
178f736a | 127 | switch (type) { |
1d776538 VS |
128 | case DP_SDP_VSC: |
129 | return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); | |
178f736a | 130 | case HDMI_INFOFRAME_TYPE_AVI: |
436c6d4a | 131 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); |
178f736a | 132 | case HDMI_INFOFRAME_TYPE_SPD: |
436c6d4a | 133 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); |
c8bb75af | 134 | case HDMI_INFOFRAME_TYPE_VENDOR: |
436c6d4a | 135 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); |
2da8af54 | 136 | default: |
ffc85dab | 137 | MISSING_CASE(type); |
f0f59a00 | 138 | return INVALID_MMIO_REG; |
2da8af54 PZ |
139 | } |
140 | } | |
141 | ||
a3da1df7 | 142 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 143 | const struct intel_crtc_state *crtc_state, |
1d776538 | 144 | unsigned int type, |
fff63867 | 145 | const void *frame, ssize_t len) |
45187ace | 146 | { |
fff63867 | 147 | const uint32_t *data = frame; |
3c17fe4b | 148 | struct drm_device *dev = encoder->dev; |
fac5e23e | 149 | struct drm_i915_private *dev_priv = to_i915(dev); |
22509ec8 | 150 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 151 | int i; |
3c17fe4b | 152 | |
822974ae PZ |
153 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
154 | ||
1d4f85ac | 155 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 156 | val |= g4x_infoframe_index(type); |
22509ec8 | 157 | |
178f736a | 158 | val &= ~g4x_infoframe_enable(type); |
45187ace | 159 | |
22509ec8 | 160 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 161 | |
9d9740f0 | 162 | mmiowb(); |
45187ace | 163 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
164 | I915_WRITE(VIDEO_DIP_DATA, *data); |
165 | data++; | |
166 | } | |
adf00b26 PZ |
167 | /* Write every possible data byte to force correct ECC calculation. */ |
168 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
169 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 170 | mmiowb(); |
3c17fe4b | 171 | |
178f736a | 172 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 173 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 174 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 175 | |
22509ec8 | 176 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 177 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
178 | } |
179 | ||
cda0aaaf VS |
180 | static bool g4x_infoframe_enabled(struct drm_encoder *encoder, |
181 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 182 | { |
cda0aaaf | 183 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
89a35ecd | 184 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
e43823ec JB |
185 | u32 val = I915_READ(VIDEO_DIP_CTL); |
186 | ||
ec1dc603 VS |
187 | if ((val & VIDEO_DIP_ENABLE) == 0) |
188 | return false; | |
89a35ecd | 189 | |
8f4f2797 | 190 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) |
ec1dc603 VS |
191 | return false; |
192 | ||
193 | return val & (VIDEO_DIP_ENABLE_AVI | | |
194 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
e43823ec JB |
195 | } |
196 | ||
fdf1250a | 197 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 198 | const struct intel_crtc_state *crtc_state, |
1d776538 | 199 | unsigned int type, |
fff63867 | 200 | const void *frame, ssize_t len) |
fdf1250a | 201 | { |
fff63867 | 202 | const uint32_t *data = frame; |
fdf1250a | 203 | struct drm_device *dev = encoder->dev; |
fac5e23e | 204 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 205 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 206 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a | 207 | u32 val = I915_READ(reg); |
f0f59a00 | 208 | int i; |
fdf1250a | 209 | |
822974ae PZ |
210 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
211 | ||
fdf1250a | 212 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 213 | val |= g4x_infoframe_index(type); |
fdf1250a | 214 | |
178f736a | 215 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
216 | |
217 | I915_WRITE(reg, val); | |
218 | ||
9d9740f0 | 219 | mmiowb(); |
fdf1250a PZ |
220 | for (i = 0; i < len; i += 4) { |
221 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
222 | data++; | |
223 | } | |
adf00b26 PZ |
224 | /* Write every possible data byte to force correct ECC calculation. */ |
225 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
226 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 227 | mmiowb(); |
fdf1250a | 228 | |
178f736a | 229 | val |= g4x_infoframe_enable(type); |
fdf1250a | 230 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 231 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
232 | |
233 | I915_WRITE(reg, val); | |
9d9740f0 | 234 | POSTING_READ(reg); |
fdf1250a PZ |
235 | } |
236 | ||
cda0aaaf VS |
237 | static bool ibx_infoframe_enabled(struct drm_encoder *encoder, |
238 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 239 | { |
cda0aaaf | 240 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
052f62f7 | 241 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
242 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
243 | i915_reg_t reg = TVIDEO_DIP_CTL(pipe); | |
e43823ec JB |
244 | u32 val = I915_READ(reg); |
245 | ||
ec1dc603 VS |
246 | if ((val & VIDEO_DIP_ENABLE) == 0) |
247 | return false; | |
248 | ||
8f4f2797 | 249 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) |
ec1dc603 | 250 | return false; |
052f62f7 | 251 | |
ec1dc603 VS |
252 | return val & (VIDEO_DIP_ENABLE_AVI | |
253 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
254 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
255 | } |
256 | ||
fdf1250a | 257 | static void cpt_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 258 | const struct intel_crtc_state *crtc_state, |
1d776538 | 259 | unsigned int type, |
fff63867 | 260 | const void *frame, ssize_t len) |
b055c8f3 | 261 | { |
fff63867 | 262 | const uint32_t *data = frame; |
b055c8f3 | 263 | struct drm_device *dev = encoder->dev; |
fac5e23e | 264 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 265 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 266 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 267 | u32 val = I915_READ(reg); |
f0f59a00 | 268 | int i; |
b055c8f3 | 269 | |
822974ae PZ |
270 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
271 | ||
64a8fc01 | 272 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 273 | val |= g4x_infoframe_index(type); |
45187ace | 274 | |
ecb97851 PZ |
275 | /* The DIP control register spec says that we need to update the AVI |
276 | * infoframe without clearing its enable bit */ | |
178f736a DL |
277 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
278 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 279 | |
22509ec8 | 280 | I915_WRITE(reg, val); |
45187ace | 281 | |
9d9740f0 | 282 | mmiowb(); |
45187ace | 283 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
284 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
285 | data++; | |
286 | } | |
adf00b26 PZ |
287 | /* Write every possible data byte to force correct ECC calculation. */ |
288 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
289 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 290 | mmiowb(); |
b055c8f3 | 291 | |
178f736a | 292 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 293 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 294 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 295 | |
22509ec8 | 296 | I915_WRITE(reg, val); |
9d9740f0 | 297 | POSTING_READ(reg); |
45187ace | 298 | } |
90b107c8 | 299 | |
cda0aaaf VS |
300 | static bool cpt_infoframe_enabled(struct drm_encoder *encoder, |
301 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 302 | { |
cda0aaaf VS |
303 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
304 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; | |
305 | u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 306 | |
ec1dc603 VS |
307 | if ((val & VIDEO_DIP_ENABLE) == 0) |
308 | return false; | |
309 | ||
310 | return val & (VIDEO_DIP_ENABLE_AVI | | |
311 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
312 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
313 | } |
314 | ||
90b107c8 | 315 | static void vlv_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 316 | const struct intel_crtc_state *crtc_state, |
1d776538 | 317 | unsigned int type, |
fff63867 | 318 | const void *frame, ssize_t len) |
90b107c8 | 319 | { |
fff63867 | 320 | const uint32_t *data = frame; |
90b107c8 | 321 | struct drm_device *dev = encoder->dev; |
fac5e23e | 322 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 323 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 | 324 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 325 | u32 val = I915_READ(reg); |
f0f59a00 | 326 | int i; |
90b107c8 | 327 | |
822974ae PZ |
328 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
329 | ||
90b107c8 | 330 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 331 | val |= g4x_infoframe_index(type); |
22509ec8 | 332 | |
178f736a | 333 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 334 | |
22509ec8 | 335 | I915_WRITE(reg, val); |
90b107c8 | 336 | |
9d9740f0 | 337 | mmiowb(); |
90b107c8 SK |
338 | for (i = 0; i < len; i += 4) { |
339 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
340 | data++; | |
341 | } | |
adf00b26 PZ |
342 | /* Write every possible data byte to force correct ECC calculation. */ |
343 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
344 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 345 | mmiowb(); |
90b107c8 | 346 | |
178f736a | 347 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 348 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 349 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 350 | |
22509ec8 | 351 | I915_WRITE(reg, val); |
9d9740f0 | 352 | POSTING_READ(reg); |
90b107c8 SK |
353 | } |
354 | ||
cda0aaaf VS |
355 | static bool vlv_infoframe_enabled(struct drm_encoder *encoder, |
356 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 357 | { |
cda0aaaf | 358 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
535afa2e | 359 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
cda0aaaf VS |
360 | enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe; |
361 | u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); | |
e43823ec | 362 | |
ec1dc603 VS |
363 | if ((val & VIDEO_DIP_ENABLE) == 0) |
364 | return false; | |
365 | ||
8f4f2797 | 366 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) |
ec1dc603 | 367 | return false; |
535afa2e | 368 | |
ec1dc603 VS |
369 | return val & (VIDEO_DIP_ENABLE_AVI | |
370 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
371 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
e43823ec JB |
372 | } |
373 | ||
8c5f5f7c | 374 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 375 | const struct intel_crtc_state *crtc_state, |
1d776538 | 376 | unsigned int type, |
fff63867 | 377 | const void *frame, ssize_t len) |
8c5f5f7c | 378 | { |
fff63867 | 379 | const uint32_t *data = frame; |
2da8af54 | 380 | struct drm_device *dev = encoder->dev; |
fac5e23e | 381 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 382 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
f0f59a00 VS |
383 | i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); |
384 | i915_reg_t data_reg; | |
1d776538 VS |
385 | int data_size = type == DP_SDP_VSC ? |
386 | VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE; | |
178f736a | 387 | int i; |
2da8af54 | 388 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 389 | |
436c6d4a | 390 | data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0); |
2da8af54 | 391 | |
178f736a | 392 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
393 | I915_WRITE(ctl_reg, val); |
394 | ||
9d9740f0 | 395 | mmiowb(); |
2da8af54 | 396 | for (i = 0; i < len; i += 4) { |
436c6d4a VS |
397 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
398 | type, i >> 2), *data); | |
2da8af54 PZ |
399 | data++; |
400 | } | |
adf00b26 | 401 | /* Write every possible data byte to force correct ECC calculation. */ |
1d776538 | 402 | for (; i < data_size; i += 4) |
436c6d4a VS |
403 | I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, |
404 | type, i >> 2), 0); | |
9d9740f0 | 405 | mmiowb(); |
8c5f5f7c | 406 | |
178f736a | 407 | val |= hsw_infoframe_enable(type); |
2da8af54 | 408 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 409 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
410 | } |
411 | ||
cda0aaaf VS |
412 | static bool hsw_infoframe_enabled(struct drm_encoder *encoder, |
413 | const struct intel_crtc_state *pipe_config) | |
e43823ec | 414 | { |
cda0aaaf VS |
415 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
416 | u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); | |
e43823ec | 417 | |
ec1dc603 VS |
418 | return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
419 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
420 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
e43823ec JB |
421 | } |
422 | ||
5adaea79 DL |
423 | /* |
424 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
425 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
426 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
427 | * used for both technologies. | |
428 | * | |
429 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
430 | * DW1: DB3 | DB2 | DB1 | DB0 | |
431 | * DW2: DB7 | DB6 | DB5 | DB4 | |
432 | * DW3: ... | |
433 | * | |
434 | * (HB is Header Byte, DB is Data Byte) | |
435 | * | |
436 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
437 | * trick them by giving an offset into the buffer and moving back the header | |
438 | * bytes by one. | |
439 | */ | |
9198ee5b | 440 | static void intel_write_infoframe(struct drm_encoder *encoder, |
ac240288 | 441 | const struct intel_crtc_state *crtc_state, |
9198ee5b | 442 | union hdmi_infoframe *frame) |
45187ace | 443 | { |
f99be1b3 | 444 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
5adaea79 DL |
445 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
446 | ssize_t len; | |
45187ace | 447 | |
5adaea79 DL |
448 | /* see comment above for the reason for this offset */ |
449 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
450 | if (len < 0) | |
451 | return; | |
452 | ||
453 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
454 | buffer[0] = buffer[1]; | |
455 | buffer[1] = buffer[2]; | |
456 | buffer[2] = buffer[3]; | |
457 | buffer[3] = 0; | |
458 | len++; | |
45187ace | 459 | |
f99be1b3 | 460 | intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len); |
45187ace JB |
461 | } |
462 | ||
687f4d06 | 463 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
ac240288 | 464 | const struct intel_crtc_state *crtc_state) |
45187ace | 465 | { |
abedc077 | 466 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
779c4c28 VS |
467 | const struct drm_display_mode *adjusted_mode = |
468 | &crtc_state->base.adjusted_mode; | |
0c1f528c SS |
469 | struct drm_connector *connector = &intel_hdmi->attached_connector->base; |
470 | bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported; | |
5adaea79 DL |
471 | union hdmi_infoframe frame; |
472 | int ret; | |
45187ace | 473 | |
5adaea79 | 474 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
0c1f528c SS |
475 | adjusted_mode, |
476 | is_hdmi2_sink); | |
5adaea79 DL |
477 | if (ret < 0) { |
478 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
479 | return; | |
480 | } | |
c846b619 | 481 | |
2d8bd2bf SS |
482 | if (crtc_state->ycbcr420) |
483 | frame.avi.colorspace = HDMI_COLORSPACE_YUV420; | |
484 | else | |
485 | frame.avi.colorspace = HDMI_COLORSPACE_RGB; | |
486 | ||
779c4c28 | 487 | drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode, |
a2ce26f8 VS |
488 | crtc_state->limited_color_range ? |
489 | HDMI_QUANTIZATION_RANGE_LIMITED : | |
490 | HDMI_QUANTIZATION_RANGE_FULL, | |
9271c0ca VS |
491 | intel_hdmi->rgb_quant_range_selectable, |
492 | is_hdmi2_sink); | |
abedc077 | 493 | |
2d8bd2bf | 494 | /* TODO: handle pixel repetition for YCBCR420 outputs */ |
ac240288 | 495 | intel_write_infoframe(encoder, crtc_state, &frame); |
b055c8f3 JB |
496 | } |
497 | ||
ac240288 ML |
498 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder, |
499 | const struct intel_crtc_state *crtc_state) | |
c0864cb3 | 500 | { |
5adaea79 DL |
501 | union hdmi_infoframe frame; |
502 | int ret; | |
503 | ||
504 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
505 | if (ret < 0) { | |
506 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
507 | return; | |
508 | } | |
c0864cb3 | 509 | |
5adaea79 | 510 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 511 | |
ac240288 | 512 | intel_write_infoframe(encoder, crtc_state, &frame); |
c0864cb3 JB |
513 | } |
514 | ||
c8bb75af LD |
515 | static void |
516 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
f1781e9b VS |
517 | const struct intel_crtc_state *crtc_state, |
518 | const struct drm_connector_state *conn_state) | |
c8bb75af LD |
519 | { |
520 | union hdmi_infoframe frame; | |
521 | int ret; | |
522 | ||
523 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
f1781e9b | 524 | conn_state->connector, |
ac240288 | 525 | &crtc_state->base.adjusted_mode); |
c8bb75af LD |
526 | if (ret < 0) |
527 | return; | |
528 | ||
ac240288 | 529 | intel_write_infoframe(encoder, crtc_state, &frame); |
c8bb75af LD |
530 | } |
531 | ||
687f4d06 | 532 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 533 | bool enable, |
ac240288 ML |
534 | const struct intel_crtc_state *crtc_state, |
535 | const struct drm_connector_state *conn_state) | |
687f4d06 | 536 | { |
fac5e23e | 537 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
69fde0a6 VS |
538 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
539 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 540 | i915_reg_t reg = VIDEO_DIP_CTL; |
0c14c7f9 | 541 | u32 val = I915_READ(reg); |
8f4f2797 | 542 | u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port); |
0c14c7f9 | 543 | |
afba0188 DV |
544 | assert_hdmi_port_disabled(intel_hdmi); |
545 | ||
0c14c7f9 PZ |
546 | /* If the registers were not initialized yet, they might be zeroes, |
547 | * which means we're selecting the AVI DIP and we're setting its | |
548 | * frequency to once. This seems to really confuse the HW and make | |
549 | * things stop working (the register spec says the AVI always needs to | |
550 | * be sent every VSync). So here we avoid writing to the register more | |
551 | * than we need and also explicitly select the AVI DIP and explicitly | |
552 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
553 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
554 | * either. */ | |
555 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
556 | ||
6897b4b5 | 557 | if (!enable) { |
0c14c7f9 PZ |
558 | if (!(val & VIDEO_DIP_ENABLE)) |
559 | return; | |
0be6f0c8 VS |
560 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
561 | DRM_DEBUG_KMS("video DIP still enabled on port %c\n", | |
562 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
563 | return; | |
564 | } | |
565 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | | |
566 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
0c14c7f9 | 567 | I915_WRITE(reg, val); |
9d9740f0 | 568 | POSTING_READ(reg); |
0c14c7f9 PZ |
569 | return; |
570 | } | |
571 | ||
72b78c9d PZ |
572 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
573 | if (val & VIDEO_DIP_ENABLE) { | |
0be6f0c8 VS |
574 | DRM_DEBUG_KMS("video DIP already enabled on port %c\n", |
575 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
576 | return; | |
72b78c9d PZ |
577 | } |
578 | val &= ~VIDEO_DIP_PORT_MASK; | |
579 | val |= port; | |
580 | } | |
581 | ||
822974ae | 582 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
583 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
584 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD); | |
822974ae | 585 | |
f278d972 | 586 | I915_WRITE(reg, val); |
9d9740f0 | 587 | POSTING_READ(reg); |
f278d972 | 588 | |
ac240288 ML |
589 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
590 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
f1781e9b | 591 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
592 | } |
593 | ||
ac240288 | 594 | static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state) |
6d67415f | 595 | { |
ac240288 | 596 | struct drm_connector *connector = conn_state->connector; |
6d67415f VS |
597 | |
598 | /* | |
599 | * HDMI cloning is only supported on g4x which doesn't | |
600 | * support deep color or GCP infoframes anyway so no | |
601 | * need to worry about multiple HDMI sinks here. | |
602 | */ | |
6d67415f | 603 | |
ac240288 | 604 | return connector->display_info.bpc > 8; |
6d67415f VS |
605 | } |
606 | ||
12aa3290 VS |
607 | /* |
608 | * Determine if default_phase=1 can be indicated in the GCP infoframe. | |
609 | * | |
610 | * From HDMI specification 1.4a: | |
611 | * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0 | |
612 | * - The first pixel following each Video Data Period shall have a pixel packing phase of 0 | |
613 | * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase | |
614 | * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing | |
615 | * phase of 0 | |
616 | */ | |
617 | static bool gcp_default_phase_possible(int pipe_bpp, | |
618 | const struct drm_display_mode *mode) | |
619 | { | |
620 | unsigned int pixels_per_group; | |
621 | ||
622 | switch (pipe_bpp) { | |
623 | case 30: | |
624 | /* 4 pixels in 5 clocks */ | |
625 | pixels_per_group = 4; | |
626 | break; | |
627 | case 36: | |
628 | /* 2 pixels in 3 clocks */ | |
629 | pixels_per_group = 2; | |
630 | break; | |
631 | case 48: | |
632 | /* 1 pixel in 2 clocks */ | |
633 | pixels_per_group = 1; | |
634 | break; | |
635 | default: | |
636 | /* phase information not relevant for 8bpc */ | |
637 | return false; | |
638 | } | |
639 | ||
640 | return mode->crtc_hdisplay % pixels_per_group == 0 && | |
641 | mode->crtc_htotal % pixels_per_group == 0 && | |
642 | mode->crtc_hblank_start % pixels_per_group == 0 && | |
643 | mode->crtc_hblank_end % pixels_per_group == 0 && | |
644 | mode->crtc_hsync_start % pixels_per_group == 0 && | |
645 | mode->crtc_hsync_end % pixels_per_group == 0 && | |
646 | ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || | |
647 | mode->crtc_htotal/2 % pixels_per_group == 0); | |
648 | } | |
649 | ||
ac240288 ML |
650 | static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder, |
651 | const struct intel_crtc_state *crtc_state, | |
652 | const struct drm_connector_state *conn_state) | |
6d67415f | 653 | { |
fac5e23e | 654 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 655 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f0f59a00 VS |
656 | i915_reg_t reg; |
657 | u32 val = 0; | |
6d67415f VS |
658 | |
659 | if (HAS_DDI(dev_priv)) | |
ac240288 | 660 | reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); |
666a4537 | 661 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6d67415f | 662 | reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); |
2d1fe073 | 663 | else if (HAS_PCH_SPLIT(dev_priv)) |
6d67415f VS |
664 | reg = TVIDEO_DIP_GCP(crtc->pipe); |
665 | else | |
666 | return false; | |
667 | ||
668 | /* Indicate color depth whenever the sink supports deep color */ | |
ac240288 | 669 | if (hdmi_sink_is_deep_color(conn_state)) |
6d67415f VS |
670 | val |= GCP_COLOR_INDICATION; |
671 | ||
12aa3290 | 672 | /* Enable default_phase whenever the display mode is suitably aligned */ |
ac240288 ML |
673 | if (gcp_default_phase_possible(crtc_state->pipe_bpp, |
674 | &crtc_state->base.adjusted_mode)) | |
12aa3290 VS |
675 | val |= GCP_DEFAULT_PHASE_ENABLE; |
676 | ||
6d67415f VS |
677 | I915_WRITE(reg, val); |
678 | ||
679 | return val != 0; | |
680 | } | |
681 | ||
687f4d06 | 682 | static void ibx_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 683 | bool enable, |
ac240288 ML |
684 | const struct intel_crtc_state *crtc_state, |
685 | const struct drm_connector_state *conn_state) | |
687f4d06 | 686 | { |
fac5e23e | 687 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 688 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
69fde0a6 VS |
689 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
690 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
f0f59a00 | 691 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 692 | u32 val = I915_READ(reg); |
8f4f2797 | 693 | u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port); |
0c14c7f9 | 694 | |
afba0188 DV |
695 | assert_hdmi_port_disabled(intel_hdmi); |
696 | ||
0c14c7f9 PZ |
697 | /* See the big comment in g4x_set_infoframes() */ |
698 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
699 | ||
6897b4b5 | 700 | if (!enable) { |
0c14c7f9 PZ |
701 | if (!(val & VIDEO_DIP_ENABLE)) |
702 | return; | |
0be6f0c8 VS |
703 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
704 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
705 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 706 | I915_WRITE(reg, val); |
9d9740f0 | 707 | POSTING_READ(reg); |
0c14c7f9 PZ |
708 | return; |
709 | } | |
710 | ||
72b78c9d | 711 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
712 | WARN(val & VIDEO_DIP_ENABLE, |
713 | "DIP already enabled on port %c\n", | |
714 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
72b78c9d PZ |
715 | val &= ~VIDEO_DIP_PORT_MASK; |
716 | val |= port; | |
717 | } | |
718 | ||
822974ae | 719 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
720 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
721 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
722 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 723 | |
ac240288 | 724 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
725 | val |= VIDEO_DIP_ENABLE_GCP; |
726 | ||
f278d972 | 727 | I915_WRITE(reg, val); |
9d9740f0 | 728 | POSTING_READ(reg); |
f278d972 | 729 | |
ac240288 ML |
730 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
731 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
f1781e9b | 732 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
733 | } |
734 | ||
735 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 736 | bool enable, |
ac240288 ML |
737 | const struct intel_crtc_state *crtc_state, |
738 | const struct drm_connector_state *conn_state) | |
687f4d06 | 739 | { |
fac5e23e | 740 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
ac240288 | 741 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 742 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 743 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 PZ |
744 | u32 val = I915_READ(reg); |
745 | ||
afba0188 DV |
746 | assert_hdmi_port_disabled(intel_hdmi); |
747 | ||
0c14c7f9 PZ |
748 | /* See the big comment in g4x_set_infoframes() */ |
749 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
750 | ||
6897b4b5 | 751 | if (!enable) { |
0c14c7f9 PZ |
752 | if (!(val & VIDEO_DIP_ENABLE)) |
753 | return; | |
0be6f0c8 VS |
754 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
755 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
756 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 757 | I915_WRITE(reg, val); |
9d9740f0 | 758 | POSTING_READ(reg); |
0c14c7f9 PZ |
759 | return; |
760 | } | |
761 | ||
822974ae PZ |
762 | /* Set both together, unset both together: see the spec. */ |
763 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 | 764 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
0be6f0c8 | 765 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); |
822974ae | 766 | |
ac240288 | 767 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
768 | val |= VIDEO_DIP_ENABLE_GCP; |
769 | ||
822974ae | 770 | I915_WRITE(reg, val); |
9d9740f0 | 771 | POSTING_READ(reg); |
822974ae | 772 | |
ac240288 ML |
773 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
774 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
f1781e9b | 775 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
776 | } |
777 | ||
778 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 779 | bool enable, |
ac240288 ML |
780 | const struct intel_crtc_state *crtc_state, |
781 | const struct drm_connector_state *conn_state) | |
687f4d06 | 782 | { |
fac5e23e | 783 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
6a2b8021 | 784 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
ac240288 | 785 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
0c14c7f9 | 786 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
f0f59a00 | 787 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
0c14c7f9 | 788 | u32 val = I915_READ(reg); |
8f4f2797 | 789 | u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port); |
0c14c7f9 | 790 | |
afba0188 DV |
791 | assert_hdmi_port_disabled(intel_hdmi); |
792 | ||
0c14c7f9 PZ |
793 | /* See the big comment in g4x_set_infoframes() */ |
794 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
795 | ||
6897b4b5 | 796 | if (!enable) { |
0c14c7f9 PZ |
797 | if (!(val & VIDEO_DIP_ENABLE)) |
798 | return; | |
0be6f0c8 VS |
799 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI | |
800 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
801 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
0c14c7f9 | 802 | I915_WRITE(reg, val); |
9d9740f0 | 803 | POSTING_READ(reg); |
0c14c7f9 PZ |
804 | return; |
805 | } | |
806 | ||
6a2b8021 | 807 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
0be6f0c8 VS |
808 | WARN(val & VIDEO_DIP_ENABLE, |
809 | "DIP already enabled on port %c\n", | |
810 | (val & VIDEO_DIP_PORT_MASK) >> 29); | |
6a2b8021 JB |
811 | val &= ~VIDEO_DIP_PORT_MASK; |
812 | val |= port; | |
813 | } | |
814 | ||
822974ae | 815 | val |= VIDEO_DIP_ENABLE; |
0be6f0c8 VS |
816 | val &= ~(VIDEO_DIP_ENABLE_AVI | |
817 | VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | | |
818 | VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 819 | |
ac240288 | 820 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
821 | val |= VIDEO_DIP_ENABLE_GCP; |
822 | ||
822974ae | 823 | I915_WRITE(reg, val); |
9d9740f0 | 824 | POSTING_READ(reg); |
822974ae | 825 | |
ac240288 ML |
826 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
827 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
f1781e9b | 828 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
829 | } |
830 | ||
831 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 832 | bool enable, |
ac240288 ML |
833 | const struct intel_crtc_state *crtc_state, |
834 | const struct drm_connector_state *conn_state) | |
687f4d06 | 835 | { |
fac5e23e | 836 | struct drm_i915_private *dev_priv = to_i915(encoder->dev); |
0c14c7f9 | 837 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
ac240288 | 838 | i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); |
0dd87d20 | 839 | u32 val = I915_READ(reg); |
0c14c7f9 | 840 | |
afba0188 DV |
841 | assert_hdmi_port_disabled(intel_hdmi); |
842 | ||
0be6f0c8 VS |
843 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | |
844 | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | | |
845 | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW); | |
846 | ||
6897b4b5 | 847 | if (!enable) { |
0be6f0c8 | 848 | I915_WRITE(reg, val); |
9d9740f0 | 849 | POSTING_READ(reg); |
0c14c7f9 PZ |
850 | return; |
851 | } | |
852 | ||
ac240288 | 853 | if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state)) |
6d67415f VS |
854 | val |= VIDEO_DIP_ENABLE_GCP_HSW; |
855 | ||
0dd87d20 | 856 | I915_WRITE(reg, val); |
9d9740f0 | 857 | POSTING_READ(reg); |
0dd87d20 | 858 | |
ac240288 ML |
859 | intel_hdmi_set_avi_infoframe(encoder, crtc_state); |
860 | intel_hdmi_set_spd_infoframe(encoder, crtc_state); | |
f1781e9b | 861 | intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state); |
687f4d06 PZ |
862 | } |
863 | ||
b2ccb822 VS |
864 | void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) |
865 | { | |
866 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); | |
867 | struct i2c_adapter *adapter = | |
868 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
869 | ||
870 | if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) | |
871 | return; | |
872 | ||
873 | DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n", | |
874 | enable ? "Enabling" : "Disabling"); | |
875 | ||
876 | drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type, | |
877 | adapter, enable); | |
878 | } | |
879 | ||
2320175f SP |
880 | static int intel_hdmi_hdcp_read(struct intel_digital_port *intel_dig_port, |
881 | unsigned int offset, void *buffer, size_t size) | |
882 | { | |
883 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
884 | struct drm_i915_private *dev_priv = | |
885 | intel_dig_port->base.base.dev->dev_private; | |
886 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
887 | hdmi->ddc_bus); | |
888 | int ret; | |
889 | u8 start = offset & 0xff; | |
890 | struct i2c_msg msgs[] = { | |
891 | { | |
892 | .addr = DRM_HDCP_DDC_ADDR, | |
893 | .flags = 0, | |
894 | .len = 1, | |
895 | .buf = &start, | |
896 | }, | |
897 | { | |
898 | .addr = DRM_HDCP_DDC_ADDR, | |
899 | .flags = I2C_M_RD, | |
900 | .len = size, | |
901 | .buf = buffer | |
902 | } | |
903 | }; | |
904 | ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs)); | |
905 | if (ret == ARRAY_SIZE(msgs)) | |
906 | return 0; | |
907 | return ret >= 0 ? -EIO : ret; | |
908 | } | |
909 | ||
910 | static int intel_hdmi_hdcp_write(struct intel_digital_port *intel_dig_port, | |
911 | unsigned int offset, void *buffer, size_t size) | |
912 | { | |
913 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
914 | struct drm_i915_private *dev_priv = | |
915 | intel_dig_port->base.base.dev->dev_private; | |
916 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
917 | hdmi->ddc_bus); | |
918 | int ret; | |
919 | u8 *write_buf; | |
920 | struct i2c_msg msg; | |
921 | ||
922 | write_buf = kzalloc(size + 1, GFP_KERNEL); | |
923 | if (!write_buf) | |
924 | return -ENOMEM; | |
925 | ||
926 | write_buf[0] = offset & 0xff; | |
927 | memcpy(&write_buf[1], buffer, size); | |
928 | ||
929 | msg.addr = DRM_HDCP_DDC_ADDR; | |
930 | msg.flags = 0, | |
931 | msg.len = size + 1, | |
932 | msg.buf = write_buf; | |
933 | ||
934 | ret = i2c_transfer(adapter, &msg, 1); | |
935 | if (ret == 1) | |
936 | return 0; | |
937 | return ret >= 0 ? -EIO : ret; | |
938 | } | |
939 | ||
940 | static | |
941 | int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, | |
942 | u8 *an) | |
943 | { | |
944 | struct intel_hdmi *hdmi = &intel_dig_port->hdmi; | |
945 | struct drm_i915_private *dev_priv = | |
946 | intel_dig_port->base.base.dev->dev_private; | |
947 | struct i2c_adapter *adapter = intel_gmbus_get_adapter(dev_priv, | |
948 | hdmi->ddc_bus); | |
949 | int ret; | |
950 | ||
951 | ret = intel_hdmi_hdcp_write(intel_dig_port, DRM_HDCP_DDC_AN, an, | |
952 | DRM_HDCP_AN_LEN); | |
953 | if (ret) { | |
954 | DRM_ERROR("Write An over DDC failed (%d)\n", ret); | |
955 | return ret; | |
956 | } | |
957 | ||
958 | ret = intel_gmbus_output_aksv(adapter); | |
959 | if (ret < 0) { | |
960 | DRM_ERROR("Failed to output aksv (%d)\n", ret); | |
961 | return ret; | |
962 | } | |
963 | return 0; | |
964 | } | |
965 | ||
966 | static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, | |
967 | u8 *bksv) | |
968 | { | |
969 | int ret; | |
970 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BKSV, bksv, | |
971 | DRM_HDCP_KSV_LEN); | |
972 | if (ret) | |
973 | DRM_ERROR("Read Bksv over DDC failed (%d)\n", ret); | |
974 | return ret; | |
975 | } | |
976 | ||
977 | static | |
978 | int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, | |
979 | u8 *bstatus) | |
980 | { | |
981 | int ret; | |
982 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BSTATUS, | |
983 | bstatus, DRM_HDCP_BSTATUS_LEN); | |
984 | if (ret) | |
985 | DRM_ERROR("Read bstatus over DDC failed (%d)\n", ret); | |
986 | return ret; | |
987 | } | |
988 | ||
989 | static | |
990 | int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, | |
991 | bool *repeater_present) | |
992 | { | |
993 | int ret; | |
994 | u8 val; | |
995 | ||
996 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
997 | if (ret) { | |
998 | DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret); | |
999 | return ret; | |
1000 | } | |
1001 | *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT; | |
1002 | return 0; | |
1003 | } | |
1004 | ||
1005 | static | |
1006 | int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, | |
1007 | u8 *ri_prime) | |
1008 | { | |
1009 | int ret; | |
1010 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_RI_PRIME, | |
1011 | ri_prime, DRM_HDCP_RI_LEN); | |
1012 | if (ret) | |
1013 | DRM_ERROR("Read Ri' over DDC failed (%d)\n", ret); | |
1014 | return ret; | |
1015 | } | |
1016 | ||
1017 | static | |
1018 | int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, | |
1019 | bool *ksv_ready) | |
1020 | { | |
1021 | int ret; | |
1022 | u8 val; | |
1023 | ||
1024 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_BCAPS, &val, 1); | |
1025 | if (ret) { | |
1026 | DRM_ERROR("Read bcaps over DDC failed (%d)\n", ret); | |
1027 | return ret; | |
1028 | } | |
1029 | *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY; | |
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | static | |
1034 | int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, | |
1035 | int num_downstream, u8 *ksv_fifo) | |
1036 | { | |
1037 | int ret; | |
1038 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_KSV_FIFO, | |
1039 | ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN); | |
1040 | if (ret) { | |
1041 | DRM_ERROR("Read ksv fifo over DDC failed (%d)\n", ret); | |
1042 | return ret; | |
1043 | } | |
1044 | return 0; | |
1045 | } | |
1046 | ||
1047 | static | |
1048 | int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, | |
1049 | int i, u32 *part) | |
1050 | { | |
1051 | int ret; | |
1052 | ||
1053 | if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) | |
1054 | return -EINVAL; | |
1055 | ||
1056 | ret = intel_hdmi_hdcp_read(intel_dig_port, DRM_HDCP_DDC_V_PRIME(i), | |
1057 | part, DRM_HDCP_V_PRIME_PART_LEN); | |
1058 | if (ret) | |
1059 | DRM_ERROR("Read V'[%d] over DDC failed (%d)\n", i, ret); | |
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | static | |
1064 | int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, | |
1065 | bool enable) | |
1066 | { | |
1067 | int ret; | |
1068 | ||
1069 | if (!enable) | |
1070 | usleep_range(6, 60); /* Bspec says >= 6us */ | |
1071 | ||
1072 | ret = intel_ddi_toggle_hdcp_signalling(&intel_dig_port->base, enable); | |
1073 | if (ret) { | |
1074 | DRM_ERROR("%s HDCP signalling failed (%d)\n", | |
1075 | enable ? "Enable" : "Disable", ret); | |
1076 | return ret; | |
1077 | } | |
1078 | return 0; | |
1079 | } | |
1080 | ||
1081 | static | |
1082 | bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) | |
1083 | { | |
1084 | struct drm_i915_private *dev_priv = | |
1085 | intel_dig_port->base.base.dev->dev_private; | |
1086 | enum port port = intel_dig_port->base.port; | |
1087 | int ret; | |
1088 | union { | |
1089 | u32 reg; | |
1090 | u8 shim[DRM_HDCP_RI_LEN]; | |
1091 | } ri; | |
1092 | ||
1093 | ret = intel_hdmi_hdcp_read_ri_prime(intel_dig_port, ri.shim); | |
1094 | if (ret) | |
1095 | return false; | |
1096 | ||
1097 | I915_WRITE(PORT_HDCP_RPRIME(port), ri.reg); | |
1098 | ||
1099 | /* Wait for Ri prime match */ | |
1100 | if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & | |
1101 | (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { | |
1102 | DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", | |
1103 | I915_READ(PORT_HDCP_STATUS(port))); | |
1104 | return false; | |
1105 | } | |
1106 | return true; | |
1107 | } | |
1108 | ||
1109 | static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = { | |
1110 | .write_an_aksv = intel_hdmi_hdcp_write_an_aksv, | |
1111 | .read_bksv = intel_hdmi_hdcp_read_bksv, | |
1112 | .read_bstatus = intel_hdmi_hdcp_read_bstatus, | |
1113 | .repeater_present = intel_hdmi_hdcp_repeater_present, | |
1114 | .read_ri_prime = intel_hdmi_hdcp_read_ri_prime, | |
1115 | .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready, | |
1116 | .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo, | |
1117 | .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part, | |
1118 | .toggle_signalling = intel_hdmi_hdcp_toggle_signalling, | |
1119 | .check_link = intel_hdmi_hdcp_check_link, | |
1120 | }; | |
1121 | ||
ac240288 ML |
1122 | static void intel_hdmi_prepare(struct intel_encoder *encoder, |
1123 | const struct intel_crtc_state *crtc_state) | |
7d57382e | 1124 | { |
c59423a3 | 1125 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1126 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1127 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
c59423a3 | 1128 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
ac240288 | 1129 | const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode; |
b242b7f7 | 1130 | u32 hdmi_val; |
7d57382e | 1131 | |
b2ccb822 VS |
1132 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, true); |
1133 | ||
b242b7f7 | 1134 | hdmi_val = SDVO_ENCODING_HDMI; |
ac240288 | 1135 | if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range) |
0f2a2a75 | 1136 | hdmi_val |= HDMI_COLOR_RANGE_16_235; |
b599c0bc | 1137 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 1138 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 1139 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 1140 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 1141 | |
ac240288 | 1142 | if (crtc_state->pipe_bpp > 24) |
4f3a8bc7 | 1143 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 1144 | else |
4f3a8bc7 | 1145 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 1146 | |
ac240288 | 1147 | if (crtc_state->has_hdmi_sink) |
dc0fa718 | 1148 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 1149 | |
6e266956 | 1150 | if (HAS_PCH_CPT(dev_priv)) |
c59423a3 | 1151 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
920a14b2 | 1152 | else if (IS_CHERRYVIEW(dev_priv)) |
44f37d1f | 1153 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); |
dc0fa718 | 1154 | else |
c59423a3 | 1155 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 1156 | |
b242b7f7 PZ |
1157 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
1158 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
1159 | } |
1160 | ||
85234cdc DV |
1161 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
1162 | enum pipe *pipe) | |
7d57382e | 1163 | { |
85234cdc | 1164 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1165 | struct drm_i915_private *dev_priv = to_i915(dev); |
85234cdc DV |
1166 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1167 | u32 tmp; | |
5b092174 | 1168 | bool ret; |
85234cdc | 1169 | |
79f255a0 ACO |
1170 | if (!intel_display_power_get_if_enabled(dev_priv, |
1171 | encoder->power_domain)) | |
6d129bea ID |
1172 | return false; |
1173 | ||
5b092174 ID |
1174 | ret = false; |
1175 | ||
b242b7f7 | 1176 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
1177 | |
1178 | if (!(tmp & SDVO_ENABLE)) | |
5b092174 | 1179 | goto out; |
85234cdc | 1180 | |
6e266956 | 1181 | if (HAS_PCH_CPT(dev_priv)) |
85234cdc | 1182 | *pipe = PORT_TO_PIPE_CPT(tmp); |
920a14b2 | 1183 | else if (IS_CHERRYVIEW(dev_priv)) |
71485e0a | 1184 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); |
85234cdc DV |
1185 | else |
1186 | *pipe = PORT_TO_PIPE(tmp); | |
1187 | ||
5b092174 ID |
1188 | ret = true; |
1189 | ||
1190 | out: | |
79f255a0 | 1191 | intel_display_power_put(dev_priv, encoder->power_domain); |
5b092174 ID |
1192 | |
1193 | return ret; | |
85234cdc DV |
1194 | } |
1195 | ||
045ac3b5 | 1196 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
5cec258b | 1197 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
1198 | { |
1199 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
f99be1b3 | 1200 | struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi); |
8c875fca | 1201 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1202 | struct drm_i915_private *dev_priv = to_i915(dev); |
045ac3b5 | 1203 | u32 tmp, flags = 0; |
18442d08 | 1204 | int dotclock; |
045ac3b5 | 1205 | |
e1214b95 VS |
1206 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); |
1207 | ||
045ac3b5 JB |
1208 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
1209 | ||
1210 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
1211 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1212 | else | |
1213 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1214 | ||
1215 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
1216 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1217 | else | |
1218 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1219 | ||
6897b4b5 DV |
1220 | if (tmp & HDMI_MODE_SELECT_HDMI) |
1221 | pipe_config->has_hdmi_sink = true; | |
1222 | ||
f99be1b3 | 1223 | if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config)) |
e43823ec JB |
1224 | pipe_config->has_infoframe = true; |
1225 | ||
c84db770 | 1226 | if (tmp & SDVO_AUDIO_ENABLE) |
9ed109a7 DV |
1227 | pipe_config->has_audio = true; |
1228 | ||
6e266956 | 1229 | if (!HAS_PCH_SPLIT(dev_priv) && |
8c875fca VS |
1230 | tmp & HDMI_COLOR_RANGE_16_235) |
1231 | pipe_config->limited_color_range = true; | |
1232 | ||
2d112de7 | 1233 | pipe_config->base.adjusted_mode.flags |= flags; |
18442d08 VS |
1234 | |
1235 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
1236 | dotclock = pipe_config->port_clock * 2 / 3; | |
1237 | else | |
1238 | dotclock = pipe_config->port_clock; | |
1239 | ||
be69a133 VS |
1240 | if (pipe_config->pixel_multiplier) |
1241 | dotclock /= pipe_config->pixel_multiplier; | |
1242 | ||
2d112de7 | 1243 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
d4d6279a ACO |
1244 | |
1245 | pipe_config->lane_count = 4; | |
045ac3b5 JB |
1246 | } |
1247 | ||
df18e721 | 1248 | static void intel_enable_hdmi_audio(struct intel_encoder *encoder, |
5f88a9c6 VS |
1249 | const struct intel_crtc_state *pipe_config, |
1250 | const struct drm_connector_state *conn_state) | |
d1b1589c | 1251 | { |
ac240288 | 1252 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c | 1253 | |
ac240288 | 1254 | WARN_ON(!pipe_config->has_hdmi_sink); |
d1b1589c VS |
1255 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
1256 | pipe_name(crtc->pipe)); | |
bbf35e9d | 1257 | intel_audio_codec_enable(encoder, pipe_config, conn_state); |
d1b1589c VS |
1258 | } |
1259 | ||
fd6bbda9 | 1260 | static void g4x_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1261 | const struct intel_crtc_state *pipe_config, |
1262 | const struct drm_connector_state *conn_state) | |
7d57382e | 1263 | { |
5ab432ef | 1264 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1265 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1266 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e EA |
1267 | u32 temp; |
1268 | ||
b242b7f7 | 1269 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 1270 | |
bf868c7d | 1271 | temp |= SDVO_ENABLE; |
df18e721 | 1272 | if (pipe_config->has_audio) |
bf868c7d | 1273 | temp |= SDVO_AUDIO_ENABLE; |
7a87c289 | 1274 | |
bf868c7d VS |
1275 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1276 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1277 | ||
df18e721 ML |
1278 | if (pipe_config->has_audio) |
1279 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
bf868c7d VS |
1280 | } |
1281 | ||
fd6bbda9 | 1282 | static void ibx_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1283 | const struct intel_crtc_state *pipe_config, |
1284 | const struct drm_connector_state *conn_state) | |
bf868c7d VS |
1285 | { |
1286 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1287 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf868c7d VS |
1288 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1289 | u32 temp; | |
1290 | ||
1291 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 1292 | |
bf868c7d | 1293 | temp |= SDVO_ENABLE; |
ac240288 | 1294 | if (pipe_config->has_audio) |
bf868c7d | 1295 | temp |= SDVO_AUDIO_ENABLE; |
5ab432ef | 1296 | |
bf868c7d VS |
1297 | /* |
1298 | * HW workaround, need to write this twice for issue | |
1299 | * that may result in first write getting masked. | |
1300 | */ | |
1301 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1302 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1303 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1304 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef | 1305 | |
bf868c7d VS |
1306 | /* |
1307 | * HW workaround, need to toggle enable bit off and on | |
1308 | * for 12bpc with pixel repeat. | |
1309 | * | |
1310 | * FIXME: BSpec says this should be done at the end of | |
1311 | * of the modeset sequence, so not sure if this isn't too soon. | |
5ab432ef | 1312 | */ |
df18e721 ML |
1313 | if (pipe_config->pipe_bpp > 24 && |
1314 | pipe_config->pixel_multiplier > 1) { | |
bf868c7d VS |
1315 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
1316 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1317 | ||
1318 | /* | |
1319 | * HW workaround, need to write this twice for issue | |
1320 | * that may result in first write getting masked. | |
1321 | */ | |
1322 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1323 | POSTING_READ(intel_hdmi->hdmi_reg); | |
b242b7f7 PZ |
1324 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1325 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 1326 | } |
c1dec79a | 1327 | |
df18e721 ML |
1328 | if (pipe_config->has_audio) |
1329 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
d1b1589c VS |
1330 | } |
1331 | ||
fd6bbda9 | 1332 | static void cpt_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1333 | const struct intel_crtc_state *pipe_config, |
1334 | const struct drm_connector_state *conn_state) | |
d1b1589c VS |
1335 | { |
1336 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1337 | struct drm_i915_private *dev_priv = to_i915(dev); |
ac240288 | 1338 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); |
d1b1589c VS |
1339 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
1340 | enum pipe pipe = crtc->pipe; | |
1341 | u32 temp; | |
1342 | ||
1343 | temp = I915_READ(intel_hdmi->hdmi_reg); | |
1344 | ||
1345 | temp |= SDVO_ENABLE; | |
df18e721 | 1346 | if (pipe_config->has_audio) |
d1b1589c VS |
1347 | temp |= SDVO_AUDIO_ENABLE; |
1348 | ||
1349 | /* | |
1350 | * WaEnableHDMI8bpcBefore12bpc:snb,ivb | |
1351 | * | |
1352 | * The procedure for 12bpc is as follows: | |
1353 | * 1. disable HDMI clock gating | |
1354 | * 2. enable HDMI with 8bpc | |
1355 | * 3. enable HDMI with 12bpc | |
1356 | * 4. enable HDMI clock gating | |
1357 | */ | |
1358 | ||
df18e721 | 1359 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1360 | I915_WRITE(TRANS_CHICKEN1(pipe), |
1361 | I915_READ(TRANS_CHICKEN1(pipe)) | | |
1362 | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1363 | ||
1364 | temp &= ~SDVO_COLOR_FORMAT_MASK; | |
1365 | temp |= SDVO_COLOR_FORMAT_8bpc; | |
c1dec79a | 1366 | } |
d1b1589c VS |
1367 | |
1368 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1369 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1370 | ||
df18e721 | 1371 | if (pipe_config->pipe_bpp > 24) { |
d1b1589c VS |
1372 | temp &= ~SDVO_COLOR_FORMAT_MASK; |
1373 | temp |= HDMI_COLOR_FORMAT_12bpc; | |
1374 | ||
1375 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1376 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1377 | ||
1378 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
1379 | I915_READ(TRANS_CHICKEN1(pipe)) & | |
1380 | ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE); | |
1381 | } | |
1382 | ||
df18e721 ML |
1383 | if (pipe_config->has_audio) |
1384 | intel_enable_hdmi_audio(encoder, pipe_config, conn_state); | |
b76cf76b | 1385 | } |
89b667f8 | 1386 | |
fd6bbda9 | 1387 | static void vlv_enable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1388 | const struct intel_crtc_state *pipe_config, |
1389 | const struct drm_connector_state *conn_state) | |
b76cf76b | 1390 | { |
5ab432ef DV |
1391 | } |
1392 | ||
fd6bbda9 | 1393 | static void intel_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1394 | const struct intel_crtc_state *old_crtc_state, |
1395 | const struct drm_connector_state *old_conn_state) | |
5ab432ef DV |
1396 | { |
1397 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 1398 | struct drm_i915_private *dev_priv = to_i915(dev); |
5ab432ef | 1399 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
f99be1b3 VS |
1400 | struct intel_digital_port *intel_dig_port = |
1401 | hdmi_to_dig_port(intel_hdmi); | |
ac240288 | 1402 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
5ab432ef | 1403 | u32 temp; |
5ab432ef | 1404 | |
b242b7f7 | 1405 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef | 1406 | |
1612c8bd | 1407 | temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE); |
b242b7f7 PZ |
1408 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
1409 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1612c8bd VS |
1410 | |
1411 | /* | |
1412 | * HW workaround for IBX, we need to move the port | |
1413 | * to transcoder A after disabling it to allow the | |
1414 | * matching DP port to be enabled on transcoder A. | |
1415 | */ | |
6e266956 | 1416 | if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { |
0c241d5b VS |
1417 | /* |
1418 | * We get CPU/PCH FIFO underruns on the other pipe when | |
1419 | * doing the workaround. Sweep them under the rug. | |
1420 | */ | |
1421 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1422 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); | |
1423 | ||
1612c8bd VS |
1424 | temp &= ~SDVO_PIPE_B_SELECT; |
1425 | temp |= SDVO_ENABLE; | |
1426 | /* | |
1427 | * HW workaround, need to write this twice for issue | |
1428 | * that may result in first write getting masked. | |
1429 | */ | |
1430 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1431 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1432 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1433 | POSTING_READ(intel_hdmi->hdmi_reg); | |
1434 | ||
1435 | temp &= ~SDVO_ENABLE; | |
1436 | I915_WRITE(intel_hdmi->hdmi_reg, temp); | |
1437 | POSTING_READ(intel_hdmi->hdmi_reg); | |
0c241d5b | 1438 | |
0f0f74bc | 1439 | intel_wait_for_vblank_if_active(dev_priv, PIPE_A); |
0c241d5b VS |
1440 | intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
1441 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); | |
1612c8bd | 1442 | } |
6d67415f | 1443 | |
f99be1b3 VS |
1444 | intel_dig_port->set_infoframes(&encoder->base, false, |
1445 | old_crtc_state, old_conn_state); | |
b2ccb822 VS |
1446 | |
1447 | intel_dp_dual_mode_set_tmds_output(intel_hdmi, false); | |
7d57382e EA |
1448 | } |
1449 | ||
fd6bbda9 | 1450 | static void g4x_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1451 | const struct intel_crtc_state *old_crtc_state, |
1452 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 1453 | { |
df18e721 | 1454 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
1455 | intel_audio_codec_disable(encoder, |
1456 | old_crtc_state, old_conn_state); | |
a4790cec | 1457 | |
fd6bbda9 | 1458 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1459 | } |
1460 | ||
fd6bbda9 | 1461 | static void pch_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1462 | const struct intel_crtc_state *old_crtc_state, |
1463 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 1464 | { |
df18e721 | 1465 | if (old_crtc_state->has_audio) |
8ec47de2 VS |
1466 | intel_audio_codec_disable(encoder, |
1467 | old_crtc_state, old_conn_state); | |
a4790cec VS |
1468 | } |
1469 | ||
fd6bbda9 | 1470 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
5f88a9c6 VS |
1471 | const struct intel_crtc_state *old_crtc_state, |
1472 | const struct drm_connector_state *old_conn_state) | |
a4790cec | 1473 | { |
fd6bbda9 | 1474 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
a4790cec VS |
1475 | } |
1476 | ||
d6038611 | 1477 | static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) |
7d148ef5 | 1478 | { |
d6038611 VS |
1479 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1480 | const struct ddi_vbt_port_info *info = | |
1481 | &dev_priv->vbt.ddi_port_info[encoder->port]; | |
1482 | int max_tmds_clock; | |
1483 | ||
9672a69c | 1484 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
d6038611 VS |
1485 | max_tmds_clock = 594000; |
1486 | else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) | |
1487 | max_tmds_clock = 300000; | |
1488 | else if (INTEL_GEN(dev_priv) >= 5) | |
1489 | max_tmds_clock = 225000; | |
7d148ef5 | 1490 | else |
d6038611 VS |
1491 | max_tmds_clock = 165000; |
1492 | ||
1493 | if (info->max_tmds_clock) | |
1494 | max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); | |
1495 | ||
1496 | return max_tmds_clock; | |
7d148ef5 DV |
1497 | } |
1498 | ||
b1ba124d | 1499 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
7a5ca19f ML |
1500 | bool respect_downstream_limits, |
1501 | bool force_dvi) | |
b1ba124d | 1502 | { |
d6038611 VS |
1503 | struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; |
1504 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); | |
b1ba124d VS |
1505 | |
1506 | if (respect_downstream_limits) { | |
8cadab0a VS |
1507 | struct intel_connector *connector = hdmi->attached_connector; |
1508 | const struct drm_display_info *info = &connector->base.display_info; | |
1509 | ||
b1ba124d VS |
1510 | if (hdmi->dp_dual_mode.max_tmds_clock) |
1511 | max_tmds_clock = min(max_tmds_clock, | |
1512 | hdmi->dp_dual_mode.max_tmds_clock); | |
8cadab0a VS |
1513 | |
1514 | if (info->max_tmds_clock) | |
1515 | max_tmds_clock = min(max_tmds_clock, | |
1516 | info->max_tmds_clock); | |
7a5ca19f | 1517 | else if (!hdmi->has_hdmi_sink || force_dvi) |
b1ba124d VS |
1518 | max_tmds_clock = min(max_tmds_clock, 165000); |
1519 | } | |
1520 | ||
1521 | return max_tmds_clock; | |
1522 | } | |
1523 | ||
e64e739e VS |
1524 | static enum drm_mode_status |
1525 | hdmi_port_clock_valid(struct intel_hdmi *hdmi, | |
7a5ca19f ML |
1526 | int clock, bool respect_downstream_limits, |
1527 | bool force_dvi) | |
e64e739e | 1528 | { |
e2d214ae | 1529 | struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi)); |
e64e739e VS |
1530 | |
1531 | if (clock < 25000) | |
1532 | return MODE_CLOCK_LOW; | |
7a5ca19f | 1533 | if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi)) |
e64e739e VS |
1534 | return MODE_CLOCK_HIGH; |
1535 | ||
5e6ccc0b | 1536 | /* BXT DPLL can't generate 223-240 MHz */ |
cc3f90f0 | 1537 | if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) |
5e6ccc0b VS |
1538 | return MODE_CLOCK_RANGE; |
1539 | ||
1540 | /* CHV DPLL can't generate 216-240 MHz */ | |
e2d214ae | 1541 | if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) |
e64e739e VS |
1542 | return MODE_CLOCK_RANGE; |
1543 | ||
1544 | return MODE_OK; | |
1545 | } | |
1546 | ||
c19de8eb DL |
1547 | static enum drm_mode_status |
1548 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
1549 | struct drm_display_mode *mode) | |
7d57382e | 1550 | { |
e64e739e VS |
1551 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1552 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
49cff963 | 1553 | struct drm_i915_private *dev_priv = to_i915(dev); |
e64e739e VS |
1554 | enum drm_mode_status status; |
1555 | int clock; | |
587bf496 | 1556 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
7a5ca19f ML |
1557 | bool force_dvi = |
1558 | READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI; | |
e64e739e | 1559 | |
e64e739e | 1560 | clock = mode->clock; |
587bf496 MK |
1561 | |
1562 | if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) | |
1563 | clock *= 2; | |
1564 | ||
1565 | if (clock > max_dotclk) | |
1566 | return MODE_CLOCK_HIGH; | |
1567 | ||
697c4078 CT |
1568 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
1569 | clock *= 2; | |
1570 | ||
b22ca995 SS |
1571 | if (drm_mode_is_420_only(&connector->display_info, mode)) |
1572 | clock /= 2; | |
1573 | ||
e64e739e | 1574 | /* check if we can do 8bpc */ |
7a5ca19f | 1575 | status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi); |
7d57382e | 1576 | |
e64e739e | 1577 | /* if we can't do 8bpc we may still be able to do 12bpc */ |
7a5ca19f ML |
1578 | if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi) |
1579 | status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi); | |
7d57382e | 1580 | |
e64e739e | 1581 | return status; |
7d57382e EA |
1582 | } |
1583 | ||
5f88a9c6 | 1584 | static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) |
71800632 | 1585 | { |
c750bdd3 VS |
1586 | struct drm_i915_private *dev_priv = |
1587 | to_i915(crtc_state->base.crtc->dev); | |
1588 | struct drm_atomic_state *state = crtc_state->base.state; | |
1589 | struct drm_connector_state *connector_state; | |
1590 | struct drm_connector *connector; | |
1591 | int i; | |
71800632 | 1592 | |
c750bdd3 | 1593 | if (HAS_GMCH_DISPLAY(dev_priv)) |
71800632 VS |
1594 | return false; |
1595 | ||
be33be5d VS |
1596 | if (crtc_state->pipe_bpp <= 8*3) |
1597 | return false; | |
1598 | ||
1599 | if (!crtc_state->has_hdmi_sink) | |
1600 | return false; | |
1601 | ||
71800632 VS |
1602 | /* |
1603 | * HDMI 12bpc affects the clocks, so it's only possible | |
1604 | * when not cloning with other encoder types. | |
1605 | */ | |
c750bdd3 VS |
1606 | if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI) |
1607 | return false; | |
1608 | ||
fe5f6b1f | 1609 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
c750bdd3 VS |
1610 | const struct drm_display_info *info = &connector->display_info; |
1611 | ||
1612 | if (connector_state->crtc != crtc_state->base.crtc) | |
1613 | continue; | |
1614 | ||
60436fd4 SS |
1615 | if (crtc_state->ycbcr420) { |
1616 | const struct drm_hdmi_info *hdmi = &info->hdmi; | |
1617 | ||
1618 | if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) | |
1619 | return false; | |
1620 | } else { | |
1621 | if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36)) | |
1622 | return false; | |
1623 | } | |
c750bdd3 VS |
1624 | } |
1625 | ||
2abf3c0d | 1626 | /* Display WA #1139: glk */ |
46649d8b ACO |
1627 | if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) && |
1628 | crtc_state->base.adjusted_mode.htotal > 5460) | |
1629 | return false; | |
1630 | ||
c750bdd3 | 1631 | return true; |
71800632 VS |
1632 | } |
1633 | ||
60436fd4 SS |
1634 | static bool |
1635 | intel_hdmi_ycbcr420_config(struct drm_connector *connector, | |
1636 | struct intel_crtc_state *config, | |
1637 | int *clock_12bpc, int *clock_8bpc) | |
1638 | { | |
e5c05931 SS |
1639 | struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc); |
1640 | ||
60436fd4 SS |
1641 | if (!connector->ycbcr_420_allowed) { |
1642 | DRM_ERROR("Platform doesn't support YCBCR420 output\n"); | |
1643 | return false; | |
1644 | } | |
1645 | ||
1646 | /* YCBCR420 TMDS rate requirement is half the pixel clock */ | |
1647 | config->port_clock /= 2; | |
1648 | *clock_12bpc /= 2; | |
1649 | *clock_8bpc /= 2; | |
1650 | config->ycbcr420 = true; | |
e5c05931 SS |
1651 | |
1652 | /* YCBCR 420 output conversion needs a scaler */ | |
1653 | if (skl_update_scaler_crtc(config)) { | |
1654 | DRM_DEBUG_KMS("Scaler allocation for output failed\n"); | |
1655 | return false; | |
1656 | } | |
1657 | ||
1658 | intel_pch_panel_fitting(intel_crtc, config, | |
1659 | DRM_MODE_SCALE_FULLSCREEN); | |
1660 | ||
60436fd4 SS |
1661 | return true; |
1662 | } | |
1663 | ||
5bfe2ac0 | 1664 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
0a478c27 ML |
1665 | struct intel_crtc_state *pipe_config, |
1666 | struct drm_connector_state *conn_state) | |
7d57382e | 1667 | { |
5bfe2ac0 | 1668 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
4f8036a2 | 1669 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2d112de7 | 1670 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
60436fd4 SS |
1671 | struct drm_connector *connector = conn_state->connector; |
1672 | struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; | |
7a5ca19f ML |
1673 | struct intel_digital_connector_state *intel_conn_state = |
1674 | to_intel_digital_connector_state(conn_state); | |
e64e739e VS |
1675 | int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock; |
1676 | int clock_12bpc = clock_8bpc * 3 / 2; | |
e29c22c0 | 1677 | int desired_bpp; |
7a5ca19f | 1678 | bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI; |
3685a8f3 | 1679 | |
7a5ca19f | 1680 | pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink; |
6897b4b5 | 1681 | |
e43823ec JB |
1682 | if (pipe_config->has_hdmi_sink) |
1683 | pipe_config->has_infoframe = true; | |
1684 | ||
7a5ca19f | 1685 | if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { |
55bc60db | 1686 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ |
0f2a2a75 VS |
1687 | pipe_config->limited_color_range = |
1688 | pipe_config->has_hdmi_sink && | |
c8127cf0 VS |
1689 | drm_default_rgb_quant_range(adjusted_mode) == |
1690 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
0f2a2a75 VS |
1691 | } else { |
1692 | pipe_config->limited_color_range = | |
7a5ca19f | 1693 | intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; |
55bc60db VS |
1694 | } |
1695 | ||
697c4078 CT |
1696 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) { |
1697 | pipe_config->pixel_multiplier = 2; | |
e64e739e | 1698 | clock_8bpc *= 2; |
3320e37f | 1699 | clock_12bpc *= 2; |
697c4078 CT |
1700 | } |
1701 | ||
60436fd4 SS |
1702 | if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) { |
1703 | if (!intel_hdmi_ycbcr420_config(connector, pipe_config, | |
1704 | &clock_12bpc, &clock_8bpc)) { | |
1705 | DRM_ERROR("Can't support YCBCR420 output\n"); | |
1706 | return false; | |
1707 | } | |
1708 | } | |
1709 | ||
4f8036a2 | 1710 | if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv)) |
5bfe2ac0 DV |
1711 | pipe_config->has_pch_encoder = true; |
1712 | ||
7a5ca19f ML |
1713 | if (pipe_config->has_hdmi_sink) { |
1714 | if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) | |
1715 | pipe_config->has_audio = intel_hdmi->has_audio; | |
1716 | else | |
1717 | pipe_config->has_audio = | |
1718 | intel_conn_state->force_audio == HDMI_AUDIO_ON; | |
1719 | } | |
9ed109a7 | 1720 | |
4e53c2e0 DV |
1721 | /* |
1722 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
1723 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
1724 | * outputs. We also need to check that the higher clock still fits |
1725 | * within limits. | |
4e53c2e0 | 1726 | */ |
be33be5d VS |
1727 | if (hdmi_12bpc_possible(pipe_config) && |
1728 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK) { | |
e29c22c0 DV |
1729 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1730 | desired_bpp = 12*3; | |
325b9d04 DV |
1731 | |
1732 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 1733 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 1734 | } else { |
e29c22c0 DV |
1735 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
1736 | desired_bpp = 8*3; | |
e64e739e VS |
1737 | |
1738 | pipe_config->port_clock = clock_8bpc; | |
e29c22c0 DV |
1739 | } |
1740 | ||
1741 | if (!pipe_config->bw_constrained) { | |
b64b7a60 | 1742 | DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp); |
e29c22c0 | 1743 | pipe_config->pipe_bpp = desired_bpp; |
4e53c2e0 DV |
1744 | } |
1745 | ||
e64e739e | 1746 | if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock, |
7a5ca19f | 1747 | false, force_dvi) != MODE_OK) { |
e64e739e | 1748 | DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n"); |
325b9d04 DV |
1749 | return false; |
1750 | } | |
1751 | ||
28b468a0 | 1752 | /* Set user selected PAR to incoming mode's member */ |
0e9f25d0 | 1753 | adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio; |
28b468a0 | 1754 | |
d4d6279a ACO |
1755 | pipe_config->lane_count = 4; |
1756 | ||
9672a69c RV |
1757 | if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || |
1758 | IS_GEMINILAKE(dev_priv))) { | |
15953637 SS |
1759 | if (scdc->scrambling.low_rates) |
1760 | pipe_config->hdmi_scrambling = true; | |
1761 | ||
1762 | if (pipe_config->port_clock > 340000) { | |
1763 | pipe_config->hdmi_scrambling = true; | |
1764 | pipe_config->hdmi_high_tmds_clock_ratio = true; | |
1765 | } | |
1766 | } | |
1767 | ||
7d57382e EA |
1768 | return true; |
1769 | } | |
1770 | ||
953ece69 CW |
1771 | static void |
1772 | intel_hdmi_unset_edid(struct drm_connector *connector) | |
9dff6af8 | 1773 | { |
df0e9248 | 1774 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
9dff6af8 | 1775 | |
953ece69 CW |
1776 | intel_hdmi->has_hdmi_sink = false; |
1777 | intel_hdmi->has_audio = false; | |
1778 | intel_hdmi->rgb_quant_range_selectable = false; | |
1779 | ||
b1ba124d VS |
1780 | intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; |
1781 | intel_hdmi->dp_dual_mode.max_tmds_clock = 0; | |
1782 | ||
953ece69 CW |
1783 | kfree(to_intel_connector(connector)->detect_edid); |
1784 | to_intel_connector(connector)->detect_edid = NULL; | |
1785 | } | |
1786 | ||
b1ba124d | 1787 | static void |
d6199256 | 1788 | intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) |
b1ba124d VS |
1789 | { |
1790 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1791 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | |
8f4f2797 | 1792 | enum port port = hdmi_to_dig_port(hdmi)->base.port; |
b1ba124d VS |
1793 | struct i2c_adapter *adapter = |
1794 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | |
1795 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | |
1796 | ||
d6199256 VS |
1797 | /* |
1798 | * Type 1 DVI adaptors are not required to implement any | |
1799 | * registers, so we can't always detect their presence. | |
1800 | * Ideally we should be able to check the state of the | |
1801 | * CONFIG1 pin, but no such luck on our hardware. | |
1802 | * | |
1803 | * The only method left to us is to check the VBT to see | |
1804 | * if the port is a dual mode capable DP port. But let's | |
1805 | * only do that when we sucesfully read the EDID, to avoid | |
1806 | * confusing log messages about DP dual mode adaptors when | |
1807 | * there's nothing connected to the port. | |
1808 | */ | |
1809 | if (type == DRM_DP_DUAL_MODE_UNKNOWN) { | |
30190629 AJ |
1810 | /* An overridden EDID imply that we want this port for testing. |
1811 | * Make sure not to set limits for that port. | |
1812 | */ | |
1813 | if (has_edid && !connector->override_edid && | |
d6199256 VS |
1814 | intel_bios_is_port_dp_dual_mode(dev_priv, port)) { |
1815 | DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n"); | |
1816 | type = DRM_DP_DUAL_MODE_TYPE1_DVI; | |
1817 | } else { | |
1818 | type = DRM_DP_DUAL_MODE_NONE; | |
1819 | } | |
1820 | } | |
1821 | ||
1822 | if (type == DRM_DP_DUAL_MODE_NONE) | |
b1ba124d VS |
1823 | return; |
1824 | ||
1825 | hdmi->dp_dual_mode.type = type; | |
1826 | hdmi->dp_dual_mode.max_tmds_clock = | |
1827 | drm_dp_dual_mode_max_tmds_clock(type, adapter); | |
1828 | ||
1829 | DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n", | |
1830 | drm_dp_get_dual_mode_type_name(type), | |
1831 | hdmi->dp_dual_mode.max_tmds_clock); | |
1832 | } | |
1833 | ||
953ece69 | 1834 | static bool |
23f889bd | 1835 | intel_hdmi_set_edid(struct drm_connector *connector) |
953ece69 CW |
1836 | { |
1837 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | |
1838 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
23f889bd | 1839 | struct edid *edid; |
953ece69 | 1840 | bool connected = false; |
cfb926e1 | 1841 | struct i2c_adapter *i2c; |
164c8598 | 1842 | |
23f889bd | 1843 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
671dedd2 | 1844 | |
cfb926e1 SB |
1845 | i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus); |
1846 | ||
1847 | edid = drm_get_edid(connector, i2c); | |
1848 | ||
1849 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
1850 | DRM_DEBUG_KMS("HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
1851 | intel_gmbus_force_bit(i2c, true); | |
1852 | edid = drm_get_edid(connector, i2c); | |
1853 | intel_gmbus_force_bit(i2c, false); | |
1854 | } | |
2ded9e27 | 1855 | |
23f889bd | 1856 | intel_hdmi_dp_dual_mode_detect(connector, edid != NULL); |
b1ba124d | 1857 | |
23f889bd | 1858 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
30ad48b7 | 1859 | |
953ece69 CW |
1860 | to_intel_connector(connector)->detect_edid = edid; |
1861 | if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { | |
1862 | intel_hdmi->rgb_quant_range_selectable = | |
1863 | drm_rgb_quant_range_selectable(edid); | |
1864 | ||
1865 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); | |
7a5ca19f | 1866 | intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid); |
953ece69 CW |
1867 | |
1868 | connected = true; | |
55b7d6e8 CW |
1869 | } |
1870 | ||
953ece69 CW |
1871 | return connected; |
1872 | } | |
1873 | ||
8166fcea DV |
1874 | static enum drm_connector_status |
1875 | intel_hdmi_detect(struct drm_connector *connector, bool force) | |
953ece69 | 1876 | { |
8166fcea | 1877 | enum drm_connector_status status; |
8166fcea | 1878 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
953ece69 | 1879 | |
8166fcea DV |
1880 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1881 | connector->base.id, connector->name); | |
1882 | ||
29bb94bb ID |
1883 | intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS); |
1884 | ||
8166fcea | 1885 | intel_hdmi_unset_edid(connector); |
0b5e88dc | 1886 | |
7e732cac | 1887 | if (intel_hdmi_set_edid(connector)) |
953ece69 | 1888 | status = connector_status_connected; |
7e732cac | 1889 | else |
953ece69 | 1890 | status = connector_status_disconnected; |
671dedd2 | 1891 | |
29bb94bb ID |
1892 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
1893 | ||
2ded9e27 | 1894 | return status; |
7d57382e EA |
1895 | } |
1896 | ||
953ece69 CW |
1897 | static void |
1898 | intel_hdmi_force(struct drm_connector *connector) | |
7d57382e | 1899 | { |
953ece69 CW |
1900 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1901 | connector->base.id, connector->name); | |
7d57382e | 1902 | |
953ece69 | 1903 | intel_hdmi_unset_edid(connector); |
671dedd2 | 1904 | |
953ece69 CW |
1905 | if (connector->status != connector_status_connected) |
1906 | return; | |
671dedd2 | 1907 | |
23f889bd | 1908 | intel_hdmi_set_edid(connector); |
953ece69 | 1909 | } |
671dedd2 | 1910 | |
953ece69 CW |
1911 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
1912 | { | |
1913 | struct edid *edid; | |
1914 | ||
1915 | edid = to_intel_connector(connector)->detect_edid; | |
1916 | if (edid == NULL) | |
1917 | return 0; | |
671dedd2 | 1918 | |
953ece69 | 1919 | return intel_connector_update_modes(connector, edid); |
7d57382e EA |
1920 | } |
1921 | ||
fd6bbda9 | 1922 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1923 | const struct intel_crtc_state *pipe_config, |
1924 | const struct drm_connector_state *conn_state) | |
13732ba7 | 1925 | { |
f99be1b3 VS |
1926 | struct intel_digital_port *intel_dig_port = |
1927 | enc_to_dig_port(&encoder->base); | |
13732ba7 | 1928 | |
ac240288 | 1929 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1930 | |
f99be1b3 VS |
1931 | intel_dig_port->set_infoframes(&encoder->base, |
1932 | pipe_config->has_infoframe, | |
1933 | pipe_config, conn_state); | |
13732ba7 JB |
1934 | } |
1935 | ||
fd6bbda9 | 1936 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1937 | const struct intel_crtc_state *pipe_config, |
1938 | const struct drm_connector_state *conn_state) | |
89b667f8 JB |
1939 | { |
1940 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2e1029c6 | 1941 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
5f68c275 | 1942 | |
2e1029c6 | 1943 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
b76cf76b | 1944 | |
53d98725 ACO |
1945 | /* HDMI 1.0V-2dB */ |
1946 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | |
1947 | 0x2b247878); | |
1948 | ||
f99be1b3 VS |
1949 | dport->set_infoframes(&encoder->base, |
1950 | pipe_config->has_infoframe, | |
1951 | pipe_config, conn_state); | |
13732ba7 | 1952 | |
fd6bbda9 | 1953 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
b76cf76b | 1954 | |
9b6de0a1 | 1955 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
89b667f8 JB |
1956 | } |
1957 | ||
fd6bbda9 | 1958 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1959 | const struct intel_crtc_state *pipe_config, |
1960 | const struct drm_connector_state *conn_state) | |
89b667f8 | 1961 | { |
ac240288 | 1962 | intel_hdmi_prepare(encoder, pipe_config); |
4cde8a21 | 1963 | |
2e1029c6 | 1964 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
89b667f8 JB |
1965 | } |
1966 | ||
fd6bbda9 | 1967 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1968 | const struct intel_crtc_state *pipe_config, |
1969 | const struct drm_connector_state *conn_state) | |
9197c88b | 1970 | { |
ac240288 | 1971 | intel_hdmi_prepare(encoder, pipe_config); |
625695f8 | 1972 | |
2e1029c6 | 1973 | chv_phy_pre_pll_enable(encoder, pipe_config); |
9197c88b VS |
1974 | } |
1975 | ||
fd6bbda9 | 1976 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1977 | const struct intel_crtc_state *old_crtc_state, |
1978 | const struct drm_connector_state *old_conn_state) | |
d6db995f | 1979 | { |
2e1029c6 | 1980 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
d6db995f VS |
1981 | } |
1982 | ||
fd6bbda9 | 1983 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1984 | const struct intel_crtc_state *old_crtc_state, |
1985 | const struct drm_connector_state *old_conn_state) | |
89b667f8 | 1986 | { |
89b667f8 | 1987 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
2e1029c6 | 1988 | vlv_phy_reset_lanes(encoder, old_crtc_state); |
89b667f8 JB |
1989 | } |
1990 | ||
fd6bbda9 | 1991 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
5f88a9c6 VS |
1992 | const struct intel_crtc_state *old_crtc_state, |
1993 | const struct drm_connector_state *old_conn_state) | |
580d3811 | 1994 | { |
580d3811 | 1995 | struct drm_device *dev = encoder->base.dev; |
fac5e23e | 1996 | struct drm_i915_private *dev_priv = to_i915(dev); |
580d3811 | 1997 | |
a580516d | 1998 | mutex_lock(&dev_priv->sb_lock); |
580d3811 | 1999 | |
a8f327fb | 2000 | /* Assert data lane reset */ |
2e1029c6 | 2001 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
580d3811 | 2002 | |
a580516d | 2003 | mutex_unlock(&dev_priv->sb_lock); |
580d3811 VS |
2004 | } |
2005 | ||
fd6bbda9 | 2006 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder, |
5f88a9c6 VS |
2007 | const struct intel_crtc_state *pipe_config, |
2008 | const struct drm_connector_state *conn_state) | |
e4a1d846 CML |
2009 | { |
2010 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
2011 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 2012 | struct drm_i915_private *dev_priv = to_i915(dev); |
2e523e98 | 2013 | |
2e1029c6 | 2014 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
a02ef3c7 | 2015 | |
e4a1d846 CML |
2016 | /* FIXME: Program the support xxx V-dB */ |
2017 | /* Use 800mV-0dB */ | |
b7fa22d8 | 2018 | chv_set_phy_signal_level(encoder, 128, 102, false); |
e4a1d846 | 2019 | |
f99be1b3 VS |
2020 | dport->set_infoframes(&encoder->base, |
2021 | pipe_config->has_infoframe, | |
2022 | pipe_config, conn_state); | |
b4eb1564 | 2023 | |
fd6bbda9 | 2024 | g4x_enable_hdmi(encoder, pipe_config, conn_state); |
e4a1d846 | 2025 | |
9b6de0a1 | 2026 | vlv_wait_port_ready(dev_priv, dport, 0x0); |
b0b33846 VS |
2027 | |
2028 | /* Second common lane will stay alive on its own now */ | |
e7d2a717 | 2029 | chv_phy_release_cl2_override(encoder); |
e4a1d846 CML |
2030 | } |
2031 | ||
7d57382e EA |
2032 | static void intel_hdmi_destroy(struct drm_connector *connector) |
2033 | { | |
10e972d3 | 2034 | kfree(to_intel_connector(connector)->detect_edid); |
7d57382e | 2035 | drm_connector_cleanup(connector); |
674e2d08 | 2036 | kfree(connector); |
7d57382e EA |
2037 | } |
2038 | ||
7d57382e | 2039 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
7d57382e | 2040 | .detect = intel_hdmi_detect, |
953ece69 | 2041 | .force = intel_hdmi_force, |
7d57382e | 2042 | .fill_modes = drm_helper_probe_single_connector_modes, |
7a5ca19f ML |
2043 | .atomic_get_property = intel_digital_connector_atomic_get_property, |
2044 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
1ebaa0b9 | 2045 | .late_register = intel_connector_register, |
c191eca1 | 2046 | .early_unregister = intel_connector_unregister, |
7d57382e | 2047 | .destroy = intel_hdmi_destroy, |
c6f95f27 | 2048 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
7a5ca19f | 2049 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
7d57382e EA |
2050 | }; |
2051 | ||
2052 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
2053 | .get_modes = intel_hdmi_get_modes, | |
2054 | .mode_valid = intel_hdmi_mode_valid, | |
7a5ca19f | 2055 | .atomic_check = intel_digital_connector_atomic_check, |
7d57382e EA |
2056 | }; |
2057 | ||
7d57382e | 2058 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 2059 | .destroy = intel_encoder_destroy, |
7d57382e EA |
2060 | }; |
2061 | ||
55b7d6e8 CW |
2062 | static void |
2063 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
2064 | { | |
3f43c48d | 2065 | intel_attach_force_audio_property(connector); |
e953fd7b | 2066 | intel_attach_broadcast_rgb_property(connector); |
94a11ddc | 2067 | intel_attach_aspect_ratio_property(connector); |
0e9f25d0 | 2068 | connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE; |
55b7d6e8 CW |
2069 | } |
2070 | ||
15953637 SS |
2071 | /* |
2072 | * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup | |
2073 | * @encoder: intel_encoder | |
2074 | * @connector: drm_connector | |
2075 | * @high_tmds_clock_ratio = bool to indicate if the function needs to set | |
2076 | * or reset the high tmds clock ratio for scrambling | |
2077 | * @scrambling: bool to Indicate if the function needs to set or reset | |
2078 | * sink scrambling | |
2079 | * | |
2080 | * This function handles scrambling on HDMI 2.0 capable sinks. | |
2081 | * If required clock rate is > 340 Mhz && scrambling is supported by sink | |
2082 | * it enables scrambling. This should be called before enabling the HDMI | |
2083 | * 2.0 port, as the sink can choose to disable the scrambling if it doesn't | |
2084 | * detect a scrambled clock within 100 ms. | |
2085 | */ | |
2086 | void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder, | |
2087 | struct drm_connector *connector, | |
2088 | bool high_tmds_clock_ratio, | |
2089 | bool scrambling) | |
2090 | { | |
2091 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
2092 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
2093 | struct drm_scrambling *sink_scrambling = | |
2094 | &connector->display_info.hdmi.scdc.scrambling; | |
2095 | struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv, | |
2096 | intel_hdmi->ddc_bus); | |
2097 | bool ret; | |
2098 | ||
2099 | if (!sink_scrambling->supported) | |
2100 | return; | |
2101 | ||
2102 | DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n", | |
2103 | encoder->base.name, connector->name); | |
2104 | ||
2105 | /* Set TMDS bit clock ratio to 1/40 or 1/10 */ | |
2106 | ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio); | |
2107 | if (!ret) { | |
2108 | DRM_ERROR("Set TMDS ratio failed\n"); | |
2109 | return; | |
2110 | } | |
2111 | ||
2112 | /* Enable/disable sink scrambling */ | |
2113 | ret = drm_scdc_set_scrambling(adptr, scrambling); | |
2114 | if (!ret) { | |
2115 | DRM_ERROR("Set sink scrambling failed\n"); | |
2116 | return; | |
2117 | } | |
2118 | ||
2119 | DRM_DEBUG_KMS("sink scrambling handled\n"); | |
2120 | } | |
2121 | ||
cec3bb01 | 2122 | static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
e4ab73a1 | 2123 | { |
e4ab73a1 VS |
2124 | u8 ddc_pin; |
2125 | ||
cec3bb01 AS |
2126 | switch (port) { |
2127 | case PORT_B: | |
2128 | ddc_pin = GMBUS_PIN_DPB; | |
2129 | break; | |
2130 | case PORT_C: | |
2131 | ddc_pin = GMBUS_PIN_DPC; | |
2132 | break; | |
2133 | case PORT_D: | |
2134 | ddc_pin = GMBUS_PIN_DPD_CHV; | |
2135 | break; | |
2136 | default: | |
2137 | MISSING_CASE(port); | |
2138 | ddc_pin = GMBUS_PIN_DPB; | |
2139 | break; | |
e4ab73a1 | 2140 | } |
cec3bb01 AS |
2141 | return ddc_pin; |
2142 | } | |
2143 | ||
2144 | static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) | |
2145 | { | |
2146 | u8 ddc_pin; | |
e4ab73a1 VS |
2147 | |
2148 | switch (port) { | |
2149 | case PORT_B: | |
cec3bb01 | 2150 | ddc_pin = GMBUS_PIN_1_BXT; |
e4ab73a1 VS |
2151 | break; |
2152 | case PORT_C: | |
cec3bb01 AS |
2153 | ddc_pin = GMBUS_PIN_2_BXT; |
2154 | break; | |
2155 | default: | |
2156 | MISSING_CASE(port); | |
2157 | ddc_pin = GMBUS_PIN_1_BXT; | |
2158 | break; | |
2159 | } | |
2160 | return ddc_pin; | |
2161 | } | |
2162 | ||
2163 | static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv, | |
2164 | enum port port) | |
2165 | { | |
2166 | u8 ddc_pin; | |
2167 | ||
2168 | switch (port) { | |
2169 | case PORT_B: | |
2170 | ddc_pin = GMBUS_PIN_1_BXT; | |
2171 | break; | |
2172 | case PORT_C: | |
2173 | ddc_pin = GMBUS_PIN_2_BXT; | |
e4ab73a1 VS |
2174 | break; |
2175 | case PORT_D: | |
cec3bb01 AS |
2176 | ddc_pin = GMBUS_PIN_4_CNP; |
2177 | break; | |
3a2a59cc RV |
2178 | case PORT_F: |
2179 | ddc_pin = GMBUS_PIN_3_BXT; | |
2180 | break; | |
cec3bb01 AS |
2181 | default: |
2182 | MISSING_CASE(port); | |
2183 | ddc_pin = GMBUS_PIN_1_BXT; | |
2184 | break; | |
2185 | } | |
2186 | return ddc_pin; | |
2187 | } | |
2188 | ||
5c749c52 AS |
2189 | static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) |
2190 | { | |
2191 | u8 ddc_pin; | |
2192 | ||
2193 | switch (port) { | |
2194 | case PORT_A: | |
2195 | ddc_pin = GMBUS_PIN_1_BXT; | |
2196 | break; | |
2197 | case PORT_B: | |
2198 | ddc_pin = GMBUS_PIN_2_BXT; | |
2199 | break; | |
2200 | case PORT_C: | |
2201 | ddc_pin = GMBUS_PIN_9_TC1_ICP; | |
2202 | break; | |
2203 | case PORT_D: | |
2204 | ddc_pin = GMBUS_PIN_10_TC2_ICP; | |
2205 | break; | |
2206 | case PORT_E: | |
2207 | ddc_pin = GMBUS_PIN_11_TC3_ICP; | |
2208 | break; | |
2209 | case PORT_F: | |
2210 | ddc_pin = GMBUS_PIN_12_TC4_ICP; | |
2211 | break; | |
2212 | default: | |
2213 | MISSING_CASE(port); | |
2214 | ddc_pin = GMBUS_PIN_2_BXT; | |
2215 | break; | |
2216 | } | |
2217 | return ddc_pin; | |
2218 | } | |
2219 | ||
cec3bb01 AS |
2220 | static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv, |
2221 | enum port port) | |
2222 | { | |
2223 | u8 ddc_pin; | |
2224 | ||
2225 | switch (port) { | |
2226 | case PORT_B: | |
2227 | ddc_pin = GMBUS_PIN_DPB; | |
2228 | break; | |
2229 | case PORT_C: | |
2230 | ddc_pin = GMBUS_PIN_DPC; | |
2231 | break; | |
2232 | case PORT_D: | |
2233 | ddc_pin = GMBUS_PIN_DPD; | |
e4ab73a1 VS |
2234 | break; |
2235 | default: | |
2236 | MISSING_CASE(port); | |
2237 | ddc_pin = GMBUS_PIN_DPB; | |
2238 | break; | |
2239 | } | |
cec3bb01 AS |
2240 | return ddc_pin; |
2241 | } | |
2242 | ||
2243 | static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, | |
2244 | enum port port) | |
2245 | { | |
2246 | const struct ddi_vbt_port_info *info = | |
2247 | &dev_priv->vbt.ddi_port_info[port]; | |
2248 | u8 ddc_pin; | |
2249 | ||
2250 | if (info->alternate_ddc_pin) { | |
2251 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", | |
2252 | info->alternate_ddc_pin, port_name(port)); | |
2253 | return info->alternate_ddc_pin; | |
2254 | } | |
2255 | ||
2256 | if (IS_CHERRYVIEW(dev_priv)) | |
2257 | ddc_pin = chv_port_to_ddc_pin(dev_priv, port); | |
2258 | else if (IS_GEN9_LP(dev_priv)) | |
2259 | ddc_pin = bxt_port_to_ddc_pin(dev_priv, port); | |
2260 | else if (HAS_PCH_CNP(dev_priv)) | |
2261 | ddc_pin = cnp_port_to_ddc_pin(dev_priv, port); | |
5c749c52 AS |
2262 | else if (IS_ICELAKE(dev_priv)) |
2263 | ddc_pin = icl_port_to_ddc_pin(dev_priv, port); | |
cec3bb01 AS |
2264 | else |
2265 | ddc_pin = g4x_port_to_ddc_pin(dev_priv, port); | |
e4ab73a1 VS |
2266 | |
2267 | DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", | |
2268 | ddc_pin, port_name(port)); | |
2269 | ||
2270 | return ddc_pin; | |
2271 | } | |
2272 | ||
385e4de0 VS |
2273 | void intel_infoframe_init(struct intel_digital_port *intel_dig_port) |
2274 | { | |
2275 | struct drm_i915_private *dev_priv = | |
2276 | to_i915(intel_dig_port->base.base.dev); | |
2277 | ||
2278 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
2279 | intel_dig_port->write_infoframe = vlv_write_infoframe; | |
2280 | intel_dig_port->set_infoframes = vlv_set_infoframes; | |
2281 | intel_dig_port->infoframe_enabled = vlv_infoframe_enabled; | |
2282 | } else if (IS_G4X(dev_priv)) { | |
2283 | intel_dig_port->write_infoframe = g4x_write_infoframe; | |
2284 | intel_dig_port->set_infoframes = g4x_set_infoframes; | |
2285 | intel_dig_port->infoframe_enabled = g4x_infoframe_enabled; | |
2286 | } else if (HAS_DDI(dev_priv)) { | |
2287 | intel_dig_port->write_infoframe = hsw_write_infoframe; | |
2288 | intel_dig_port->set_infoframes = hsw_set_infoframes; | |
2289 | intel_dig_port->infoframe_enabled = hsw_infoframe_enabled; | |
2290 | } else if (HAS_PCH_IBX(dev_priv)) { | |
2291 | intel_dig_port->write_infoframe = ibx_write_infoframe; | |
2292 | intel_dig_port->set_infoframes = ibx_set_infoframes; | |
2293 | intel_dig_port->infoframe_enabled = ibx_infoframe_enabled; | |
2294 | } else { | |
2295 | intel_dig_port->write_infoframe = cpt_write_infoframe; | |
2296 | intel_dig_port->set_infoframes = cpt_set_infoframes; | |
2297 | intel_dig_port->infoframe_enabled = cpt_infoframe_enabled; | |
2298 | } | |
2299 | } | |
2300 | ||
00c09d70 PZ |
2301 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
2302 | struct intel_connector *intel_connector) | |
7d57382e | 2303 | { |
b9cb234c PZ |
2304 | struct drm_connector *connector = &intel_connector->base; |
2305 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
2306 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
2307 | struct drm_device *dev = intel_encoder->base.dev; | |
fac5e23e | 2308 | struct drm_i915_private *dev_priv = to_i915(dev); |
8f4f2797 | 2309 | enum port port = intel_encoder->port; |
373a3cf7 | 2310 | |
22f35042 VS |
2311 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2312 | port_name(port)); | |
2313 | ||
ccb1a831 VS |
2314 | if (WARN(intel_dig_port->max_lanes < 4, |
2315 | "Not enough lanes (%d) for HDMI on port %c\n", | |
2316 | intel_dig_port->max_lanes, port_name(port))) | |
2317 | return; | |
2318 | ||
7d57382e | 2319 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 2320 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
2321 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
2322 | ||
c3febcc4 | 2323 | connector->interlace_allowed = 1; |
7d57382e | 2324 | connector->doublescan_allowed = 0; |
573e74ad | 2325 | connector->stereo_allowed = 1; |
66a9278e | 2326 | |
9672a69c | 2327 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
eadc2e51 SS |
2328 | connector->ycbcr_420_allowed = true; |
2329 | ||
e4ab73a1 VS |
2330 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
2331 | ||
f761bef2 | 2332 | if (WARN_ON(port == PORT_A)) |
e4ab73a1 | 2333 | return; |
cf53902f | 2334 | intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); |
7d57382e | 2335 | |
4f8036a2 | 2336 | if (HAS_DDI(dev_priv)) |
bcbc889b PZ |
2337 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2338 | else | |
2339 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
b9cb234c PZ |
2340 | |
2341 | intel_hdmi_add_properties(intel_hdmi, connector); | |
2342 | ||
fdddd08c | 2343 | if (is_hdcp_supported(dev_priv, port)) { |
2320175f SP |
2344 | int ret = intel_hdcp_init(intel_connector, |
2345 | &intel_hdmi_hdcp_shim); | |
2346 | if (ret) | |
2347 | DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); | |
2348 | } | |
2349 | ||
b9cb234c | 2350 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
d8b4c43a | 2351 | intel_hdmi->attached_connector = intel_connector; |
b9cb234c PZ |
2352 | |
2353 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
2354 | * 0xd. Failure to do so will result in spurious interrupts being | |
2355 | * generated on the port when a cable is not attached. | |
2356 | */ | |
50a0bc90 | 2357 | if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) { |
b9cb234c PZ |
2358 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
2359 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
2360 | } | |
2361 | } | |
2362 | ||
c39055b0 | 2363 | void intel_hdmi_init(struct drm_i915_private *dev_priv, |
f0f59a00 | 2364 | i915_reg_t hdmi_reg, enum port port) |
b9cb234c PZ |
2365 | { |
2366 | struct intel_digital_port *intel_dig_port; | |
2367 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
2368 | struct intel_connector *intel_connector; |
2369 | ||
b14c5679 | 2370 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
2371 | if (!intel_dig_port) |
2372 | return; | |
2373 | ||
08d9bc92 | 2374 | intel_connector = intel_connector_alloc(); |
b9cb234c PZ |
2375 | if (!intel_connector) { |
2376 | kfree(intel_dig_port); | |
2377 | return; | |
2378 | } | |
2379 | ||
2380 | intel_encoder = &intel_dig_port->base; | |
b9cb234c | 2381 | |
c39055b0 ACO |
2382 | drm_encoder_init(&dev_priv->drm, &intel_encoder->base, |
2383 | &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS, | |
2384 | "HDMI %c", port_name(port)); | |
00c09d70 | 2385 | |
dba14b27 | 2386 | intel_encoder->hotplug = intel_encoder_hotplug; |
5bfe2ac0 | 2387 | intel_encoder->compute_config = intel_hdmi_compute_config; |
6e266956 | 2388 | if (HAS_PCH_SPLIT(dev_priv)) { |
a4790cec VS |
2389 | intel_encoder->disable = pch_disable_hdmi; |
2390 | intel_encoder->post_disable = pch_post_disable_hdmi; | |
2391 | } else { | |
2392 | intel_encoder->disable = g4x_disable_hdmi; | |
2393 | } | |
00c09d70 | 2394 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; |
045ac3b5 | 2395 | intel_encoder->get_config = intel_hdmi_get_config; |
920a14b2 | 2396 | if (IS_CHERRYVIEW(dev_priv)) { |
9197c88b | 2397 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
2398 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
2399 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 2400 | intel_encoder->post_disable = chv_hdmi_post_disable; |
d6db995f | 2401 | intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable; |
11a914c2 | 2402 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9514ac6e CML |
2403 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
2404 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 2405 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 2406 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 2407 | } else { |
13732ba7 | 2408 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
6e266956 | 2409 | if (HAS_PCH_CPT(dev_priv)) |
d1b1589c | 2410 | intel_encoder->enable = cpt_enable_hdmi; |
6e266956 | 2411 | else if (HAS_PCH_IBX(dev_priv)) |
bf868c7d | 2412 | intel_encoder->enable = ibx_enable_hdmi; |
d1b1589c | 2413 | else |
bf868c7d | 2414 | intel_encoder->enable = g4x_enable_hdmi; |
89b667f8 | 2415 | } |
5ab432ef | 2416 | |
b9cb234c | 2417 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
79f255a0 | 2418 | intel_encoder->power_domain = intel_port_to_power_domain(port); |
03cdc1d4 | 2419 | intel_encoder->port = port; |
920a14b2 | 2420 | if (IS_CHERRYVIEW(dev_priv)) { |
882ec384 VS |
2421 | if (port == PORT_D) |
2422 | intel_encoder->crtc_mask = 1 << 2; | |
2423 | else | |
2424 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
2425 | } else { | |
2426 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
2427 | } | |
301ea74a | 2428 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
2429 | /* |
2430 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
2431 | * to work on real hardware. And since g4x can send infoframes to | |
2432 | * only one port anyway, nothing is lost by allowing it. | |
2433 | */ | |
9beb5fea | 2434 | if (IS_G4X(dev_priv)) |
c6f1495d | 2435 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
7d57382e | 2436 | |
b242b7f7 | 2437 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
f0f59a00 | 2438 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
ccb1a831 | 2439 | intel_dig_port->max_lanes = 4; |
55b7d6e8 | 2440 | |
385e4de0 VS |
2441 | intel_infoframe_init(intel_dig_port); |
2442 | ||
b9cb234c | 2443 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 2444 | } |