[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dvo.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */
#include <linux/i2c.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "dvo.h"

#define SIL164_ADDR	0x38
#define CH7xxx_ADDR	0x76
#define TFP410_ADDR	0x38
#define NS2501_ADDR     0x38

static const struct intel_dvo_device intel_dvo_devices[] = {
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "sil164",
		.dvo_reg = DVOC,
		.slave_addr = SIL164_ADDR,
		.dev_ops = &sil164_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.slave_addr = CH7xxx_ADDR,
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.slave_addr = 0x75, /* For some ch7010 */
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ivch",
		.dvo_reg = DVOA,
		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
		.dev_ops = &ivch_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "tfp410",
		.dvo_reg = DVOC,
		.slave_addr = TFP410_ADDR,
		.dev_ops = &tfp410_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ch7017",
		.dvo_reg = DVOC,
		.slave_addr = 0x75,
		.gpio = GMBUS_PORT_DPB,
		.dev_ops = &ch7017_ops,
	},
	{
	        .type = INTEL_DVO_CHIP_TMDS,
		.name = "ns2501",
		.dvo_reg = DVOC,
		.slave_addr = NS2501_ADDR,
		.dev_ops = &ns2501_ops,
       }
};

struct intel_dvo {
	struct intel_encoder base;

	struct intel_dvo_device dev;

	struct drm_display_mode *panel_fixed_mode;
	bool panel_wants_dither;
};

static struct intel_dvo *enc_to_intel_dvo(struct drm_encoder *encoder)
{
	return container_of(encoder, struct intel_dvo, base.base);
}

static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
{
	return container_of(intel_attached_encoder(connector),
			    struct intel_dvo, base);
}

static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);

	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
}

static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
				   enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_intel_dvo(&encoder->base);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	if (!(tmp & DVO_ENABLE))
		return false;

	*pipe = PORT_TO_PIPE(tmp);

	return true;
}

static void intel_disable_dvo(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_intel_dvo(&encoder->base);
	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	I915_READ(dvo_reg);
}

static void intel_enable_dvo(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_intel_dvo(&encoder->base);
	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
	I915_READ(dvo_reg);
	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
}

static void intel_dvo_dpms(struct drm_connector *connector, int mode)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	struct drm_crtc *crtc;

	/* dvo supports only 2 dpms states. */
	if (mode != DRM_MODE_DPMS_ON)
		mode = DRM_MODE_DPMS_OFF;

	if (mode == connector->dpms)
		return;

	connector->dpms = mode;

	/* Only need to change hw state when actually enabled */
	crtc = intel_dvo->base.base.crtc;
	if (!crtc) {
		intel_dvo->base.connectors_active = false;
		return;
	}

	if (mode == DRM_MODE_DPMS_ON) {
		intel_dvo->base.connectors_active = true;

		intel_crtc_update_dpms(crtc);

		intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
	} else {
		intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);

		intel_dvo->base.connectors_active = false;

		intel_crtc_update_dpms(crtc);
	}

	intel_modeset_check_state(connector->dev);
}

static int intel_dvo_mode_valid(struct drm_connector *connector,
				struct drm_display_mode *mode)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	/* XXX: Validate clock range */

	if (intel_dvo->panel_fixed_mode) {
		if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
			return MODE_PANEL;
		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
			return MODE_PANEL;
	}

	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
}

static bool intel_dvo_mode_fixup(struct drm_encoder *encoder,
				 const struct drm_display_mode *mode,
				 struct drm_display_mode *adjusted_mode)
{
	struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);

	/* If we have timings from the BIOS for the panel, put them in
	 * to the adjusted mode.  The CRTC will be set up for this mode,
	 * with the panel scaling set up to source from the H/VDisplay
	 * of the original mode.
	 */
	if (intel_dvo->panel_fixed_mode != NULL) {
#define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x
		C(hdisplay);
		C(hsync_start);
		C(hsync_end);
		C(htotal);
		C(vdisplay);
		C(vsync_start);
		C(vsync_end);
		C(vtotal);
		C(clock);
#undef C
	}

	if (intel_dvo->dev.dev_ops->mode_fixup)
		return intel_dvo->dev.dev_ops->mode_fixup(&intel_dvo->dev, mode, adjusted_mode);

	return true;
}

static void intel_dvo_mode_set(struct drm_encoder *encoder,
			       struct drm_display_mode *mode,
			       struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
	int pipe = intel_crtc->pipe;
	u32 dvo_val;
	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
	int dpll_reg = DPLL(pipe);

	switch (dvo_reg) {
	case DVOA:
	default:
		dvo_srcdim_reg = DVOA_SRCDIM;
		break;
	case DVOB:
		dvo_srcdim_reg = DVOB_SRCDIM;
		break;
	case DVOC:
		dvo_srcdim_reg = DVOC_SRCDIM;
		break;
	}

	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, mode, adjusted_mode);

	/* Save the data order, since I don't know what it should be set to. */
	dvo_val = I915_READ(dvo_reg) &
		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
		   DVO_BLANK_ACTIVE_HIGH;

	if (pipe == 1)
		dvo_val |= DVO_PIPE_B_SELECT;
	dvo_val |= DVO_PIPE_STALL;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;

	I915_WRITE(dpll_reg, I915_READ(dpll_reg) | DPLL_DVO_HIGH_SPEED);

	/*I915_WRITE(DVOB_SRCDIM,
	  (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
	  (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	I915_WRITE(dvo_srcdim_reg,
		   (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
		   (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	/*I915_WRITE(DVOB, dvo_val);*/
	I915_WRITE(dvo_reg, dvo_val);
}

/**
 * Detect the output connection on our DVO device.
 *
 * Unimplemented.
 */
static enum drm_connector_status
intel_dvo_detect(struct drm_connector *connector, bool force)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
}

static int intel_dvo_get_modes(struct drm_connector *connector)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	/* We should probably have an i2c driver get_modes function for those
	 * devices which will have a fixed set of modes determined by the chip
	 * (TV-out, for example), but for now with just TMDS and LVDS,
	 * that's not the case.
	 */
	intel_ddc_get_modes(connector,
			    intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC));
	if (!list_empty(&connector->probed_modes))
		return 1;

	if (intel_dvo->panel_fixed_mode != NULL) {
		struct drm_display_mode *mode;
		mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode);
		if (mode) {
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}

	return 0;
}

static void intel_dvo_destroy(struct drm_connector *connector)
{
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
	kfree(connector);
}

static const struct drm_encoder_helper_funcs intel_dvo_helper_funcs = {
	.mode_fixup = intel_dvo_mode_fixup,
	.mode_set = intel_dvo_mode_set,
};

static const struct drm_connector_funcs intel_dvo_connector_funcs = {
	.dpms = intel_dvo_dpms,
	.detect = intel_dvo_detect,
	.destroy = intel_dvo_destroy,
	.fill_modes = drm_helper_probe_single_connector_modes,
};

static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	.mode_valid = intel_dvo_mode_valid,
	.get_modes = intel_dvo_get_modes,
	.best_encoder = intel_best_encoder,
};

static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
{
	struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);

	if (intel_dvo->dev.dev_ops->destroy)
		intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);

	kfree(intel_dvo->panel_fixed_mode);

	intel_encoder_destroy(encoder);
}

static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	.destroy = intel_dvo_enc_destroy,
};

/**
 * Attempts to get a fixed panel timing for LVDS (currently only the i830).
 *
 * Other chips with DVO LVDS will need to extend this to deal with the LVDS
 * chip being on DVOB/C and having multiple pipes.
 */
static struct drm_display_mode *
intel_dvo_get_current_mode(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
	struct drm_display_mode *mode = NULL;

	/* If the DVO port is active, that'll be the LVDS, so we can pull out
	 * its timings to get how the BIOS set up the panel.
	 */
	if (dvo_val & DVO_ENABLE) {
		struct drm_crtc *crtc;
		int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0;

		crtc = intel_get_crtc_for_pipe(dev, pipe);
		if (crtc) {
			mode = intel_crtc_mode_get(dev, crtc);
			if (mode) {
				mode->type |= DRM_MODE_TYPE_PREFERRED;
				if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
					mode->flags |= DRM_MODE_FLAG_PHSYNC;
				if (dvo_val & DVO_VSYNC_ACTIVE_HIGH)
					mode->flags |= DRM_MODE_FLAG_PVSYNC;
			}
		}
	}

	return mode;
}

void intel_dvo_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	struct intel_dvo *intel_dvo;
	struct intel_connector *intel_connector;
	int i;
	int encoder_type = DRM_MODE_ENCODER_NONE;

	intel_dvo = kzalloc(sizeof(struct intel_dvo), GFP_KERNEL);
	if (!intel_dvo)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_dvo);
		return;
	}

	intel_encoder = &intel_dvo->base;
	drm_encoder_init(dev, &intel_encoder->base,
			 &intel_dvo_enc_funcs, encoder_type);

	intel_encoder->disable = intel_disable_dvo;
	intel_encoder->enable = intel_enable_dvo;
	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;

	/* Now, try to find a controller */
	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
		struct drm_connector *connector = &intel_connector->base;
		const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
		struct i2c_adapter *i2c;
		int gpio;
		bool dvoinit;

		/* Allow the I2C driver info to specify the GPIO to be used in
		 * special cases, but otherwise default to what's defined
		 * in the spec.
		 */
		if (intel_gmbus_is_port_valid(dvo->gpio))
			gpio = dvo->gpio;
		else if (dvo->type == INTEL_DVO_CHIP_LVDS)
			gpio = GMBUS_PORT_SSC;
		else
			gpio = GMBUS_PORT_DPB;

		/* Set up the I2C bus necessary for the chip we're probing.
		 * It appears that everything is on GPIOE except for panels
		 * on i830 laptops, which are on GPIOB (DVOA).
		 */
		i2c = intel_gmbus_get_adapter(dev_priv, gpio);

		intel_dvo->dev = *dvo;

		/* GMBUS NAK handling seems to be unstable, hence let the
		 * transmitter detection run in bit banging mode for now.
		 */
		intel_gmbus_force_bit(i2c, true);

		dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);

		intel_gmbus_force_bit(i2c, false);

		if (!dvoinit)
			continue;

		intel_encoder->type = INTEL_OUTPUT_DVO;
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
		switch (dvo->type) {
		case INTEL_DVO_CHIP_TMDS:
			intel_encoder->cloneable = true;
			drm_connector_init(dev, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_DVII);
			encoder_type = DRM_MODE_ENCODER_TMDS;
			break;
		case INTEL_DVO_CHIP_LVDS:
			intel_encoder->cloneable = false;
			drm_connector_init(dev, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_LVDS);
			encoder_type = DRM_MODE_ENCODER_LVDS;
			break;
		}

		drm_connector_helper_add(connector,
					 &intel_dvo_connector_helper_funcs);
		connector->display_info.subpixel_order = SubPixelHorizontalRGB;
		connector->interlace_allowed = false;
		connector->doublescan_allowed = false;

		drm_encoder_helper_add(&intel_encoder->base,
				       &intel_dvo_helper_funcs);

		intel_connector_attach_encoder(intel_connector, intel_encoder);
		if (dvo->type == INTEL_DVO_CHIP_LVDS) {
			/* For our LVDS chipsets, we should hopefully be able
			 * to dig the fixed panel mode out of the BIOS data.
			 * However, it's in a different format from the BIOS
			 * data on chipsets with integrated LVDS (stored in AIM
			 * headers, likely), so for now, just get the current
			 * mode being output through DVO.
			 */
			intel_dvo->panel_fixed_mode =
				intel_dvo_get_current_mode(connector);
			intel_dvo->panel_wants_dither = true;
		}

		drm_sysfs_connector_add(connector);
		return;
	}

	drm_encoder_cleanup(&intel_encoder->base);
	kfree(intel_dvo);
	kfree(intel_connector);
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2007 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	*/
	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
760285e7 DH	29	#include <drm/drmP.h>
760285e7 DH	30	#include <drm/drm_crtc.h>
79e53945	31	#include "intel_drv.h"
760285e7	32	#include <drm/i915_drm.h>
79e53945 JB	33	#include "i915_drv.h"
	34	#include "dvo.h"
	35
	36	#define SIL164_ADDR 0x38
	37	#define CH7xxx_ADDR 0x76
	38	#define TFP410_ADDR 0x38
7434a255	39	#define NS2501_ADDR 0x38
79e53945	40
ea5b213a	41	static const struct intel_dvo_device intel_dvo_devices[] = {
79e53945 JB	42	{
	43	.type = INTEL_DVO_CHIP_TMDS,
	44	.name = "sil164",
	45	.dvo_reg = DVOC,
	46	.slave_addr = SIL164_ADDR,
	47	.dev_ops = &sil164_ops,
	48	},
	49	{
	50	.type = INTEL_DVO_CHIP_TMDS,
	51	.name = "ch7xxx",
	52	.dvo_reg = DVOC,
	53	.slave_addr = CH7xxx_ADDR,
	54	.dev_ops = &ch7xxx_ops,
	55	},
98304ad1	56	{
	57	.type = INTEL_DVO_CHIP_TMDS,
	58	.name = "ch7xxx",
	59	.dvo_reg = DVOC,
	60	.slave_addr = 0x75, /* For some ch7010 */
	61	.dev_ops = &ch7xxx_ops,
	62	},
79e53945 JB	63	{
	64	.type = INTEL_DVO_CHIP_LVDS,
	65	.name = "ivch",
	66	.dvo_reg = DVOA,
	67	.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
	68	.dev_ops = &ivch_ops,
	69	},
	70	{
	71	.type = INTEL_DVO_CHIP_TMDS,
	72	.name = "tfp410",
	73	.dvo_reg = DVOC,
	74	.slave_addr = TFP410_ADDR,
	75	.dev_ops = &tfp410_ops,
	76	},
	77	{
	78	.type = INTEL_DVO_CHIP_LVDS,
	79	.name = "ch7017",
	80	.dvo_reg = DVOC,
	81	.slave_addr = 0x75,
a6b17b43	82	.gpio = GMBUS_PORT_DPB,
79e53945	83	.dev_ops = &ch7017_ops,
7434a255 TR	84	},
	85	{
	86	.type = INTEL_DVO_CHIP_TMDS,
	87	.name = "ns2501",
	88	.dvo_reg = DVOC,
	89	.slave_addr = NS2501_ADDR,
	90	.dev_ops = &ns2501_ops,
	91	}
79e53945 JB	92	};
79e53945 JB	93
ea5b213a CW	94	struct intel_dvo {
	95	struct intel_encoder base;
	96
	97	struct intel_dvo_device dev;
	98
	99	struct drm_display_mode *panel_fixed_mode;
	100	bool panel_wants_dither;
	101	};
	102
	103	static struct intel_dvo enc_to_intel_dvo(struct drm_encoder encoder)
	104	{
4ef69c7a	105	return container_of(encoder, struct intel_dvo, base.base);
ea5b213a CW	106	}
ea5b213a CW	107
df0e9248 CW	108	static struct intel_dvo intel_attached_dvo(struct drm_connector connector)
	109	{
	110	return container_of(intel_attached_encoder(connector),
	111	struct intel_dvo, base);
	112	}
	113
732ce74f	114	static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
79e53945	115	{
732ce74f DV	116	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
	117
	118	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
	119	}
	120
	121	static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
	122	enum pipe *pipe)
	123	{
	124	struct drm_device *dev = encoder->base.dev;
	125	struct drm_i915_private *dev_priv = dev->dev_private;
	126	struct intel_dvo *intel_dvo = enc_to_intel_dvo(&encoder->base);
	127	u32 tmp;
	128
	129	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	130
	131	if (!(tmp & DVO_ENABLE))
	132	return false;
	133
	134	*pipe = PORT_TO_PIPE(tmp);
	135
	136	return true;
	137	}
	138
19c63fa8 DV	139	static void intel_disable_dvo(struct intel_encoder *encoder)
	140	{
	141	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	142	struct intel_dvo *intel_dvo = enc_to_intel_dvo(&encoder->base);
	143	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	144	u32 temp = I915_READ(dvo_reg);
	145
	146	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	147	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	148	I915_READ(dvo_reg);
	149	}
	150
	151	static void intel_enable_dvo(struct intel_encoder *encoder)
	152	{
	153	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	154	struct intel_dvo *intel_dvo = enc_to_intel_dvo(&encoder->base);
ea5b213a	155	u32 dvo_reg = intel_dvo->dev.dvo_reg;
79e53945 JB	156	u32 temp = I915_READ(dvo_reg);
79e53945 JB	157
19c63fa8 DV	158	I915_WRITE(dvo_reg, temp \| DVO_ENABLE);
	159	I915_READ(dvo_reg);
	160	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
	161	}
	162
b2cabb0e	163	static void intel_dvo_dpms(struct drm_connector *connector, int mode)
79e53945	164	{
b2cabb0e DV	165	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	166	struct drm_crtc *crtc;
	167
	168	/* dvo supports only 2 dpms states. */
	169	if (mode != DRM_MODE_DPMS_ON)
	170	mode = DRM_MODE_DPMS_OFF;
	171
	172	if (mode == connector->dpms)
	173	return;
	174
	175	connector->dpms = mode;
	176
	177	/* Only need to change hw state when actually enabled */
	178	crtc = intel_dvo->base.base.crtc;
	179	if (!crtc) {
	180	intel_dvo->base.connectors_active = false;
	181	return;
	182	}
79e53945 JB	183
79e53945 JB	184	if (mode == DRM_MODE_DPMS_ON) {
b2cabb0e DV	185	intel_dvo->base.connectors_active = true;
	186
	187	intel_crtc_update_dpms(crtc);
	188
fac3274c	189	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
79e53945	190	} else {
fac3274c	191	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
b2cabb0e DV	192
	193	intel_dvo->base.connectors_active = false;
	194
	195	intel_crtc_update_dpms(crtc);
79e53945	196	}
0a91ca29	197
b980514c	198	intel_modeset_check_state(connector->dev);
79e53945 JB	199	}
79e53945 JB	200
79e53945 JB	201	static int intel_dvo_mode_valid(struct drm_connector *connector,
	202	struct drm_display_mode *mode)
	203	{
df0e9248	204	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
79e53945 JB	205
	206	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	207	return MODE_NO_DBLESCAN;
	208
	209	/* XXX: Validate clock range */
	210
ea5b213a CW	211	if (intel_dvo->panel_fixed_mode) {
ea5b213a CW	212	if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
79e53945	213	return MODE_PANEL;
ea5b213a	214	if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
79e53945 JB	215	return MODE_PANEL;
	216	}
	217
ea5b213a	218	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
79e53945 JB	219	}
	220
	221	static bool intel_dvo_mode_fixup(struct drm_encoder *encoder,
e811f5ae	222	const struct drm_display_mode *mode,
79e53945 JB	223	struct drm_display_mode *adjusted_mode)
79e53945 JB	224	{
ea5b213a	225	struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
79e53945 JB	226
	227	/* If we have timings from the BIOS for the panel, put them in
	228	* to the adjusted mode. The CRTC will be set up for this mode,
	229	* with the panel scaling set up to source from the H/VDisplay
	230	* of the original mode.
	231	*/
ea5b213a CW	232	if (intel_dvo->panel_fixed_mode != NULL) {
ea5b213a CW	233	#define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x
79e53945 JB	234	C(hdisplay);
	235	C(hsync_start);
	236	C(hsync_end);
	237	C(htotal);
	238	C(vdisplay);
	239	C(vsync_start);
	240	C(vsync_end);
	241	C(vtotal);
	242	C(clock);
79e53945 JB	243	#undef C
	244	}
	245
ea5b213a CW	246	if (intel_dvo->dev.dev_ops->mode_fixup)
ea5b213a CW	247	return intel_dvo->dev.dev_ops->mode_fixup(&intel_dvo->dev, mode, adjusted_mode);
79e53945 JB	248
	249	return true;
	250	}
	251
	252	static void intel_dvo_mode_set(struct drm_encoder *encoder,
	253	struct drm_display_mode *mode,
	254	struct drm_display_mode *adjusted_mode)
	255	{
	256	struct drm_device *dev = encoder->dev;
	257	struct drm_i915_private *dev_priv = dev->dev_private;
	258	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
ea5b213a	259	struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
79e53945 JB	260	int pipe = intel_crtc->pipe;
79e53945 JB	261	u32 dvo_val;
ea5b213a	262	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
9db4a9c7	263	int dpll_reg = DPLL(pipe);
79e53945 JB	264
	265	switch (dvo_reg) {
	266	case DVOA:
	267	default:
	268	dvo_srcdim_reg = DVOA_SRCDIM;
	269	break;
	270	case DVOB:
	271	dvo_srcdim_reg = DVOB_SRCDIM;
	272	break;
	273	case DVOC:
	274	dvo_srcdim_reg = DVOC_SRCDIM;
	275	break;
	276	}
	277
ea5b213a	278	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev, mode, adjusted_mode);
79e53945 JB	279
	280	/* Save the data order, since I don't know what it should be set to. */
	281	dvo_val = I915_READ(dvo_reg) &
	282	(DVO_PRESERVE_MASK \| DVO_DATA_ORDER_GBRG);
	283	dvo_val \|= DVO_DATA_ORDER_FP \| DVO_BORDER_ENABLE \|
	284	DVO_BLANK_ACTIVE_HIGH;
	285
	286	if (pipe == 1)
	287	dvo_val \|= DVO_PIPE_B_SELECT;
	288	dvo_val \|= DVO_PIPE_STALL;
	289	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	290	dvo_val \|= DVO_HSYNC_ACTIVE_HIGH;
	291	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	292	dvo_val \|= DVO_VSYNC_ACTIVE_HIGH;
	293
	294	I915_WRITE(dpll_reg, I915_READ(dpll_reg) \| DPLL_DVO_HIGH_SPEED);
	295
	296	/*I915_WRITE(DVOB_SRCDIM,
	297	(adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
	298	(adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	299	I915_WRITE(dvo_srcdim_reg,
	300	(adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
	301	(adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	302	/I915_WRITE(DVOB, dvo_val);/
	303	I915_WRITE(dvo_reg, dvo_val);
	304	}
	305
	306	/**
	307	* Detect the output connection on our DVO device.
	308	*
	309	* Unimplemented.
	310	*/
7b334fcb	311	static enum drm_connector_status
930a9e28	312	intel_dvo_detect(struct drm_connector *connector, bool force)
79e53945	313	{
df0e9248	314	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
ea5b213a	315	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
79e53945 JB	316	}
	317
	318	static int intel_dvo_get_modes(struct drm_connector *connector)
	319	{
df0e9248	320	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
f899fc64	321	struct drm_i915_private *dev_priv = connector->dev->dev_private;
79e53945 JB	322
	323	/* We should probably have an i2c driver get_modes function for those
	324	* devices which will have a fixed set of modes determined by the chip
	325	* (TV-out, for example), but for now with just TMDS and LVDS,
	326	* that's not the case.
	327	*/
f899fc64	328	intel_ddc_get_modes(connector,
3bd7d909	329	intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC));
79e53945 JB	330	if (!list_empty(&connector->probed_modes))
	331	return 1;
	332
ea5b213a	333	if (intel_dvo->panel_fixed_mode != NULL) {
79e53945	334	struct drm_display_mode *mode;
ea5b213a	335	mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode);
79e53945 JB	336	if (mode) {
	337	drm_mode_probed_add(connector, mode);
	338	return 1;
	339	}
	340	}
ea5b213a	341
79e53945 JB	342	return 0;
	343	}
	344
ea5b213a	345	static void intel_dvo_destroy(struct drm_connector *connector)
79e53945	346	{
79e53945 JB	347	drm_sysfs_connector_remove(connector);
79e53945 JB	348	drm_connector_cleanup(connector);
599be16c	349	kfree(connector);
79e53945	350	}
79e53945 JB	351
79e53945 JB	352	static const struct drm_encoder_helper_funcs intel_dvo_helper_funcs = {
79e53945	353	.mode_fixup = intel_dvo_mode_fixup,
79e53945	354	.mode_set = intel_dvo_mode_set,
79e53945 JB	355	};
	356
	357	static const struct drm_connector_funcs intel_dvo_connector_funcs = {
b2cabb0e	358	.dpms = intel_dvo_dpms,
79e53945 JB	359	.detect = intel_dvo_detect,
	360	.destroy = intel_dvo_destroy,
	361	.fill_modes = drm_helper_probe_single_connector_modes,
	362	};
	363
	364	static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	365	.mode_valid = intel_dvo_mode_valid,
	366	.get_modes = intel_dvo_get_modes,
df0e9248	367	.best_encoder = intel_best_encoder,
79e53945 JB	368	};
79e53945 JB	369
b358d0a6	370	static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
79e53945	371	{
ea5b213a CW	372	struct intel_dvo *intel_dvo = enc_to_intel_dvo(encoder);
	373
	374	if (intel_dvo->dev.dev_ops->destroy)
	375	intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
	376
	377	kfree(intel_dvo->panel_fixed_mode);
	378
	379	intel_encoder_destroy(encoder);
79e53945 JB	380	}
	381
	382	static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	383	.destroy = intel_dvo_enc_destroy,
	384	};
	385
79e53945 JB	386	/**
	387	* Attempts to get a fixed panel timing for LVDS (currently only the i830).
	388	*
	389	* Other chips with DVO LVDS will need to extend this to deal with the LVDS
	390	* chip being on DVOB/C and having multiple pipes.
	391	*/
	392	static struct drm_display_mode *
ea5b213a	393	intel_dvo_get_current_mode(struct drm_connector *connector)
79e53945 JB	394	{
	395	struct drm_device *dev = connector->dev;
	396	struct drm_i915_private *dev_priv = dev->dev_private;
df0e9248	397	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
ea5b213a	398	uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
79e53945 JB	399	struct drm_display_mode *mode = NULL;
	400
	401	/* If the DVO port is active, that'll be the LVDS, so we can pull out
	402	* its timings to get how the BIOS set up the panel.
	403	*/
	404	if (dvo_val & DVO_ENABLE) {
	405	struct drm_crtc *crtc;
	406	int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0;
	407
f875c15a	408	crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945 JB	409	if (crtc) {
79e53945 JB	410	mode = intel_crtc_mode_get(dev, crtc);
79e53945 JB	411	if (mode) {
	412	mode->type \|= DRM_MODE_TYPE_PREFERRED;
	413	if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
	414	mode->flags \|= DRM_MODE_FLAG_PHSYNC;
	415	if (dvo_val & DVO_VSYNC_ACTIVE_HIGH)
	416	mode->flags \|= DRM_MODE_FLAG_PVSYNC;
	417	}
	418	}
	419	}
ea5b213a	420
79e53945 JB	421	return mode;
	422	}
	423
	424	void intel_dvo_init(struct drm_device *dev)
	425	{
f899fc64	426	struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37	427	struct intel_encoder *intel_encoder;
ea5b213a	428	struct intel_dvo *intel_dvo;
599be16c	429	struct intel_connector *intel_connector;
79e53945	430	int i;
79e53945	431	int encoder_type = DRM_MODE_ENCODER_NONE;
ea5b213a CW	432
	433	intel_dvo = kzalloc(sizeof(struct intel_dvo), GFP_KERNEL);
	434	if (!intel_dvo)
79e53945 JB	435	return;
79e53945 JB	436
599be16c ZW	437	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
599be16c ZW	438	if (!intel_connector) {
ea5b213a	439	kfree(intel_dvo);
599be16c ZW	440	return;
	441	}
	442
ea5b213a	443	intel_encoder = &intel_dvo->base;
373a3cf7 CW	444	drm_encoder_init(dev, &intel_encoder->base,
373a3cf7 CW	445	&intel_dvo_enc_funcs, encoder_type);
ea5b213a	446
19c63fa8 DV	447	intel_encoder->disable = intel_disable_dvo;
19c63fa8 DV	448	intel_encoder->enable = intel_enable_dvo;
732ce74f DV	449	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
732ce74f DV	450	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
19c63fa8	451
79e53945 JB	452	/* Now, try to find a controller */
79e53945 JB	453	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
599be16c	454	struct drm_connector *connector = &intel_connector->base;
ea5b213a	455	const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
f899fc64	456	struct i2c_adapter *i2c;
79e53945	457	int gpio;
e4bfff54	458	bool dvoinit;
79e53945	459
79e53945 JB	460	/* Allow the I2C driver info to specify the GPIO to be used in
	461	* special cases, but otherwise default to what's defined
	462	* in the spec.
	463	*/
3bd7d909	464	if (intel_gmbus_is_port_valid(dvo->gpio))
79e53945 JB	465	gpio = dvo->gpio;
79e53945 JB	466	else if (dvo->type == INTEL_DVO_CHIP_LVDS)
f573c660	467	gpio = GMBUS_PORT_SSC;
79e53945	468	else
a6b17b43	469	gpio = GMBUS_PORT_DPB;
79e53945 JB	470
	471	/* Set up the I2C bus necessary for the chip we're probing.
	472	* It appears that everything is on GPIOE except for panels
	473	* on i830 laptops, which are on GPIOB (DVOA).
	474	*/
3bd7d909	475	i2c = intel_gmbus_get_adapter(dev_priv, gpio);
79e53945	476
ea5b213a	477	intel_dvo->dev = *dvo;
e4bfff54 DMEA	478
	479	/* GMBUS NAK handling seems to be unstable, hence let the
	480	* transmitter detection run in bit banging mode for now.
	481	*/
	482	intel_gmbus_force_bit(i2c, true);
	483
	484	dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
	485
	486	intel_gmbus_force_bit(i2c, false);
	487
	488	if (!dvoinit)
79e53945 JB	489	continue;
79e53945 JB	490
21d40d37 EA	491	intel_encoder->type = INTEL_OUTPUT_DVO;
21d40d37 EA	492	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
79e53945 JB	493	switch (dvo->type) {
79e53945 JB	494	case INTEL_DVO_CHIP_TMDS:
66a9278e	495	intel_encoder->cloneable = true;
79e53945 JB	496	drm_connector_init(dev, connector,
	497	&intel_dvo_connector_funcs,
	498	DRM_MODE_CONNECTOR_DVII);
	499	encoder_type = DRM_MODE_ENCODER_TMDS;
	500	break;
	501	case INTEL_DVO_CHIP_LVDS:
66a9278e	502	intel_encoder->cloneable = false;
79e53945 JB	503	drm_connector_init(dev, connector,
	504	&intel_dvo_connector_funcs,
	505	DRM_MODE_CONNECTOR_LVDS);
	506	encoder_type = DRM_MODE_ENCODER_LVDS;
	507	break;
	508	}
	509
	510	drm_connector_helper_add(connector,
	511	&intel_dvo_connector_helper_funcs);
	512	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
	513	connector->interlace_allowed = false;
	514	connector->doublescan_allowed = false;
	515
4ef69c7a	516	drm_encoder_helper_add(&intel_encoder->base,
79e53945 JB	517	&intel_dvo_helper_funcs);
79e53945 JB	518
df0e9248	519	intel_connector_attach_encoder(intel_connector, intel_encoder);
79e53945 JB	520	if (dvo->type == INTEL_DVO_CHIP_LVDS) {
	521	/* For our LVDS chipsets, we should hopefully be able
	522	* to dig the fixed panel mode out of the BIOS data.
	523	* However, it's in a different format from the BIOS
	524	* data on chipsets with integrated LVDS (stored in AIM
	525	* headers, likely), so for now, just get the current
	526	* mode being output through DVO.
	527	*/
ea5b213a	528	intel_dvo->panel_fixed_mode =
79e53945	529	intel_dvo_get_current_mode(connector);
ea5b213a	530	intel_dvo->panel_wants_dither = true;
79e53945 JB	531	}
	532
	533	drm_sysfs_connector_add(connector);
	534	return;
	535	}
	536
373a3cf7	537	drm_encoder_cleanup(&intel_encoder->base);
ea5b213a	538	kfree(intel_dvo);
599be16c	539	kfree(intel_connector);
79e53945	540	}