[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dvo.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */
#include <linux/i2c.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "dvo.h"

#define SIL164_ADDR	0x38
#define CH7xxx_ADDR	0x76
#define TFP410_ADDR	0x38
#define NS2501_ADDR     0x38

static const struct intel_dvo_device intel_dvo_devices[] = {
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "sil164",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = SIL164_ADDR,
		.dev_ops = &sil164_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = CH7xxx_ADDR,
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = 0x75, /* For some ch7010 */
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ivch",
		.dvo_reg = DVOA,
		.dvo_srcdim_reg = DVOA_SRCDIM,
		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
		.dev_ops = &ivch_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "tfp410",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = TFP410_ADDR,
		.dev_ops = &tfp410_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ch7017",
		.dvo_reg = DVOC,
		.dvo_srcdim_reg = DVOC_SRCDIM,
		.slave_addr = 0x75,
		.gpio = GMBUS_PIN_DPB,
		.dev_ops = &ch7017_ops,
	},
	{
	        .type = INTEL_DVO_CHIP_TMDS,
		.name = "ns2501",
		.dvo_reg = DVOB,
		.dvo_srcdim_reg = DVOB_SRCDIM,
		.slave_addr = NS2501_ADDR,
		.dev_ops = &ns2501_ops,
       }
};

struct intel_dvo {
	struct intel_encoder base;

	struct intel_dvo_device dev;

	struct intel_connector *attached_connector;

	bool panel_wants_dither;
};

static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
{
	return container_of(encoder, struct intel_dvo, base);
}

static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
{
	return enc_to_dvo(intel_attached_encoder(connector));
}

static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
{
	struct drm_device *dev = connector->base.dev;
	struct drm_i915_private *dev_priv = to_i915(dev);
	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	if (!(tmp & DVO_ENABLE))
		return false;

	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
}

static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
				   enum pipe *pipe)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;

	return tmp & DVO_ENABLE;
}

static void intel_dvo_get_config(struct intel_encoder *encoder,
				 struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp, flags = 0;

	pipe_config->output_types |= BIT(INTEL_OUTPUT_DVO);

	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

	pipe_config->base.adjusted_mode.flags |= flags;

	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}

static void intel_disable_dvo(struct intel_encoder *encoder,
			      const struct intel_crtc_state *old_crtc_state,
			      const struct drm_connector_state *old_conn_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	I915_READ(dvo_reg);
}

static void intel_enable_dvo(struct intel_encoder *encoder,
			     const struct intel_crtc_state *pipe_config,
			     const struct drm_connector_state *conn_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
					 &pipe_config->base.mode,
					 &pipe_config->base.adjusted_mode);

	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
	I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
}

static enum drm_mode_status
intel_dvo_mode_valid(struct drm_connector *connector,
		     struct drm_display_mode *mode)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	const struct drm_display_mode *fixed_mode =
		to_intel_connector(connector)->panel.fixed_mode;
	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
	int target_clock = mode->clock;

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	/* XXX: Validate clock range */

	if (fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
			return MODE_PANEL;
		if (mode->vdisplay > fixed_mode->vdisplay)
			return MODE_PANEL;

		target_clock = fixed_mode->clock;
	}

	if (target_clock > max_dotclk)
		return MODE_CLOCK_HIGH;

	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
}

static bool intel_dvo_compute_config(struct intel_encoder *encoder,
				     struct intel_crtc_state *pipe_config,
				     struct drm_connector_state *conn_state)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	const struct drm_display_mode *fixed_mode =
		intel_dvo->attached_connector->panel.fixed_mode;
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;

	/*
	 * If we have timings from the BIOS for the panel, put them in
	 * to the adjusted mode.  The CRTC will be set up for this mode,
	 * with the panel scaling set up to source from the H/VDisplay
	 * of the original mode.
	 */
	if (fixed_mode)
		intel_fixed_panel_mode(fixed_mode, adjusted_mode);

	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return false;

	return true;
}

static void intel_dvo_pre_enable(struct intel_encoder *encoder,
				 const struct intel_crtc_state *pipe_config,
				 const struct drm_connector_state *conn_state)
{
	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	int pipe = crtc->pipe;
	u32 dvo_val;
	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
	i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;

	/* Save the data order, since I don't know what it should be set to. */
	dvo_val = I915_READ(dvo_reg) &
		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
		   DVO_BLANK_ACTIVE_HIGH;

	dvo_val |= DVO_PIPE_SEL(pipe);
	dvo_val |= DVO_PIPE_STALL;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;

	/*I915_WRITE(DVOB_SRCDIM,
	  (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
	  (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	I915_WRITE(dvo_srcdim_reg,
		   (adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
		   (adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	/*I915_WRITE(DVOB, dvo_val);*/
	I915_WRITE(dvo_reg, dvo_val);
}

static enum drm_connector_status
intel_dvo_detect(struct drm_connector *connector, bool force)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
}

static int intel_dvo_get_modes(struct drm_connector *connector)
{
	struct drm_i915_private *dev_priv = to_i915(connector->dev);
	const struct drm_display_mode *fixed_mode =
		to_intel_connector(connector)->panel.fixed_mode;

	/*
	 * We should probably have an i2c driver get_modes function for those
	 * devices which will have a fixed set of modes determined by the chip
	 * (TV-out, for example), but for now with just TMDS and LVDS,
	 * that's not the case.
	 */
	intel_ddc_get_modes(connector,
			    intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC));
	if (!list_empty(&connector->probed_modes))
		return 1;

	if (fixed_mode) {
		struct drm_display_mode *mode;
		mode = drm_mode_duplicate(connector->dev, fixed_mode);
		if (mode) {
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}

	return 0;
}

static void intel_dvo_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
	intel_panel_fini(&to_intel_connector(connector)->panel);
	kfree(connector);
}

static const struct drm_connector_funcs intel_dvo_connector_funcs = {
	.detect = intel_dvo_detect,
	.late_register = intel_connector_register,
	.early_unregister = intel_connector_unregister,
	.destroy = intel_dvo_destroy,
	.fill_modes = drm_helper_probe_single_connector_modes,
	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
};

static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	.mode_valid = intel_dvo_mode_valid,
	.get_modes = intel_dvo_get_modes,
};

static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));

	if (intel_dvo->dev.dev_ops->destroy)
		intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);

	intel_encoder_destroy(encoder);
}

static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	.destroy = intel_dvo_enc_destroy,
};

/*
 * Attempts to get a fixed panel timing for LVDS (currently only the i830).
 *
 * Other chips with DVO LVDS will need to extend this to deal with the LVDS
 * chip being on DVOB/C and having multiple pipes.
 */
static struct drm_display_mode *
intel_dvo_get_current_mode(struct intel_encoder *encoder)
{
	struct drm_display_mode *mode;

	mode = intel_encoder_current_mode(encoder);
	if (mode) {
		DRM_DEBUG_KMS("using current (BIOS) mode: ");
		drm_mode_debug_printmodeline(mode);
		mode->type |= DRM_MODE_TYPE_PREFERRED;
	}

	return mode;
}

static enum port intel_dvo_port(i915_reg_t dvo_reg)
{
	if (i915_mmio_reg_equal(dvo_reg, DVOA))
		return PORT_A;
	else if (i915_mmio_reg_equal(dvo_reg, DVOB))
		return PORT_B;
	else
		return PORT_C;
}

void intel_dvo_init(struct drm_i915_private *dev_priv)
{
	struct intel_encoder *intel_encoder;
	struct intel_dvo *intel_dvo;
	struct intel_connector *intel_connector;
	int i;
	int encoder_type = DRM_MODE_ENCODER_NONE;

	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
	if (!intel_dvo)
		return;

	intel_connector = intel_connector_alloc();
	if (!intel_connector) {
		kfree(intel_dvo);
		return;
	}

	intel_dvo->attached_connector = intel_connector;

	intel_encoder = &intel_dvo->base;

	intel_encoder->disable = intel_disable_dvo;
	intel_encoder->enable = intel_enable_dvo;
	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
	intel_encoder->get_config = intel_dvo_get_config;
	intel_encoder->compute_config = intel_dvo_compute_config;
	intel_encoder->pre_enable = intel_dvo_pre_enable;
	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;

	/* Now, try to find a controller */
	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
		struct drm_connector *connector = &intel_connector->base;
		const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
		struct i2c_adapter *i2c;
		int gpio;
		bool dvoinit;
		enum pipe pipe;
		u32 dpll[I915_MAX_PIPES];
		enum port port;

		/*
		 * Allow the I2C driver info to specify the GPIO to be used in
		 * special cases, but otherwise default to what's defined
		 * in the spec.
		 */
		if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
			gpio = dvo->gpio;
		else if (dvo->type == INTEL_DVO_CHIP_LVDS)
			gpio = GMBUS_PIN_SSC;
		else
			gpio = GMBUS_PIN_DPB;

		/*
		 * Set up the I2C bus necessary for the chip we're probing.
		 * It appears that everything is on GPIOE except for panels
		 * on i830 laptops, which are on GPIOB (DVOA).
		 */
		i2c = intel_gmbus_get_adapter(dev_priv, gpio);

		intel_dvo->dev = *dvo;

		/*
		 * GMBUS NAK handling seems to be unstable, hence let the
		 * transmitter detection run in bit banging mode for now.
		 */
		intel_gmbus_force_bit(i2c, true);

		/*
		 * ns2501 requires the DVO 2x clock before it will
		 * respond to i2c accesses, so make sure we have
		 * have the clock enabled before we attempt to
		 * initialize the device.
		 */
		for_each_pipe(dev_priv, pipe) {
			dpll[pipe] = I915_READ(DPLL(pipe));
			I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
		}

		dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);

		/* restore the DVO 2x clock state to original */
		for_each_pipe(dev_priv, pipe) {
			I915_WRITE(DPLL(pipe), dpll[pipe]);
		}

		intel_gmbus_force_bit(i2c, false);

		if (!dvoinit)
			continue;

		port = intel_dvo_port(dvo->dvo_reg);
		drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
				 &intel_dvo_enc_funcs, encoder_type,
				 "DVO %c", port_name(port));

		intel_encoder->type = INTEL_OUTPUT_DVO;
		intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
		intel_encoder->port = port;
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);

		switch (dvo->type) {
		case INTEL_DVO_CHIP_TMDS:
			intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) |
				(1 << INTEL_OUTPUT_DVO);
			drm_connector_init(&dev_priv->drm, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_DVII);
			encoder_type = DRM_MODE_ENCODER_TMDS;
			break;
		case INTEL_DVO_CHIP_LVDS:
			intel_encoder->cloneable = 0;
			drm_connector_init(&dev_priv->drm, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_LVDS);
			encoder_type = DRM_MODE_ENCODER_LVDS;
			break;
		}

		drm_connector_helper_add(connector,
					 &intel_dvo_connector_helper_funcs);
		connector->display_info.subpixel_order = SubPixelHorizontalRGB;
		connector->interlace_allowed = false;
		connector->doublescan_allowed = false;

		intel_connector_attach_encoder(intel_connector, intel_encoder);
		if (dvo->type == INTEL_DVO_CHIP_LVDS) {
			/*
			 * For our LVDS chipsets, we should hopefully be able
			 * to dig the fixed panel mode out of the BIOS data.
			 * However, it's in a different format from the BIOS
			 * data on chipsets with integrated LVDS (stored in AIM
			 * headers, likely), so for now, just get the current
			 * mode being output through DVO.
			 */
			intel_panel_init(&intel_connector->panel,
					 intel_dvo_get_current_mode(intel_encoder),
					 NULL);
			intel_dvo->panel_wants_dither = true;
		}

		return;
	}

	kfree(intel_dvo);
	kfree(intel_connector);
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2007 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	*/
	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
760285e7	29	#include <drm/drmP.h>
c6f95f27	30	#include <drm/drm_atomic_helper.h>
760285e7	31	#include <drm/drm_crtc.h>
79e53945	32	#include "intel_drv.h"
760285e7	33	#include <drm/i915_drm.h>
79e53945 JB	34	#include "i915_drv.h"
	35	#include "dvo.h"
	36
	37	#define SIL164_ADDR 0x38
	38	#define CH7xxx_ADDR 0x76
	39	#define TFP410_ADDR 0x38
7434a255	40	#define NS2501_ADDR 0x38
79e53945	41
ea5b213a	42	static const struct intel_dvo_device intel_dvo_devices[] = {
79e53945 JB	43	{
	44	.type = INTEL_DVO_CHIP_TMDS,
	45	.name = "sil164",
	46	.dvo_reg = DVOC,
78e0d2e3	47	.dvo_srcdim_reg = DVOC_SRCDIM,
79e53945 JB	48	.slave_addr = SIL164_ADDR,
	49	.dev_ops = &sil164_ops,
	50	},
	51	{
	52	.type = INTEL_DVO_CHIP_TMDS,
	53	.name = "ch7xxx",
	54	.dvo_reg = DVOC,
78e0d2e3	55	.dvo_srcdim_reg = DVOC_SRCDIM,
79e53945 JB	56	.slave_addr = CH7xxx_ADDR,
	57	.dev_ops = &ch7xxx_ops,
	58	},
98304ad1	59	{
	60	.type = INTEL_DVO_CHIP_TMDS,
	61	.name = "ch7xxx",
	62	.dvo_reg = DVOC,
78e0d2e3	63	.dvo_srcdim_reg = DVOC_SRCDIM,
98304ad1	64	.slave_addr = 0x75, /* For some ch7010 */
	65	.dev_ops = &ch7xxx_ops,
	66	},
79e53945 JB	67	{
	68	.type = INTEL_DVO_CHIP_LVDS,
	69	.name = "ivch",
	70	.dvo_reg = DVOA,
78e0d2e3	71	.dvo_srcdim_reg = DVOA_SRCDIM,
79e53945 JB	72	.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
	73	.dev_ops = &ivch_ops,
	74	},
	75	{
	76	.type = INTEL_DVO_CHIP_TMDS,
	77	.name = "tfp410",
	78	.dvo_reg = DVOC,
78e0d2e3	79	.dvo_srcdim_reg = DVOC_SRCDIM,
79e53945 JB	80	.slave_addr = TFP410_ADDR,
	81	.dev_ops = &tfp410_ops,
	82	},
	83	{
	84	.type = INTEL_DVO_CHIP_LVDS,
	85	.name = "ch7017",
	86	.dvo_reg = DVOC,
78e0d2e3	87	.dvo_srcdim_reg = DVOC_SRCDIM,
79e53945	88	.slave_addr = 0x75,
988c7015	89	.gpio = GMBUS_PIN_DPB,
79e53945	90	.dev_ops = &ch7017_ops,
7434a255 TR	91	},
	92	{
	93	.type = INTEL_DVO_CHIP_TMDS,
	94	.name = "ns2501",
316e0157	95	.dvo_reg = DVOB,
78e0d2e3	96	.dvo_srcdim_reg = DVOB_SRCDIM,
7434a255 TR	97	.slave_addr = NS2501_ADDR,
	98	.dev_ops = &ns2501_ops,
	99	}
79e53945 JB	100	};
79e53945 JB	101
ea5b213a CW	102	struct intel_dvo {
	103	struct intel_encoder base;
	104
	105	struct intel_dvo_device dev;
	106
28694070 VS	107	struct intel_connector *attached_connector;
28694070 VS	108
ea5b213a CW	109	bool panel_wants_dither;
	110	};
	111
69438e64	112	static struct intel_dvo enc_to_dvo(struct intel_encoder encoder)
ea5b213a	113	{
69438e64	114	return container_of(encoder, struct intel_dvo, base);
ea5b213a CW	115	}
ea5b213a CW	116
df0e9248 CW	117	static struct intel_dvo intel_attached_dvo(struct drm_connector connector)
df0e9248 CW	118	{
79fde301	119	return enc_to_dvo(intel_attached_encoder(connector));
df0e9248 CW	120	}
df0e9248 CW	121
732ce74f	122	static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
79e53945	123	{
f417c11b	124	struct drm_device *dev = connector->base.dev;
fac5e23e	125	struct drm_i915_private *dev_priv = to_i915(dev);
732ce74f	126	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
f417c11b VS	127	u32 tmp;
	128
	129	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	130
	131	if (!(tmp & DVO_ENABLE))
	132	return false;
732ce74f DV	133
	134	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
	135	}
	136
	137	static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
	138	enum pipe *pipe)
	139	{
b45a2588	140	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
69438e64	141	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
732ce74f DV	142	u32 tmp;
	143
	144	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	145
b45a2588	146	*pipe = (tmp & DVO_PIPE_SEL_MASK) >> DVO_PIPE_SEL_SHIFT;
732ce74f	147
b45a2588	148	return tmp & DVO_ENABLE;
732ce74f DV	149	}
732ce74f DV	150
045ac3b5	151	static void intel_dvo_get_config(struct intel_encoder *encoder,
5cec258b	152	struct intel_crtc_state *pipe_config)
045ac3b5	153	{
fac5e23e	154	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
69438e64	155	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
045ac3b5 JB	156	u32 tmp, flags = 0;
045ac3b5 JB	157
e1214b95 VS	158	pipe_config->output_types \|= BIT(INTEL_OUTPUT_DVO);
e1214b95 VS	159
045ac3b5 JB	160	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	161	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
	162	flags \|= DRM_MODE_FLAG_PHSYNC;
	163	else
	164	flags \|= DRM_MODE_FLAG_NHSYNC;
	165	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
	166	flags \|= DRM_MODE_FLAG_PVSYNC;
	167	else
	168	flags \|= DRM_MODE_FLAG_NVSYNC;
	169
2d112de7	170	pipe_config->base.adjusted_mode.flags \|= flags;
18442d08	171
2d112de7	172	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
045ac3b5 JB	173	}
045ac3b5 JB	174
fd6bbda9	175	static void intel_disable_dvo(struct intel_encoder *encoder,
5f88a9c6 VS	176	const struct intel_crtc_state *old_crtc_state,
5f88a9c6 VS	177	const struct drm_connector_state *old_conn_state)
19c63fa8	178	{
fac5e23e	179	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
69438e64	180	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
f0f59a00	181	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
19c63fa8 DV	182	u32 temp = I915_READ(dvo_reg);
	183
	184	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	185	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	186	I915_READ(dvo_reg);
	187	}
	188
fd6bbda9	189	static void intel_enable_dvo(struct intel_encoder *encoder,
5f88a9c6 VS	190	const struct intel_crtc_state *pipe_config,
5f88a9c6 VS	191	const struct drm_connector_state *conn_state)
19c63fa8	192	{
fac5e23e	193	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
69438e64	194	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
f0f59a00	195	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
79e53945 JB	196	u32 temp = I915_READ(dvo_reg);
79e53945 JB	197
48f34e10	198	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
ae9a911b ML	199	&pipe_config->base.mode,
ae9a911b ML	200	&pipe_config->base.adjusted_mode);
48f34e10	201
c9c054c2 VS	202	I915_WRITE(dvo_reg, temp \| DVO_ENABLE);
	203	I915_READ(dvo_reg);
	204
19c63fa8 DV	205	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
	206	}
	207
c19de8eb DL	208	static enum drm_mode_status
	209	intel_dvo_mode_valid(struct drm_connector *connector,
	210	struct drm_display_mode *mode)
79e53945	211	{
df0e9248	212	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
28694070 VS	213	const struct drm_display_mode *fixed_mode =
28694070 VS	214	to_intel_connector(connector)->panel.fixed_mode;
26a91555 MK	215	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
26a91555 MK	216	int target_clock = mode->clock;
79e53945	217
e4dd27aa VS	218	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	219	return MODE_NO_DBLESCAN;
	220
79e53945 JB	221	/* XXX: Validate clock range */
79e53945 JB	222
28694070 VS	223	if (fixed_mode) {
28694070 VS	224	if (mode->hdisplay > fixed_mode->hdisplay)
79e53945	225	return MODE_PANEL;
28694070	226	if (mode->vdisplay > fixed_mode->vdisplay)
79e53945	227	return MODE_PANEL;
26a91555	228
28694070	229	target_clock = fixed_mode->clock;
79e53945 JB	230	}
79e53945 JB	231
26a91555 MK	232	if (target_clock > max_dotclk)
	233	return MODE_CLOCK_HIGH;
	234
ea5b213a	235	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
79e53945 JB	236	}
79e53945 JB	237
a3470375	238	static bool intel_dvo_compute_config(struct intel_encoder *encoder,
0a478c27 ML	239	struct intel_crtc_state *pipe_config,
0a478c27 ML	240	struct drm_connector_state *conn_state)
79e53945	241	{
a3470375	242	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
28694070 VS	243	const struct drm_display_mode *fixed_mode =
28694070 VS	244	intel_dvo->attached_connector->panel.fixed_mode;
2d112de7	245	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
79e53945	246
d5fdd43f CW	247	/*
d5fdd43f CW	248	* If we have timings from the BIOS for the panel, put them in
79e53945 JB	249	* to the adjusted mode. The CRTC will be set up for this mode,
	250	* with the panel scaling set up to source from the H/VDisplay
	251	* of the original mode.
	252	*/
28694070 VS	253	if (fixed_mode)
28694070 VS	254	intel_fixed_panel_mode(fixed_mode, adjusted_mode);
79e53945	255
e4dd27aa VS	256	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
	257	return false;
	258
79e53945 JB	259	return true;
	260	}
	261
fd6bbda9	262	static void intel_dvo_pre_enable(struct intel_encoder *encoder,
5f88a9c6 VS	263	const struct intel_crtc_state *pipe_config,
5f88a9c6 VS	264	const struct drm_connector_state *conn_state)
79e53945	265	{
ae9a911b ML	266	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
	267	struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
	268	const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
79fde301 DV	269	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
79fde301 DV	270	int pipe = crtc->pipe;
79e53945	271	u32 dvo_val;
f0f59a00 VS	272	i915_reg_t dvo_reg = intel_dvo->dev.dvo_reg;
f0f59a00 VS	273	i915_reg_t dvo_srcdim_reg = intel_dvo->dev.dvo_srcdim_reg;
79e53945	274
79e53945 JB	275	/* Save the data order, since I don't know what it should be set to. */
	276	dvo_val = I915_READ(dvo_reg) &
	277	(DVO_PRESERVE_MASK \| DVO_DATA_ORDER_GBRG);
	278	dvo_val \|= DVO_DATA_ORDER_FP \| DVO_BORDER_ENABLE \|
	279	DVO_BLANK_ACTIVE_HIGH;
	280
b45a2588	281	dvo_val \|= DVO_PIPE_SEL(pipe);
79e53945 JB	282	dvo_val \|= DVO_PIPE_STALL;
	283	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	284	dvo_val \|= DVO_HSYNC_ACTIVE_HIGH;
	285	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	286	dvo_val \|= DVO_VSYNC_ACTIVE_HIGH;
	287
79e53945	288	/*I915_WRITE(DVOB_SRCDIM,
aad941d5 VS	289	(adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
aad941d5 VS	290	(adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
79e53945	291	I915_WRITE(dvo_srcdim_reg,
aad941d5 VS	292	(adjusted_mode->crtc_hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
aad941d5 VS	293	(adjusted_mode->crtc_vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
79e53945 JB	294	/I915_WRITE(DVOB, dvo_val);/
	295	I915_WRITE(dvo_reg, dvo_val);
	296	}
	297
7b334fcb	298	static enum drm_connector_status
930a9e28	299	intel_dvo_detect(struct drm_connector *connector, bool force)
79e53945	300	{
df0e9248	301	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
164c8598	302	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417	303	connector->base.id, connector->name);
ea5b213a	304	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
79e53945 JB	305	}
	306
	307	static int intel_dvo_get_modes(struct drm_connector *connector)
	308	{
fac5e23e	309	struct drm_i915_private *dev_priv = to_i915(connector->dev);
28694070 VS	310	const struct drm_display_mode *fixed_mode =
28694070 VS	311	to_intel_connector(connector)->panel.fixed_mode;
79e53945	312
d5fdd43f CW	313	/*
d5fdd43f CW	314	* We should probably have an i2c driver get_modes function for those
79e53945 JB	315	* devices which will have a fixed set of modes determined by the chip
	316	* (TV-out, for example), but for now with just TMDS and LVDS,
	317	* that's not the case.
	318	*/
f899fc64	319	intel_ddc_get_modes(connector,
988c7015	320	intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPC));
79e53945 JB	321	if (!list_empty(&connector->probed_modes))
	322	return 1;
	323
28694070	324	if (fixed_mode) {
79e53945	325	struct drm_display_mode *mode;
28694070	326	mode = drm_mode_duplicate(connector->dev, fixed_mode);
79e53945 JB	327	if (mode) {
	328	drm_mode_probed_add(connector, mode);
	329	return 1;
	330	}
	331	}
ea5b213a	332
79e53945 JB	333	return 0;
	334	}
	335
ea5b213a	336	static void intel_dvo_destroy(struct drm_connector *connector)
79e53945	337	{
79e53945	338	drm_connector_cleanup(connector);
28694070	339	intel_panel_fini(&to_intel_connector(connector)->panel);
599be16c	340	kfree(connector);
79e53945	341	}
79e53945	342
79e53945	343	static const struct drm_connector_funcs intel_dvo_connector_funcs = {
79e53945	344	.detect = intel_dvo_detect,
1ebaa0b9	345	.late_register = intel_connector_register,
c191eca1	346	.early_unregister = intel_connector_unregister,
79e53945 JB	347	.destroy = intel_dvo_destroy,
79e53945 JB	348	.fill_modes = drm_helper_probe_single_connector_modes,
c6f95f27	349	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725	350	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
79e53945 JB	351	};
	352
	353	static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	354	.mode_valid = intel_dvo_mode_valid,
	355	.get_modes = intel_dvo_get_modes,
79e53945 JB	356	};
79e53945 JB	357
b358d0a6	358	static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
79e53945	359	{
69438e64	360	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));
ea5b213a CW	361
	362	if (intel_dvo->dev.dev_ops->destroy)
	363	intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
	364
ea5b213a	365	intel_encoder_destroy(encoder);
79e53945 JB	366	}
	367
	368	static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	369	.destroy = intel_dvo_enc_destroy,
	370	};
	371
d5fdd43f	372	/*
79e53945 JB	373	* Attempts to get a fixed panel timing for LVDS (currently only the i830).
	374	*
	375	* Other chips with DVO LVDS will need to extend this to deal with the LVDS
	376	* chip being on DVOB/C and having multiple pipes.
	377	*/
	378	static struct drm_display_mode *
de330815	379	intel_dvo_get_current_mode(struct intel_encoder *encoder)
79e53945	380	{
de330815	381	struct drm_display_mode *mode;
79e53945	382
de330815 VS	383	mode = intel_encoder_current_mode(encoder);
	384	if (mode) {
	385	DRM_DEBUG_KMS("using current (BIOS) mode: ");
	386	drm_mode_debug_printmodeline(mode);
	387	mode->type \|= DRM_MODE_TYPE_PREFERRED;
79e53945	388	}
ea5b213a	389
79e53945 JB	390	return mode;
	391	}
	392
5748be60	393	static enum port intel_dvo_port(i915_reg_t dvo_reg)
580d8ed5 VS	394	{
580d8ed5 VS	395	if (i915_mmio_reg_equal(dvo_reg, DVOA))
5748be60	396	return PORT_A;
580d8ed5	397	else if (i915_mmio_reg_equal(dvo_reg, DVOB))
5748be60	398	return PORT_B;
580d8ed5	399	else
5748be60	400	return PORT_C;
580d8ed5 VS	401	}
580d8ed5 VS	402
c39055b0	403	void intel_dvo_init(struct drm_i915_private *dev_priv)
79e53945	404	{
21d40d37	405	struct intel_encoder *intel_encoder;
ea5b213a	406	struct intel_dvo *intel_dvo;
599be16c	407	struct intel_connector *intel_connector;
79e53945	408	int i;
79e53945	409	int encoder_type = DRM_MODE_ENCODER_NONE;
ea5b213a	410
b14c5679	411	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
ea5b213a	412	if (!intel_dvo)
79e53945 JB	413	return;
79e53945 JB	414
9bdbd0b9	415	intel_connector = intel_connector_alloc();
599be16c	416	if (!intel_connector) {
ea5b213a	417	kfree(intel_dvo);
599be16c ZW	418	return;
	419	}
	420
28694070 VS	421	intel_dvo->attached_connector = intel_connector;
28694070 VS	422
ea5b213a CW	423	intel_encoder = &intel_dvo->base;
ea5b213a CW	424
19c63fa8 DV	425	intel_encoder->disable = intel_disable_dvo;
19c63fa8 DV	426	intel_encoder->enable = intel_enable_dvo;
732ce74f	427	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
045ac3b5	428	intel_encoder->get_config = intel_dvo_get_config;
a3470375	429	intel_encoder->compute_config = intel_dvo_compute_config;
912b0e2d	430	intel_encoder->pre_enable = intel_dvo_pre_enable;
732ce74f	431	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
19c63fa8	432
79e53945 JB	433	/* Now, try to find a controller */
79e53945 JB	434	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
599be16c	435	struct drm_connector *connector = &intel_connector->base;
ea5b213a	436	const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
f899fc64	437	struct i2c_adapter *i2c;
79e53945	438	int gpio;
e4bfff54	439	bool dvoinit;
46509475	440	enum pipe pipe;
accb1eb5	441	u32 dpll[I915_MAX_PIPES];
5748be60	442	enum port port;
79e53945	443
d5fdd43f CW	444	/*
d5fdd43f CW	445	* Allow the I2C driver info to specify the GPIO to be used in
79e53945 JB	446	* special cases, but otherwise default to what's defined
	447	* in the spec.
	448	*/
88ac7939	449	if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
79e53945 JB	450	gpio = dvo->gpio;
79e53945 JB	451	else if (dvo->type == INTEL_DVO_CHIP_LVDS)
988c7015	452	gpio = GMBUS_PIN_SSC;
79e53945	453	else
988c7015	454	gpio = GMBUS_PIN_DPB;
79e53945	455
d5fdd43f CW	456	/*
d5fdd43f CW	457	* Set up the I2C bus necessary for the chip we're probing.
79e53945 JB	458	* It appears that everything is on GPIOE except for panels
	459	* on i830 laptops, which are on GPIOB (DVOA).
	460	*/
3bd7d909	461	i2c = intel_gmbus_get_adapter(dev_priv, gpio);
79e53945	462
ea5b213a	463	intel_dvo->dev = *dvo;
e4bfff54	464
d5fdd43f CW	465	/*
d5fdd43f CW	466	* GMBUS NAK handling seems to be unstable, hence let the
e4bfff54 DMEA	467	* transmitter detection run in bit banging mode for now.
	468	*/
	469	intel_gmbus_force_bit(i2c, true);
	470
d5fdd43f CW	471	/*
d5fdd43f CW	472	* ns2501 requires the DVO 2x clock before it will
46509475 VS	473	* respond to i2c accesses, so make sure we have
	474	* have the clock enabled before we attempt to
	475	* initialize the device.
	476	*/
	477	for_each_pipe(dev_priv, pipe) {
	478	dpll[pipe] = I915_READ(DPLL(pipe));
	479	I915_WRITE(DPLL(pipe), dpll[pipe] \| DPLL_DVO_2X_MODE);
	480	}
	481
e4bfff54 DMEA	482	dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
e4bfff54 DMEA	483
46509475 VS	484	/* restore the DVO 2x clock state to original */
	485	for_each_pipe(dev_priv, pipe) {
	486	I915_WRITE(DPLL(pipe), dpll[pipe]);
	487	}
	488
e4bfff54 DMEA	489	intel_gmbus_force_bit(i2c, false);
	490
	491	if (!dvoinit)
79e53945 JB	492	continue;
79e53945 JB	493
5748be60	494	port = intel_dvo_port(dvo->dvo_reg);
c39055b0	495	drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
580d8ed5	496	&intel_dvo_enc_funcs, encoder_type,
5748be60	497	"DVO %c", port_name(port));
580d8ed5	498
21d40d37	499	intel_encoder->type = INTEL_OUTPUT_DVO;
79f255a0	500	intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4	501	intel_encoder->port = port;
21d40d37	502	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
03cdc1d4	503
79e53945 JB	504	switch (dvo->type) {
79e53945 JB	505	case INTEL_DVO_CHIP_TMDS:
bc079e8b VS	506	intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) \|
bc079e8b VS	507	(1 << INTEL_OUTPUT_DVO);
c39055b0	508	drm_connector_init(&dev_priv->drm, connector,
79e53945 JB	509	&intel_dvo_connector_funcs,
	510	DRM_MODE_CONNECTOR_DVII);
	511	encoder_type = DRM_MODE_ENCODER_TMDS;
	512	break;
	513	case INTEL_DVO_CHIP_LVDS:
bc079e8b	514	intel_encoder->cloneable = 0;
c39055b0	515	drm_connector_init(&dev_priv->drm, connector,
79e53945 JB	516	&intel_dvo_connector_funcs,
	517	DRM_MODE_CONNECTOR_LVDS);
	518	encoder_type = DRM_MODE_ENCODER_LVDS;
	519	break;
	520	}
	521
	522	drm_connector_helper_add(connector,
	523	&intel_dvo_connector_helper_funcs);
	524	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
	525	connector->interlace_allowed = false;
	526	connector->doublescan_allowed = false;
	527
df0e9248	528	intel_connector_attach_encoder(intel_connector, intel_encoder);
79e53945	529	if (dvo->type == INTEL_DVO_CHIP_LVDS) {
d5fdd43f CW	530	/*
d5fdd43f CW	531	* For our LVDS chipsets, we should hopefully be able
79e53945 JB	532	* to dig the fixed panel mode out of the BIOS data.
	533	* However, it's in a different format from the BIOS
	534	* data on chipsets with integrated LVDS (stored in AIM
	535	* headers, likely), so for now, just get the current
	536	* mode being output through DVO.
	537	*/
28694070	538	intel_panel_init(&intel_connector->panel,
de330815	539	intel_dvo_get_current_mode(intel_encoder),
d93fa1b4	540	NULL);
ea5b213a	541	intel_dvo->panel_wants_dither = true;
79e53945 JB	542	}
79e53945 JB	543
79e53945 JB	544	return;
	545	}
	546
ea5b213a	547	kfree(intel_dvo);
599be16c	548	kfree(intel_connector);
79e53945	549	}