[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dvo.c

/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 */
#include <linux/i2c.h>
#include <linux/slab.h>
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "dvo.h"

#define SIL164_ADDR	0x38
#define CH7xxx_ADDR	0x76
#define TFP410_ADDR	0x38
#define NS2501_ADDR     0x38

static const struct intel_dvo_device intel_dvo_devices[] = {
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "sil164",
		.dvo_reg = DVOC,
		.slave_addr = SIL164_ADDR,
		.dev_ops = &sil164_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.slave_addr = CH7xxx_ADDR,
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "ch7xxx",
		.dvo_reg = DVOC,
		.slave_addr = 0x75, /* For some ch7010 */
		.dev_ops = &ch7xxx_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ivch",
		.dvo_reg = DVOA,
		.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
		.dev_ops = &ivch_ops,
	},
	{
		.type = INTEL_DVO_CHIP_TMDS,
		.name = "tfp410",
		.dvo_reg = DVOC,
		.slave_addr = TFP410_ADDR,
		.dev_ops = &tfp410_ops,
	},
	{
		.type = INTEL_DVO_CHIP_LVDS,
		.name = "ch7017",
		.dvo_reg = DVOC,
		.slave_addr = 0x75,
		.gpio = GMBUS_PORT_DPB,
		.dev_ops = &ch7017_ops,
	},
	{
	        .type = INTEL_DVO_CHIP_TMDS,
		.name = "ns2501",
		.dvo_reg = DVOB,
		.slave_addr = NS2501_ADDR,
		.dev_ops = &ns2501_ops,
       }
};

struct intel_dvo {
	struct intel_encoder base;

	struct intel_dvo_device dev;

	struct drm_display_mode *panel_fixed_mode;
	bool panel_wants_dither;
};

static struct intel_dvo *enc_to_dvo(struct intel_encoder *encoder)
{
	return container_of(encoder, struct intel_dvo, base);
}

static struct intel_dvo *intel_attached_dvo(struct drm_connector *connector)
{
	return enc_to_dvo(intel_attached_encoder(connector));
}

static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
{
	struct drm_device *dev = connector->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	if (!(tmp & DVO_ENABLE))
		return false;

	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
}

static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
				   enum pipe *pipe)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);

	if (!(tmp & DVO_ENABLE))
		return false;

	*pipe = PORT_TO_PIPE(tmp);

	return true;
}

static void intel_dvo_get_config(struct intel_encoder *encoder,
				 struct intel_crtc_state *pipe_config)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 tmp, flags = 0;

	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;
	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

	pipe_config->base.adjusted_mode.flags |= flags;

	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
}

static void intel_disable_dvo(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	I915_READ(dvo_reg);
}

static void intel_enable_dvo(struct intel_encoder *encoder)
{
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	u32 temp = I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
					 &crtc->config->base.mode,
					 &crtc->config->base.adjusted_mode);

	I915_WRITE(dvo_reg, temp | DVO_ENABLE);
	I915_READ(dvo_reg);

	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
}

/* Special dpms function to support cloning between dvo/sdvo/crt. */
static void intel_dvo_dpms(struct drm_connector *connector, int mode)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	struct drm_crtc *crtc;
	struct intel_crtc_state *config;

	/* dvo supports only 2 dpms states. */
	if (mode != DRM_MODE_DPMS_ON)
		mode = DRM_MODE_DPMS_OFF;

	if (mode == connector->dpms)
		return;

	connector->dpms = mode;

	/* Only need to change hw state when actually enabled */
	crtc = intel_dvo->base.base.crtc;
	if (!crtc) {
		intel_dvo->base.connectors_active = false;
		return;
	}

	/* We call connector dpms manually below in case pipe dpms doesn't
	 * change due to cloning. */
	if (mode == DRM_MODE_DPMS_ON) {
		config = to_intel_crtc(crtc)->config;

		intel_dvo->base.connectors_active = true;

		intel_crtc_update_dpms(crtc);

		intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
	} else {
		intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);

		intel_dvo->base.connectors_active = false;

		intel_crtc_update_dpms(crtc);
	}

	intel_modeset_check_state(connector->dev);
}

static enum drm_mode_status
intel_dvo_mode_valid(struct drm_connector *connector,
		     struct drm_display_mode *mode)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	/* XXX: Validate clock range */

	if (intel_dvo->panel_fixed_mode) {
		if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
			return MODE_PANEL;
		if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
			return MODE_PANEL;
	}

	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
}

static bool intel_dvo_compute_config(struct intel_encoder *encoder,
				     struct intel_crtc_state *pipe_config)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;

	/* If we have timings from the BIOS for the panel, put them in
	 * to the adjusted mode.  The CRTC will be set up for this mode,
	 * with the panel scaling set up to source from the H/VDisplay
	 * of the original mode.
	 */
	if (intel_dvo->panel_fixed_mode != NULL) {
#define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x
		C(hdisplay);
		C(hsync_start);
		C(hsync_end);
		C(htotal);
		C(vdisplay);
		C(vsync_start);
		C(vsync_end);
		C(vtotal);
		C(clock);
#undef C

		drm_mode_set_crtcinfo(adjusted_mode, 0);
	}

	return true;
}

static void intel_dvo_pre_enable(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
	int pipe = crtc->pipe;
	u32 dvo_val;
	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;

	switch (dvo_reg) {
	case DVOA:
	default:
		dvo_srcdim_reg = DVOA_SRCDIM;
		break;
	case DVOB:
		dvo_srcdim_reg = DVOB_SRCDIM;
		break;
	case DVOC:
		dvo_srcdim_reg = DVOC_SRCDIM;
		break;
	}

	/* Save the data order, since I don't know what it should be set to. */
	dvo_val = I915_READ(dvo_reg) &
		  (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
	dvo_val |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE |
		   DVO_BLANK_ACTIVE_HIGH;

	if (pipe == 1)
		dvo_val |= DVO_PIPE_B_SELECT;
	dvo_val |= DVO_PIPE_STALL;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
		dvo_val |= DVO_HSYNC_ACTIVE_HIGH;
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
		dvo_val |= DVO_VSYNC_ACTIVE_HIGH;

	/*I915_WRITE(DVOB_SRCDIM,
	  (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
	  (adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	I915_WRITE(dvo_srcdim_reg,
		   (adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
		   (adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	/*I915_WRITE(DVOB, dvo_val);*/
	I915_WRITE(dvo_reg, dvo_val);
}

/**
 * Detect the output connection on our DVO device.
 *
 * Unimplemented.
 */
static enum drm_connector_status
intel_dvo_detect(struct drm_connector *connector, bool force)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
}

static int intel_dvo_get_modes(struct drm_connector *connector)
{
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	struct drm_i915_private *dev_priv = connector->dev->dev_private;

	/* We should probably have an i2c driver get_modes function for those
	 * devices which will have a fixed set of modes determined by the chip
	 * (TV-out, for example), but for now with just TMDS and LVDS,
	 * that's not the case.
	 */
	intel_ddc_get_modes(connector,
			    intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC));
	if (!list_empty(&connector->probed_modes))
		return 1;

	if (intel_dvo->panel_fixed_mode != NULL) {
		struct drm_display_mode *mode;
		mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode);
		if (mode) {
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}

	return 0;
}

static void intel_dvo_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
	kfree(connector);
}

static const struct drm_connector_funcs intel_dvo_connector_funcs = {
	.dpms = intel_dvo_dpms,
	.detect = intel_dvo_detect,
	.destroy = intel_dvo_destroy,
	.fill_modes = drm_helper_probe_single_connector_modes,
};

static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	.mode_valid = intel_dvo_mode_valid,
	.get_modes = intel_dvo_get_modes,
	.best_encoder = intel_best_encoder,
};

static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
{
	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));

	if (intel_dvo->dev.dev_ops->destroy)
		intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);

	kfree(intel_dvo->panel_fixed_mode);

	intel_encoder_destroy(encoder);
}

static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	.destroy = intel_dvo_enc_destroy,
};

/**
 * Attempts to get a fixed panel timing for LVDS (currently only the i830).
 *
 * Other chips with DVO LVDS will need to extend this to deal with the LVDS
 * chip being on DVOB/C and having multiple pipes.
 */
static struct drm_display_mode *
intel_dvo_get_current_mode(struct drm_connector *connector)
{
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
	uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
	struct drm_display_mode *mode = NULL;

	/* If the DVO port is active, that'll be the LVDS, so we can pull out
	 * its timings to get how the BIOS set up the panel.
	 */
	if (dvo_val & DVO_ENABLE) {
		struct drm_crtc *crtc;
		int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0;

		crtc = intel_get_crtc_for_pipe(dev, pipe);
		if (crtc) {
			mode = intel_crtc_mode_get(dev, crtc);
			if (mode) {
				mode->type |= DRM_MODE_TYPE_PREFERRED;
				if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
					mode->flags |= DRM_MODE_FLAG_PHSYNC;
				if (dvo_val & DVO_VSYNC_ACTIVE_HIGH)
					mode->flags |= DRM_MODE_FLAG_PVSYNC;
			}
		}
	}

	return mode;
}

void intel_dvo_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *intel_encoder;
	struct intel_dvo *intel_dvo;
	struct intel_connector *intel_connector;
	int i;
	int encoder_type = DRM_MODE_ENCODER_NONE;

	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
	if (!intel_dvo)
		return;

	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_dvo);
		return;
	}

	intel_encoder = &intel_dvo->base;
	drm_encoder_init(dev, &intel_encoder->base,
			 &intel_dvo_enc_funcs, encoder_type);

	intel_encoder->disable = intel_disable_dvo;
	intel_encoder->enable = intel_enable_dvo;
	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
	intel_encoder->get_config = intel_dvo_get_config;
	intel_encoder->compute_config = intel_dvo_compute_config;
	intel_encoder->pre_enable = intel_dvo_pre_enable;
	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
	intel_connector->unregister = intel_connector_unregister;

	/* Now, try to find a controller */
	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
		struct drm_connector *connector = &intel_connector->base;
		const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
		struct i2c_adapter *i2c;
		int gpio;
		bool dvoinit;

		/* Allow the I2C driver info to specify the GPIO to be used in
		 * special cases, but otherwise default to what's defined
		 * in the spec.
		 */
		if (intel_gmbus_is_port_valid(dvo->gpio))
			gpio = dvo->gpio;
		else if (dvo->type == INTEL_DVO_CHIP_LVDS)
			gpio = GMBUS_PORT_SSC;
		else
			gpio = GMBUS_PORT_DPB;

		/* Set up the I2C bus necessary for the chip we're probing.
		 * It appears that everything is on GPIOE except for panels
		 * on i830 laptops, which are on GPIOB (DVOA).
		 */
		i2c = intel_gmbus_get_adapter(dev_priv, gpio);

		intel_dvo->dev = *dvo;

		/* GMBUS NAK handling seems to be unstable, hence let the
		 * transmitter detection run in bit banging mode for now.
		 */
		intel_gmbus_force_bit(i2c, true);

		dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);

		intel_gmbus_force_bit(i2c, false);

		if (!dvoinit)
			continue;

		intel_encoder->type = INTEL_OUTPUT_DVO;
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
		switch (dvo->type) {
		case INTEL_DVO_CHIP_TMDS:
			intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) |
				(1 << INTEL_OUTPUT_DVO);
			drm_connector_init(dev, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_DVII);
			encoder_type = DRM_MODE_ENCODER_TMDS;
			break;
		case INTEL_DVO_CHIP_LVDS:
			intel_encoder->cloneable = 0;
			drm_connector_init(dev, connector,
					   &intel_dvo_connector_funcs,
					   DRM_MODE_CONNECTOR_LVDS);
			encoder_type = DRM_MODE_ENCODER_LVDS;
			break;
		}

		drm_connector_helper_add(connector,
					 &intel_dvo_connector_helper_funcs);
		connector->display_info.subpixel_order = SubPixelHorizontalRGB;
		connector->interlace_allowed = false;
		connector->doublescan_allowed = false;

		intel_connector_attach_encoder(intel_connector, intel_encoder);
		if (dvo->type == INTEL_DVO_CHIP_LVDS) {
			/* For our LVDS chipsets, we should hopefully be able
			 * to dig the fixed panel mode out of the BIOS data.
			 * However, it's in a different format from the BIOS
			 * data on chipsets with integrated LVDS (stored in AIM
			 * headers, likely), so for now, just get the current
			 * mode being output through DVO.
			 */
			intel_dvo->panel_fixed_mode =
				intel_dvo_get_current_mode(connector);
			intel_dvo->panel_wants_dither = true;
		}

		drm_connector_register(connector);
		return;
	}

	drm_encoder_cleanup(&intel_encoder->base);
	kfree(intel_dvo);
	kfree(intel_connector);
}
Commit	Line	Data
79e53945 JB	1	/*
	2	* Copyright 2006 Dave Airlie <airlied@linux.ie>
	3	* Copyright © 2006-2007 Intel Corporation
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	21	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	22	* DEALINGS IN THE SOFTWARE.
	23	*
	24	* Authors:
	25	* Eric Anholt <eric@anholt.net>
	26	*/
	27	#include <linux/i2c.h>
5a0e3ad6	28	#include <linux/slab.h>
760285e7 DH	29	#include <drm/drmP.h>
760285e7 DH	30	#include <drm/drm_crtc.h>
79e53945	31	#include "intel_drv.h"
760285e7	32	#include <drm/i915_drm.h>
79e53945 JB	33	#include "i915_drv.h"
	34	#include "dvo.h"
	35
	36	#define SIL164_ADDR 0x38
	37	#define CH7xxx_ADDR 0x76
	38	#define TFP410_ADDR 0x38
7434a255	39	#define NS2501_ADDR 0x38
79e53945	40
ea5b213a	41	static const struct intel_dvo_device intel_dvo_devices[] = {
79e53945 JB	42	{
	43	.type = INTEL_DVO_CHIP_TMDS,
	44	.name = "sil164",
	45	.dvo_reg = DVOC,
	46	.slave_addr = SIL164_ADDR,
	47	.dev_ops = &sil164_ops,
	48	},
	49	{
	50	.type = INTEL_DVO_CHIP_TMDS,
	51	.name = "ch7xxx",
	52	.dvo_reg = DVOC,
	53	.slave_addr = CH7xxx_ADDR,
	54	.dev_ops = &ch7xxx_ops,
	55	},
98304ad1	56	{
	57	.type = INTEL_DVO_CHIP_TMDS,
	58	.name = "ch7xxx",
	59	.dvo_reg = DVOC,
	60	.slave_addr = 0x75, /* For some ch7010 */
	61	.dev_ops = &ch7xxx_ops,
	62	},
79e53945 JB	63	{
	64	.type = INTEL_DVO_CHIP_LVDS,
	65	.name = "ivch",
	66	.dvo_reg = DVOA,
	67	.slave_addr = 0x02, /* Might also be 0x44, 0x84, 0xc4 */
	68	.dev_ops = &ivch_ops,
	69	},
	70	{
	71	.type = INTEL_DVO_CHIP_TMDS,
	72	.name = "tfp410",
	73	.dvo_reg = DVOC,
	74	.slave_addr = TFP410_ADDR,
	75	.dev_ops = &tfp410_ops,
	76	},
	77	{
	78	.type = INTEL_DVO_CHIP_LVDS,
	79	.name = "ch7017",
	80	.dvo_reg = DVOC,
	81	.slave_addr = 0x75,
a6b17b43	82	.gpio = GMBUS_PORT_DPB,
79e53945	83	.dev_ops = &ch7017_ops,
7434a255 TR	84	},
	85	{
	86	.type = INTEL_DVO_CHIP_TMDS,
	87	.name = "ns2501",
316e0157	88	.dvo_reg = DVOB,
7434a255 TR	89	.slave_addr = NS2501_ADDR,
	90	.dev_ops = &ns2501_ops,
	91	}
79e53945 JB	92	};
79e53945 JB	93
ea5b213a CW	94	struct intel_dvo {
	95	struct intel_encoder base;
	96
	97	struct intel_dvo_device dev;
	98
	99	struct drm_display_mode *panel_fixed_mode;
	100	bool panel_wants_dither;
	101	};
	102
69438e64	103	static struct intel_dvo enc_to_dvo(struct intel_encoder encoder)
ea5b213a	104	{
69438e64	105	return container_of(encoder, struct intel_dvo, base);
ea5b213a CW	106	}
ea5b213a CW	107
df0e9248 CW	108	static struct intel_dvo intel_attached_dvo(struct drm_connector connector)
df0e9248 CW	109	{
79fde301	110	return enc_to_dvo(intel_attached_encoder(connector));
df0e9248 CW	111	}
df0e9248 CW	112
732ce74f	113	static bool intel_dvo_connector_get_hw_state(struct intel_connector *connector)
79e53945	114	{
f417c11b VS	115	struct drm_device *dev = connector->base.dev;
f417c11b VS	116	struct drm_i915_private *dev_priv = dev->dev_private;
732ce74f	117	struct intel_dvo *intel_dvo = intel_attached_dvo(&connector->base);
f417c11b VS	118	u32 tmp;
	119
	120	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	121
	122	if (!(tmp & DVO_ENABLE))
	123	return false;
732ce74f DV	124
	125	return intel_dvo->dev.dev_ops->get_hw_state(&intel_dvo->dev);
	126	}
	127
	128	static bool intel_dvo_get_hw_state(struct intel_encoder *encoder,
	129	enum pipe *pipe)
	130	{
	131	struct drm_device *dev = encoder->base.dev;
	132	struct drm_i915_private *dev_priv = dev->dev_private;
69438e64	133	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
732ce74f DV	134	u32 tmp;
	135
	136	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	137
	138	if (!(tmp & DVO_ENABLE))
	139	return false;
	140
	141	*pipe = PORT_TO_PIPE(tmp);
	142
	143	return true;
	144	}
	145
045ac3b5	146	static void intel_dvo_get_config(struct intel_encoder *encoder,
5cec258b	147	struct intel_crtc_state *pipe_config)
045ac3b5 JB	148	{
045ac3b5 JB	149	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
69438e64	150	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
045ac3b5 JB	151	u32 tmp, flags = 0;
	152
	153	tmp = I915_READ(intel_dvo->dev.dvo_reg);
	154	if (tmp & DVO_HSYNC_ACTIVE_HIGH)
	155	flags \|= DRM_MODE_FLAG_PHSYNC;
	156	else
	157	flags \|= DRM_MODE_FLAG_NHSYNC;
	158	if (tmp & DVO_VSYNC_ACTIVE_HIGH)
	159	flags \|= DRM_MODE_FLAG_PVSYNC;
	160	else
	161	flags \|= DRM_MODE_FLAG_NVSYNC;
	162
2d112de7	163	pipe_config->base.adjusted_mode.flags \|= flags;
18442d08	164
2d112de7	165	pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
045ac3b5 JB	166	}
045ac3b5 JB	167
19c63fa8 DV	168	static void intel_disable_dvo(struct intel_encoder *encoder)
	169	{
	170	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
69438e64	171	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
19c63fa8 DV	172	u32 dvo_reg = intel_dvo->dev.dvo_reg;
	173	u32 temp = I915_READ(dvo_reg);
	174
	175	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
	176	I915_WRITE(dvo_reg, temp & ~DVO_ENABLE);
	177	I915_READ(dvo_reg);
	178	}
	179
	180	static void intel_enable_dvo(struct intel_encoder *encoder)
	181	{
	182	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
69438e64	183	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
48f34e10	184	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
ea5b213a	185	u32 dvo_reg = intel_dvo->dev.dvo_reg;
79e53945 JB	186	u32 temp = I915_READ(dvo_reg);
79e53945 JB	187
48f34e10	188	intel_dvo->dev.dev_ops->mode_set(&intel_dvo->dev,
6e3c9717 ACO	189	&crtc->config->base.mode,
6e3c9717 ACO	190	&crtc->config->base.adjusted_mode);
48f34e10	191
c9c054c2 VS	192	I915_WRITE(dvo_reg, temp \| DVO_ENABLE);
	193	I915_READ(dvo_reg);
	194
19c63fa8 DV	195	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
	196	}
	197
6b1c087b	198	/* Special dpms function to support cloning between dvo/sdvo/crt. */
b2cabb0e	199	static void intel_dvo_dpms(struct drm_connector *connector, int mode)
79e53945	200	{
b2cabb0e DV	201	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
b2cabb0e DV	202	struct drm_crtc *crtc;
5cec258b	203	struct intel_crtc_state *config;
b2cabb0e DV	204
	205	/* dvo supports only 2 dpms states. */
	206	if (mode != DRM_MODE_DPMS_ON)
	207	mode = DRM_MODE_DPMS_OFF;
	208
	209	if (mode == connector->dpms)
	210	return;
	211
	212	connector->dpms = mode;
	213
	214	/* Only need to change hw state when actually enabled */
	215	crtc = intel_dvo->base.base.crtc;
	216	if (!crtc) {
	217	intel_dvo->base.connectors_active = false;
	218	return;
	219	}
79e53945	220
6b1c087b JN	221	/* We call connector dpms manually below in case pipe dpms doesn't
6b1c087b JN	222	* change due to cloning. */
79e53945	223	if (mode == DRM_MODE_DPMS_ON) {
6e3c9717	224	config = to_intel_crtc(crtc)->config;
48f34e10	225
b2cabb0e DV	226	intel_dvo->base.connectors_active = true;
	227
	228	intel_crtc_update_dpms(crtc);
	229
fac3274c	230	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, true);
79e53945	231	} else {
fac3274c	232	intel_dvo->dev.dev_ops->dpms(&intel_dvo->dev, false);
b2cabb0e DV	233
	234	intel_dvo->base.connectors_active = false;
	235
	236	intel_crtc_update_dpms(crtc);
79e53945	237	}
0a91ca29	238
b980514c	239	intel_modeset_check_state(connector->dev);
79e53945 JB	240	}
79e53945 JB	241
c19de8eb DL	242	static enum drm_mode_status
	243	intel_dvo_mode_valid(struct drm_connector *connector,
	244	struct drm_display_mode *mode)
79e53945	245	{
df0e9248	246	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
79e53945 JB	247
	248	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
	249	return MODE_NO_DBLESCAN;
	250
	251	/* XXX: Validate clock range */
	252
ea5b213a CW	253	if (intel_dvo->panel_fixed_mode) {
ea5b213a CW	254	if (mode->hdisplay > intel_dvo->panel_fixed_mode->hdisplay)
79e53945	255	return MODE_PANEL;
ea5b213a	256	if (mode->vdisplay > intel_dvo->panel_fixed_mode->vdisplay)
79e53945 JB	257	return MODE_PANEL;
	258	}
	259
ea5b213a	260	return intel_dvo->dev.dev_ops->mode_valid(&intel_dvo->dev, mode);
79e53945 JB	261	}
79e53945 JB	262
a3470375	263	static bool intel_dvo_compute_config(struct intel_encoder *encoder,
5cec258b	264	struct intel_crtc_state *pipe_config)
79e53945	265	{
a3470375	266	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
2d112de7	267	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
79e53945 JB	268
	269	/* If we have timings from the BIOS for the panel, put them in
	270	* to the adjusted mode. The CRTC will be set up for this mode,
	271	* with the panel scaling set up to source from the H/VDisplay
	272	* of the original mode.
	273	*/
ea5b213a CW	274	if (intel_dvo->panel_fixed_mode != NULL) {
ea5b213a CW	275	#define C(x) adjusted_mode->x = intel_dvo->panel_fixed_mode->x
79e53945 JB	276	C(hdisplay);
	277	C(hsync_start);
	278	C(hsync_end);
	279	C(htotal);
	280	C(vdisplay);
	281	C(vsync_start);
	282	C(vsync_end);
	283	C(vtotal);
	284	C(clock);
79e53945	285	#undef C
0d971748 DV	286
0d971748 DV	287	drm_mode_set_crtcinfo(adjusted_mode, 0);
79e53945 JB	288	}
79e53945 JB	289
79e53945 JB	290	return true;
	291	}
	292
912b0e2d	293	static void intel_dvo_pre_enable(struct intel_encoder *encoder)
79e53945	294	{
79fde301	295	struct drm_device *dev = encoder->base.dev;
79e53945	296	struct drm_i915_private *dev_priv = dev->dev_private;
79fde301	297	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
6e3c9717	298	struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
79fde301 DV	299	struct intel_dvo *intel_dvo = enc_to_dvo(encoder);
79fde301 DV	300	int pipe = crtc->pipe;
79e53945	301	u32 dvo_val;
ea5b213a	302	u32 dvo_reg = intel_dvo->dev.dvo_reg, dvo_srcdim_reg;
79e53945 JB	303
	304	switch (dvo_reg) {
	305	case DVOA:
	306	default:
	307	dvo_srcdim_reg = DVOA_SRCDIM;
	308	break;
	309	case DVOB:
	310	dvo_srcdim_reg = DVOB_SRCDIM;
	311	break;
	312	case DVOC:
	313	dvo_srcdim_reg = DVOC_SRCDIM;
	314	break;
	315	}
	316
79e53945 JB	317	/* Save the data order, since I don't know what it should be set to. */
	318	dvo_val = I915_READ(dvo_reg) &
	319	(DVO_PRESERVE_MASK \| DVO_DATA_ORDER_GBRG);
	320	dvo_val \|= DVO_DATA_ORDER_FP \| DVO_BORDER_ENABLE \|
	321	DVO_BLANK_ACTIVE_HIGH;
	322
	323	if (pipe == 1)
	324	dvo_val \|= DVO_PIPE_B_SELECT;
	325	dvo_val \|= DVO_PIPE_STALL;
	326	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
	327	dvo_val \|= DVO_HSYNC_ACTIVE_HIGH;
	328	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
	329	dvo_val \|= DVO_VSYNC_ACTIVE_HIGH;
	330
79e53945 JB	331	/*I915_WRITE(DVOB_SRCDIM,
	332	(adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
	333	(adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
	334	I915_WRITE(dvo_srcdim_reg,
	335	(adjusted_mode->hdisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) \|
	336	(adjusted_mode->vdisplay << DVO_SRCDIM_VERTICAL_SHIFT));
	337	/I915_WRITE(DVOB, dvo_val);/
	338	I915_WRITE(dvo_reg, dvo_val);
	339	}
	340
	341	/**
	342	* Detect the output connection on our DVO device.
	343	*
	344	* Unimplemented.
	345	*/
7b334fcb	346	static enum drm_connector_status
930a9e28	347	intel_dvo_detect(struct drm_connector *connector, bool force)
79e53945	348	{
df0e9248	349	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
164c8598	350	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417	351	connector->base.id, connector->name);
ea5b213a	352	return intel_dvo->dev.dev_ops->detect(&intel_dvo->dev);
79e53945 JB	353	}
	354
	355	static int intel_dvo_get_modes(struct drm_connector *connector)
	356	{
df0e9248	357	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
f899fc64	358	struct drm_i915_private *dev_priv = connector->dev->dev_private;
79e53945 JB	359
	360	/* We should probably have an i2c driver get_modes function for those
	361	* devices which will have a fixed set of modes determined by the chip
	362	* (TV-out, for example), but for now with just TMDS and LVDS,
	363	* that's not the case.
	364	*/
f899fc64	365	intel_ddc_get_modes(connector,
3bd7d909	366	intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPC));
79e53945 JB	367	if (!list_empty(&connector->probed_modes))
	368	return 1;
	369
ea5b213a	370	if (intel_dvo->panel_fixed_mode != NULL) {
79e53945	371	struct drm_display_mode *mode;
ea5b213a	372	mode = drm_mode_duplicate(connector->dev, intel_dvo->panel_fixed_mode);
79e53945 JB	373	if (mode) {
	374	drm_mode_probed_add(connector, mode);
	375	return 1;
	376	}
	377	}
ea5b213a	378
79e53945 JB	379	return 0;
	380	}
	381
ea5b213a	382	static void intel_dvo_destroy(struct drm_connector *connector)
79e53945	383	{
79e53945	384	drm_connector_cleanup(connector);
599be16c	385	kfree(connector);
79e53945	386	}
79e53945	387
79e53945	388	static const struct drm_connector_funcs intel_dvo_connector_funcs = {
b2cabb0e	389	.dpms = intel_dvo_dpms,
79e53945 JB	390	.detect = intel_dvo_detect,
	391	.destroy = intel_dvo_destroy,
	392	.fill_modes = drm_helper_probe_single_connector_modes,
	393	};
	394
	395	static const struct drm_connector_helper_funcs intel_dvo_connector_helper_funcs = {
	396	.mode_valid = intel_dvo_mode_valid,
	397	.get_modes = intel_dvo_get_modes,
df0e9248	398	.best_encoder = intel_best_encoder,
79e53945 JB	399	};
79e53945 JB	400
b358d0a6	401	static void intel_dvo_enc_destroy(struct drm_encoder *encoder)
79e53945	402	{
69438e64	403	struct intel_dvo *intel_dvo = enc_to_dvo(to_intel_encoder(encoder));
ea5b213a CW	404
	405	if (intel_dvo->dev.dev_ops->destroy)
	406	intel_dvo->dev.dev_ops->destroy(&intel_dvo->dev);
	407
	408	kfree(intel_dvo->panel_fixed_mode);
	409
	410	intel_encoder_destroy(encoder);
79e53945 JB	411	}
	412
	413	static const struct drm_encoder_funcs intel_dvo_enc_funcs = {
	414	.destroy = intel_dvo_enc_destroy,
	415	};
	416
79e53945 JB	417	/**
	418	* Attempts to get a fixed panel timing for LVDS (currently only the i830).
	419	*
	420	* Other chips with DVO LVDS will need to extend this to deal with the LVDS
	421	* chip being on DVOB/C and having multiple pipes.
	422	*/
	423	static struct drm_display_mode *
ea5b213a	424	intel_dvo_get_current_mode(struct drm_connector *connector)
79e53945 JB	425	{
	426	struct drm_device *dev = connector->dev;
	427	struct drm_i915_private *dev_priv = dev->dev_private;
df0e9248	428	struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
ea5b213a	429	uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg);
79e53945 JB	430	struct drm_display_mode *mode = NULL;
	431
	432	/* If the DVO port is active, that'll be the LVDS, so we can pull out
	433	* its timings to get how the BIOS set up the panel.
	434	*/
	435	if (dvo_val & DVO_ENABLE) {
	436	struct drm_crtc *crtc;
	437	int pipe = (dvo_val & DVO_PIPE_B_SELECT) ? 1 : 0;
	438
f875c15a	439	crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945 JB	440	if (crtc) {
79e53945 JB	441	mode = intel_crtc_mode_get(dev, crtc);
79e53945 JB	442	if (mode) {
	443	mode->type \|= DRM_MODE_TYPE_PREFERRED;
	444	if (dvo_val & DVO_HSYNC_ACTIVE_HIGH)
	445	mode->flags \|= DRM_MODE_FLAG_PHSYNC;
	446	if (dvo_val & DVO_VSYNC_ACTIVE_HIGH)
	447	mode->flags \|= DRM_MODE_FLAG_PVSYNC;
	448	}
	449	}
	450	}
ea5b213a	451
79e53945 JB	452	return mode;
	453	}
	454
	455	void intel_dvo_init(struct drm_device *dev)
	456	{
f899fc64	457	struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37	458	struct intel_encoder *intel_encoder;
ea5b213a	459	struct intel_dvo *intel_dvo;
599be16c	460	struct intel_connector *intel_connector;
79e53945	461	int i;
79e53945	462	int encoder_type = DRM_MODE_ENCODER_NONE;
ea5b213a	463
b14c5679	464	intel_dvo = kzalloc(sizeof(*intel_dvo), GFP_KERNEL);
ea5b213a	465	if (!intel_dvo)
79e53945 JB	466	return;
79e53945 JB	467
b14c5679	468	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
599be16c	469	if (!intel_connector) {
ea5b213a	470	kfree(intel_dvo);
599be16c ZW	471	return;
	472	}
	473
ea5b213a	474	intel_encoder = &intel_dvo->base;
373a3cf7 CW	475	drm_encoder_init(dev, &intel_encoder->base,
373a3cf7 CW	476	&intel_dvo_enc_funcs, encoder_type);
ea5b213a	477
19c63fa8 DV	478	intel_encoder->disable = intel_disable_dvo;
19c63fa8 DV	479	intel_encoder->enable = intel_enable_dvo;
732ce74f	480	intel_encoder->get_hw_state = intel_dvo_get_hw_state;
045ac3b5	481	intel_encoder->get_config = intel_dvo_get_config;
a3470375	482	intel_encoder->compute_config = intel_dvo_compute_config;
912b0e2d	483	intel_encoder->pre_enable = intel_dvo_pre_enable;
732ce74f	484	intel_connector->get_hw_state = intel_dvo_connector_get_hw_state;
4932e2c3	485	intel_connector->unregister = intel_connector_unregister;
19c63fa8	486
79e53945 JB	487	/* Now, try to find a controller */
79e53945 JB	488	for (i = 0; i < ARRAY_SIZE(intel_dvo_devices); i++) {
599be16c	489	struct drm_connector *connector = &intel_connector->base;
ea5b213a	490	const struct intel_dvo_device *dvo = &intel_dvo_devices[i];
f899fc64	491	struct i2c_adapter *i2c;
79e53945	492	int gpio;
e4bfff54	493	bool dvoinit;
79e53945	494
79e53945 JB	495	/* Allow the I2C driver info to specify the GPIO to be used in
	496	* special cases, but otherwise default to what's defined
	497	* in the spec.
	498	*/
3bd7d909	499	if (intel_gmbus_is_port_valid(dvo->gpio))
79e53945 JB	500	gpio = dvo->gpio;
79e53945 JB	501	else if (dvo->type == INTEL_DVO_CHIP_LVDS)
f573c660	502	gpio = GMBUS_PORT_SSC;
79e53945	503	else
a6b17b43	504	gpio = GMBUS_PORT_DPB;
79e53945 JB	505
	506	/* Set up the I2C bus necessary for the chip we're probing.
	507	* It appears that everything is on GPIOE except for panels
	508	* on i830 laptops, which are on GPIOB (DVOA).
	509	*/
3bd7d909	510	i2c = intel_gmbus_get_adapter(dev_priv, gpio);
79e53945	511
ea5b213a	512	intel_dvo->dev = *dvo;
e4bfff54 DMEA	513
	514	/* GMBUS NAK handling seems to be unstable, hence let the
	515	* transmitter detection run in bit banging mode for now.
	516	*/
	517	intel_gmbus_force_bit(i2c, true);
	518
	519	dvoinit = dvo->dev_ops->init(&intel_dvo->dev, i2c);
	520
	521	intel_gmbus_force_bit(i2c, false);
	522
	523	if (!dvoinit)
79e53945 JB	524	continue;
79e53945 JB	525
21d40d37 EA	526	intel_encoder->type = INTEL_OUTPUT_DVO;
21d40d37 EA	527	intel_encoder->crtc_mask = (1 << 0) \| (1 << 1);
79e53945 JB	528	switch (dvo->type) {
79e53945 JB	529	case INTEL_DVO_CHIP_TMDS:
bc079e8b VS	530	intel_encoder->cloneable = (1 << INTEL_OUTPUT_ANALOG) \|
bc079e8b VS	531	(1 << INTEL_OUTPUT_DVO);
79e53945 JB	532	drm_connector_init(dev, connector,
	533	&intel_dvo_connector_funcs,
	534	DRM_MODE_CONNECTOR_DVII);
	535	encoder_type = DRM_MODE_ENCODER_TMDS;
	536	break;
	537	case INTEL_DVO_CHIP_LVDS:
bc079e8b	538	intel_encoder->cloneable = 0;
79e53945 JB	539	drm_connector_init(dev, connector,
	540	&intel_dvo_connector_funcs,
	541	DRM_MODE_CONNECTOR_LVDS);
	542	encoder_type = DRM_MODE_ENCODER_LVDS;
	543	break;
	544	}
	545
	546	drm_connector_helper_add(connector,
	547	&intel_dvo_connector_helper_funcs);
	548	connector->display_info.subpixel_order = SubPixelHorizontalRGB;
	549	connector->interlace_allowed = false;
	550	connector->doublescan_allowed = false;
	551
df0e9248	552	intel_connector_attach_encoder(intel_connector, intel_encoder);
79e53945 JB	553	if (dvo->type == INTEL_DVO_CHIP_LVDS) {
	554	/* For our LVDS chipsets, we should hopefully be able
	555	* to dig the fixed panel mode out of the BIOS data.
	556	* However, it's in a different format from the BIOS
	557	* data on chipsets with integrated LVDS (stored in AIM
	558	* headers, likely), so for now, just get the current
	559	* mode being output through DVO.
	560	*/
ea5b213a	561	intel_dvo->panel_fixed_mode =
79e53945	562	intel_dvo_get_current_mode(connector);
ea5b213a	563	intel_dvo->panel_wants_dither = true;
79e53945 JB	564	}
79e53945 JB	565
34ea3d38	566	drm_connector_register(connector);
79e53945 JB	567	return;
	568	}
	569
373a3cf7	570	drm_encoder_cleanup(&intel_encoder->base);
ea5b213a	571	kfree(intel_dvo);
599be16c	572	kfree(intel_connector);
79e53945	573	}