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drm/i915: cleanup opregion asle pipestat enable
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
1d5bfac9
DV		 36/**
37 * _wait_for - magic (register) wait macro
38 *
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
43 */
481b6af3 44#define _wait_for(COND, MS, W) ({ \
1d5bfac9 45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
913d8d11 46 int ret__ = 0; \
0206e353 47 while (!(COND)) { \
913d8d11 48 if (time_after(jiffies, timeout__)) { \
1d5bfac9
DV		 49 if (!(COND)) \
50 ret__ = -ETIMEDOUT; \
913d8d11
CW		 51 break; \
52 } \
0cc2764c
BW		 53 if (W && drm_can_sleep()) { \
54 msleep(W); \
55 } else { \
56 cpu_relax(); \
57 } \
913d8d11
CW		 58 } \
59 ret__; \
60})
61
481b6af3
CW		 62#define wait_for(COND, MS) _wait_for(COND, MS, 1)
63#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
6effa33b
DV		 64#define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
481b6af3 66
021357ac
CW		 67#define KHz(x) (1000*x)
68#define MHz(x) KHz(1000*x)
69
79e53945
JB		 70/*
71 * Display related stuff
72 */
73
74/* store information about an Ixxx DVO */
75/* The i830->i865 use multiple DVOs with multiple i2cs */
76/* the i915, i945 have a single sDVO i2c bus - which is different */
77#define MAX_OUTPUTS 6
78/* maximum connectors per crtcs in the mode set */
79#define INTELFB_CONN_LIMIT 4
80
81#define INTEL_I2C_BUS_DVO 1
82#define INTEL_I2C_BUS_SDVO 2
83
84/* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86#define INTEL_OUTPUT_UNUSED 0
87#define INTEL_OUTPUT_ANALOG 1
88#define INTEL_OUTPUT_DVO 2
89#define INTEL_OUTPUT_SDVO 3
90#define INTEL_OUTPUT_LVDS 4
91#define INTEL_OUTPUT_TVOUT 5
7d57382e 92#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 93#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 94#define INTEL_OUTPUT_EDP 8
00c09d70 95#define INTEL_OUTPUT_UNKNOWN 9
79e53945
JB		 96
97#define INTEL_DVO_CHIP_NONE 0
98#define INTEL_DVO_CHIP_LVDS 1
99#define INTEL_DVO_CHIP_TMDS 2
100#define INTEL_DVO_CHIP_TVOUT 4
101
79e53945
JB		 102struct intel_framebuffer {
103 struct drm_framebuffer base;
05394f39 104 struct drm_i915_gem_object *obj;
79e53945
JB		 105};
106
37811fcc
CW		 107struct intel_fbdev {
108 struct drm_fb_helper helper;
109 struct intel_framebuffer ifb;
110 struct list_head fbdev_list;
111 struct drm_display_mode *our_mode;
112};
79e53945 113
21d40d37 114struct intel_encoder {
4ef69c7a 115 struct drm_encoder base;
9a935856
DV		 116 /*
117 * The new crtc this encoder will be driven from. Only differs from
118 * base->crtc while a modeset is in progress.
119 */
120 struct intel_crtc *new_crtc;
121
79e53945 122 int type;
e2f0ba97 123 bool needs_tv_clock;
66a9278e
DV		 124 /*
125 * Intel hw has only one MUX where encoders could be clone, hence a
126 * simple flag is enough to compute the possible_clones mask.
127 */
128 bool cloneable;
5ab432ef 129 bool connectors_active;
21d40d37 130 void (*hot_plug)(struct intel_encoder *);
7ae89233
DV		 131 bool (*compute_config)(struct intel_encoder *,
132 struct intel_crtc_config *);
dafd226c 133 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 134 void (*pre_enable)(struct intel_encoder *);
ef9c3aee 135 void (*enable)(struct intel_encoder *);
6cc5f341 136 void (*mode_set)(struct intel_encoder *intel_encoder);
ef9c3aee 137 void (*disable)(struct intel_encoder *);
bf49ec8c 138 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 139 /* Read out the current hw state of this connector, returning true if
140 * the encoder is active. If the encoder is enabled it also set the pipe
141 * it is connected to in the pipe parameter. */
142 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 143 int crtc_mask;
1d843f9d 144 enum hpd_pin hpd_pin;
79e53945
JB		 145};
146
1d508706 147struct intel_panel {
dd06f90e 148 struct drm_display_mode *fixed_mode;
4d891523 149 int fitting_mode;
1d508706
JN		 150};
151
5daa55eb
ZW		 152struct intel_connector {
153 struct drm_connector base;
9a935856
DV		 154 /*
155 * The fixed encoder this connector is connected to.
156 */
df0e9248 157 struct intel_encoder *encoder;
9a935856
DV		 158
159 /*
160 * The new encoder this connector will be driven. Only differs from
161 * encoder while a modeset is in progress.
162 */
163 struct intel_encoder *new_encoder;
164
f0947c37
DV		 165 /* Reads out the current hw, returning true if the connector is enabled
166 * and active (i.e. dpms ON state). */
167 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 168
169 /* Panel info for eDP and LVDS */
170 struct intel_panel panel;
9cd300e0
JN		 171
172 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
173 struct edid *edid;
821450c6
EE		 174
175 /* since POLL and HPD connectors may use the same HPD line keep the native
176 state of connector->polled in case hotplug storm detection changes it */
177 u8 polled;
5daa55eb
ZW		 178};
179
80ad9206
VS		 180typedef struct dpll {
181 /* given values */
182 int n;
183 int m1, m2;
184 int p1, p2;
185 /* derived values */
186 int dot;
187 int vco;
188 int m;
189 int p;
190} intel_clock_t;
191
b8cecdf5
DV		 192struct intel_crtc_config {
193 struct drm_display_mode requested_mode;
194 struct drm_display_mode adjusted_mode;
7ae89233
DV		 195 /* This flag must be set by the encoder's compute_config callback if it
196 * changes the crtc timings in the mode to prevent the crtc fixup from
197 * overwriting them. Currently only lvds needs that. */
198 bool timings_set;
5bfe2ac0
DV		 199 /* Whether to set up the PCH/FDI. Note that we never allow sharing
200 * between pch encoders and cpu encoders. */
201 bool has_pch_encoder;
50f3b016 202
3b117c8f
DV		 203 /* CPU Transcoder for the pipe. Currently this can only differ from the
204 * pipe on Haswell (where we have a special eDP transcoder). */
205 enum transcoder cpu_transcoder;
206
50f3b016
DV		 207 /*
208 * Use reduced/limited/broadcast rbg range, compressing from the full
209 * range fed into the crtcs.
210 */
211 bool limited_color_range;
212
03afc4a2
DV		 213 /* DP has a bunch of special case unfortunately, so mark the pipe
214 * accordingly. */
215 bool has_dp_encoder;
d8b32247
DV		 216
217 /*
218 * Enable dithering, used when the selected pipe bpp doesn't match the
219 * plane bpp.
220 */
965e0c48 221 bool dither;
f47709a9
DV		 222
223 /* Controls for the clock computation, to override various stages. */
224 bool clock_set;
225
e29c22c0
DV		 226 /*
227 * crtc bandwidth limit, don't increase pipe bpp or clock if not really
228 * required. This is set in the 2nd loop of calling encoder's
229 * ->compute_config if the first pick doesn't work out.
230 */
231 bool bw_constrained;
232
f47709a9
DV		 233 /* Settings for the intel dpll used on pretty much everything but
234 * haswell. */
80ad9206 235 struct dpll dpll;
f47709a9 236
965e0c48 237 int pipe_bpp;
6cf86a5e 238 struct intel_link_m_n dp_m_n;
df92b1e6
DV		 239 /**
240 * This is currently used by DP and HDMI encoders since those can have a
241 * target pixel clock != the port link clock (which is currently stored
242 * in adjusted_mode->clock).
243 */
244 int pixel_target_clock;
6cc5f341
DV		 245 /* Used by SDVO (and if we ever fix it, HDMI). */
246 unsigned pixel_multiplier;
2dd24552
JB		 247
248 /* Panel fitter controls for gen2-gen4 + VLV */
b074cec8
JB		 249 struct {
250 u32 control;
251 u32 pgm_ratios;
252 } gmch_pfit;
253
254 /* Panel fitter placement and size for Ironlake+ */
255 struct {
256 u32 pos;
257 u32 size;
258 } pch_pfit;
33d29b14 259
ca3a0ff8 260 /* FDI configuration, only valid if has_pch_encoder is set. */
33d29b14 261 int fdi_lanes;
ca3a0ff8 262 struct intel_link_m_n fdi_m_n;
b8cecdf5
DV		 263};
264
79e53945
JB		 265struct intel_crtc {
266 struct drm_crtc base;
80824003
JB		 267 enum pipe pipe;
268 enum plane plane;
79e53945 269 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 270 /*
271 * Whether the crtc and the connected output pipeline is active. Implies
272 * that crtc->enabled is set, i.e. the current mode configuration has
273 * some outputs connected to this crtc.
08a48469
DV		 274 */
275 bool active;
7b9f35a6 276 bool eld_vld;
93314b5b 277 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 278 bool lowfreq_avail;
02e792fb 279 struct intel_overlay *overlay;
6b95a207 280 struct intel_unpin_work *unpin_work;
cda4b7d3 281
b4a98e57
CW		 282 atomic_t unpin_work_count;
283
e506a0c6
DV		 284 /* Display surface base address adjustement for pageflips. Note that on
285 * gen4+ this only adjusts up to a tile, offsets within a tile are
286 * handled in the hw itself (with the TILEOFF register). */
287 unsigned long dspaddr_offset;
288
05394f39 289 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 290 uint32_t cursor_addr;
291 int16_t cursor_x, cursor_y;
292 int16_t cursor_width, cursor_height;
6b383a7f 293 bool cursor_visible;
4b645f14 294
b8cecdf5
DV		 295 struct intel_crtc_config config;
296
ee7b9f93
JB		 297 /* We can share PLLs across outputs if the timings match */
298 struct intel_pch_pll *pch_pll;
6441ab5f 299 uint32_t ddi_pll_sel;
10d83730
VS		 300
301 /* reset counter value when the last flip was submitted */
302 unsigned int reset_counter;
8664281b
PZ		 303
304 /* Access to these should be protected by dev_priv->irq_lock. */
305 bool cpu_fifo_underrun_disabled;
306 bool pch_fifo_underrun_disabled;
79e53945
JB		 307};
308
b840d907
JB		 309struct intel_plane {
310 struct drm_plane base;
7f1f3851 311 int plane;
b840d907
JB		 312 enum pipe pipe;
313 struct drm_i915_gem_object *obj;
2d354c34 314 bool can_scale;
b840d907
JB		 315 int max_downscale;
316 u32 lut_r[1024], lut_g[1024], lut_b[1024];
5e1bac2f
JB		 317 int crtc_x, crtc_y;
318 unsigned int crtc_w, crtc_h;
319 uint32_t src_x, src_y;
320 uint32_t src_w, src_h;
b840d907
JB		 321 void (*update_plane)(struct drm_plane *plane,
322 struct drm_framebuffer *fb,
323 struct drm_i915_gem_object *obj,
324 int crtc_x, int crtc_y,
325 unsigned int crtc_w, unsigned int crtc_h,
326 uint32_t x, uint32_t y,
327 uint32_t src_w, uint32_t src_h);
328 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 329 int (*update_colorkey)(struct drm_plane *plane,
330 struct drm_intel_sprite_colorkey *key);
331 void (*get_colorkey)(struct drm_plane *plane,
332 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 333};
334
b445e3b0
ED		 335struct intel_watermark_params {
336 unsigned long fifo_size;
337 unsigned long max_wm;
338 unsigned long default_wm;
339 unsigned long guard_size;
340 unsigned long cacheline_size;
341};
342
343struct cxsr_latency {
344 int is_desktop;
345 int is_ddr3;
346 unsigned long fsb_freq;
347 unsigned long mem_freq;
348 unsigned long display_sr;
349 unsigned long display_hpll_disable;
350 unsigned long cursor_sr;
351 unsigned long cursor_hpll_disable;
352};
353
79e53945 354#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 355#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 356#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 357#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 358#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 359
45187ace
JB		 360#define DIP_HEADER_SIZE 5
361
3c17fe4b
DH		 362#define DIP_TYPE_AVI 0x82
363#define DIP_VERSION_AVI 0x2
364#define DIP_LEN_AVI 13
c846b619
PZ		 365#define DIP_AVI_PR_1 0
366#define DIP_AVI_PR_2 1
abedc077
VS		 367#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
368#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
369#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
3c17fe4b 370
26005210 371#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 372#define DIP_VERSION_SPD 0x1
373#define DIP_LEN_SPD 25
374#define DIP_SPD_UNKNOWN 0
375#define DIP_SPD_DSTB 0x1
376#define DIP_SPD_DVDP 0x2
377#define DIP_SPD_DVHS 0x3
378#define DIP_SPD_HDDVR 0x4
379#define DIP_SPD_DVC 0x5
380#define DIP_SPD_DSC 0x6
381#define DIP_SPD_VCD 0x7
382#define DIP_SPD_GAME 0x8
383#define DIP_SPD_PC 0x9
384#define DIP_SPD_BD 0xa
385#define DIP_SPD_SCD 0xb
386
3c17fe4b
DH		 387struct dip_infoframe {
388 uint8_t type; /* HB0 */
389 uint8_t ver; /* HB1 */
390 uint8_t len; /* HB2 - body len, not including checksum */
391 uint8_t ecc; /* Header ECC */
392 uint8_t checksum; /* PB0 */
393 union {
394 struct {
395 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
396 uint8_t Y_A_B_S;
397 /* PB2 - C 7:6, M 5:4, R 3:0 */
398 uint8_t C_M_R;
399 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
400 uint8_t ITC_EC_Q_SC;
401 /* PB4 - VIC 6:0 */
402 uint8_t VIC;
0aa534df
PZ		 403 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
404 uint8_t YQ_CN_PR;
3c17fe4b
DH		 405 /* PB6 to PB13 */
406 uint16_t top_bar_end;
407 uint16_t bottom_bar_start;
408 uint16_t left_bar_end;
409 uint16_t right_bar_start;
81014b9d 410 } __attribute__ ((packed)) avi;
c0864cb3
JB		 411 struct {
412 uint8_t vn[8];
413 uint8_t pd[16];
414 uint8_t sdi;
81014b9d 415 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 416 uint8_t payload[27];
417 } __attribute__ ((packed)) body;
418} __attribute__((packed));
419
f5bbfca3 420struct intel_hdmi {
b242b7f7 421 u32 hdmi_reg;
f5bbfca3 422 int ddc_bus;
f5bbfca3 423 uint32_t color_range;
55bc60db 424 bool color_range_auto;
f5bbfca3
ED		 425 bool has_hdmi_sink;
426 bool has_audio;
427 enum hdmi_force_audio force_audio;
abedc077 428 bool rgb_quant_range_selectable;
f5bbfca3
ED		 429 void (*write_infoframe)(struct drm_encoder *encoder,
430 struct dip_infoframe *frame);
687f4d06
PZ		 431 void (*set_infoframes)(struct drm_encoder *encoder,
432 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 433};
434
b091cd92 435#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 436#define DP_LINK_CONFIGURATION_SIZE 9
437
438struct intel_dp {
54d63ca6 439 uint32_t output_reg;
9ed35ab1 440 uint32_t aux_ch_ctl_reg;
54d63ca6
SK		 441 uint32_t DP;
442 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
443 bool has_audio;
444 enum hdmi_force_audio force_audio;
445 uint32_t color_range;
55bc60db 446 bool color_range_auto;
54d63ca6
SK		 447 uint8_t link_bw;
448 uint8_t lane_count;
449 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 450 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 451 struct i2c_adapter adapter;
452 struct i2c_algo_dp_aux_data algo;
453 bool is_pch_edp;
454 uint8_t train_set[4];
455 int panel_power_up_delay;
456 int panel_power_down_delay;
457 int panel_power_cycle_delay;
458 int backlight_on_delay;
459 int backlight_off_delay;
54d63ca6
SK		 460 struct delayed_work panel_vdd_work;
461 bool want_panel_vdd;
dd06f90e 462 struct intel_connector *attached_connector;
54d63ca6
SK		 463};
464
da63a9f2
PZ		 465struct intel_digital_port {
466 struct intel_encoder base;
174edf1f 467 enum port port;
876a8cdf 468 u32 port_reversal;
da63a9f2
PZ		 469 struct intel_dp dp;
470 struct intel_hdmi hdmi;
471};
472
89b667f8
JB		 473static inline int
474vlv_dport_to_channel(struct intel_digital_port *dport)
475{
476 switch (dport->port) {
477 case PORT_B:
478 return 0;
479 case PORT_C:
480 return 1;
481 default:
482 BUG();
483 }
484}
485
f875c15a
CW		 486static inline struct drm_crtc *
487intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
488{
489 struct drm_i915_private *dev_priv = dev->dev_private;
490 return dev_priv->pipe_to_crtc_mapping[pipe];
491}
492
417ae147
CW		 493static inline struct drm_crtc *
494intel_get_crtc_for_plane(struct drm_device *dev, int plane)
495{
496 struct drm_i915_private *dev_priv = dev->dev_private;
497 return dev_priv->plane_to_crtc_mapping[plane];
498}
499
4e5359cd
SF		 500struct intel_unpin_work {
501 struct work_struct work;
b4a98e57 502 struct drm_crtc *crtc;
05394f39
CW		 503 struct drm_i915_gem_object *old_fb_obj;
504 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 505 struct drm_pending_vblank_event *event;
e7d841ca
CW		 506 atomic_t pending;
507#define INTEL_FLIP_INACTIVE 0
508#define INTEL_FLIP_PENDING 1
509#define INTEL_FLIP_COMPLETE 2
4e5359cd
SF		 510 bool enable_stall_check;
511};
512
1630fe75
CW		 513struct intel_fbc_work {
514 struct delayed_work work;
515 struct drm_crtc *crtc;
516 struct drm_framebuffer *fb;
517 int interval;
518};
519
d2acd215
DV		 520int intel_pch_rawclk(struct drm_device *dev);
521
4eab8136
JN		 522int intel_connector_update_modes(struct drm_connector *connector,
523 struct edid *edid);
335af9a2 524int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 525
3f43c48d 526extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 527extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
528
8664281b 529extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
79e53945 530extern void intel_crt_init(struct drm_device *dev);
08d644ad 531extern void intel_hdmi_init(struct drm_device *dev,
b242b7f7 532 int hdmi_reg, enum port port);
00c09d70
PZ		 533extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
534 struct intel_connector *intel_connector);
f5bbfca3 535extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
5bfe2ac0
DV		 536extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
537 struct intel_crtc_config *pipe_config);
f5bbfca3 538extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 539extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
540 bool is_sdvob);
79e53945
JB		 541extern void intel_dvo_init(struct drm_device *dev);
542extern void intel_tv_init(struct drm_device *dev);
f047e395 543extern void intel_mark_busy(struct drm_device *dev);
f047e395 544extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
725a5b54 545extern void intel_mark_idle(struct drm_device *dev);
c5d1b51d 546extern bool intel_lvds_init(struct drm_device *dev);
1974cad0 547extern bool intel_is_dual_link_lvds(struct drm_device *dev);
ab9d7c30
PZ		 548extern void intel_dp_init(struct drm_device *dev, int output_reg,
549 enum port port);
00c09d70
PZ		 550extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
551 struct intel_connector *intel_connector);
247d89f6 552extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 553extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
554extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
555extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
00c09d70
PZ		 556extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
557extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
5bfe2ac0
DV		 558extern bool intel_dp_compute_config(struct intel_encoder *encoder,
559 struct intel_crtc_config *pipe_config);
cb0953d7 560extern bool intel_dpd_is_edp(struct drm_device *dev);
d6c50ff8
PZ		 561extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
562extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
82a4d9c0
PZ		 563extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
564extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
565extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
566extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
814948ad 567extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
7f1f3851 568extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
6f1d69b0
ED		 569extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
570 enum plane plane);
32f9d658 571
a9573556 572/* intel_panel.c */
dd06f90e
JN		 573extern int intel_panel_init(struct intel_panel *panel,
574 struct drm_display_mode *fixed_mode);
1d508706
JN		 575extern void intel_panel_fini(struct intel_panel *panel);
576
1d8e1c75
CW		 577extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
578 struct drm_display_mode *adjusted_mode);
b074cec8
JB		 579extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
580 struct intel_crtc_config *pipe_config,
581 int fitting_mode);
2dd24552
JB		 582extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
583 struct intel_crtc_config *pipe_config,
584 int fitting_mode);
d6540632
JN		 585extern void intel_panel_set_backlight(struct drm_device *dev,
586 u32 level, u32 max);
0657b6b1 587extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 588extern void intel_panel_enable_backlight(struct drm_device *dev,
589 enum pipe pipe);
47356eb6 590extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 591extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 592extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 593
d9e55608 594struct intel_set_config {
1aa4b628
DV		 595 struct drm_encoder **save_connector_encoders;
596 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 597
598 bool fb_changed;
599 bool mode_changed;
d9e55608
DV		 600};
601
c0c36b94
CW		 602extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
603 int x, int y, struct drm_framebuffer *old_fb);
a261b246 604extern void intel_modeset_disable(struct drm_device *dev);
c0c36b94 605extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
79e53945 606extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 607extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
ea5b213a 608extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 609extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 610extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 611extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 612extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c 613extern void intel_modeset_check_state(struct drm_device *dev);
5e1bac2f 614extern void intel_plane_restore(struct drm_plane *plane);
b980514c 615
79e53945 616
df0e9248
CW		 617static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
618{
619 return to_intel_connector(connector)->encoder;
620}
621
7739c33b
PZ		 622static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
623{
da63a9f2
PZ		 624 struct intel_digital_port *intel_dig_port =
625 container_of(encoder, struct intel_digital_port, base.base);
626 return &intel_dig_port->dp;
627}
628
629static inline struct intel_digital_port *
630enc_to_dig_port(struct drm_encoder *encoder)
631{
632 return container_of(encoder, struct intel_digital_port, base.base);
633}
634
635static inline struct intel_digital_port *
636dp_to_dig_port(struct intel_dp *intel_dp)
637{
638 return container_of(intel_dp, struct intel_digital_port, dp);
639}
640
641static inline struct intel_digital_port *
642hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
643{
644 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ		 645}
646
b0ea7d37
DL		 647bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
648 struct intel_digital_port *port);
649
df0e9248
CW		 650extern void intel_connector_attach_encoder(struct intel_connector *connector,
651 struct intel_encoder *encoder);
652extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 653
654extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
655 struct drm_crtc *crtc);
08d7b3d1
CW		 656int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
657 struct drm_file *file_priv);
a5c961d1
PZ		 658extern enum transcoder
659intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
660 enum pipe pipe);
9d0498a2 661extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 662extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
d4b1931c 663extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
89b667f8 664extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
8261b191
CW		 665
666struct intel_load_detect_pipe {
d2dff872 667 struct drm_framebuffer *release_fb;
8261b191
CW		 668 bool load_detect_temp;
669 int dpms_mode;
670};
d2434ab7 671extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 672 struct drm_display_mode *mode,
8261b191 673 struct intel_load_detect_pipe *old);
d2434ab7 674extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 675 struct intel_load_detect_pipe *old);
79e53945 676
79e53945
JB		 677extern void intelfb_restore(void);
678extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
679 u16 blue, int regno);
b8c00ac5
DA		 680extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
681 u16 *blue, int regno);
0cdab21f 682extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 683
127bd2ac 684extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 685 struct drm_i915_gem_object *obj,
919926ae 686 struct intel_ring_buffer *pipelined);
1690e1eb 687extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 688
38651674
DA		 689extern int intel_framebuffer_init(struct drm_device *dev,
690 struct intel_framebuffer *ifb,
308e5bcb 691 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 692 struct drm_i915_gem_object *obj);
38651674 693extern int intel_fbdev_init(struct drm_device *dev);
20afbda2 694extern void intel_fbdev_initial_config(struct drm_device *dev);
38651674 695extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 696extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 697extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
698extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 699extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 700
02e792fb
DV		 701extern void intel_setup_overlay(struct drm_device *dev);
702extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 703extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 704extern int intel_overlay_put_image(struct drm_device *dev, void *data,
705 struct drm_file *file_priv);
706extern int intel_overlay_attrs(struct drm_device *dev, void *data,
707 struct drm_file *file_priv);
4abe3520 708
eb1f8e4f 709extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 710extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 711
b840d907
JB		 712extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
713 bool state);
714#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
715#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
716
645c62a5 717extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 718extern void intel_write_eld(struct drm_encoder *encoder,
719 struct drm_display_mode *mode);
d4270e57 720extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
6cf86a5e
DV		 721extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
722 struct intel_link_m_n *m_n);
723extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
724 struct intel_link_m_n *m_n);
45244b87 725extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 726extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 727extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 728
b840d907 729/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 730extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 731extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
732 uint32_t sprite_width,
733 int pixel_size);
1f8eeabf
ED		 734extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
735 struct drm_display_mode *mode);
8ea30864 736
bc752862
CW		 737extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
738 unsigned int tiling_mode,
739 unsigned int bpp,
740 unsigned int pitch);
5a35e99e 741
8ea30864
JB		 742extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
743 struct drm_file *file_priv);
744extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
745 struct drm_file *file_priv);
746
57f350b6 747extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
e2fa6fba
P		 748extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
749 u32 val);
57f350b6 750
85208be0 751/* Power-related functions, located in intel_pm.c */
1fa61106 752extern void intel_init_pm(struct drm_device *dev);
85208be0 753/* FBC */
85208be0
ED		 754extern bool intel_fbc_enabled(struct drm_device *dev);
755extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
756extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 757/* IPS */
758extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
759extern void intel_gpu_ips_teardown(void);
85208be0 760
15d199ea 761extern bool intel_using_power_well(struct drm_device *dev);
fa42e23c 762extern void intel_init_power_well(struct drm_device *dev);
cb10799c 763extern void intel_set_power_well(struct drm_device *dev, bool enable);
8090c6b9
DV		 764extern void intel_enable_gt_powersave(struct drm_device *dev);
765extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 766extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 767extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 768
85234cdc
DV		 769extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
770 enum pipe *pipe);
b8fc2f6a 771extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
79f689aa 772extern void intel_ddi_pll_init(struct drm_device *dev);
8228c251 773extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
ad80a810
PZ		 774extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
775 enum transcoder cpu_transcoder);
fc914639
PZ		 776extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
777extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 778extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
779extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
6441ab5f 780extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 781extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 782extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
1ad960f2
PZ		 783extern bool
784intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
785extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
72662e10 786
96a02917 787extern void intel_display_handle_reset(struct drm_device *dev);
8664281b
PZ		 788extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
789 enum pipe pipe,
790 bool enable);
791extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
792 enum transcoder pch_transcoder,
793 bool enable);
96a02917 794
79e53945 795#endif /* __INTEL_DRV_H__ */
Linux 6.x block layer and io_uring tree(s)