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drm/i915: fold wait_for_atomic_us into wait_for_atomic
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
0cc2764c
BW		 44 if (W && drm_can_sleep()) { \
45 msleep(W); \
46 } else { \
47 cpu_relax(); \
48 } \
913d8d11
CW		 49 } \
50 ret__; \
51})
52
481b6af3
CW		 53#define wait_for(COND, MS) _wait_for(COND, MS, 1)
54#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
6effa33b
DV		 55#define wait_for_atomic_us(COND, US) _wait_for((COND), \
56 DIV_ROUND_UP((US), 1000), 0)
481b6af3 57
021357ac
CW		 58#define KHz(x) (1000*x)
59#define MHz(x) KHz(1000*x)
60
79e53945
JB		 61/*
62 * Display related stuff
63 */
64
65/* store information about an Ixxx DVO */
66/* The i830->i865 use multiple DVOs with multiple i2cs */
67/* the i915, i945 have a single sDVO i2c bus - which is different */
68#define MAX_OUTPUTS 6
69/* maximum connectors per crtcs in the mode set */
70#define INTELFB_CONN_LIMIT 4
71
72#define INTEL_I2C_BUS_DVO 1
73#define INTEL_I2C_BUS_SDVO 2
74
75/* these are outputs from the chip - integrated only
76 external chips are via DVO or SDVO output */
77#define INTEL_OUTPUT_UNUSED 0
78#define INTEL_OUTPUT_ANALOG 1
79#define INTEL_OUTPUT_DVO 2
80#define INTEL_OUTPUT_SDVO 3
81#define INTEL_OUTPUT_LVDS 4
82#define INTEL_OUTPUT_TVOUT 5
7d57382e 83#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 84#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 85#define INTEL_OUTPUT_EDP 8
00c09d70 86#define INTEL_OUTPUT_UNKNOWN 9
79e53945
JB		 87
88#define INTEL_DVO_CHIP_NONE 0
89#define INTEL_DVO_CHIP_LVDS 1
90#define INTEL_DVO_CHIP_TMDS 2
91#define INTEL_DVO_CHIP_TVOUT 4
92
79e53945
JB		 93struct intel_framebuffer {
94 struct drm_framebuffer base;
05394f39 95 struct drm_i915_gem_object *obj;
79e53945
JB		 96};
97
37811fcc
CW		 98struct intel_fbdev {
99 struct drm_fb_helper helper;
100 struct intel_framebuffer ifb;
101 struct list_head fbdev_list;
102 struct drm_display_mode *our_mode;
103};
79e53945 104
21d40d37 105struct intel_encoder {
4ef69c7a 106 struct drm_encoder base;
9a935856
DV		 107 /*
108 * The new crtc this encoder will be driven from. Only differs from
109 * base->crtc while a modeset is in progress.
110 */
111 struct intel_crtc *new_crtc;
112
79e53945 113 int type;
e2f0ba97 114 bool needs_tv_clock;
66a9278e
DV		 115 /*
116 * Intel hw has only one MUX where encoders could be clone, hence a
117 * simple flag is enough to compute the possible_clones mask.
118 */
119 bool cloneable;
5ab432ef 120 bool connectors_active;
21d40d37 121 void (*hot_plug)(struct intel_encoder *);
7ae89233
DV		 122 bool (*compute_config)(struct intel_encoder *,
123 struct intel_crtc_config *);
dafd226c 124 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 125 void (*pre_enable)(struct intel_encoder *);
ef9c3aee 126 void (*enable)(struct intel_encoder *);
6cc5f341 127 void (*mode_set)(struct intel_encoder *intel_encoder);
ef9c3aee 128 void (*disable)(struct intel_encoder *);
bf49ec8c 129 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 130 /* Read out the current hw state of this connector, returning true if
131 * the encoder is active. If the encoder is enabled it also set the pipe
132 * it is connected to in the pipe parameter. */
133 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 134 int crtc_mask;
1d843f9d 135 enum hpd_pin hpd_pin;
79e53945
JB		 136};
137
1d508706 138struct intel_panel {
dd06f90e 139 struct drm_display_mode *fixed_mode;
4d891523 140 int fitting_mode;
1d508706
JN		 141};
142
5daa55eb
ZW		 143struct intel_connector {
144 struct drm_connector base;
9a935856
DV		 145 /*
146 * The fixed encoder this connector is connected to.
147 */
df0e9248 148 struct intel_encoder *encoder;
9a935856
DV		 149
150 /*
151 * The new encoder this connector will be driven. Only differs from
152 * encoder while a modeset is in progress.
153 */
154 struct intel_encoder *new_encoder;
155
f0947c37
DV		 156 /* Reads out the current hw, returning true if the connector is enabled
157 * and active (i.e. dpms ON state). */
158 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 159
160 /* Panel info for eDP and LVDS */
161 struct intel_panel panel;
9cd300e0
JN		 162
163 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
164 struct edid *edid;
5daa55eb
ZW		 165};
166
b8cecdf5
DV		 167struct intel_crtc_config {
168 struct drm_display_mode requested_mode;
169 struct drm_display_mode adjusted_mode;
7ae89233
DV		 170 /* This flag must be set by the encoder's compute_config callback if it
171 * changes the crtc timings in the mode to prevent the crtc fixup from
172 * overwriting them. Currently only lvds needs that. */
173 bool timings_set;
5bfe2ac0
DV		 174 /* Whether to set up the PCH/FDI. Note that we never allow sharing
175 * between pch encoders and cpu encoders. */
176 bool has_pch_encoder;
50f3b016
DV		 177
178 /*
179 * Use reduced/limited/broadcast rbg range, compressing from the full
180 * range fed into the crtcs.
181 */
182 bool limited_color_range;
183
965e0c48
DV		 184 bool dither;
185 int pipe_bpp;
186
6cc5f341
DV		 187 /* Used by SDVO (and if we ever fix it, HDMI). */
188 unsigned pixel_multiplier;
b8cecdf5
DV		 189};
190
79e53945
JB		 191struct intel_crtc {
192 struct drm_crtc base;
80824003
JB		 193 enum pipe pipe;
194 enum plane plane;
a5c961d1 195 enum transcoder cpu_transcoder;
79e53945 196 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 197 /*
198 * Whether the crtc and the connected output pipeline is active. Implies
199 * that crtc->enabled is set, i.e. the current mode configuration has
200 * some outputs connected to this crtc.
08a48469
DV		 201 */
202 bool active;
7b9f35a6 203 bool eld_vld;
93314b5b 204 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 205 bool lowfreq_avail;
02e792fb 206 struct intel_overlay *overlay;
6b95a207 207 struct intel_unpin_work *unpin_work;
77ffb597 208 int fdi_lanes;
cda4b7d3 209
b4a98e57
CW		 210 atomic_t unpin_work_count;
211
e506a0c6
DV		 212 /* Display surface base address adjustement for pageflips. Note that on
213 * gen4+ this only adjusts up to a tile, offsets within a tile are
214 * handled in the hw itself (with the TILEOFF register). */
215 unsigned long dspaddr_offset;
216
05394f39 217 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 218 uint32_t cursor_addr;
219 int16_t cursor_x, cursor_y;
220 int16_t cursor_width, cursor_height;
6b383a7f 221 bool cursor_visible;
4b645f14 222
b8cecdf5
DV		 223 struct intel_crtc_config config;
224
ee7b9f93
JB		 225 /* We can share PLLs across outputs if the timings match */
226 struct intel_pch_pll *pch_pll;
6441ab5f 227 uint32_t ddi_pll_sel;
10d83730
VS		 228
229 /* reset counter value when the last flip was submitted */
230 unsigned int reset_counter;
79e53945
JB		 231};
232
b840d907
JB		 233struct intel_plane {
234 struct drm_plane base;
235 enum pipe pipe;
236 struct drm_i915_gem_object *obj;
2d354c34 237 bool can_scale;
b840d907
JB		 238 int max_downscale;
239 u32 lut_r[1024], lut_g[1024], lut_b[1024];
5e1bac2f
JB		 240 int crtc_x, crtc_y;
241 unsigned int crtc_w, crtc_h;
242 uint32_t src_x, src_y;
243 uint32_t src_w, src_h;
b840d907
JB		 244 void (*update_plane)(struct drm_plane *plane,
245 struct drm_framebuffer *fb,
246 struct drm_i915_gem_object *obj,
247 int crtc_x, int crtc_y,
248 unsigned int crtc_w, unsigned int crtc_h,
249 uint32_t x, uint32_t y,
250 uint32_t src_w, uint32_t src_h);
251 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 252 int (*update_colorkey)(struct drm_plane *plane,
253 struct drm_intel_sprite_colorkey *key);
254 void (*get_colorkey)(struct drm_plane *plane,
255 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 256};
257
b445e3b0
ED		 258struct intel_watermark_params {
259 unsigned long fifo_size;
260 unsigned long max_wm;
261 unsigned long default_wm;
262 unsigned long guard_size;
263 unsigned long cacheline_size;
264};
265
266struct cxsr_latency {
267 int is_desktop;
268 int is_ddr3;
269 unsigned long fsb_freq;
270 unsigned long mem_freq;
271 unsigned long display_sr;
272 unsigned long display_hpll_disable;
273 unsigned long cursor_sr;
274 unsigned long cursor_hpll_disable;
275};
276
79e53945 277#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 278#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 279#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 280#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 281#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 282
45187ace
JB		 283#define DIP_HEADER_SIZE 5
284
3c17fe4b
DH		 285#define DIP_TYPE_AVI 0x82
286#define DIP_VERSION_AVI 0x2
287#define DIP_LEN_AVI 13
c846b619
PZ		 288#define DIP_AVI_PR_1 0
289#define DIP_AVI_PR_2 1
abedc077
VS		 290#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
291#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
292#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
3c17fe4b 293
26005210 294#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 295#define DIP_VERSION_SPD 0x1
296#define DIP_LEN_SPD 25
297#define DIP_SPD_UNKNOWN 0
298#define DIP_SPD_DSTB 0x1
299#define DIP_SPD_DVDP 0x2
300#define DIP_SPD_DVHS 0x3
301#define DIP_SPD_HDDVR 0x4
302#define DIP_SPD_DVC 0x5
303#define DIP_SPD_DSC 0x6
304#define DIP_SPD_VCD 0x7
305#define DIP_SPD_GAME 0x8
306#define DIP_SPD_PC 0x9
307#define DIP_SPD_BD 0xa
308#define DIP_SPD_SCD 0xb
309
3c17fe4b
DH		 310struct dip_infoframe {
311 uint8_t type; /* HB0 */
312 uint8_t ver; /* HB1 */
313 uint8_t len; /* HB2 - body len, not including checksum */
314 uint8_t ecc; /* Header ECC */
315 uint8_t checksum; /* PB0 */
316 union {
317 struct {
318 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
319 uint8_t Y_A_B_S;
320 /* PB2 - C 7:6, M 5:4, R 3:0 */
321 uint8_t C_M_R;
322 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
323 uint8_t ITC_EC_Q_SC;
324 /* PB4 - VIC 6:0 */
325 uint8_t VIC;
0aa534df
PZ		 326 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
327 uint8_t YQ_CN_PR;
3c17fe4b
DH		 328 /* PB6 to PB13 */
329 uint16_t top_bar_end;
330 uint16_t bottom_bar_start;
331 uint16_t left_bar_end;
332 uint16_t right_bar_start;
81014b9d 333 } __attribute__ ((packed)) avi;
c0864cb3
JB		 334 struct {
335 uint8_t vn[8];
336 uint8_t pd[16];
337 uint8_t sdi;
81014b9d 338 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 339 uint8_t payload[27];
340 } __attribute__ ((packed)) body;
341} __attribute__((packed));
342
f5bbfca3 343struct intel_hdmi {
b242b7f7 344 u32 hdmi_reg;
f5bbfca3 345 int ddc_bus;
f5bbfca3 346 uint32_t color_range;
55bc60db 347 bool color_range_auto;
f5bbfca3
ED		 348 bool has_hdmi_sink;
349 bool has_audio;
350 enum hdmi_force_audio force_audio;
abedc077 351 bool rgb_quant_range_selectable;
f5bbfca3
ED		 352 void (*write_infoframe)(struct drm_encoder *encoder,
353 struct dip_infoframe *frame);
687f4d06
PZ		 354 void (*set_infoframes)(struct drm_encoder *encoder,
355 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 356};
357
b091cd92 358#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 359#define DP_LINK_CONFIGURATION_SIZE 9
360
361struct intel_dp {
54d63ca6 362 uint32_t output_reg;
9ed35ab1 363 uint32_t aux_ch_ctl_reg;
54d63ca6
SK		 364 uint32_t DP;
365 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
366 bool has_audio;
367 enum hdmi_force_audio force_audio;
368 uint32_t color_range;
55bc60db 369 bool color_range_auto;
54d63ca6
SK		 370 uint8_t link_bw;
371 uint8_t lane_count;
372 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 373 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 374 struct i2c_adapter adapter;
375 struct i2c_algo_dp_aux_data algo;
376 bool is_pch_edp;
377 uint8_t train_set[4];
378 int panel_power_up_delay;
379 int panel_power_down_delay;
380 int panel_power_cycle_delay;
381 int backlight_on_delay;
382 int backlight_off_delay;
54d63ca6
SK		 383 struct delayed_work panel_vdd_work;
384 bool want_panel_vdd;
dd06f90e 385 struct intel_connector *attached_connector;
54d63ca6
SK		 386};
387
da63a9f2
PZ		 388struct intel_digital_port {
389 struct intel_encoder base;
174edf1f 390 enum port port;
876a8cdf 391 u32 port_reversal;
da63a9f2
PZ		 392 struct intel_dp dp;
393 struct intel_hdmi hdmi;
394};
395
f875c15a
CW		 396static inline struct drm_crtc *
397intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
398{
399 struct drm_i915_private *dev_priv = dev->dev_private;
400 return dev_priv->pipe_to_crtc_mapping[pipe];
401}
402
417ae147
CW		 403static inline struct drm_crtc *
404intel_get_crtc_for_plane(struct drm_device *dev, int plane)
405{
406 struct drm_i915_private *dev_priv = dev->dev_private;
407 return dev_priv->plane_to_crtc_mapping[plane];
408}
409
4e5359cd
SF		 410struct intel_unpin_work {
411 struct work_struct work;
b4a98e57 412 struct drm_crtc *crtc;
05394f39
CW		 413 struct drm_i915_gem_object *old_fb_obj;
414 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 415 struct drm_pending_vblank_event *event;
e7d841ca
CW		 416 atomic_t pending;
417#define INTEL_FLIP_INACTIVE 0
418#define INTEL_FLIP_PENDING 1
419#define INTEL_FLIP_COMPLETE 2
4e5359cd
SF		 420 bool enable_stall_check;
421};
422
1630fe75
CW		 423struct intel_fbc_work {
424 struct delayed_work work;
425 struct drm_crtc *crtc;
426 struct drm_framebuffer *fb;
427 int interval;
428};
429
d2acd215
DV		 430int intel_pch_rawclk(struct drm_device *dev);
431
4eab8136
JN		 432int intel_connector_update_modes(struct drm_connector *connector,
433 struct edid *edid);
335af9a2 434int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 435
3f43c48d 436extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 437extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
438
79e53945 439extern void intel_crt_init(struct drm_device *dev);
08d644ad 440extern void intel_hdmi_init(struct drm_device *dev,
b242b7f7 441 int hdmi_reg, enum port port);
00c09d70
PZ		 442extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
443 struct intel_connector *intel_connector);
f5bbfca3 444extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
5bfe2ac0
DV		 445extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
446 struct intel_crtc_config *pipe_config);
f5bbfca3 447extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 448extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
449 bool is_sdvob);
79e53945
JB		 450extern void intel_dvo_init(struct drm_device *dev);
451extern void intel_tv_init(struct drm_device *dev);
f047e395 452extern void intel_mark_busy(struct drm_device *dev);
f047e395 453extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
725a5b54 454extern void intel_mark_idle(struct drm_device *dev);
c5d1b51d 455extern bool intel_lvds_init(struct drm_device *dev);
1974cad0 456extern bool intel_is_dual_link_lvds(struct drm_device *dev);
ab9d7c30
PZ		 457extern void intel_dp_init(struct drm_device *dev, int output_reg,
458 enum port port);
00c09d70
PZ		 459extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
460 struct intel_connector *intel_connector);
a4fc5ed6
KP		 461void
462intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
463 struct drm_display_mode *adjusted_mode);
247d89f6 464extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 465extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
466extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
467extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
00c09d70
PZ		 468extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
469extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
5bfe2ac0
DV		 470extern bool intel_dp_compute_config(struct intel_encoder *encoder,
471 struct intel_crtc_config *pipe_config);
cb0953d7 472extern bool intel_dpd_is_edp(struct drm_device *dev);
d6c50ff8
PZ		 473extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
474extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
82a4d9c0
PZ		 475extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
476extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
477extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
478extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0206e353 479extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 480extern int intel_edp_target_clock(struct intel_encoder *,
481 struct drm_display_mode *mode);
814948ad 482extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 483extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 484extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
485 enum plane plane);
32f9d658 486
a9573556 487/* intel_panel.c */
dd06f90e
JN		 488extern int intel_panel_init(struct intel_panel *panel,
489 struct drm_display_mode *fixed_mode);
1d508706
JN		 490extern void intel_panel_fini(struct intel_panel *panel);
491
1d8e1c75
CW		 492extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
493 struct drm_display_mode *adjusted_mode);
494extern void intel_pch_panel_fitting(struct drm_device *dev,
495 int fitting_mode,
cb1793ce 496 const struct drm_display_mode *mode,
1d8e1c75 497 struct drm_display_mode *adjusted_mode);
a9573556 498extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 499extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
0657b6b1 500extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 501extern void intel_panel_enable_backlight(struct drm_device *dev,
502 enum pipe pipe);
47356eb6 503extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 504extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 505extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 506
d9e55608 507struct intel_set_config {
1aa4b628
DV		 508 struct drm_encoder **save_connector_encoders;
509 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 510
511 bool fb_changed;
512 bool mode_changed;
d9e55608
DV		 513};
514
c0c36b94
CW		 515extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
516 int x, int y, struct drm_framebuffer *old_fb);
a261b246 517extern void intel_modeset_disable(struct drm_device *dev);
c0c36b94 518extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
79e53945 519extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 520extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
ea5b213a 521extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 522extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 523extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 524extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 525extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c 526extern void intel_modeset_check_state(struct drm_device *dev);
5e1bac2f 527extern void intel_plane_restore(struct drm_plane *plane);
b980514c 528
79e53945 529
df0e9248
CW		 530static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
531{
532 return to_intel_connector(connector)->encoder;
533}
534
7739c33b
PZ		 535static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
536{
da63a9f2
PZ		 537 struct intel_digital_port *intel_dig_port =
538 container_of(encoder, struct intel_digital_port, base.base);
539 return &intel_dig_port->dp;
540}
541
542static inline struct intel_digital_port *
543enc_to_dig_port(struct drm_encoder *encoder)
544{
545 return container_of(encoder, struct intel_digital_port, base.base);
546}
547
548static inline struct intel_digital_port *
549dp_to_dig_port(struct intel_dp *intel_dp)
550{
551 return container_of(intel_dp, struct intel_digital_port, dp);
552}
553
554static inline struct intel_digital_port *
555hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
556{
557 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ		 558}
559
b0ea7d37
DL		 560bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
561 struct intel_digital_port *port);
562
df0e9248
CW		 563extern void intel_connector_attach_encoder(struct intel_connector *connector,
564 struct intel_encoder *encoder);
565extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 566
567extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
568 struct drm_crtc *crtc);
08d7b3d1
CW		 569int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
570 struct drm_file *file_priv);
a5c961d1
PZ		 571extern enum transcoder
572intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
573 enum pipe pipe);
9d0498a2 574extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 575extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
d4b1931c 576extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
8261b191
CW		 577
578struct intel_load_detect_pipe {
d2dff872 579 struct drm_framebuffer *release_fb;
8261b191
CW		 580 bool load_detect_temp;
581 int dpms_mode;
582};
d2434ab7 583extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 584 struct drm_display_mode *mode,
8261b191 585 struct intel_load_detect_pipe *old);
d2434ab7 586extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 587 struct intel_load_detect_pipe *old);
79e53945 588
79e53945
JB		 589extern void intelfb_restore(void);
590extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
591 u16 blue, int regno);
b8c00ac5
DA		 592extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
593 u16 *blue, int regno);
0cdab21f 594extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 595
127bd2ac 596extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 597 struct drm_i915_gem_object *obj,
919926ae 598 struct intel_ring_buffer *pipelined);
1690e1eb 599extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 600
38651674
DA		 601extern int intel_framebuffer_init(struct drm_device *dev,
602 struct intel_framebuffer *ifb,
308e5bcb 603 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 604 struct drm_i915_gem_object *obj);
38651674 605extern int intel_fbdev_init(struct drm_device *dev);
20afbda2 606extern void intel_fbdev_initial_config(struct drm_device *dev);
38651674 607extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 608extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 609extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
610extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 611extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 612
02e792fb
DV		 613extern void intel_setup_overlay(struct drm_device *dev);
614extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 615extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 616extern int intel_overlay_put_image(struct drm_device *dev, void *data,
617 struct drm_file *file_priv);
618extern int intel_overlay_attrs(struct drm_device *dev, void *data,
619 struct drm_file *file_priv);
4abe3520 620
eb1f8e4f 621extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 622extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 623
b840d907
JB		 624extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
625 bool state);
626#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
627#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
628
645c62a5 629extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 630extern void intel_write_eld(struct drm_encoder *encoder,
631 struct drm_display_mode *mode);
d4270e57 632extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 633extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 634extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 635extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 636
b840d907 637/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 638extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 639extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
640 uint32_t sprite_width,
641 int pixel_size);
1f8eeabf
ED		 642extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
643 struct drm_display_mode *mode);
8ea30864 644
bc752862
CW		 645extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
646 unsigned int tiling_mode,
647 unsigned int bpp,
648 unsigned int pitch);
5a35e99e 649
8ea30864
JB		 650extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
651 struct drm_file *file_priv);
652extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
653 struct drm_file *file_priv);
654
57f350b6
JB		 655extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
656
85208be0 657/* Power-related functions, located in intel_pm.c */
1fa61106 658extern void intel_init_pm(struct drm_device *dev);
85208be0 659/* FBC */
85208be0
ED		 660extern bool intel_fbc_enabled(struct drm_device *dev);
661extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
662extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 663/* IPS */
664extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
665extern void intel_gpu_ips_teardown(void);
85208be0 666
fa42e23c 667extern void intel_init_power_well(struct drm_device *dev);
cb10799c 668extern void intel_set_power_well(struct drm_device *dev, bool enable);
8090c6b9
DV		 669extern void intel_enable_gt_powersave(struct drm_device *dev);
670extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 671extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 672extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 673
85234cdc
DV		 674extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
675 enum pipe *pipe);
b8fc2f6a 676extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
79f689aa 677extern void intel_ddi_pll_init(struct drm_device *dev);
8228c251 678extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
ad80a810
PZ		 679extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
680 enum transcoder cpu_transcoder);
fc914639
PZ		 681extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
682extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 683extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
684extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
6441ab5f 685extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 686extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 687extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
1ad960f2
PZ		 688extern bool
689intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
690extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
72662e10 691
96a02917
VS		 692extern void intel_display_handle_reset(struct drm_device *dev);
693
79e53945 694#endif /* __INTEL_DRV_H__ */
Linux 6.x block layer and io_uring tree(s)