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drm/i915: fixup 12bpc hdmi dotclock handling
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
1d5bfac9
DV		 36/**
37 * _wait_for - magic (register) wait macro
38 *
39 * Does the right thing for modeset paths when run under kdgb or similar atomic
40 * contexts. Note that it's important that we check the condition again after
41 * having timed out, since the timeout could be due to preemption or similar and
42 * we've never had a chance to check the condition before the timeout.
43 */
481b6af3 44#define _wait_for(COND, MS, W) ({ \
1d5bfac9 45 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
913d8d11 46 int ret__ = 0; \
0206e353 47 while (!(COND)) { \
913d8d11 48 if (time_after(jiffies, timeout__)) { \
1d5bfac9
DV		 49 if (!(COND)) \
50 ret__ = -ETIMEDOUT; \
913d8d11
CW		 51 break; \
52 } \
0cc2764c
BW		 53 if (W && drm_can_sleep()) { \
54 msleep(W); \
55 } else { \
56 cpu_relax(); \
57 } \
913d8d11
CW		 58 } \
59 ret__; \
60})
61
481b6af3
CW		 62#define wait_for(COND, MS) _wait_for(COND, MS, 1)
63#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
6effa33b
DV		 64#define wait_for_atomic_us(COND, US) _wait_for((COND), \
65 DIV_ROUND_UP((US), 1000), 0)
481b6af3 66
021357ac
CW		 67#define KHz(x) (1000*x)
68#define MHz(x) KHz(1000*x)
69
79e53945
JB		 70/*
71 * Display related stuff
72 */
73
74/* store information about an Ixxx DVO */
75/* The i830->i865 use multiple DVOs with multiple i2cs */
76/* the i915, i945 have a single sDVO i2c bus - which is different */
77#define MAX_OUTPUTS 6
78/* maximum connectors per crtcs in the mode set */
79#define INTELFB_CONN_LIMIT 4
80
81#define INTEL_I2C_BUS_DVO 1
82#define INTEL_I2C_BUS_SDVO 2
83
84/* these are outputs from the chip - integrated only
85 external chips are via DVO or SDVO output */
86#define INTEL_OUTPUT_UNUSED 0
87#define INTEL_OUTPUT_ANALOG 1
88#define INTEL_OUTPUT_DVO 2
89#define INTEL_OUTPUT_SDVO 3
90#define INTEL_OUTPUT_LVDS 4
91#define INTEL_OUTPUT_TVOUT 5
7d57382e 92#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 93#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 94#define INTEL_OUTPUT_EDP 8
00c09d70 95#define INTEL_OUTPUT_UNKNOWN 9
79e53945
JB		 96
97#define INTEL_DVO_CHIP_NONE 0
98#define INTEL_DVO_CHIP_LVDS 1
99#define INTEL_DVO_CHIP_TMDS 2
100#define INTEL_DVO_CHIP_TVOUT 4
101
79e53945
JB		 102struct intel_framebuffer {
103 struct drm_framebuffer base;
05394f39 104 struct drm_i915_gem_object *obj;
79e53945
JB		 105};
106
37811fcc
CW		 107struct intel_fbdev {
108 struct drm_fb_helper helper;
109 struct intel_framebuffer ifb;
110 struct list_head fbdev_list;
111 struct drm_display_mode *our_mode;
112};
79e53945 113
21d40d37 114struct intel_encoder {
4ef69c7a 115 struct drm_encoder base;
9a935856
DV		 116 /*
117 * The new crtc this encoder will be driven from. Only differs from
118 * base->crtc while a modeset is in progress.
119 */
120 struct intel_crtc *new_crtc;
121
79e53945 122 int type;
e2f0ba97 123 bool needs_tv_clock;
66a9278e
DV		 124 /*
125 * Intel hw has only one MUX where encoders could be clone, hence a
126 * simple flag is enough to compute the possible_clones mask.
127 */
128 bool cloneable;
5ab432ef 129 bool connectors_active;
21d40d37 130 void (*hot_plug)(struct intel_encoder *);
7ae89233
DV		 131 bool (*compute_config)(struct intel_encoder *,
132 struct intel_crtc_config *);
dafd226c 133 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 134 void (*pre_enable)(struct intel_encoder *);
ef9c3aee 135 void (*enable)(struct intel_encoder *);
6cc5f341 136 void (*mode_set)(struct intel_encoder *intel_encoder);
ef9c3aee 137 void (*disable)(struct intel_encoder *);
bf49ec8c 138 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 139 /* Read out the current hw state of this connector, returning true if
140 * the encoder is active. If the encoder is enabled it also set the pipe
141 * it is connected to in the pipe parameter. */
142 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 143 int crtc_mask;
1d843f9d 144 enum hpd_pin hpd_pin;
79e53945
JB		 145};
146
1d508706 147struct intel_panel {
dd06f90e 148 struct drm_display_mode *fixed_mode;
4d891523 149 int fitting_mode;
1d508706
JN		 150};
151
5daa55eb
ZW		 152struct intel_connector {
153 struct drm_connector base;
9a935856
DV		 154 /*
155 * The fixed encoder this connector is connected to.
156 */
df0e9248 157 struct intel_encoder *encoder;
9a935856
DV		 158
159 /*
160 * The new encoder this connector will be driven. Only differs from
161 * encoder while a modeset is in progress.
162 */
163 struct intel_encoder *new_encoder;
164
f0947c37
DV		 165 /* Reads out the current hw, returning true if the connector is enabled
166 * and active (i.e. dpms ON state). */
167 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 168
169 /* Panel info for eDP and LVDS */
170 struct intel_panel panel;
9cd300e0
JN		 171
172 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
173 struct edid *edid;
821450c6
EE		 174
175 /* since POLL and HPD connectors may use the same HPD line keep the native
176 state of connector->polled in case hotplug storm detection changes it */
177 u8 polled;
5daa55eb
ZW		 178};
179
80ad9206
VS		 180typedef struct dpll {
181 /* given values */
182 int n;
183 int m1, m2;
184 int p1, p2;
185 /* derived values */
186 int dot;
187 int vco;
188 int m;
189 int p;
190} intel_clock_t;
191
b8cecdf5
DV		 192struct intel_crtc_config {
193 struct drm_display_mode requested_mode;
194 struct drm_display_mode adjusted_mode;
7ae89233
DV		 195 /* This flag must be set by the encoder's compute_config callback if it
196 * changes the crtc timings in the mode to prevent the crtc fixup from
197 * overwriting them. Currently only lvds needs that. */
198 bool timings_set;
5bfe2ac0
DV		 199 /* Whether to set up the PCH/FDI. Note that we never allow sharing
200 * between pch encoders and cpu encoders. */
201 bool has_pch_encoder;
50f3b016 202
3b117c8f
DV		 203 /* CPU Transcoder for the pipe. Currently this can only differ from the
204 * pipe on Haswell (where we have a special eDP transcoder). */
205 enum transcoder cpu_transcoder;
206
50f3b016
DV		 207 /*
208 * Use reduced/limited/broadcast rbg range, compressing from the full
209 * range fed into the crtcs.
210 */
211 bool limited_color_range;
212
03afc4a2
DV		 213 /* DP has a bunch of special case unfortunately, so mark the pipe
214 * accordingly. */
215 bool has_dp_encoder;
d8b32247
DV		 216
217 /*
218 * Enable dithering, used when the selected pipe bpp doesn't match the
219 * plane bpp.
220 */
965e0c48 221 bool dither;
f47709a9
DV		 222
223 /* Controls for the clock computation, to override various stages. */
224 bool clock_set;
225
226 /* Settings for the intel dpll used on pretty much everything but
227 * haswell. */
80ad9206 228 struct dpll dpll;
f47709a9 229
965e0c48 230 int pipe_bpp;
6cf86a5e 231 struct intel_link_m_n dp_m_n;
df92b1e6
DV		 232 /**
233 * This is currently used by DP and HDMI encoders since those can have a
234 * target pixel clock != the port link clock (which is currently stored
235 * in adjusted_mode->clock).
236 */
237 int pixel_target_clock;
6cc5f341
DV		 238 /* Used by SDVO (and if we ever fix it, HDMI). */
239 unsigned pixel_multiplier;
2dd24552
JB		 240
241 /* Panel fitter controls for gen2-gen4 + VLV */
b074cec8
JB		 242 struct {
243 u32 control;
244 u32 pgm_ratios;
245 } gmch_pfit;
246
247 /* Panel fitter placement and size for Ironlake+ */
248 struct {
249 u32 pos;
250 u32 size;
251 } pch_pfit;
33d29b14 252
ca3a0ff8 253 /* FDI configuration, only valid if has_pch_encoder is set. */
33d29b14 254 int fdi_lanes;
ca3a0ff8 255 struct intel_link_m_n fdi_m_n;
b8cecdf5
DV		 256};
257
79e53945
JB		 258struct intel_crtc {
259 struct drm_crtc base;
80824003
JB		 260 enum pipe pipe;
261 enum plane plane;
79e53945 262 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 263 /*
264 * Whether the crtc and the connected output pipeline is active. Implies
265 * that crtc->enabled is set, i.e. the current mode configuration has
266 * some outputs connected to this crtc.
08a48469
DV		 267 */
268 bool active;
7b9f35a6 269 bool eld_vld;
93314b5b 270 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 271 bool lowfreq_avail;
02e792fb 272 struct intel_overlay *overlay;
6b95a207 273 struct intel_unpin_work *unpin_work;
cda4b7d3 274
b4a98e57
CW		 275 atomic_t unpin_work_count;
276
e506a0c6
DV		 277 /* Display surface base address adjustement for pageflips. Note that on
278 * gen4+ this only adjusts up to a tile, offsets within a tile are
279 * handled in the hw itself (with the TILEOFF register). */
280 unsigned long dspaddr_offset;
281
05394f39 282 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 283 uint32_t cursor_addr;
284 int16_t cursor_x, cursor_y;
285 int16_t cursor_width, cursor_height;
6b383a7f 286 bool cursor_visible;
4b645f14 287
b8cecdf5
DV		 288 struct intel_crtc_config config;
289
ee7b9f93
JB		 290 /* We can share PLLs across outputs if the timings match */
291 struct intel_pch_pll *pch_pll;
6441ab5f 292 uint32_t ddi_pll_sel;
10d83730
VS		 293
294 /* reset counter value when the last flip was submitted */
295 unsigned int reset_counter;
8664281b
PZ		 296
297 /* Access to these should be protected by dev_priv->irq_lock. */
298 bool cpu_fifo_underrun_disabled;
299 bool pch_fifo_underrun_disabled;
79e53945
JB		 300};
301
b840d907
JB		 302struct intel_plane {
303 struct drm_plane base;
7f1f3851 304 int plane;
b840d907
JB		 305 enum pipe pipe;
306 struct drm_i915_gem_object *obj;
2d354c34 307 bool can_scale;
b840d907
JB		 308 int max_downscale;
309 u32 lut_r[1024], lut_g[1024], lut_b[1024];
5e1bac2f
JB		 310 int crtc_x, crtc_y;
311 unsigned int crtc_w, crtc_h;
312 uint32_t src_x, src_y;
313 uint32_t src_w, src_h;
b840d907
JB		 314 void (*update_plane)(struct drm_plane *plane,
315 struct drm_framebuffer *fb,
316 struct drm_i915_gem_object *obj,
317 int crtc_x, int crtc_y,
318 unsigned int crtc_w, unsigned int crtc_h,
319 uint32_t x, uint32_t y,
320 uint32_t src_w, uint32_t src_h);
321 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 322 int (*update_colorkey)(struct drm_plane *plane,
323 struct drm_intel_sprite_colorkey *key);
324 void (*get_colorkey)(struct drm_plane *plane,
325 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 326};
327
b445e3b0
ED		 328struct intel_watermark_params {
329 unsigned long fifo_size;
330 unsigned long max_wm;
331 unsigned long default_wm;
332 unsigned long guard_size;
333 unsigned long cacheline_size;
334};
335
336struct cxsr_latency {
337 int is_desktop;
338 int is_ddr3;
339 unsigned long fsb_freq;
340 unsigned long mem_freq;
341 unsigned long display_sr;
342 unsigned long display_hpll_disable;
343 unsigned long cursor_sr;
344 unsigned long cursor_hpll_disable;
345};
346
79e53945 347#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 348#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 349#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 350#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 351#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 352
45187ace
JB		 353#define DIP_HEADER_SIZE 5
354
3c17fe4b
DH		 355#define DIP_TYPE_AVI 0x82
356#define DIP_VERSION_AVI 0x2
357#define DIP_LEN_AVI 13
c846b619
PZ		 358#define DIP_AVI_PR_1 0
359#define DIP_AVI_PR_2 1
abedc077
VS		 360#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
361#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
362#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
3c17fe4b 363
26005210 364#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 365#define DIP_VERSION_SPD 0x1
366#define DIP_LEN_SPD 25
367#define DIP_SPD_UNKNOWN 0
368#define DIP_SPD_DSTB 0x1
369#define DIP_SPD_DVDP 0x2
370#define DIP_SPD_DVHS 0x3
371#define DIP_SPD_HDDVR 0x4
372#define DIP_SPD_DVC 0x5
373#define DIP_SPD_DSC 0x6
374#define DIP_SPD_VCD 0x7
375#define DIP_SPD_GAME 0x8
376#define DIP_SPD_PC 0x9
377#define DIP_SPD_BD 0xa
378#define DIP_SPD_SCD 0xb
379
3c17fe4b
DH		 380struct dip_infoframe {
381 uint8_t type; /* HB0 */
382 uint8_t ver; /* HB1 */
383 uint8_t len; /* HB2 - body len, not including checksum */
384 uint8_t ecc; /* Header ECC */
385 uint8_t checksum; /* PB0 */
386 union {
387 struct {
388 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
389 uint8_t Y_A_B_S;
390 /* PB2 - C 7:6, M 5:4, R 3:0 */
391 uint8_t C_M_R;
392 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
393 uint8_t ITC_EC_Q_SC;
394 /* PB4 - VIC 6:0 */
395 uint8_t VIC;
0aa534df
PZ		 396 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
397 uint8_t YQ_CN_PR;
3c17fe4b
DH		 398 /* PB6 to PB13 */
399 uint16_t top_bar_end;
400 uint16_t bottom_bar_start;
401 uint16_t left_bar_end;
402 uint16_t right_bar_start;
81014b9d 403 } __attribute__ ((packed)) avi;
c0864cb3
JB		 404 struct {
405 uint8_t vn[8];
406 uint8_t pd[16];
407 uint8_t sdi;
81014b9d 408 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 409 uint8_t payload[27];
410 } __attribute__ ((packed)) body;
411} __attribute__((packed));
412
f5bbfca3 413struct intel_hdmi {
b242b7f7 414 u32 hdmi_reg;
f5bbfca3 415 int ddc_bus;
f5bbfca3 416 uint32_t color_range;
55bc60db 417 bool color_range_auto;
f5bbfca3
ED		 418 bool has_hdmi_sink;
419 bool has_audio;
420 enum hdmi_force_audio force_audio;
abedc077 421 bool rgb_quant_range_selectable;
f5bbfca3
ED		 422 void (*write_infoframe)(struct drm_encoder *encoder,
423 struct dip_infoframe *frame);
687f4d06
PZ		 424 void (*set_infoframes)(struct drm_encoder *encoder,
425 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 426};
427
b091cd92 428#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 429#define DP_LINK_CONFIGURATION_SIZE 9
430
431struct intel_dp {
54d63ca6 432 uint32_t output_reg;
9ed35ab1 433 uint32_t aux_ch_ctl_reg;
54d63ca6
SK		 434 uint32_t DP;
435 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
436 bool has_audio;
437 enum hdmi_force_audio force_audio;
438 uint32_t color_range;
55bc60db 439 bool color_range_auto;
54d63ca6
SK		 440 uint8_t link_bw;
441 uint8_t lane_count;
442 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 443 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 444 struct i2c_adapter adapter;
445 struct i2c_algo_dp_aux_data algo;
446 bool is_pch_edp;
447 uint8_t train_set[4];
448 int panel_power_up_delay;
449 int panel_power_down_delay;
450 int panel_power_cycle_delay;
451 int backlight_on_delay;
452 int backlight_off_delay;
54d63ca6
SK		 453 struct delayed_work panel_vdd_work;
454 bool want_panel_vdd;
dd06f90e 455 struct intel_connector *attached_connector;
54d63ca6
SK		 456};
457
da63a9f2
PZ		 458struct intel_digital_port {
459 struct intel_encoder base;
174edf1f 460 enum port port;
876a8cdf 461 u32 port_reversal;
da63a9f2
PZ		 462 struct intel_dp dp;
463 struct intel_hdmi hdmi;
464};
465
89b667f8
JB		 466static inline int
467vlv_dport_to_channel(struct intel_digital_port *dport)
468{
469 switch (dport->port) {
470 case PORT_B:
471 return 0;
472 case PORT_C:
473 return 1;
474 default:
475 BUG();
476 }
477}
478
f875c15a
CW		 479static inline struct drm_crtc *
480intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
481{
482 struct drm_i915_private *dev_priv = dev->dev_private;
483 return dev_priv->pipe_to_crtc_mapping[pipe];
484}
485
417ae147
CW		 486static inline struct drm_crtc *
487intel_get_crtc_for_plane(struct drm_device *dev, int plane)
488{
489 struct drm_i915_private *dev_priv = dev->dev_private;
490 return dev_priv->plane_to_crtc_mapping[plane];
491}
492
4e5359cd
SF		 493struct intel_unpin_work {
494 struct work_struct work;
b4a98e57 495 struct drm_crtc *crtc;
05394f39
CW		 496 struct drm_i915_gem_object *old_fb_obj;
497 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 498 struct drm_pending_vblank_event *event;
e7d841ca
CW		 499 atomic_t pending;
500#define INTEL_FLIP_INACTIVE 0
501#define INTEL_FLIP_PENDING 1
502#define INTEL_FLIP_COMPLETE 2
4e5359cd
SF		 503 bool enable_stall_check;
504};
505
1630fe75
CW		 506struct intel_fbc_work {
507 struct delayed_work work;
508 struct drm_crtc *crtc;
509 struct drm_framebuffer *fb;
510 int interval;
511};
512
d2acd215
DV		 513int intel_pch_rawclk(struct drm_device *dev);
514
4eab8136
JN		 515int intel_connector_update_modes(struct drm_connector *connector,
516 struct edid *edid);
335af9a2 517int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 518
3f43c48d 519extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 520extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
521
8664281b 522extern bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
79e53945 523extern void intel_crt_init(struct drm_device *dev);
08d644ad 524extern void intel_hdmi_init(struct drm_device *dev,
b242b7f7 525 int hdmi_reg, enum port port);
00c09d70
PZ		 526extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
527 struct intel_connector *intel_connector);
f5bbfca3 528extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
5bfe2ac0
DV		 529extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
530 struct intel_crtc_config *pipe_config);
f5bbfca3 531extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 532extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
533 bool is_sdvob);
79e53945
JB		 534extern void intel_dvo_init(struct drm_device *dev);
535extern void intel_tv_init(struct drm_device *dev);
f047e395 536extern void intel_mark_busy(struct drm_device *dev);
f047e395 537extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
725a5b54 538extern void intel_mark_idle(struct drm_device *dev);
c5d1b51d 539extern bool intel_lvds_init(struct drm_device *dev);
1974cad0 540extern bool intel_is_dual_link_lvds(struct drm_device *dev);
ab9d7c30
PZ		 541extern void intel_dp_init(struct drm_device *dev, int output_reg,
542 enum port port);
00c09d70
PZ		 543extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
544 struct intel_connector *intel_connector);
247d89f6 545extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 546extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
547extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
548extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
00c09d70
PZ		 549extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
550extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
5bfe2ac0
DV		 551extern bool intel_dp_compute_config(struct intel_encoder *encoder,
552 struct intel_crtc_config *pipe_config);
cb0953d7 553extern bool intel_dpd_is_edp(struct drm_device *dev);
d6c50ff8
PZ		 554extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
555extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
82a4d9c0
PZ		 556extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
557extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
558extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
559extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
814948ad 560extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
7f1f3851 561extern int intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane);
6f1d69b0
ED		 562extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
563 enum plane plane);
32f9d658 564
a9573556 565/* intel_panel.c */
dd06f90e
JN		 566extern int intel_panel_init(struct intel_panel *panel,
567 struct drm_display_mode *fixed_mode);
1d508706
JN		 568extern void intel_panel_fini(struct intel_panel *panel);
569
1d8e1c75
CW		 570extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
571 struct drm_display_mode *adjusted_mode);
b074cec8
JB		 572extern void intel_pch_panel_fitting(struct intel_crtc *crtc,
573 struct intel_crtc_config *pipe_config,
574 int fitting_mode);
2dd24552
JB		 575extern void intel_gmch_panel_fitting(struct intel_crtc *crtc,
576 struct intel_crtc_config *pipe_config,
577 int fitting_mode);
d6540632
JN		 578extern void intel_panel_set_backlight(struct drm_device *dev,
579 u32 level, u32 max);
0657b6b1 580extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 581extern void intel_panel_enable_backlight(struct drm_device *dev,
582 enum pipe pipe);
47356eb6 583extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 584extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 585extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 586
d9e55608 587struct intel_set_config {
1aa4b628
DV		 588 struct drm_encoder **save_connector_encoders;
589 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 590
591 bool fb_changed;
592 bool mode_changed;
d9e55608
DV		 593};
594
c0c36b94
CW		 595extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
596 int x, int y, struct drm_framebuffer *old_fb);
a261b246 597extern void intel_modeset_disable(struct drm_device *dev);
c0c36b94 598extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
79e53945 599extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 600extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
ea5b213a 601extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 602extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 603extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 604extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 605extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c 606extern void intel_modeset_check_state(struct drm_device *dev);
5e1bac2f 607extern void intel_plane_restore(struct drm_plane *plane);
b980514c 608
79e53945 609
df0e9248
CW		 610static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
611{
612 return to_intel_connector(connector)->encoder;
613}
614
7739c33b
PZ		 615static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
616{
da63a9f2
PZ		 617 struct intel_digital_port *intel_dig_port =
618 container_of(encoder, struct intel_digital_port, base.base);
619 return &intel_dig_port->dp;
620}
621
622static inline struct intel_digital_port *
623enc_to_dig_port(struct drm_encoder *encoder)
624{
625 return container_of(encoder, struct intel_digital_port, base.base);
626}
627
628static inline struct intel_digital_port *
629dp_to_dig_port(struct intel_dp *intel_dp)
630{
631 return container_of(intel_dp, struct intel_digital_port, dp);
632}
633
634static inline struct intel_digital_port *
635hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
636{
637 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ		 638}
639
b0ea7d37
DL		 640bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
641 struct intel_digital_port *port);
642
df0e9248
CW		 643extern void intel_connector_attach_encoder(struct intel_connector *connector,
644 struct intel_encoder *encoder);
645extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 646
647extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
648 struct drm_crtc *crtc);
08d7b3d1
CW		 649int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
650 struct drm_file *file_priv);
a5c961d1
PZ		 651extern enum transcoder
652intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
653 enum pipe pipe);
9d0498a2 654extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 655extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
d4b1931c 656extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
89b667f8 657extern void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port);
8261b191
CW		 658
659struct intel_load_detect_pipe {
d2dff872 660 struct drm_framebuffer *release_fb;
8261b191
CW		 661 bool load_detect_temp;
662 int dpms_mode;
663};
d2434ab7 664extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 665 struct drm_display_mode *mode,
8261b191 666 struct intel_load_detect_pipe *old);
d2434ab7 667extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 668 struct intel_load_detect_pipe *old);
79e53945 669
79e53945
JB		 670extern void intelfb_restore(void);
671extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
672 u16 blue, int regno);
b8c00ac5
DA		 673extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
674 u16 *blue, int regno);
0cdab21f 675extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 676
127bd2ac 677extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 678 struct drm_i915_gem_object *obj,
919926ae 679 struct intel_ring_buffer *pipelined);
1690e1eb 680extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 681
38651674
DA		 682extern int intel_framebuffer_init(struct drm_device *dev,
683 struct intel_framebuffer *ifb,
308e5bcb 684 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 685 struct drm_i915_gem_object *obj);
38651674 686extern int intel_fbdev_init(struct drm_device *dev);
20afbda2 687extern void intel_fbdev_initial_config(struct drm_device *dev);
38651674 688extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 689extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 690extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
691extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 692extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 693
02e792fb
DV		 694extern void intel_setup_overlay(struct drm_device *dev);
695extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 696extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 697extern int intel_overlay_put_image(struct drm_device *dev, void *data,
698 struct drm_file *file_priv);
699extern int intel_overlay_attrs(struct drm_device *dev, void *data,
700 struct drm_file *file_priv);
4abe3520 701
eb1f8e4f 702extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 703extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 704
b840d907
JB		 705extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
706 bool state);
707#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
708#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
709
645c62a5 710extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 711extern void intel_write_eld(struct drm_encoder *encoder,
712 struct drm_display_mode *mode);
d4270e57 713extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
6cf86a5e
DV		 714extern void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
715 struct intel_link_m_n *m_n);
716extern void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
717 struct intel_link_m_n *m_n);
45244b87 718extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 719extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 720extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 721
b840d907 722/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 723extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 724extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
725 uint32_t sprite_width,
726 int pixel_size);
1f8eeabf
ED		 727extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
728 struct drm_display_mode *mode);
8ea30864 729
bc752862
CW		 730extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
731 unsigned int tiling_mode,
732 unsigned int bpp,
733 unsigned int pitch);
5a35e99e 734
8ea30864
JB		 735extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
736 struct drm_file *file_priv);
737extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
738 struct drm_file *file_priv);
739
57f350b6 740extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
e2fa6fba
P		 741extern void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
742 u32 val);
57f350b6 743
85208be0 744/* Power-related functions, located in intel_pm.c */
1fa61106 745extern void intel_init_pm(struct drm_device *dev);
85208be0 746/* FBC */
85208be0
ED		 747extern bool intel_fbc_enabled(struct drm_device *dev);
748extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
749extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 750/* IPS */
751extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
752extern void intel_gpu_ips_teardown(void);
85208be0 753
15d199ea 754extern bool intel_using_power_well(struct drm_device *dev);
fa42e23c 755extern void intel_init_power_well(struct drm_device *dev);
cb10799c 756extern void intel_set_power_well(struct drm_device *dev, bool enable);
8090c6b9
DV		 757extern void intel_enable_gt_powersave(struct drm_device *dev);
758extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 759extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 760extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 761
85234cdc
DV		 762extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
763 enum pipe *pipe);
b8fc2f6a 764extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
79f689aa 765extern void intel_ddi_pll_init(struct drm_device *dev);
8228c251 766extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
ad80a810
PZ		 767extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
768 enum transcoder cpu_transcoder);
fc914639
PZ		 769extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
770extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 771extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
772extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
6441ab5f 773extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 774extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 775extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
1ad960f2
PZ		 776extern bool
777intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
778extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
72662e10 779
96a02917 780extern void intel_display_handle_reset(struct drm_device *dev);
8664281b
PZ		 781extern bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
782 enum pipe pipe,
783 bool enable);
784extern bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
785 enum transcoder pch_transcoder,
786 bool enable);
96a02917 787
79e53945 788#endif /* __INTEL_DRV_H__ */
Linux 6.x block layer and io_uring tree(s)