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drm/i915: remove "inline" keyword from ironlake_disable_display_irq
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_drv.h
CommitLineData
79e53945
JB		 1/*
2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25#ifndef __INTEL_DRV_H__
26#define __INTEL_DRV_H__
27
28#include <linux/i2c.h>
760285e7 29#include <drm/i915_drm.h>
80824003 30#include "i915_drv.h"
760285e7
DH		 31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_fb_helper.h>
612a9aab 34#include <drm/drm_dp_helper.h>
913d8d11 35
481b6af3 36#define _wait_for(COND, MS, W) ({ \
913d8d11
CW		 37 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
38 int ret__ = 0; \
0206e353 39 while (!(COND)) { \
913d8d11
CW		 40 if (time_after(jiffies, timeout__)) { \
41 ret__ = -ETIMEDOUT; \
42 break; \
43 } \
0cc2764c
BW		 44 if (W && drm_can_sleep()) { \
45 msleep(W); \
46 } else { \
47 cpu_relax(); \
48 } \
913d8d11
CW		 49 } \
50 ret__; \
51})
52
57f350b6 53#define wait_for_atomic_us(COND, US) ({ \
bcf9dcc1
CW		 54 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
55 int ret__ = 0; \
56 while (!(COND)) { \
57 if (time_after(jiffies, timeout__)) { \
58 ret__ = -ETIMEDOUT; \
59 break; \
60 } \
61 cpu_relax(); \
62 } \
63 ret__; \
57f350b6
JB		 64})
65
481b6af3
CW		 66#define wait_for(COND, MS) _wait_for(COND, MS, 1)
67#define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
68
021357ac
CW		 69#define KHz(x) (1000*x)
70#define MHz(x) KHz(1000*x)
71
79e53945
JB		 72/*
73 * Display related stuff
74 */
75
76/* store information about an Ixxx DVO */
77/* The i830->i865 use multiple DVOs with multiple i2cs */
78/* the i915, i945 have a single sDVO i2c bus - which is different */
79#define MAX_OUTPUTS 6
80/* maximum connectors per crtcs in the mode set */
81#define INTELFB_CONN_LIMIT 4
82
83#define INTEL_I2C_BUS_DVO 1
84#define INTEL_I2C_BUS_SDVO 2
85
86/* these are outputs from the chip - integrated only
87 external chips are via DVO or SDVO output */
88#define INTEL_OUTPUT_UNUSED 0
89#define INTEL_OUTPUT_ANALOG 1
90#define INTEL_OUTPUT_DVO 2
91#define INTEL_OUTPUT_SDVO 3
92#define INTEL_OUTPUT_LVDS 4
93#define INTEL_OUTPUT_TVOUT 5
7d57382e 94#define INTEL_OUTPUT_HDMI 6
a4fc5ed6 95#define INTEL_OUTPUT_DISPLAYPORT 7
32f9d658 96#define INTEL_OUTPUT_EDP 8
00c09d70 97#define INTEL_OUTPUT_UNKNOWN 9
79e53945
JB		 98
99#define INTEL_DVO_CHIP_NONE 0
100#define INTEL_DVO_CHIP_LVDS 1
101#define INTEL_DVO_CHIP_TMDS 2
102#define INTEL_DVO_CHIP_TVOUT 4
103
79e53945
JB		 104struct intel_framebuffer {
105 struct drm_framebuffer base;
05394f39 106 struct drm_i915_gem_object *obj;
79e53945
JB		 107};
108
37811fcc
CW		 109struct intel_fbdev {
110 struct drm_fb_helper helper;
111 struct intel_framebuffer ifb;
112 struct list_head fbdev_list;
113 struct drm_display_mode *our_mode;
114};
79e53945 115
21d40d37 116struct intel_encoder {
4ef69c7a 117 struct drm_encoder base;
9a935856
DV		 118 /*
119 * The new crtc this encoder will be driven from. Only differs from
120 * base->crtc while a modeset is in progress.
121 */
122 struct intel_crtc *new_crtc;
123
79e53945 124 int type;
e2f0ba97 125 bool needs_tv_clock;
66a9278e
DV		 126 /*
127 * Intel hw has only one MUX where encoders could be clone, hence a
128 * simple flag is enough to compute the possible_clones mask.
129 */
130 bool cloneable;
5ab432ef 131 bool connectors_active;
21d40d37 132 void (*hot_plug)(struct intel_encoder *);
7ae89233
DV		 133 bool (*compute_config)(struct intel_encoder *,
134 struct intel_crtc_config *);
dafd226c 135 void (*pre_pll_enable)(struct intel_encoder *);
bf49ec8c 136 void (*pre_enable)(struct intel_encoder *);
ef9c3aee 137 void (*enable)(struct intel_encoder *);
6cc5f341 138 void (*mode_set)(struct intel_encoder *intel_encoder);
ef9c3aee 139 void (*disable)(struct intel_encoder *);
bf49ec8c 140 void (*post_disable)(struct intel_encoder *);
f0947c37
DV		 141 /* Read out the current hw state of this connector, returning true if
142 * the encoder is active. If the encoder is enabled it also set the pipe
143 * it is connected to in the pipe parameter. */
144 bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
f8aed700 145 int crtc_mask;
1d843f9d 146 enum hpd_pin hpd_pin;
79e53945
JB		 147};
148
1d508706 149struct intel_panel {
dd06f90e 150 struct drm_display_mode *fixed_mode;
4d891523 151 int fitting_mode;
1d508706
JN		 152};
153
5daa55eb
ZW		 154struct intel_connector {
155 struct drm_connector base;
9a935856
DV		 156 /*
157 * The fixed encoder this connector is connected to.
158 */
df0e9248 159 struct intel_encoder *encoder;
9a935856
DV		 160
161 /*
162 * The new encoder this connector will be driven. Only differs from
163 * encoder while a modeset is in progress.
164 */
165 struct intel_encoder *new_encoder;
166
f0947c37
DV		 167 /* Reads out the current hw, returning true if the connector is enabled
168 * and active (i.e. dpms ON state). */
169 bool (*get_hw_state)(struct intel_connector *);
1d508706
JN		 170
171 /* Panel info for eDP and LVDS */
172 struct intel_panel panel;
9cd300e0
JN		 173
174 /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
175 struct edid *edid;
5daa55eb
ZW		 176};
177
b8cecdf5
DV		 178struct intel_crtc_config {
179 struct drm_display_mode requested_mode;
180 struct drm_display_mode adjusted_mode;
7ae89233
DV		 181 /* This flag must be set by the encoder's compute_config callback if it
182 * changes the crtc timings in the mode to prevent the crtc fixup from
183 * overwriting them. Currently only lvds needs that. */
184 bool timings_set;
5bfe2ac0
DV		 185 /* Whether to set up the PCH/FDI. Note that we never allow sharing
186 * between pch encoders and cpu encoders. */
187 bool has_pch_encoder;
50f3b016
DV		 188
189 /*
190 * Use reduced/limited/broadcast rbg range, compressing from the full
191 * range fed into the crtcs.
192 */
193 bool limited_color_range;
194
965e0c48
DV		 195 bool dither;
196 int pipe_bpp;
197
6cc5f341
DV		 198 /* Used by SDVO (and if we ever fix it, HDMI). */
199 unsigned pixel_multiplier;
b8cecdf5
DV		 200};
201
79e53945
JB		 202struct intel_crtc {
203 struct drm_crtc base;
80824003
JB		 204 enum pipe pipe;
205 enum plane plane;
a5c961d1 206 enum transcoder cpu_transcoder;
79e53945 207 u8 lut_r[256], lut_g[256], lut_b[256];
08a48469
DV		 208 /*
209 * Whether the crtc and the connected output pipeline is active. Implies
210 * that crtc->enabled is set, i.e. the current mode configuration has
211 * some outputs connected to this crtc.
08a48469
DV		 212 */
213 bool active;
7b9f35a6 214 bool eld_vld;
93314b5b 215 bool primary_disabled; /* is the crtc obscured by a plane? */
652c393a 216 bool lowfreq_avail;
02e792fb 217 struct intel_overlay *overlay;
6b95a207 218 struct intel_unpin_work *unpin_work;
77ffb597 219 int fdi_lanes;
cda4b7d3 220
b4a98e57
CW		 221 atomic_t unpin_work_count;
222
e506a0c6
DV		 223 /* Display surface base address adjustement for pageflips. Note that on
224 * gen4+ this only adjusts up to a tile, offsets within a tile are
225 * handled in the hw itself (with the TILEOFF register). */
226 unsigned long dspaddr_offset;
227
05394f39 228 struct drm_i915_gem_object *cursor_bo;
cda4b7d3
CW		 229 uint32_t cursor_addr;
230 int16_t cursor_x, cursor_y;
231 int16_t cursor_width, cursor_height;
6b383a7f 232 bool cursor_visible;
4b645f14 233
b8cecdf5
DV		 234 struct intel_crtc_config config;
235
ee7b9f93
JB		 236 /* We can share PLLs across outputs if the timings match */
237 struct intel_pch_pll *pch_pll;
6441ab5f 238 uint32_t ddi_pll_sel;
10d83730
VS		 239
240 /* reset counter value when the last flip was submitted */
241 unsigned int reset_counter;
79e53945
JB		 242};
243
b840d907
JB		 244struct intel_plane {
245 struct drm_plane base;
246 enum pipe pipe;
247 struct drm_i915_gem_object *obj;
2d354c34 248 bool can_scale;
b840d907
JB		 249 int max_downscale;
250 u32 lut_r[1024], lut_g[1024], lut_b[1024];
5e1bac2f
JB		 251 int crtc_x, crtc_y;
252 unsigned int crtc_w, crtc_h;
253 uint32_t src_x, src_y;
254 uint32_t src_w, src_h;
b840d907
JB		 255 void (*update_plane)(struct drm_plane *plane,
256 struct drm_framebuffer *fb,
257 struct drm_i915_gem_object *obj,
258 int crtc_x, int crtc_y,
259 unsigned int crtc_w, unsigned int crtc_h,
260 uint32_t x, uint32_t y,
261 uint32_t src_w, uint32_t src_h);
262 void (*disable_plane)(struct drm_plane *plane);
8ea30864
JB		 263 int (*update_colorkey)(struct drm_plane *plane,
264 struct drm_intel_sprite_colorkey *key);
265 void (*get_colorkey)(struct drm_plane *plane,
266 struct drm_intel_sprite_colorkey *key);
b840d907
JB		 267};
268
b445e3b0
ED		 269struct intel_watermark_params {
270 unsigned long fifo_size;
271 unsigned long max_wm;
272 unsigned long default_wm;
273 unsigned long guard_size;
274 unsigned long cacheline_size;
275};
276
277struct cxsr_latency {
278 int is_desktop;
279 int is_ddr3;
280 unsigned long fsb_freq;
281 unsigned long mem_freq;
282 unsigned long display_sr;
283 unsigned long display_hpll_disable;
284 unsigned long cursor_sr;
285 unsigned long cursor_hpll_disable;
286};
287
79e53945 288#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
5daa55eb 289#define to_intel_connector(x) container_of(x, struct intel_connector, base)
4ef69c7a 290#define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
79e53945 291#define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
b840d907 292#define to_intel_plane(x) container_of(x, struct intel_plane, base)
79e53945 293
45187ace
JB		 294#define DIP_HEADER_SIZE 5
295
3c17fe4b
DH		 296#define DIP_TYPE_AVI 0x82
297#define DIP_VERSION_AVI 0x2
298#define DIP_LEN_AVI 13
c846b619
PZ		 299#define DIP_AVI_PR_1 0
300#define DIP_AVI_PR_2 1
abedc077
VS		 301#define DIP_AVI_RGB_QUANT_RANGE_DEFAULT (0 << 2)
302#define DIP_AVI_RGB_QUANT_RANGE_LIMITED (1 << 2)
303#define DIP_AVI_RGB_QUANT_RANGE_FULL (2 << 2)
3c17fe4b 304
26005210 305#define DIP_TYPE_SPD 0x83
c0864cb3
JB		 306#define DIP_VERSION_SPD 0x1
307#define DIP_LEN_SPD 25
308#define DIP_SPD_UNKNOWN 0
309#define DIP_SPD_DSTB 0x1
310#define DIP_SPD_DVDP 0x2
311#define DIP_SPD_DVHS 0x3
312#define DIP_SPD_HDDVR 0x4
313#define DIP_SPD_DVC 0x5
314#define DIP_SPD_DSC 0x6
315#define DIP_SPD_VCD 0x7
316#define DIP_SPD_GAME 0x8
317#define DIP_SPD_PC 0x9
318#define DIP_SPD_BD 0xa
319#define DIP_SPD_SCD 0xb
320
3c17fe4b
DH		 321struct dip_infoframe {
322 uint8_t type; /* HB0 */
323 uint8_t ver; /* HB1 */
324 uint8_t len; /* HB2 - body len, not including checksum */
325 uint8_t ecc; /* Header ECC */
326 uint8_t checksum; /* PB0 */
327 union {
328 struct {
329 /* PB1 - Y 6:5, A 4:4, B 3:2, S 1:0 */
330 uint8_t Y_A_B_S;
331 /* PB2 - C 7:6, M 5:4, R 3:0 */
332 uint8_t C_M_R;
333 /* PB3 - ITC 7:7, EC 6:4, Q 3:2, SC 1:0 */
334 uint8_t ITC_EC_Q_SC;
335 /* PB4 - VIC 6:0 */
336 uint8_t VIC;
0aa534df
PZ		 337 /* PB5 - YQ 7:6, CN 5:4, PR 3:0 */
338 uint8_t YQ_CN_PR;
3c17fe4b
DH		 339 /* PB6 to PB13 */
340 uint16_t top_bar_end;
341 uint16_t bottom_bar_start;
342 uint16_t left_bar_end;
343 uint16_t right_bar_start;
81014b9d 344 } __attribute__ ((packed)) avi;
c0864cb3
JB		 345 struct {
346 uint8_t vn[8];
347 uint8_t pd[16];
348 uint8_t sdi;
81014b9d 349 } __attribute__ ((packed)) spd;
3c17fe4b
DH		 350 uint8_t payload[27];
351 } __attribute__ ((packed)) body;
352} __attribute__((packed));
353
f5bbfca3 354struct intel_hdmi {
b242b7f7 355 u32 hdmi_reg;
f5bbfca3 356 int ddc_bus;
f5bbfca3 357 uint32_t color_range;
55bc60db 358 bool color_range_auto;
f5bbfca3
ED		 359 bool has_hdmi_sink;
360 bool has_audio;
361 enum hdmi_force_audio force_audio;
abedc077 362 bool rgb_quant_range_selectable;
f5bbfca3
ED		 363 void (*write_infoframe)(struct drm_encoder *encoder,
364 struct dip_infoframe *frame);
687f4d06
PZ		 365 void (*set_infoframes)(struct drm_encoder *encoder,
366 struct drm_display_mode *adjusted_mode);
f5bbfca3
ED		 367};
368
b091cd92 369#define DP_MAX_DOWNSTREAM_PORTS 0x10
54d63ca6
SK		 370#define DP_LINK_CONFIGURATION_SIZE 9
371
372struct intel_dp {
54d63ca6 373 uint32_t output_reg;
9ed35ab1 374 uint32_t aux_ch_ctl_reg;
54d63ca6
SK		 375 uint32_t DP;
376 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
377 bool has_audio;
378 enum hdmi_force_audio force_audio;
379 uint32_t color_range;
55bc60db 380 bool color_range_auto;
54d63ca6
SK		 381 uint8_t link_bw;
382 uint8_t lane_count;
383 uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
b091cd92 384 uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
54d63ca6
SK		 385 struct i2c_adapter adapter;
386 struct i2c_algo_dp_aux_data algo;
387 bool is_pch_edp;
388 uint8_t train_set[4];
389 int panel_power_up_delay;
390 int panel_power_down_delay;
391 int panel_power_cycle_delay;
392 int backlight_on_delay;
393 int backlight_off_delay;
54d63ca6
SK		 394 struct delayed_work panel_vdd_work;
395 bool want_panel_vdd;
dd06f90e 396 struct intel_connector *attached_connector;
54d63ca6
SK		 397};
398
da63a9f2
PZ		 399struct intel_digital_port {
400 struct intel_encoder base;
174edf1f 401 enum port port;
876a8cdf 402 u32 port_reversal;
da63a9f2
PZ		 403 struct intel_dp dp;
404 struct intel_hdmi hdmi;
405};
406
f875c15a
CW		 407static inline struct drm_crtc *
408intel_get_crtc_for_pipe(struct drm_device *dev, int pipe)
409{
410 struct drm_i915_private *dev_priv = dev->dev_private;
411 return dev_priv->pipe_to_crtc_mapping[pipe];
412}
413
417ae147
CW		 414static inline struct drm_crtc *
415intel_get_crtc_for_plane(struct drm_device *dev, int plane)
416{
417 struct drm_i915_private *dev_priv = dev->dev_private;
418 return dev_priv->plane_to_crtc_mapping[plane];
419}
420
4e5359cd
SF		 421struct intel_unpin_work {
422 struct work_struct work;
b4a98e57 423 struct drm_crtc *crtc;
05394f39
CW		 424 struct drm_i915_gem_object *old_fb_obj;
425 struct drm_i915_gem_object *pending_flip_obj;
4e5359cd 426 struct drm_pending_vblank_event *event;
e7d841ca
CW		 427 atomic_t pending;
428#define INTEL_FLIP_INACTIVE 0
429#define INTEL_FLIP_PENDING 1
430#define INTEL_FLIP_COMPLETE 2
4e5359cd
SF		 431 bool enable_stall_check;
432};
433
1630fe75
CW		 434struct intel_fbc_work {
435 struct delayed_work work;
436 struct drm_crtc *crtc;
437 struct drm_framebuffer *fb;
438 int interval;
439};
440
d2acd215
DV		 441int intel_pch_rawclk(struct drm_device *dev);
442
4eab8136
JN		 443int intel_connector_update_modes(struct drm_connector *connector,
444 struct edid *edid);
335af9a2 445int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
f0217c42 446
3f43c48d 447extern void intel_attach_force_audio_property(struct drm_connector *connector);
e953fd7b
CW		 448extern void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
449
79e53945 450extern void intel_crt_init(struct drm_device *dev);
08d644ad 451extern void intel_hdmi_init(struct drm_device *dev,
b242b7f7 452 int hdmi_reg, enum port port);
00c09d70
PZ		 453extern void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
454 struct intel_connector *intel_connector);
f5bbfca3 455extern struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
5bfe2ac0
DV		 456extern bool intel_hdmi_compute_config(struct intel_encoder *encoder,
457 struct intel_crtc_config *pipe_config);
f5bbfca3 458extern void intel_dip_infoframe_csum(struct dip_infoframe *avi_if);
eef4eacb
DV		 459extern bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg,
460 bool is_sdvob);
79e53945
JB		 461extern void intel_dvo_init(struct drm_device *dev);
462extern void intel_tv_init(struct drm_device *dev);
f047e395 463extern void intel_mark_busy(struct drm_device *dev);
f047e395 464extern void intel_mark_fb_busy(struct drm_i915_gem_object *obj);
725a5b54 465extern void intel_mark_idle(struct drm_device *dev);
c5d1b51d 466extern bool intel_lvds_init(struct drm_device *dev);
1974cad0 467extern bool intel_is_dual_link_lvds(struct drm_device *dev);
ab9d7c30
PZ		 468extern void intel_dp_init(struct drm_device *dev, int output_reg,
469 enum port port);
00c09d70
PZ		 470extern void intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
471 struct intel_connector *intel_connector);
a4fc5ed6
KP		 472void
473intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
474 struct drm_display_mode *adjusted_mode);
247d89f6 475extern void intel_dp_init_link_config(struct intel_dp *intel_dp);
c19b0669
PZ		 476extern void intel_dp_start_link_train(struct intel_dp *intel_dp);
477extern void intel_dp_complete_link_train(struct intel_dp *intel_dp);
478extern void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
00c09d70
PZ		 479extern void intel_dp_encoder_destroy(struct drm_encoder *encoder);
480extern void intel_dp_check_link_status(struct intel_dp *intel_dp);
5bfe2ac0
DV		 481extern bool intel_dp_compute_config(struct intel_encoder *encoder,
482 struct intel_crtc_config *pipe_config);
cb0953d7 483extern bool intel_dpd_is_edp(struct drm_device *dev);
d6c50ff8
PZ		 484extern void ironlake_edp_backlight_on(struct intel_dp *intel_dp);
485extern void ironlake_edp_backlight_off(struct intel_dp *intel_dp);
82a4d9c0
PZ		 486extern void ironlake_edp_panel_on(struct intel_dp *intel_dp);
487extern void ironlake_edp_panel_off(struct intel_dp *intel_dp);
488extern void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
489extern void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0206e353 490extern void intel_edp_link_config(struct intel_encoder *, int *, int *);
94bf2ced
DV		 491extern int intel_edp_target_clock(struct intel_encoder *,
492 struct drm_display_mode *mode);
814948ad 493extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder);
b840d907 494extern int intel_plane_init(struct drm_device *dev, enum pipe pipe);
6f1d69b0
ED		 495extern void intel_flush_display_plane(struct drm_i915_private *dev_priv,
496 enum plane plane);
32f9d658 497
a9573556 498/* intel_panel.c */
dd06f90e
JN		 499extern int intel_panel_init(struct intel_panel *panel,
500 struct drm_display_mode *fixed_mode);
1d508706
JN		 501extern void intel_panel_fini(struct intel_panel *panel);
502
1d8e1c75
CW		 503extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
504 struct drm_display_mode *adjusted_mode);
505extern void intel_pch_panel_fitting(struct drm_device *dev,
506 int fitting_mode,
cb1793ce 507 const struct drm_display_mode *mode,
1d8e1c75 508 struct drm_display_mode *adjusted_mode);
a9573556 509extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
a9573556 510extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
0657b6b1 511extern int intel_panel_setup_backlight(struct drm_connector *connector);
24ded204
DV		 512extern void intel_panel_enable_backlight(struct drm_device *dev,
513 enum pipe pipe);
47356eb6 514extern void intel_panel_disable_backlight(struct drm_device *dev);
aaa6fd2a 515extern void intel_panel_destroy_backlight(struct drm_device *dev);
fe16d949 516extern enum drm_connector_status intel_panel_detect(struct drm_device *dev);
1d8e1c75 517
d9e55608 518struct intel_set_config {
1aa4b628
DV		 519 struct drm_encoder **save_connector_encoders;
520 struct drm_crtc **save_encoder_crtcs;
5e2b584e
DV		 521
522 bool fb_changed;
523 bool mode_changed;
d9e55608
DV		 524};
525
c0c36b94
CW		 526extern int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
527 int x, int y, struct drm_framebuffer *old_fb);
a261b246 528extern void intel_modeset_disable(struct drm_device *dev);
c0c36b94 529extern void intel_crtc_restore_mode(struct drm_crtc *crtc);
79e53945 530extern void intel_crtc_load_lut(struct drm_crtc *crtc);
b2cabb0e 531extern void intel_crtc_update_dpms(struct drm_crtc *crtc);
ea5b213a 532extern void intel_encoder_destroy(struct drm_encoder *encoder);
5ab432ef 533extern void intel_encoder_dpms(struct intel_encoder *encoder, int mode);
6ed0f796 534extern bool intel_encoder_check_is_cloned(struct intel_encoder *encoder);
5ab432ef 535extern void intel_connector_dpms(struct drm_connector *, int mode);
f0947c37 536extern bool intel_connector_get_hw_state(struct intel_connector *connector);
b980514c 537extern void intel_modeset_check_state(struct drm_device *dev);
5e1bac2f 538extern void intel_plane_restore(struct drm_plane *plane);
b980514c 539
79e53945 540
df0e9248
CW		 541static inline struct intel_encoder *intel_attached_encoder(struct drm_connector *connector)
542{
543 return to_intel_connector(connector)->encoder;
544}
545
7739c33b
PZ		 546static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
547{
da63a9f2
PZ		 548 struct intel_digital_port *intel_dig_port =
549 container_of(encoder, struct intel_digital_port, base.base);
550 return &intel_dig_port->dp;
551}
552
553static inline struct intel_digital_port *
554enc_to_dig_port(struct drm_encoder *encoder)
555{
556 return container_of(encoder, struct intel_digital_port, base.base);
557}
558
559static inline struct intel_digital_port *
560dp_to_dig_port(struct intel_dp *intel_dp)
561{
562 return container_of(intel_dp, struct intel_digital_port, dp);
563}
564
565static inline struct intel_digital_port *
566hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
567{
568 return container_of(intel_hdmi, struct intel_digital_port, hdmi);
7739c33b
PZ		 569}
570
b0ea7d37
DL		 571bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
572 struct intel_digital_port *port);
573
df0e9248
CW		 574extern void intel_connector_attach_encoder(struct intel_connector *connector,
575 struct intel_encoder *encoder);
576extern struct drm_encoder *intel_best_encoder(struct drm_connector *connector);
79e53945
JB		 577
578extern struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
579 struct drm_crtc *crtc);
08d7b3d1
CW		 580int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
581 struct drm_file *file_priv);
a5c961d1
PZ		 582extern enum transcoder
583intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
584 enum pipe pipe);
9d0498a2 585extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
58e10eb9 586extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
d4b1931c 587extern int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
8261b191
CW		 588
589struct intel_load_detect_pipe {
d2dff872 590 struct drm_framebuffer *release_fb;
8261b191
CW		 591 bool load_detect_temp;
592 int dpms_mode;
593};
d2434ab7 594extern bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 595 struct drm_display_mode *mode,
8261b191 596 struct intel_load_detect_pipe *old);
d2434ab7 597extern void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 598 struct intel_load_detect_pipe *old);
79e53945 599
79e53945
JB		 600extern void intelfb_restore(void);
601extern void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
602 u16 blue, int regno);
b8c00ac5
DA		 603extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
604 u16 *blue, int regno);
0cdab21f 605extern void intel_enable_clock_gating(struct drm_device *dev);
79e53945 606
127bd2ac 607extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 608 struct drm_i915_gem_object *obj,
919926ae 609 struct intel_ring_buffer *pipelined);
1690e1eb 610extern void intel_unpin_fb_obj(struct drm_i915_gem_object *obj);
127bd2ac 611
38651674
DA		 612extern int intel_framebuffer_init(struct drm_device *dev,
613 struct intel_framebuffer *ifb,
308e5bcb 614 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 615 struct drm_i915_gem_object *obj);
38651674 616extern int intel_fbdev_init(struct drm_device *dev);
20afbda2 617extern void intel_fbdev_initial_config(struct drm_device *dev);
38651674 618extern void intel_fbdev_fini(struct drm_device *dev);
3fa016a0 619extern void intel_fbdev_set_suspend(struct drm_device *dev, int state);
6b95a207
KH		 620extern void intel_prepare_page_flip(struct drm_device *dev, int plane);
621extern void intel_finish_page_flip(struct drm_device *dev, int pipe);
1afe3e9d 622extern void intel_finish_page_flip_plane(struct drm_device *dev, int plane);
6b95a207 623
02e792fb
DV		 624extern void intel_setup_overlay(struct drm_device *dev);
625extern void intel_cleanup_overlay(struct drm_device *dev);
ce453d81 626extern int intel_overlay_switch_off(struct intel_overlay *overlay);
02e792fb
DV		 627extern int intel_overlay_put_image(struct drm_device *dev, void *data,
628 struct drm_file *file_priv);
629extern int intel_overlay_attrs(struct drm_device *dev, void *data,
630 struct drm_file *file_priv);
4abe3520 631
eb1f8e4f 632extern void intel_fb_output_poll_changed(struct drm_device *dev);
e8e7a2b8 633extern void intel_fb_restore_mode(struct drm_device *dev);
645c62a5 634
b840d907
JB		 635extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
636 bool state);
637#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
638#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
639
645c62a5 640extern void intel_init_clock_gating(struct drm_device *dev);
e0dac65e
WF		 641extern void intel_write_eld(struct drm_encoder *encoder,
642 struct drm_display_mode *mode);
d4270e57 643extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
45244b87 644extern void intel_prepare_ddi(struct drm_device *dev);
c82e4d26 645extern void hsw_fdi_link_train(struct drm_crtc *crtc);
0e72a5b5 646extern void intel_ddi_init(struct drm_device *dev, enum port port);
d4270e57 647
b840d907 648/* For use by IVB LP watermark workaround in intel_sprite.c */
f681fa23 649extern void intel_update_watermarks(struct drm_device *dev);
b840d907
JB		 650extern void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
651 uint32_t sprite_width,
652 int pixel_size);
1f8eeabf
ED		 653extern void intel_update_linetime_watermarks(struct drm_device *dev, int pipe,
654 struct drm_display_mode *mode);
8ea30864 655
bc752862
CW		 656extern unsigned long intel_gen4_compute_page_offset(int *x, int *y,
657 unsigned int tiling_mode,
658 unsigned int bpp,
659 unsigned int pitch);
5a35e99e 660
8ea30864
JB		 661extern int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
662 struct drm_file *file_priv);
663extern int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
664 struct drm_file *file_priv);
665
57f350b6
JB		 666extern u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg);
667
85208be0 668/* Power-related functions, located in intel_pm.c */
1fa61106 669extern void intel_init_pm(struct drm_device *dev);
85208be0 670/* FBC */
85208be0
ED		 671extern bool intel_fbc_enabled(struct drm_device *dev);
672extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
673extern void intel_update_fbc(struct drm_device *dev);
eb48eb00
DV		 674/* IPS */
675extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
676extern void intel_gpu_ips_teardown(void);
85208be0 677
fa42e23c 678extern void intel_init_power_well(struct drm_device *dev);
cb10799c 679extern void intel_set_power_well(struct drm_device *dev, bool enable);
8090c6b9
DV		 680extern void intel_enable_gt_powersave(struct drm_device *dev);
681extern void intel_disable_gt_powersave(struct drm_device *dev);
6590190d 682extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
930ebb46 683extern void ironlake_teardown_rc6(struct drm_device *dev);
b3daeaef 684
85234cdc
DV		 685extern bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
686 enum pipe *pipe);
b8fc2f6a 687extern int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv);
79f689aa 688extern void intel_ddi_pll_init(struct drm_device *dev);
8228c251 689extern void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc);
ad80a810
PZ		 690extern void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
691 enum transcoder cpu_transcoder);
fc914639
PZ		 692extern void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc);
693extern void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc);
6441ab5f
PZ		 694extern void intel_ddi_setup_hw_pll_state(struct drm_device *dev);
695extern bool intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock);
6441ab5f 696extern void intel_ddi_put_crtc_pll(struct drm_crtc *crtc);
dae84799 697extern void intel_ddi_set_pipe_settings(struct drm_crtc *crtc);
c19b0669 698extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
1ad960f2
PZ		 699extern bool
700intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
701extern void intel_ddi_fdi_disable(struct drm_crtc *crtc);
72662e10 702
96a02917
VS		 703extern void intel_display_handle_reset(struct drm_device *dev);
704
79e53945 705#endif /* __INTEL_DRV_H__ */
Linux 6.x block layer and io_uring tree(s)