[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp_link_training.c

/*
 * Copyright © 2008-2015 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#include "intel_drv.h"

static void
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
	uint8_t voltage_max;
	uint8_t preemph_max;

	for (lane = 0; lane < intel_dp->lane_count; lane++) {
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

	voltage_max = intel_dp_voltage_max(intel_dp);
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;

	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

	for (lane = 0; lane < 4; lane++)
		intel_dp->train_set[lane] = v | p;
}

static bool
intel_dp_set_link_train(struct intel_dp *intel_dp,
			uint8_t dp_train_pat)
{
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;

	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);

	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
	    DP_TRAINING_PATTERN_DISABLE) {
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
	}

	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);

	return ret == len;
}

static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp,
			uint8_t dp_train_pat)
{
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
	intel_dp_set_signal_levels(intel_dp);
	return intel_dp_set_link_train(intel_dp, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp)
{
	int ret;

	intel_dp_set_signal_levels(intel_dp);

	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
				intel_dp->train_set, intel_dp->lane_count);

	return ret == intel_dp->lane_count;
}

/* Enable corresponding port and start training pattern 1 */
static void
intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
{
	int i;
	uint8_t voltage;
	int voltage_tries, loop_tries;
	uint8_t link_config[2];
	uint8_t link_bw, rate_select;

	if (intel_dp->prepare_link_retrain)
		intel_dp->prepare_link_retrain(intel_dp);

	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
			      &link_bw, &rate_select);

	/* Write the link configuration data */
	link_config[0] = link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
	if (intel_dp->num_sink_rates)
		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
				  &rate_select, 1);

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);

	intel_dp->DP |= DP_PORT_EN;

	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

	voltage = 0xff;
	voltage_tries = 0;
	loop_tries = 0;
	for (;;) {
		uint8_t link_status[DP_LINK_STATUS_SIZE];

		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
			break;
		}

		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
			DRM_DEBUG_KMS("clock recovery OK\n");
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
				break;
		if (i == intel_dp->lane_count) {
			++loop_tries;
			if (loop_tries == 5) {
				DRM_ERROR("too many full retries, give up\n");
				break;
			}
			intel_dp_reset_link_train(intel_dp,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
			voltage_tries = 0;
			continue;
		}

		/* Check to see if we've tried the same voltage 5 times */
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
			++voltage_tries;
			if (voltage_tries == 5) {
				DRM_ERROR("too many voltage retries, give up\n");
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;

		/* Update training set as requested by target */
		intel_get_adjust_train(intel_dp, link_status);
		if (!intel_dp_update_link_train(intel_dp)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
	}
}

/*
 * Pick training pattern for channel equalization. Training Pattern 3 for HBR2
 * or 1.2 devices that support it, Training Pattern 2 otherwise.
 */
static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
{
	u32 training_pattern = DP_TRAINING_PATTERN_2;
	bool source_tps3, sink_tps3;

	/*
	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
	 * also mandatory for downstream devices that support HBR2. However, not
	 * all sinks follow the spec.
	 *
	 * Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
	 * supported in source but still not enabled.
	 */
	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);

	if (source_tps3 && sink_tps3) {
		training_pattern = DP_TRAINING_PATTERN_3;
	} else if (intel_dp->link_rate == 540000) {
		if (!source_tps3)
			DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
		if (!sink_tps3)
			DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
	}

	return training_pattern;
}

static void
intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
	int tries, cr_tries;
	u32 training_pattern;

	training_pattern = intel_dp_training_pattern(intel_dp);

	/* channel equalization */
	if (!intel_dp_set_link_train(intel_dp,
				     training_pattern |
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

	tries = 0;
	cr_tries = 0;
	channel_eq = false;
	for (;;) {
		uint8_t link_status[DP_LINK_STATUS_SIZE];

		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
			break;
		}

		/* Make sure clock is still ok */
		if (!drm_dp_clock_recovery_ok(link_status,
					      intel_dp->lane_count)) {
			intel_dp_link_training_clock_recovery(intel_dp);
			intel_dp_set_link_train(intel_dp,
						training_pattern |
						DP_LINK_SCRAMBLING_DISABLE);
			cr_tries++;
			continue;
		}

		if (drm_dp_channel_eq_ok(link_status,
					 intel_dp->lane_count)) {
			channel_eq = true;
			break;
		}

		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_training_clock_recovery(intel_dp);
			intel_dp_set_link_train(intel_dp,
						training_pattern |
						DP_LINK_SCRAMBLING_DISABLE);
			tries = 0;
			cr_tries++;
			continue;
		}

		/* Update training set as requested by target */
		intel_get_adjust_train(intel_dp, link_status);
		if (!intel_dp_update_link_train(intel_dp)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
		++tries;
	}

	intel_dp_set_idle_link_train(intel_dp);

	if (channel_eq)
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
	intel_dp_set_link_train(intel_dp,
				DP_TRAINING_PATTERN_DISABLE);
}

void
intel_dp_start_link_train(struct intel_dp *intel_dp)
{
	intel_dp_link_training_clock_recovery(intel_dp);
	intel_dp_link_training_channel_equalization(intel_dp);
}
Commit	Line	Data
94223d04 ACO	1	/*
	2	* Copyright © 2008-2015 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*/
	23
	24	#include "intel_drv.h"
	25
	26	static void
	27	intel_get_adjust_train(struct intel_dp *intel_dp,
	28	const uint8_t link_status[DP_LINK_STATUS_SIZE])
	29	{
	30	uint8_t v = 0;
	31	uint8_t p = 0;
	32	int lane;
	33	uint8_t voltage_max;
	34	uint8_t preemph_max;
	35
	36	for (lane = 0; lane < intel_dp->lane_count; lane++) {
	37	uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
	38	uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
	39
	40	if (this_v > v)
	41	v = this_v;
	42	if (this_p > p)
	43	p = this_p;
	44	}
	45
	46	voltage_max = intel_dp_voltage_max(intel_dp);
	47	if (v >= voltage_max)
	48	v = voltage_max \| DP_TRAIN_MAX_SWING_REACHED;
	49
	50	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	51	if (p >= preemph_max)
	52	p = preemph_max \| DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
	53
	54	for (lane = 0; lane < 4; lane++)
	55	intel_dp->train_set[lane] = v \| p;
	56	}
	57
	58	static bool
	59	intel_dp_set_link_train(struct intel_dp *intel_dp,
	60	uint8_t dp_train_pat)
	61	{
	62	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	63	int ret, len;
	64
65	intel_dp_program_link_training_pattern(intel_dp, dp_train_pat);
66
67	buf[0] = dp_train_pat;
68	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
69	DP_TRAINING_PATTERN_DISABLE) {
70	/* don't write DP_TRAINING_LANEx_SET on disable */
71	len = 1;
72	} else {
73	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
74	memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
75	len = intel_dp->lane_count + 1;
76	}
77
78	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
79	buf, len);
80
81	return ret == len;
82	}
83
84	static bool
85	intel_dp_reset_link_train(struct intel_dp *intel_dp,
86	uint8_t dp_train_pat)
87	{
34511dce	88	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
94223d04 ACO	89	intel_dp_set_signal_levels(intel_dp);
	90	return intel_dp_set_link_train(intel_dp, dp_train_pat);
	91	}
	92
	93	static bool
	94	intel_dp_update_link_train(struct intel_dp *intel_dp)
	95	{
	96	int ret;
	97
	98	intel_dp_set_signal_levels(intel_dp);
	99
	100	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
	101	intel_dp->train_set, intel_dp->lane_count);
	102
	103	return ret == intel_dp->lane_count;
	104	}
	105
	106	/* Enable corresponding port and start training pattern 1 */
	107	static void
	108	intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp)
	109	{
94223d04 ACO	110	int i;
	111	uint8_t voltage;
	112	int voltage_tries, loop_tries;
	113	uint8_t link_config[2];
	114	uint8_t link_bw, rate_select;
	115
ad64217b ACO	116	if (intel_dp->prepare_link_retrain)
ad64217b ACO	117	intel_dp->prepare_link_retrain(intel_dp);
94223d04 ACO	118
	119	intel_dp_compute_rate(intel_dp, intel_dp->link_rate,
	120	&link_bw, &rate_select);
	121
	122	/* Write the link configuration data */
	123	link_config[0] = link_bw;
	124	link_config[1] = intel_dp->lane_count;
	125	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
	126	link_config[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	127	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
	128	if (intel_dp->num_sink_rates)
	129	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
	130	&rate_select, 1);
	131
	132	link_config[0] = 0;
	133	link_config[1] = DP_SET_ANSI_8B10B;
	134	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
	135
	136	intel_dp->DP \|= DP_PORT_EN;
	137
	138	/* clock recovery */
	139	if (!intel_dp_reset_link_train(intel_dp,
	140	DP_TRAINING_PATTERN_1 \|
	141	DP_LINK_SCRAMBLING_DISABLE)) {
	142	DRM_ERROR("failed to enable link training\n");
	143	return;
	144	}
	145
	146	voltage = 0xff;
	147	voltage_tries = 0;
	148	loop_tries = 0;
	149	for (;;) {
	150	uint8_t link_status[DP_LINK_STATUS_SIZE];
	151
	152	drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
	153	if (!intel_dp_get_link_status(intel_dp, link_status)) {
	154	DRM_ERROR("failed to get link status\n");
	155	break;
	156	}
	157
	158	if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
	159	DRM_DEBUG_KMS("clock recovery OK\n");
	160	break;
	161	}
	162
94223d04 ACO	163	/* Check to see if we've tried the max voltage */
	164	for (i = 0; i < intel_dp->lane_count; i++)
	165	if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
	166	break;
	167	if (i == intel_dp->lane_count) {
	168	++loop_tries;
	169	if (loop_tries == 5) {
	170	DRM_ERROR("too many full retries, give up\n");
	171	break;
	172	}
	173	intel_dp_reset_link_train(intel_dp,
	174	DP_TRAINING_PATTERN_1 \|
	175	DP_LINK_SCRAMBLING_DISABLE);
	176	voltage_tries = 0;
	177	continue;
	178	}
	179
	180	/* Check to see if we've tried the same voltage 5 times */
	181	if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
	182	++voltage_tries;
	183	if (voltage_tries == 5) {
	184	DRM_ERROR("too many voltage retries, give up\n");
	185	break;
	186	}
	187	} else
	188	voltage_tries = 0;
	189	voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	190
	191	/* Update training set as requested by target */
	192	intel_get_adjust_train(intel_dp, link_status);
	193	if (!intel_dp_update_link_train(intel_dp)) {
	194	DRM_ERROR("failed to update link training\n");
	195	break;
	196	}
	197	}
	198	}
	199
bf039fa9 JN	200	/*
	201	* Pick training pattern for channel equalization. Training Pattern 3 for HBR2
	202	* or 1.2 devices that support it, Training Pattern 2 otherwise.
	203	*/
	204	static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
94223d04	205	{
bf039fa9	206	u32 training_pattern = DP_TRAINING_PATTERN_2;
0fd64e82	207	bool source_tps3, sink_tps3;
94223d04 ACO	208
94223d04 ACO	209	/*
94223d04	210	* Intel platforms that support HBR2 also support TPS3. TPS3 support is
0fd64e82 JN	211	* also mandatory for downstream devices that support HBR2. However, not
0fd64e82 JN	212	* all sinks follow the spec.
94223d04 ACO	213	*
94223d04 ACO	214	* Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
0fd64e82	215	* supported in source but still not enabled.
94223d04	216	*/
0fd64e82 JN	217	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
	218	sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
	219
	220	if (source_tps3 && sink_tps3) {
94223d04	221	training_pattern = DP_TRAINING_PATTERN_3;
0fd64e82 JN	222	} else if (intel_dp->link_rate == 540000) {
	223	if (!source_tps3)
	224	DRM_DEBUG_KMS("5.4 Gbps link rate without source HBR2/TPS3 support\n");
	225	if (!sink_tps3)
	226	DRM_DEBUG_KMS("5.4 Gbps link rate without sink TPS3 support\n");
	227	}
94223d04	228
bf039fa9 JN	229	return training_pattern;
	230	}
	231
	232	static void
	233	intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp)
	234	{
	235	bool channel_eq = false;
	236	int tries, cr_tries;
	237	u32 training_pattern;
	238
	239	training_pattern = intel_dp_training_pattern(intel_dp);
	240
94223d04 ACO	241	/* channel equalization */
	242	if (!intel_dp_set_link_train(intel_dp,
	243	training_pattern \|
	244	DP_LINK_SCRAMBLING_DISABLE)) {
	245	DRM_ERROR("failed to start channel equalization\n");
	246	return;
	247	}
	248
	249	tries = 0;
	250	cr_tries = 0;
	251	channel_eq = false;
	252	for (;;) {
	253	uint8_t link_status[DP_LINK_STATUS_SIZE];
	254
	255	if (cr_tries > 5) {
	256	DRM_ERROR("failed to train DP, aborting\n");
	257	break;
	258	}
	259
	260	drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
	261	if (!intel_dp_get_link_status(intel_dp, link_status)) {
	262	DRM_ERROR("failed to get link status\n");
	263	break;
	264	}
	265
	266	/* Make sure clock is still ok */
	267	if (!drm_dp_clock_recovery_ok(link_status,
	268	intel_dp->lane_count)) {
94223d04 ACO	269	intel_dp_link_training_clock_recovery(intel_dp);
	270	intel_dp_set_link_train(intel_dp,
	271	training_pattern \|
	272	DP_LINK_SCRAMBLING_DISABLE);
	273	cr_tries++;
	274	continue;
	275	}
	276
	277	if (drm_dp_channel_eq_ok(link_status,
	278	intel_dp->lane_count)) {
	279	channel_eq = true;
	280	break;
	281	}
	282
	283	/* Try 5 times, then try clock recovery if that fails */
	284	if (tries > 5) {
94223d04 ACO	285	intel_dp_link_training_clock_recovery(intel_dp);
	286	intel_dp_set_link_train(intel_dp,
	287	training_pattern \|
	288	DP_LINK_SCRAMBLING_DISABLE);
	289	tries = 0;
	290	cr_tries++;
	291	continue;
	292	}
	293
	294	/* Update training set as requested by target */
	295	intel_get_adjust_train(intel_dp, link_status);
	296	if (!intel_dp_update_link_train(intel_dp)) {
	297	DRM_ERROR("failed to update link training\n");
	298	break;
	299	}
	300	++tries;
	301	}
	302
	303	intel_dp_set_idle_link_train(intel_dp);
	304
34511dce	305	if (channel_eq)
94223d04	306	DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
94223d04 ACO	307	}
	308
	309	void intel_dp_stop_link_train(struct intel_dp *intel_dp)
	310	{
	311	intel_dp_set_link_train(intel_dp,
	312	DP_TRAINING_PATTERN_DISABLE);
	313	}
	314
	315	void
	316	intel_dp_start_link_train(struct intel_dp *intel_dp)
	317	{
	318	intel_dp_link_training_clock_recovery(intel_dp);
	319	intel_dp_link_training_channel_equalization(intel_dp);
	320	}