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drm/i915: Do not free the passed EDID in intel_connector_update_modes()
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
b091cd92 39#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 40#define DP_LINK_STATUS_SIZE 6
41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
cfcb0fc9
JB		 43/**
44 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
45 * @intel_dp: DP struct
46 *
47 * If a CPU or PCH DP output is attached to an eDP panel, this function
48 * will return true, and false otherwise.
49 */
50static bool is_edp(struct intel_dp *intel_dp)
51{
52 return intel_dp->base.type == INTEL_OUTPUT_EDP;
53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
df0e9248
CW		 79static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
80{
81 return container_of(intel_attached_encoder(connector),
82 struct intel_dp, base);
83}
84
814948ad
JB		 85/**
86 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
87 * @encoder: DRM encoder
88 *
89 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
90 * by intel_display.c.
91 */
92bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
93{
94 struct intel_dp *intel_dp;
95
96 if (!encoder)
97 return false;
98
99 intel_dp = enc_to_intel_dp(encoder);
100
101 return is_pch_edp(intel_dp);
102}
103
ea5b213a 104static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 105
32f9d658 106void
0206e353 107intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 108 int *lane_num, int *link_bw)
32f9d658 109{
ea5b213a 110 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 111
ea5b213a
CW		 112 *lane_num = intel_dp->lane_count;
113 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 114 *link_bw = 162000;
ea5b213a 115 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 116 *link_bw = 270000;
117}
118
94bf2ced
DV		 119int
120intel_edp_target_clock(struct intel_encoder *intel_encoder,
121 struct drm_display_mode *mode)
122{
123 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
dd06f90e 124 struct intel_connector *intel_connector = intel_dp->attached_connector;
94bf2ced 125
dd06f90e
JN		 126 if (intel_connector->panel.fixed_mode)
127 return intel_connector->panel.fixed_mode->clock;
94bf2ced
DV		 128 else
129 return mode->clock;
130}
131
a4fc5ed6 132static int
ea5b213a 133intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 134{
9a10f401
KP		 135 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
136 switch (max_lane_count) {
137 case 1: case 2: case 4:
138 break;
139 default:
140 max_lane_count = 4;
a4fc5ed6
KP		 141 }
142 return max_lane_count;
143}
144
145static int
ea5b213a 146intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 147{
7183dc29 148 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 149
150 switch (max_link_bw) {
151 case DP_LINK_BW_1_62:
152 case DP_LINK_BW_2_7:
153 break;
154 default:
155 max_link_bw = DP_LINK_BW_1_62;
156 break;
157 }
158 return max_link_bw;
159}
160
161static int
162intel_dp_link_clock(uint8_t link_bw)
163{
164 if (link_bw == DP_LINK_BW_2_7)
165 return 270000;
166 else
167 return 162000;
168}
169
cd9dde44
AJ		 170/*
171 * The units on the numbers in the next two are... bizarre. Examples will
172 * make it clearer; this one parallels an example in the eDP spec.
173 *
174 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
175 *
176 * 270000 * 1 * 8 / 10 == 216000
177 *
178 * The actual data capacity of that configuration is 2.16Gbit/s, so the
179 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
180 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
181 * 119000. At 18bpp that's 2142000 kilobits per second.
182 *
183 * Thus the strange-looking division by 10 in intel_dp_link_required, to
184 * get the result in decakilobits instead of kilobits.
185 */
186
a4fc5ed6 187static int
c898261c 188intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 189{
cd9dde44 190 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 191}
192
fe27d53e
DA		 193static int
194intel_dp_max_data_rate(int max_link_clock, int max_lanes)
195{
196 return (max_link_clock * max_lanes * 8) / 10;
197}
198
c4867936
DV		 199static bool
200intel_dp_adjust_dithering(struct intel_dp *intel_dp,
201 struct drm_display_mode *mode,
cb1793ce 202 bool adjust_mode)
c4867936
DV		 203{
204 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
205 int max_lanes = intel_dp_max_lane_count(intel_dp);
206 int max_rate, mode_rate;
207
208 mode_rate = intel_dp_link_required(mode->clock, 24);
209 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
210
211 if (mode_rate > max_rate) {
212 mode_rate = intel_dp_link_required(mode->clock, 18);
213 if (mode_rate > max_rate)
214 return false;
215
cb1793ce
DV		 216 if (adjust_mode)
217 mode->private_flags
c4867936
DV		 218 |= INTEL_MODE_DP_FORCE_6BPC;
219
220 return true;
221 }
222
223 return true;
224}
225
a4fc5ed6
KP		 226static int
227intel_dp_mode_valid(struct drm_connector *connector,
228 struct drm_display_mode *mode)
229{
df0e9248 230 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 231 struct intel_connector *intel_connector = to_intel_connector(connector);
232 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
a4fc5ed6 233
dd06f90e
JN		 234 if (is_edp(intel_dp) && fixed_mode) {
235 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 236 return MODE_PANEL;
237
dd06f90e 238 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43
ZY		 239 return MODE_PANEL;
240 }
241
cb1793ce 242 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 243 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 244
245 if (mode->clock < 10000)
246 return MODE_CLOCK_LOW;
247
0af78a2b
DV		 248 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
249 return MODE_H_ILLEGAL;
250
a4fc5ed6
KP		 251 return MODE_OK;
252}
253
254static uint32_t
255pack_aux(uint8_t *src, int src_bytes)
256{
257 int i;
258 uint32_t v = 0;
259
260 if (src_bytes > 4)
261 src_bytes = 4;
262 for (i = 0; i < src_bytes; i++)
263 v |= ((uint32_t) src[i]) << ((3-i) * 8);
264 return v;
265}
266
267static void
268unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
269{
270 int i;
271 if (dst_bytes > 4)
272 dst_bytes = 4;
273 for (i = 0; i < dst_bytes; i++)
274 dst[i] = src >> ((3-i) * 8);
275}
276
fb0f8fbf
KP		 277/* hrawclock is 1/4 the FSB frequency */
278static int
279intel_hrawclk(struct drm_device *dev)
280{
281 struct drm_i915_private *dev_priv = dev->dev_private;
282 uint32_t clkcfg;
283
9473c8f4
VP		 284 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
285 if (IS_VALLEYVIEW(dev))
286 return 200;
287
fb0f8fbf
KP		 288 clkcfg = I915_READ(CLKCFG);
289 switch (clkcfg & CLKCFG_FSB_MASK) {
290 case CLKCFG_FSB_400:
291 return 100;
292 case CLKCFG_FSB_533:
293 return 133;
294 case CLKCFG_FSB_667:
295 return 166;
296 case CLKCFG_FSB_800:
297 return 200;
298 case CLKCFG_FSB_1067:
299 return 266;
300 case CLKCFG_FSB_1333:
301 return 333;
302 /* these two are just a guess; one of them might be right */
303 case CLKCFG_FSB_1600:
304 case CLKCFG_FSB_1600_ALT:
305 return 400;
306 default:
307 return 133;
308 }
309}
310
ebf33b18
KP		 311static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
312{
313 struct drm_device *dev = intel_dp->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
317}
318
319static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
320{
321 struct drm_device *dev = intel_dp->base.base.dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
325}
326
9b984dae
KP		 327static void
328intel_dp_check_edp(struct intel_dp *intel_dp)
329{
330 struct drm_device *dev = intel_dp->base.base.dev;
331 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 332
9b984dae
KP		 333 if (!is_edp(intel_dp))
334 return;
ebf33b18 335 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 336 WARN(1, "eDP powered off while attempting aux channel communication.\n");
337 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 338 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 339 I915_READ(PCH_PP_CONTROL));
340 }
341}
342
a4fc5ed6 343static int
ea5b213a 344intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 345 uint8_t *send, int send_bytes,
346 uint8_t *recv, int recv_size)
347{
ea5b213a 348 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 349 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 350 struct drm_i915_private *dev_priv = dev->dev_private;
351 uint32_t ch_ctl = output_reg + 0x10;
352 uint32_t ch_data = ch_ctl + 4;
353 int i;
354 int recv_bytes;
a4fc5ed6 355 uint32_t status;
fb0f8fbf 356 uint32_t aux_clock_divider;
6b4e0a93 357 int try, precharge;
a4fc5ed6 358
750eb99e
PZ		 359 if (IS_HASWELL(dev)) {
360 switch (intel_dp->port) {
361 case PORT_A:
362 ch_ctl = DPA_AUX_CH_CTL;
363 ch_data = DPA_AUX_CH_DATA1;
364 break;
365 case PORT_B:
366 ch_ctl = PCH_DPB_AUX_CH_CTL;
367 ch_data = PCH_DPB_AUX_CH_DATA1;
368 break;
369 case PORT_C:
370 ch_ctl = PCH_DPC_AUX_CH_CTL;
371 ch_data = PCH_DPC_AUX_CH_DATA1;
372 break;
373 case PORT_D:
374 ch_ctl = PCH_DPD_AUX_CH_CTL;
375 ch_data = PCH_DPD_AUX_CH_DATA1;
376 break;
377 default:
378 BUG();
379 }
380 }
381
9b984dae 382 intel_dp_check_edp(intel_dp);
a4fc5ed6 383 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 384 * and would like to run at 2MHz. So, take the
385 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 386 *
387 * Note that PCH attached eDP panels should use a 125MHz input
388 * clock divider.
a4fc5ed6 389 */
1c95822a 390 if (is_cpu_edp(intel_dp)) {
9473c8f4
VP		 391 if (IS_VALLEYVIEW(dev))
392 aux_clock_divider = 100;
393 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 394 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 395 else
396 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
397 } else if (HAS_PCH_SPLIT(dev))
6919132e 398 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 399 else
400 aux_clock_divider = intel_hrawclk(dev) / 2;
401
6b4e0a93
DV		 402 if (IS_GEN6(dev))
403 precharge = 3;
404 else
405 precharge = 5;
406
11bee43e
JB		 407 /* Try to wait for any previous AUX channel activity */
408 for (try = 0; try < 3; try++) {
409 status = I915_READ(ch_ctl);
410 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
411 break;
412 msleep(1);
413 }
414
415 if (try == 3) {
416 WARN(1, "dp_aux_ch not started status 0x%08x\n",
417 I915_READ(ch_ctl));
4f7f7b7e
CW		 418 return -EBUSY;
419 }
420
fb0f8fbf
KP		 421 /* Must try at least 3 times according to DP spec */
422 for (try = 0; try < 5; try++) {
423 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 424 for (i = 0; i < send_bytes; i += 4)
425 I915_WRITE(ch_data + i,
426 pack_aux(send + i, send_bytes - i));
0206e353 427
fb0f8fbf 428 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 429 I915_WRITE(ch_ctl,
430 DP_AUX_CH_CTL_SEND_BUSY |
431 DP_AUX_CH_CTL_TIME_OUT_400us |
432 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
433 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
434 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
435 DP_AUX_CH_CTL_DONE |
436 DP_AUX_CH_CTL_TIME_OUT_ERROR |
437 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 438 for (;;) {
fb0f8fbf
KP		 439 status = I915_READ(ch_ctl);
440 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
441 break;
4f7f7b7e 442 udelay(100);
fb0f8fbf 443 }
0206e353 444
fb0f8fbf 445 /* Clear done status and any errors */
4f7f7b7e
CW		 446 I915_WRITE(ch_ctl,
447 status |
448 DP_AUX_CH_CTL_DONE |
449 DP_AUX_CH_CTL_TIME_OUT_ERROR |
450 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 451
452 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
453 DP_AUX_CH_CTL_RECEIVE_ERROR))
454 continue;
4f7f7b7e 455 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 456 break;
457 }
458
a4fc5ed6 459 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 460 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 461 return -EBUSY;
a4fc5ed6
KP		 462 }
463
464 /* Check for timeout or receive error.
465 * Timeouts occur when the sink is not connected
466 */
a5b3da54 467 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 468 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 469 return -EIO;
470 }
1ae8c0a5
KP		 471
472 /* Timeouts occur when the device isn't connected, so they're
473 * "normal" -- don't fill the kernel log with these */
a5b3da54 474 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 475 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 476 return -ETIMEDOUT;
a4fc5ed6
KP		 477 }
478
479 /* Unload any bytes sent back from the other side */
480 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
481 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 482 if (recv_bytes > recv_size)
483 recv_bytes = recv_size;
0206e353 484
4f7f7b7e
CW		 485 for (i = 0; i < recv_bytes; i += 4)
486 unpack_aux(I915_READ(ch_data + i),
487 recv + i, recv_bytes - i);
a4fc5ed6
KP		 488
489 return recv_bytes;
490}
491
492/* Write data to the aux channel in native mode */
493static int
ea5b213a 494intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 495 uint16_t address, uint8_t *send, int send_bytes)
496{
497 int ret;
498 uint8_t msg[20];
499 int msg_bytes;
500 uint8_t ack;
501
9b984dae 502 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 503 if (send_bytes > 16)
504 return -1;
505 msg[0] = AUX_NATIVE_WRITE << 4;
506 msg[1] = address >> 8;
eebc863e 507 msg[2] = address & 0xff;
a4fc5ed6
KP		 508 msg[3] = send_bytes - 1;
509 memcpy(&msg[4], send, send_bytes);
510 msg_bytes = send_bytes + 4;
511 for (;;) {
ea5b213a 512 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 513 if (ret < 0)
514 return ret;
515 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
516 break;
517 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
518 udelay(100);
519 else
a5b3da54 520 return -EIO;
a4fc5ed6
KP		 521 }
522 return send_bytes;
523}
524
525/* Write a single byte to the aux channel in native mode */
526static int
ea5b213a 527intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 528 uint16_t address, uint8_t byte)
529{
ea5b213a 530 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 531}
532
533/* read bytes from a native aux channel */
534static int
ea5b213a 535intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 536 uint16_t address, uint8_t *recv, int recv_bytes)
537{
538 uint8_t msg[4];
539 int msg_bytes;
540 uint8_t reply[20];
541 int reply_bytes;
542 uint8_t ack;
543 int ret;
544
9b984dae 545 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 546 msg[0] = AUX_NATIVE_READ << 4;
547 msg[1] = address >> 8;
548 msg[2] = address & 0xff;
549 msg[3] = recv_bytes - 1;
550
551 msg_bytes = 4;
552 reply_bytes = recv_bytes + 1;
553
554 for (;;) {
ea5b213a 555 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 556 reply, reply_bytes);
a5b3da54
KP		 557 if (ret == 0)
558 return -EPROTO;
559 if (ret < 0)
a4fc5ed6
KP		 560 return ret;
561 ack = reply[0];
562 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
563 memcpy(recv, reply + 1, ret - 1);
564 return ret - 1;
565 }
566 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
567 udelay(100);
568 else
a5b3da54 569 return -EIO;
a4fc5ed6
KP		 570 }
571}
572
573static int
ab2c0672
DA		 574intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
575 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 576{
ab2c0672 577 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 578 struct intel_dp *intel_dp = container_of(adapter,
579 struct intel_dp,
580 adapter);
ab2c0672
DA		 581 uint16_t address = algo_data->address;
582 uint8_t msg[5];
583 uint8_t reply[2];
8316f337 584 unsigned retry;
ab2c0672
DA		 585 int msg_bytes;
586 int reply_bytes;
587 int ret;
588
9b984dae 589 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 590 /* Set up the command byte */
591 if (mode & MODE_I2C_READ)
592 msg[0] = AUX_I2C_READ << 4;
593 else
594 msg[0] = AUX_I2C_WRITE << 4;
595
596 if (!(mode & MODE_I2C_STOP))
597 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 598
ab2c0672
DA		 599 msg[1] = address >> 8;
600 msg[2] = address;
601
602 switch (mode) {
603 case MODE_I2C_WRITE:
604 msg[3] = 0;
605 msg[4] = write_byte;
606 msg_bytes = 5;
607 reply_bytes = 1;
608 break;
609 case MODE_I2C_READ:
610 msg[3] = 0;
611 msg_bytes = 4;
612 reply_bytes = 2;
613 break;
614 default:
615 msg_bytes = 3;
616 reply_bytes = 1;
617 break;
618 }
619
8316f337
DF		 620 for (retry = 0; retry < 5; retry++) {
621 ret = intel_dp_aux_ch(intel_dp,
622 msg, msg_bytes,
623 reply, reply_bytes);
ab2c0672 624 if (ret < 0) {
3ff99164 625 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 626 return ret;
627 }
8316f337
DF		 628
629 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
630 case AUX_NATIVE_REPLY_ACK:
631 /* I2C-over-AUX Reply field is only valid
632 * when paired with AUX ACK.
633 */
634 break;
635 case AUX_NATIVE_REPLY_NACK:
636 DRM_DEBUG_KMS("aux_ch native nack\n");
637 return -EREMOTEIO;
638 case AUX_NATIVE_REPLY_DEFER:
639 udelay(100);
640 continue;
641 default:
642 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
643 reply[0]);
644 return -EREMOTEIO;
645 }
646
ab2c0672
DA		 647 switch (reply[0] & AUX_I2C_REPLY_MASK) {
648 case AUX_I2C_REPLY_ACK:
649 if (mode == MODE_I2C_READ) {
650 *read_byte = reply[1];
651 }
652 return reply_bytes - 1;
653 case AUX_I2C_REPLY_NACK:
8316f337 654 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 655 return -EREMOTEIO;
656 case AUX_I2C_REPLY_DEFER:
8316f337 657 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 658 udelay(100);
659 break;
660 default:
8316f337 661 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 662 return -EREMOTEIO;
663 }
664 }
8316f337
DF		 665
666 DRM_ERROR("too many retries, giving up\n");
667 return -EREMOTEIO;
a4fc5ed6
KP		 668}
669
0b5c541b 670static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 671static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 672
a4fc5ed6 673static int
ea5b213a 674intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 675 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 676{
0b5c541b
KP		 677 int ret;
678
d54e9d28 679 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 680 intel_dp->algo.running = false;
681 intel_dp->algo.address = 0;
682 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
683
0206e353 684 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 685 intel_dp->adapter.owner = THIS_MODULE;
686 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 687 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 688 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
689 intel_dp->adapter.algo_data = &intel_dp->algo;
690 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
691
0b5c541b
KP		 692 ironlake_edp_panel_vdd_on(intel_dp);
693 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 694 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 695 return ret;
a4fc5ed6
KP		 696}
697
698static bool
e811f5ae
LP		 699intel_dp_mode_fixup(struct drm_encoder *encoder,
700 const struct drm_display_mode *mode,
a4fc5ed6
KP		 701 struct drm_display_mode *adjusted_mode)
702{
0d3a1bee 703 struct drm_device *dev = encoder->dev;
ea5b213a 704 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
dd06f90e 705 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 706 int lane_count, clock;
ea5b213a
CW		 707 int max_lane_count = intel_dp_max_lane_count(intel_dp);
708 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 709 int bpp, mode_rate;
a4fc5ed6
KP		 710 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
711
dd06f90e
JN		 712 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
713 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
714 adjusted_mode);
1d8e1c75
CW		 715 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
716 mode, adjusted_mode);
0d3a1bee
ZY		 717 }
718
cb1793ce 719 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 720 return false;
721
083f9560
DV		 722 DRM_DEBUG_KMS("DP link computation with max lane count %i "
723 "max bw %02x pixel clock %iKHz\n",
71244653 724 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 725
cb1793ce 726 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 727 return false;
728
729 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 730 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 731
2514bc51
JB		 732 for (clock = 0; clock <= max_clock; clock++) {
733 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 734 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 735
083f9560 736 if (mode_rate <= link_avail) {
ea5b213a
CW		 737 intel_dp->link_bw = bws[clock];
738 intel_dp->lane_count = lane_count;
739 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 740 DRM_DEBUG_KMS("DP link bw %02x lane "
741 "count %d clock %d bpp %d\n",
ea5b213a 742 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 743 adjusted_mode->clock, bpp);
744 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
745 mode_rate, link_avail);
a4fc5ed6
KP		 746 return true;
747 }
748 }
749 }
fe27d53e 750
a4fc5ed6
KP		 751 return false;
752}
753
754struct intel_dp_m_n {
755 uint32_t tu;
756 uint32_t gmch_m;
757 uint32_t gmch_n;
758 uint32_t link_m;
759 uint32_t link_n;
760};
761
762static void
763intel_reduce_ratio(uint32_t *num, uint32_t *den)
764{
765 while (*num > 0xffffff || *den > 0xffffff) {
766 *num >>= 1;
767 *den >>= 1;
768 }
769}
770
771static void
36e83a18 772intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 773 int nlanes,
774 int pixel_clock,
775 int link_clock,
776 struct intel_dp_m_n *m_n)
777{
778 m_n->tu = 64;
36e83a18 779 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 780 m_n->gmch_n = link_clock * nlanes;
781 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
782 m_n->link_m = pixel_clock;
783 m_n->link_n = link_clock;
784 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
785}
786
787void
788intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
789 struct drm_display_mode *adjusted_mode)
790{
791 struct drm_device *dev = crtc->dev;
6c2b7c12 792 struct intel_encoder *encoder;
a4fc5ed6
KP		 793 struct drm_i915_private *dev_priv = dev->dev_private;
794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 795 int lane_count = 4;
a4fc5ed6 796 struct intel_dp_m_n m_n;
9db4a9c7 797 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 798
799 /*
21d40d37 800 * Find the lane count in the intel_encoder private
a4fc5ed6 801 */
6c2b7c12
DV		 802 for_each_encoder_on_crtc(dev, crtc, encoder) {
803 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 804
9a10f401
KP		 805 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
806 intel_dp->base.type == INTEL_OUTPUT_EDP)
807 {
ea5b213a 808 lane_count = intel_dp->lane_count;
51190667 809 break;
a4fc5ed6
KP		 810 }
811 }
812
813 /*
814 * Compute the GMCH and Link ratios. The '3' here is
815 * the number of bytes_per_pixel post-LUT, which we always
816 * set up for 8-bits of R/G/B, or 3 bytes total.
817 */
858fa035 818 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 819 mode->clock, adjusted_mode->clock, &m_n);
820
1eb8dfec
PZ		 821 if (IS_HASWELL(dev)) {
822 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
823 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
824 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
825 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
826 } else if (HAS_PCH_SPLIT(dev)) {
7346bfa0 827 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 828 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
829 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
830 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
74a4dd2e
VP		 831 } else if (IS_VALLEYVIEW(dev)) {
832 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
833 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
834 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
835 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
a4fc5ed6 836 } else {
9db4a9c7 837 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
7346bfa0 838 TU_SIZE(m_n.tu) | m_n.gmch_m);
9db4a9c7
JB		 839 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
840 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
841 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 842 }
843}
844
247d89f6
PZ		 845void intel_dp_init_link_config(struct intel_dp *intel_dp)
846{
847 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
848 intel_dp->link_configuration[0] = intel_dp->link_bw;
849 intel_dp->link_configuration[1] = intel_dp->lane_count;
850 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
851 /*
852 * Check for DPCD version > 1.1 and enhanced framing support
853 */
854 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
855 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
856 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
857 }
858}
859
a4fc5ed6
KP		 860static void
861intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
862 struct drm_display_mode *adjusted_mode)
863{
e3421a18 864 struct drm_device *dev = encoder->dev;
417e822d 865 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 866 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 867 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
869
417e822d 870 /*
1a2eb460 871 * There are four kinds of DP registers:
417e822d
KP		 872 *
873 * IBX PCH
1a2eb460
KP		 874 * SNB CPU
875 * IVB CPU
417e822d
KP		 876 * CPT PCH
877 *
878 * IBX PCH and CPU are the same for almost everything,
879 * except that the CPU DP PLL is configured in this
880 * register
881 *
882 * CPT PCH is quite different, having many bits moved
883 * to the TRANS_DP_CTL register instead. That
884 * configuration happens (oddly) in ironlake_pch_enable
885 */
9c9e7927 886
417e822d
KP		 887 /* Preserve the BIOS-computed detected bit. This is
888 * supposed to be read-only.
889 */
890 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 891
417e822d 892 /* Handle DP bits in common between all three register formats */
417e822d 893 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 894
ea5b213a 895 switch (intel_dp->lane_count) {
a4fc5ed6 896 case 1:
ea5b213a 897 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 898 break;
899 case 2:
ea5b213a 900 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 901 break;
902 case 4:
ea5b213a 903 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 904 break;
905 }
e0dac65e
WF		 906 if (intel_dp->has_audio) {
907 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
908 pipe_name(intel_crtc->pipe));
ea5b213a 909 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 910 intel_write_eld(encoder, adjusted_mode);
911 }
247d89f6
PZ		 912
913 intel_dp_init_link_config(intel_dp);
a4fc5ed6 914
417e822d 915 /* Split out the IBX/CPU vs CPT settings */
32f9d658 916
19c03924 917 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 918 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
919 intel_dp->DP |= DP_SYNC_HS_HIGH;
920 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
921 intel_dp->DP |= DP_SYNC_VS_HIGH;
922 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
923
924 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
925 intel_dp->DP |= DP_ENHANCED_FRAMING;
926
927 intel_dp->DP |= intel_crtc->pipe << 29;
928
929 /* don't miss out required setting for eDP */
1a2eb460
KP		 930 if (adjusted_mode->clock < 200000)
931 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
932 else
933 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
934 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 935 intel_dp->DP |= intel_dp->color_range;
936
937 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
938 intel_dp->DP |= DP_SYNC_HS_HIGH;
939 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
940 intel_dp->DP |= DP_SYNC_VS_HIGH;
941 intel_dp->DP |= DP_LINK_TRAIN_OFF;
942
943 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
944 intel_dp->DP |= DP_ENHANCED_FRAMING;
945
946 if (intel_crtc->pipe == 1)
947 intel_dp->DP |= DP_PIPEB_SELECT;
948
949 if (is_cpu_edp(intel_dp)) {
950 /* don't miss out required setting for eDP */
417e822d
KP		 951 if (adjusted_mode->clock < 200000)
952 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
953 else
954 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
955 }
956 } else {
957 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 958 }
a4fc5ed6
KP		 959}
960
99ea7127
KP		 961#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
962#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
963
964#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
965#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
966
967#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
968#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
969
970static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
971 u32 mask,
972 u32 value)
bd943159 973{
99ea7127
KP		 974 struct drm_device *dev = intel_dp->base.base.dev;
975 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 976
99ea7127
KP		 977 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
978 mask, value,
979 I915_READ(PCH_PP_STATUS),
980 I915_READ(PCH_PP_CONTROL));
32ce697c 981
99ea7127
KP		 982 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
983 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
984 I915_READ(PCH_PP_STATUS),
985 I915_READ(PCH_PP_CONTROL));
32ce697c 986 }
99ea7127 987}
32ce697c 988
99ea7127
KP		 989static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
990{
991 DRM_DEBUG_KMS("Wait for panel power on\n");
992 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 993}
994
99ea7127
KP		 995static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
996{
997 DRM_DEBUG_KMS("Wait for panel power off time\n");
998 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
999}
1000
1001static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1002{
1003 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1004 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1005}
1006
1007
832dd3c1
KP		 1008/* Read the current pp_control value, unlocking the register if it
1009 * is locked
1010 */
1011
1012static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1013{
1014 u32 control = I915_READ(PCH_PP_CONTROL);
1015
1016 control &= ~PANEL_UNLOCK_MASK;
1017 control |= PANEL_UNLOCK_REGS;
1018 return control;
bd943159
KP		 1019}
1020
5d613501
JB		 1021static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1022{
1023 struct drm_device *dev = intel_dp->base.base.dev;
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 u32 pp;
1026
97af61f5
KP		 1027 if (!is_edp(intel_dp))
1028 return;
f01eca2e 1029 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 1030
bd943159
KP		 1031 WARN(intel_dp->want_panel_vdd,
1032 "eDP VDD already requested on\n");
1033
1034 intel_dp->want_panel_vdd = true;
99ea7127 1035
bd943159
KP		 1036 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1037 DRM_DEBUG_KMS("eDP VDD already on\n");
1038 return;
1039 }
1040
99ea7127
KP		 1041 if (!ironlake_edp_have_panel_power(intel_dp))
1042 ironlake_wait_panel_power_cycle(intel_dp);
1043
832dd3c1 1044 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1045 pp |= EDP_FORCE_VDD;
1046 I915_WRITE(PCH_PP_CONTROL, pp);
1047 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1048 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1049 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1050
1051 /*
1052 * If the panel wasn't on, delay before accessing aux channel
1053 */
1054 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1055 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1056 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1057 }
5d613501
JB		 1058}
1059
bd943159 1060static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1061{
1062 struct drm_device *dev = intel_dp->base.base.dev;
1063 struct drm_i915_private *dev_priv = dev->dev_private;
1064 u32 pp;
1065
bd943159 1066 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1067 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1068 pp &= ~EDP_FORCE_VDD;
1069 I915_WRITE(PCH_PP_CONTROL, pp);
1070 POSTING_READ(PCH_PP_CONTROL);
1071
1072 /* Make sure sequencer is idle before allowing subsequent activity */
1073 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1074 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1075
1076 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1077 }
1078}
5d613501 1079
bd943159
KP		 1080static void ironlake_panel_vdd_work(struct work_struct *__work)
1081{
1082 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1083 struct intel_dp, panel_vdd_work);
1084 struct drm_device *dev = intel_dp->base.base.dev;
1085
627f7675 1086 mutex_lock(&dev->mode_config.mutex);
bd943159 1087 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1088 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1089}
1090
1091static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1092{
97af61f5
KP		 1093 if (!is_edp(intel_dp))
1094 return;
5d613501 1095
bd943159
KP		 1096 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1097 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1098
bd943159
KP		 1099 intel_dp->want_panel_vdd = false;
1100
1101 if (sync) {
1102 ironlake_panel_vdd_off_sync(intel_dp);
1103 } else {
1104 /*
1105 * Queue the timer to fire a long
1106 * time from now (relative to the power down delay)
1107 * to keep the panel power up across a sequence of operations
1108 */
1109 schedule_delayed_work(&intel_dp->panel_vdd_work,
1110 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1111 }
5d613501
JB		 1112}
1113
86a3073e 1114static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1115{
01cb9ea6 1116 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1117 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1118 u32 pp;
9934c132 1119
97af61f5 1120 if (!is_edp(intel_dp))
bd943159 1121 return;
99ea7127
KP		 1122
1123 DRM_DEBUG_KMS("Turn eDP power on\n");
1124
1125 if (ironlake_edp_have_panel_power(intel_dp)) {
1126 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1127 return;
99ea7127 1128 }
9934c132 1129
99ea7127 1130 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1131
99ea7127 1132 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1133 if (IS_GEN5(dev)) {
1134 /* ILK workaround: disable reset around power sequence */
1135 pp &= ~PANEL_POWER_RESET;
1136 I915_WRITE(PCH_PP_CONTROL, pp);
1137 POSTING_READ(PCH_PP_CONTROL);
1138 }
37c6c9b0 1139
1c0ae80a 1140 pp |= POWER_TARGET_ON;
99ea7127
KP		 1141 if (!IS_GEN5(dev))
1142 pp |= PANEL_POWER_RESET;
1143
9934c132 1144 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1145 POSTING_READ(PCH_PP_CONTROL);
9934c132 1146
99ea7127 1147 ironlake_wait_panel_on(intel_dp);
9934c132 1148
05ce1a49
KP		 1149 if (IS_GEN5(dev)) {
1150 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1151 I915_WRITE(PCH_PP_CONTROL, pp);
1152 POSTING_READ(PCH_PP_CONTROL);
1153 }
9934c132
JB		 1154}
1155
99ea7127 1156static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1157{
99ea7127 1158 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1159 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1160 u32 pp;
9934c132 1161
97af61f5
KP		 1162 if (!is_edp(intel_dp))
1163 return;
37c6c9b0 1164
99ea7127 1165 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1166
6cb49835 1167 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1168
99ea7127 1169 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1170 /* We need to switch off panel power _and_ force vdd, for otherwise some
1171 * panels get very unhappy and cease to work. */
1172 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1173 I915_WRITE(PCH_PP_CONTROL, pp);
1174 POSTING_READ(PCH_PP_CONTROL);
9934c132 1175
35a38556
DV		 1176 intel_dp->want_panel_vdd = false;
1177
99ea7127 1178 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1179}
1180
86a3073e 1181static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1182{
f01eca2e 1183 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1184 struct drm_i915_private *dev_priv = dev->dev_private;
1185 u32 pp;
1186
f01eca2e
KP		 1187 if (!is_edp(intel_dp))
1188 return;
1189
28c97730 1190 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1191 /*
1192 * If we enable the backlight right away following a panel power
1193 * on, we may see slight flicker as the panel syncs with the eDP
1194 * link. So delay a bit to make sure the image is solid before
1195 * allowing it to appear.
1196 */
f01eca2e 1197 msleep(intel_dp->backlight_on_delay);
832dd3c1 1198 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1199 pp |= EDP_BLC_ENABLE;
1200 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1201 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1202}
1203
86a3073e 1204static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1205{
f01eca2e 1206 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1207 struct drm_i915_private *dev_priv = dev->dev_private;
1208 u32 pp;
1209
f01eca2e
KP		 1210 if (!is_edp(intel_dp))
1211 return;
1212
28c97730 1213 DRM_DEBUG_KMS("\n");
832dd3c1 1214 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1215 pp &= ~EDP_BLC_ENABLE;
1216 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1217 POSTING_READ(PCH_PP_CONTROL);
1218 msleep(intel_dp->backlight_off_delay);
32f9d658 1219}
a4fc5ed6 1220
2bd2ad64 1221static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1222{
2bd2ad64
DV		 1223 struct drm_device *dev = intel_dp->base.base.dev;
1224 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1225 struct drm_i915_private *dev_priv = dev->dev_private;
1226 u32 dpa_ctl;
1227
2bd2ad64
DV		 1228 assert_pipe_disabled(dev_priv,
1229 to_intel_crtc(crtc)->pipe);
1230
d240f20f
JB		 1231 DRM_DEBUG_KMS("\n");
1232 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1233 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1234 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1235
1236 /* We don't adjust intel_dp->DP while tearing down the link, to
1237 * facilitate link retraining (e.g. after hotplug). Hence clear all
1238 * enable bits here to ensure that we don't enable too much. */
1239 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1240 intel_dp->DP |= DP_PLL_ENABLE;
1241 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1242 POSTING_READ(DP_A);
1243 udelay(200);
d240f20f
JB		 1244}
1245
2bd2ad64 1246static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1247{
2bd2ad64
DV		 1248 struct drm_device *dev = intel_dp->base.base.dev;
1249 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1250 struct drm_i915_private *dev_priv = dev->dev_private;
1251 u32 dpa_ctl;
1252
2bd2ad64
DV		 1253 assert_pipe_disabled(dev_priv,
1254 to_intel_crtc(crtc)->pipe);
1255
d240f20f 1256 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1257 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1258 "dp pll off, should be on\n");
1259 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1260
1261 /* We can't rely on the value tracked for the DP register in
1262 * intel_dp->DP because link_down must not change that (otherwise link
1263 * re-training will fail. */
298b0b39 1264 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1265 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1266 POSTING_READ(DP_A);
d240f20f
JB		 1267 udelay(200);
1268}
1269
c7ad3810 1270/* If the sink supports it, try to set the power state appropriately */
c19b0669 1271void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1272{
1273 int ret, i;
1274
1275 /* Should have a valid DPCD by this point */
1276 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1277 return;
1278
1279 if (mode != DRM_MODE_DPMS_ON) {
1280 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1281 DP_SET_POWER_D3);
1282 if (ret != 1)
1283 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1284 } else {
1285 /*
1286 * When turning on, we need to retry for 1ms to give the sink
1287 * time to wake up.
1288 */
1289 for (i = 0; i < 3; i++) {
1290 ret = intel_dp_aux_native_write_1(intel_dp,
1291 DP_SET_POWER,
1292 DP_SET_POWER_D0);
1293 if (ret == 1)
1294 break;
1295 msleep(1);
1296 }
1297 }
1298}
1299
19d8fe15
DV		 1300static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1301 enum pipe *pipe)
d240f20f 1302{
19d8fe15
DV		 1303 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1304 struct drm_device *dev = encoder->base.dev;
1305 struct drm_i915_private *dev_priv = dev->dev_private;
1306 u32 tmp = I915_READ(intel_dp->output_reg);
1307
1308 if (!(tmp & DP_PORT_EN))
1309 return false;
1310
1311 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1312 *pipe = PORT_TO_PIPE_CPT(tmp);
1313 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1314 *pipe = PORT_TO_PIPE(tmp);
1315 } else {
1316 u32 trans_sel;
1317 u32 trans_dp;
1318 int i;
1319
1320 switch (intel_dp->output_reg) {
1321 case PCH_DP_B:
1322 trans_sel = TRANS_DP_PORT_SEL_B;
1323 break;
1324 case PCH_DP_C:
1325 trans_sel = TRANS_DP_PORT_SEL_C;
1326 break;
1327 case PCH_DP_D:
1328 trans_sel = TRANS_DP_PORT_SEL_D;
1329 break;
1330 default:
1331 return true;
1332 }
1333
1334 for_each_pipe(i) {
1335 trans_dp = I915_READ(TRANS_DP_CTL(i));
1336 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1337 *pipe = i;
1338 return true;
1339 }
1340 }
1341 }
1342
1343 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1344
19d8fe15
DV		 1345 return true;
1346}
1347
e8cb4558 1348static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1349{
e8cb4558 1350 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1351
1352 /* Make sure the panel is off before trying to change the mode. But also
1353 * ensure that we have vdd while we switch off the panel. */
1354 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1355 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1356 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1357 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1358
1359 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1360 if (!is_cpu_edp(intel_dp))
1361 intel_dp_link_down(intel_dp);
d240f20f
JB		 1362}
1363
2bd2ad64
DV		 1364static void intel_post_disable_dp(struct intel_encoder *encoder)
1365{
1366 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1367
3739850b
DV		 1368 if (is_cpu_edp(intel_dp)) {
1369 intel_dp_link_down(intel_dp);
2bd2ad64 1370 ironlake_edp_pll_off(intel_dp);
3739850b 1371 }
2bd2ad64
DV		 1372}
1373
e8cb4558 1374static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1375{
e8cb4558
DV		 1376 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1377 struct drm_device *dev = encoder->base.dev;
1378 struct drm_i915_private *dev_priv = dev->dev_private;
1379 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1380
0c33d8d7
DV		 1381 if (WARN_ON(dp_reg & DP_PORT_EN))
1382 return;
1383
97af61f5 1384 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1385 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1386 intel_dp_start_link_train(intel_dp);
1387 ironlake_edp_panel_on(intel_dp);
1388 ironlake_edp_panel_vdd_off(intel_dp, true);
1389 intel_dp_complete_link_train(intel_dp);
f01eca2e 1390 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1391}
1392
2bd2ad64 1393static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1394{
2bd2ad64 1395 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1396
2bd2ad64
DV		 1397 if (is_cpu_edp(intel_dp))
1398 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1399}
1400
1401/*
df0c237d
JB		 1402 * Native read with retry for link status and receiver capability reads for
1403 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1404 */
1405static bool
df0c237d
JB		 1406intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1407 uint8_t *recv, int recv_bytes)
a4fc5ed6 1408{
61da5fab
JB		 1409 int ret, i;
1410
df0c237d
JB		 1411 /*
1412 * Sinks are *supposed* to come up within 1ms from an off state,
1413 * but we're also supposed to retry 3 times per the spec.
1414 */
61da5fab 1415 for (i = 0; i < 3; i++) {
df0c237d
JB		 1416 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1417 recv_bytes);
1418 if (ret == recv_bytes)
61da5fab
JB		 1419 return true;
1420 msleep(1);
1421 }
a4fc5ed6 1422
61da5fab 1423 return false;
a4fc5ed6
KP		 1424}
1425
1426/*
1427 * Fetch AUX CH registers 0x202 - 0x207 which contain
1428 * link status information
1429 */
1430static bool
93f62dad 1431intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1432{
df0c237d
JB		 1433 return intel_dp_aux_native_read_retry(intel_dp,
1434 DP_LANE0_1_STATUS,
93f62dad 1435 link_status,
df0c237d 1436 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1437}
1438
1439static uint8_t
1440intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1441 int r)
1442{
1443 return link_status[r - DP_LANE0_1_STATUS];
1444}
1445
a4fc5ed6 1446static uint8_t
93f62dad 1447intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1448 int lane)
1449{
a4fc5ed6
KP		 1450 int s = ((lane & 1) ?
1451 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1452 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1453 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1454
1455 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1456}
1457
1458static uint8_t
93f62dad 1459intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1460 int lane)
1461{
a4fc5ed6
KP		 1462 int s = ((lane & 1) ?
1463 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1464 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1465 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1466
1467 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1468}
1469
1470
1471#if 0
1472static char *voltage_names[] = {
1473 "0.4V", "0.6V", "0.8V", "1.2V"
1474};
1475static char *pre_emph_names[] = {
1476 "0dB", "3.5dB", "6dB", "9.5dB"
1477};
1478static char *link_train_names[] = {
1479 "pattern 1", "pattern 2", "idle", "off"
1480};
1481#endif
1482
1483/*
1484 * These are source-specific values; current Intel hardware supports
1485 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1486 */
a4fc5ed6
KP		 1487
1488static uint8_t
1a2eb460 1489intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1490{
1a2eb460
KP		 1491 struct drm_device *dev = intel_dp->base.base.dev;
1492
1493 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1494 return DP_TRAIN_VOLTAGE_SWING_800;
1495 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1496 return DP_TRAIN_VOLTAGE_SWING_1200;
1497 else
1498 return DP_TRAIN_VOLTAGE_SWING_800;
1499}
1500
1501static uint8_t
1502intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1503{
1504 struct drm_device *dev = intel_dp->base.base.dev;
1505
d6c0d722
PZ		 1506 if (IS_HASWELL(dev)) {
1507 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1508 case DP_TRAIN_VOLTAGE_SWING_400:
1509 return DP_TRAIN_PRE_EMPHASIS_9_5;
1510 case DP_TRAIN_VOLTAGE_SWING_600:
1511 return DP_TRAIN_PRE_EMPHASIS_6;
1512 case DP_TRAIN_VOLTAGE_SWING_800:
1513 return DP_TRAIN_PRE_EMPHASIS_3_5;
1514 case DP_TRAIN_VOLTAGE_SWING_1200:
1515 default:
1516 return DP_TRAIN_PRE_EMPHASIS_0;
1517 }
1518 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1519 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1520 case DP_TRAIN_VOLTAGE_SWING_400:
1521 return DP_TRAIN_PRE_EMPHASIS_6;
1522 case DP_TRAIN_VOLTAGE_SWING_600:
1523 case DP_TRAIN_VOLTAGE_SWING_800:
1524 return DP_TRAIN_PRE_EMPHASIS_3_5;
1525 default:
1526 return DP_TRAIN_PRE_EMPHASIS_0;
1527 }
1528 } else {
1529 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1530 case DP_TRAIN_VOLTAGE_SWING_400:
1531 return DP_TRAIN_PRE_EMPHASIS_6;
1532 case DP_TRAIN_VOLTAGE_SWING_600:
1533 return DP_TRAIN_PRE_EMPHASIS_6;
1534 case DP_TRAIN_VOLTAGE_SWING_800:
1535 return DP_TRAIN_PRE_EMPHASIS_3_5;
1536 case DP_TRAIN_VOLTAGE_SWING_1200:
1537 default:
1538 return DP_TRAIN_PRE_EMPHASIS_0;
1539 }
a4fc5ed6
KP		 1540 }
1541}
1542
1543static void
93f62dad 1544intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1545{
1546 uint8_t v = 0;
1547 uint8_t p = 0;
1548 int lane;
93f62dad 1549 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1550 uint8_t voltage_max;
1551 uint8_t preemph_max;
a4fc5ed6 1552
33a34e4e 1553 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1554 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1555 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1556
1557 if (this_v > v)
1558 v = this_v;
1559 if (this_p > p)
1560 p = this_p;
1561 }
1562
1a2eb460 1563 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1564 if (v >= voltage_max)
1565 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1566
1a2eb460
KP		 1567 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1568 if (p >= preemph_max)
1569 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1570
1571 for (lane = 0; lane < 4; lane++)
33a34e4e 1572 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1573}
1574
1575static uint32_t
93f62dad 1576intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1577{
3cf2efb1 1578 uint32_t signal_levels = 0;
a4fc5ed6 1579
3cf2efb1 1580 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1581 case DP_TRAIN_VOLTAGE_SWING_400:
1582 default:
1583 signal_levels |= DP_VOLTAGE_0_4;
1584 break;
1585 case DP_TRAIN_VOLTAGE_SWING_600:
1586 signal_levels |= DP_VOLTAGE_0_6;
1587 break;
1588 case DP_TRAIN_VOLTAGE_SWING_800:
1589 signal_levels |= DP_VOLTAGE_0_8;
1590 break;
1591 case DP_TRAIN_VOLTAGE_SWING_1200:
1592 signal_levels |= DP_VOLTAGE_1_2;
1593 break;
1594 }
3cf2efb1 1595 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1596 case DP_TRAIN_PRE_EMPHASIS_0:
1597 default:
1598 signal_levels |= DP_PRE_EMPHASIS_0;
1599 break;
1600 case DP_TRAIN_PRE_EMPHASIS_3_5:
1601 signal_levels |= DP_PRE_EMPHASIS_3_5;
1602 break;
1603 case DP_TRAIN_PRE_EMPHASIS_6:
1604 signal_levels |= DP_PRE_EMPHASIS_6;
1605 break;
1606 case DP_TRAIN_PRE_EMPHASIS_9_5:
1607 signal_levels |= DP_PRE_EMPHASIS_9_5;
1608 break;
1609 }
1610 return signal_levels;
1611}
1612
e3421a18
ZW		 1613/* Gen6's DP voltage swing and pre-emphasis control */
1614static uint32_t
1615intel_gen6_edp_signal_levels(uint8_t train_set)
1616{
3c5a62b5
YL		 1617 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1618 DP_TRAIN_PRE_EMPHASIS_MASK);
1619 switch (signal_levels) {
e3421a18 1620 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1621 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1622 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1623 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1624 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1625 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1626 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1627 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1628 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1629 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1630 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1631 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1632 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1633 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1634 default:
3c5a62b5
YL		 1635 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1636 "0x%x\n", signal_levels);
1637 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1638 }
1639}
1640
1a2eb460
KP		 1641/* Gen7's DP voltage swing and pre-emphasis control */
1642static uint32_t
1643intel_gen7_edp_signal_levels(uint8_t train_set)
1644{
1645 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1646 DP_TRAIN_PRE_EMPHASIS_MASK);
1647 switch (signal_levels) {
1648 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1649 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1650 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1651 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1652 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1653 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1654
1655 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1656 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1657 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1658 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1659
1660 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1661 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1662 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1663 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1664
1665 default:
1666 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1667 "0x%x\n", signal_levels);
1668 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1669 }
1670}
1671
d6c0d722
PZ		 1672/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1673static uint32_t
1674intel_dp_signal_levels_hsw(uint8_t train_set)
1675{
1676 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1677 DP_TRAIN_PRE_EMPHASIS_MASK);
1678 switch (signal_levels) {
1679 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1680 return DDI_BUF_EMP_400MV_0DB_HSW;
1681 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1682 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1683 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1684 return DDI_BUF_EMP_400MV_6DB_HSW;
1685 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1686 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1687
1688 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1689 return DDI_BUF_EMP_600MV_0DB_HSW;
1690 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1691 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1692 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1693 return DDI_BUF_EMP_600MV_6DB_HSW;
1694
1695 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1696 return DDI_BUF_EMP_800MV_0DB_HSW;
1697 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1698 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1699 default:
1700 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1701 "0x%x\n", signal_levels);
1702 return DDI_BUF_EMP_400MV_0DB_HSW;
1703 }
1704}
1705
a4fc5ed6
KP		 1706static uint8_t
1707intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1708 int lane)
1709{
a4fc5ed6 1710 int s = (lane & 1) * 4;
93f62dad 1711 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1712
1713 return (l >> s) & 0xf;
1714}
1715
1716/* Check for clock recovery is done on all channels */
1717static bool
1718intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1719{
1720 int lane;
1721 uint8_t lane_status;
1722
1723 for (lane = 0; lane < lane_count; lane++) {
1724 lane_status = intel_get_lane_status(link_status, lane);
1725 if ((lane_status & DP_LANE_CR_DONE) == 0)
1726 return false;
1727 }
1728 return true;
1729}
1730
1731/* Check to see if channel eq is done on all channels */
1732#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1733 DP_LANE_CHANNEL_EQ_DONE|\
1734 DP_LANE_SYMBOL_LOCKED)
1735static bool
93f62dad 1736intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1737{
1738 uint8_t lane_align;
1739 uint8_t lane_status;
1740 int lane;
1741
93f62dad 1742 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1743 DP_LANE_ALIGN_STATUS_UPDATED);
1744 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1745 return false;
33a34e4e 1746 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1747 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1748 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1749 return false;
1750 }
1751 return true;
1752}
1753
1754static bool
ea5b213a 1755intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1756 uint32_t dp_reg_value,
58e10eb9 1757 uint8_t dp_train_pat)
a4fc5ed6 1758{
4ef69c7a 1759 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1760 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1761 int ret;
d6c0d722 1762 uint32_t temp;
a4fc5ed6 1763
d6c0d722
PZ		 1764 if (IS_HASWELL(dev)) {
1765 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1766
1767 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1768 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1769 else
1770 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1771
1772 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1773 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1774 case DP_TRAINING_PATTERN_DISABLE:
1775 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1776 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1777
1778 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1779 DP_TP_STATUS_IDLE_DONE), 1))
1780 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1781
1782 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1783 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1784
1785 break;
1786 case DP_TRAINING_PATTERN_1:
1787 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1788 break;
1789 case DP_TRAINING_PATTERN_2:
1790 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1791 break;
1792 case DP_TRAINING_PATTERN_3:
1793 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1794 break;
1795 }
1796 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1797
1798 } else if (HAS_PCH_CPT(dev) &&
1799 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1800 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1801
1802 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1803 case DP_TRAINING_PATTERN_DISABLE:
1804 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1805 break;
1806 case DP_TRAINING_PATTERN_1:
1807 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1808 break;
1809 case DP_TRAINING_PATTERN_2:
1810 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1811 break;
1812 case DP_TRAINING_PATTERN_3:
1813 DRM_ERROR("DP training pattern 3 not supported\n");
1814 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1815 break;
1816 }
1817
1818 } else {
1819 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1820
1821 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1822 case DP_TRAINING_PATTERN_DISABLE:
1823 dp_reg_value |= DP_LINK_TRAIN_OFF;
1824 break;
1825 case DP_TRAINING_PATTERN_1:
1826 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1827 break;
1828 case DP_TRAINING_PATTERN_2:
1829 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1830 break;
1831 case DP_TRAINING_PATTERN_3:
1832 DRM_ERROR("DP training pattern 3 not supported\n");
1833 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1834 break;
1835 }
1836 }
1837
ea5b213a
CW		 1838 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1839 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1840
ea5b213a 1841 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1842 DP_TRAINING_PATTERN_SET,
1843 dp_train_pat);
1844
47ea7542
PZ		 1845 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1846 DP_TRAINING_PATTERN_DISABLE) {
1847 ret = intel_dp_aux_native_write(intel_dp,
1848 DP_TRAINING_LANE0_SET,
1849 intel_dp->train_set,
1850 intel_dp->lane_count);
1851 if (ret != intel_dp->lane_count)
1852 return false;
1853 }
a4fc5ed6
KP		 1854
1855 return true;
1856}
1857
33a34e4e 1858/* Enable corresponding port and start training pattern 1 */
c19b0669 1859void
33a34e4e 1860intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1861{
c19b0669
PZ		 1862 struct drm_encoder *encoder = &intel_dp->base.base;
1863 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1864 int i;
1865 uint8_t voltage;
1866 bool clock_recovery = false;
cdb0e95b 1867 int voltage_tries, loop_tries;
ea5b213a 1868 uint32_t DP = intel_dp->DP;
a4fc5ed6 1869
c19b0669
PZ		 1870 if (IS_HASWELL(dev))
1871 intel_ddi_prepare_link_retrain(encoder);
1872
3cf2efb1
CW		 1873 /* Write the link configuration data */
1874 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1875 intel_dp->link_configuration,
1876 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1877
1878 DP |= DP_PORT_EN;
1a2eb460 1879
33a34e4e 1880 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1881 voltage = 0xff;
cdb0e95b
KP		 1882 voltage_tries = 0;
1883 loop_tries = 0;
a4fc5ed6
KP		 1884 clock_recovery = false;
1885 for (;;) {
33a34e4e 1886 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1887 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1888 uint32_t signal_levels;
417e822d 1889
d6c0d722
PZ		 1890 if (IS_HASWELL(dev)) {
1891 signal_levels = intel_dp_signal_levels_hsw(
1892 intel_dp->train_set[0]);
1893 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1894 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1895 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1896 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1897 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1898 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1899 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1900 } else {
93f62dad 1901 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1902 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1903 }
d6c0d722
PZ		 1904 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1905 signal_levels);
a4fc5ed6 1906
47ea7542 1907 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1908 DP_TRAINING_PATTERN_1 |
1909 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1910 break;
a4fc5ed6
KP		 1911 /* Set training pattern 1 */
1912
3cf2efb1 1913 udelay(100);
93f62dad
KP		 1914 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1915 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1916 break;
93f62dad 1917 }
a4fc5ed6 1918
93f62dad
KP		 1919 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1920 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1921 clock_recovery = true;
1922 break;
1923 }
1924
1925 /* Check to see if we've tried the max voltage */
1926 for (i = 0; i < intel_dp->lane_count; i++)
1927 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1928 break;
0d710688 1929 if (i == intel_dp->lane_count && voltage_tries == 5) {
24773670 1930 if (++loop_tries == 5) {
cdb0e95b
KP		 1931 DRM_DEBUG_KMS("too many full retries, give up\n");
1932 break;
1933 }
1934 memset(intel_dp->train_set, 0, 4);
1935 voltage_tries = 0;
1936 continue;
1937 }
a4fc5ed6 1938
3cf2efb1 1939 /* Check to see if we've tried the same voltage 5 times */
24773670
CW		 1940 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1941 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
cdb0e95b 1942 voltage_tries = 0;
24773670
CW		 1943 } else
1944 ++voltage_tries;
a4fc5ed6 1945
3cf2efb1 1946 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1947 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1948 }
1949
33a34e4e
JB		 1950 intel_dp->DP = DP;
1951}
1952
c19b0669 1953void
33a34e4e
JB		 1954intel_dp_complete_link_train(struct intel_dp *intel_dp)
1955{
4ef69c7a 1956 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1957 bool channel_eq = false;
37f80975 1958 int tries, cr_tries;
33a34e4e
JB		 1959 uint32_t DP = intel_dp->DP;
1960
a4fc5ed6
KP		 1961 /* channel equalization */
1962 tries = 0;
37f80975 1963 cr_tries = 0;
a4fc5ed6
KP		 1964 channel_eq = false;
1965 for (;;) {
33a34e4e 1966 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1967 uint32_t signal_levels;
93f62dad 1968 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1969
37f80975
JB		 1970 if (cr_tries > 5) {
1971 DRM_ERROR("failed to train DP, aborting\n");
1972 intel_dp_link_down(intel_dp);
1973 break;
1974 }
1975
d6c0d722
PZ		 1976 if (IS_HASWELL(dev)) {
1977 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1978 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1979 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1980 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1981 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1982 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1983 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1984 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1985 } else {
93f62dad 1986 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1987 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1988 }
1989
a4fc5ed6 1990 /* channel eq pattern */
47ea7542 1991 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1992 DP_TRAINING_PATTERN_2 |
1993 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1994 break;
1995
3cf2efb1 1996 udelay(400);
93f62dad 1997 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1998 break;
a4fc5ed6 1999
37f80975 2000 /* Make sure clock is still ok */
93f62dad 2001 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2002 intel_dp_start_link_train(intel_dp);
2003 cr_tries++;
2004 continue;
2005 }
2006
93f62dad 2007 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 2008 channel_eq = true;
2009 break;
2010 }
a4fc5ed6 2011
37f80975
JB		 2012 /* Try 5 times, then try clock recovery if that fails */
2013 if (tries > 5) {
2014 intel_dp_link_down(intel_dp);
2015 intel_dp_start_link_train(intel_dp);
2016 tries = 0;
2017 cr_tries++;
2018 continue;
2019 }
a4fc5ed6 2020
3cf2efb1 2021 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2022 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2023 ++tries;
869184a6 2024 }
3cf2efb1 2025
d6c0d722
PZ		 2026 if (channel_eq)
2027 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2028
47ea7542 2029 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2030}
2031
2032static void
ea5b213a 2033intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2034{
4ef69c7a 2035 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2036 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 2037 uint32_t DP = intel_dp->DP;
a4fc5ed6 2038
c19b0669
PZ		 2039 /*
2040 * DDI code has a strict mode set sequence and we should try to respect
2041 * it, otherwise we might hang the machine in many different ways. So we
2042 * really should be disabling the port only on a complete crtc_disable
2043 * sequence. This function is just called under two conditions on DDI
2044 * code:
2045 * - Link train failed while doing crtc_enable, and on this case we
2046 * really should respect the mode set sequence and wait for a
2047 * crtc_disable.
2048 * - Someone turned the monitor off and intel_dp_check_link_status
2049 * called us. We don't need to disable the whole port on this case, so
2050 * when someone turns the monitor on again,
2051 * intel_ddi_prepare_link_retrain will take care of redoing the link
2052 * train.
2053 */
2054 if (IS_HASWELL(dev))
2055 return;
2056
0c33d8d7 2057 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2058 return;
2059
28c97730 2060 DRM_DEBUG_KMS("\n");
32f9d658 2061
1a2eb460 2062 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 2063 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2064 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2065 } else {
2066 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2067 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2068 }
fe255d00 2069 POSTING_READ(intel_dp->output_reg);
5eb08b69 2070
fe255d00 2071 msleep(17);
5eb08b69 2072
493a7081 2073 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2074 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 2075 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2076
5bddd17f
EA		 2077 /* Hardware workaround: leaving our transcoder select
2078 * set to transcoder B while it's off will prevent the
2079 * corresponding HDMI output on transcoder A.
2080 *
2081 * Combine this with another hardware workaround:
2082 * transcoder select bit can only be cleared while the
2083 * port is enabled.
2084 */
2085 DP &= ~DP_PIPEB_SELECT;
2086 I915_WRITE(intel_dp->output_reg, DP);
2087
2088 /* Changes to enable or select take place the vblank
2089 * after being written.
2090 */
31acbcc4
CW		 2091 if (crtc == NULL) {
2092 /* We can arrive here never having been attached
2093 * to a CRTC, for instance, due to inheriting
2094 * random state from the BIOS.
2095 *
2096 * If the pipe is not running, play safe and
2097 * wait for the clocks to stabilise before
2098 * continuing.
2099 */
2100 POSTING_READ(intel_dp->output_reg);
2101 msleep(50);
2102 } else
2103 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 2104 }
2105
832afda6 2106 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2107 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2108 POSTING_READ(intel_dp->output_reg);
f01eca2e 2109 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2110}
2111
26d61aad
KP		 2112static bool
2113intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2114{
92fd8fd1 2115 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
b091cd92
AJ		 2116 sizeof(intel_dp->dpcd)) == 0)
2117 return false; /* aux transfer failed */
92fd8fd1 2118
b091cd92
AJ		 2119 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2120 return false; /* DPCD not present */
2121
2122 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2123 DP_DWN_STRM_PORT_PRESENT))
2124 return true; /* native DP sink */
2125
2126 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2127 return true; /* no per-port downstream info */
2128
2129 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2130 intel_dp->downstream_ports,
2131 DP_MAX_DOWNSTREAM_PORTS) == 0)
2132 return false; /* downstream port status fetch failed */
2133
2134 return true;
92fd8fd1
KP		 2135}
2136
0d198328
AJ		 2137static void
2138intel_dp_probe_oui(struct intel_dp *intel_dp)
2139{
2140 u8 buf[3];
2141
2142 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2143 return;
2144
351cfc34
DV		 2145 ironlake_edp_panel_vdd_on(intel_dp);
2146
0d198328
AJ		 2147 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2148 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2149 buf[0], buf[1], buf[2]);
2150
2151 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2152 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2153 buf[0], buf[1], buf[2]);
351cfc34
DV		 2154
2155 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2156}
2157
a60f0e38
JB		 2158static bool
2159intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2160{
2161 int ret;
2162
2163 ret = intel_dp_aux_native_read_retry(intel_dp,
2164 DP_DEVICE_SERVICE_IRQ_VECTOR,
2165 sink_irq_vector, 1);
2166 if (!ret)
2167 return false;
2168
2169 return true;
2170}
2171
2172static void
2173intel_dp_handle_test_request(struct intel_dp *intel_dp)
2174{
2175 /* NAK by default */
2176 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2177}
2178
a4fc5ed6
KP		 2179/*
2180 * According to DP spec
2181 * 5.1.2:
2182 * 1. Read DPCD
2183 * 2. Configure link according to Receiver Capabilities
2184 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2185 * 4. Check link status on receipt of hot-plug interrupt
2186 */
2187
2188static void
ea5b213a 2189intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2190{
a60f0e38 2191 u8 sink_irq_vector;
93f62dad 2192 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2193
24e804ba 2194 if (!intel_dp->base.connectors_active)
d2b996ac 2195 return;
59cd09e1 2196
24e804ba 2197 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2198 return;
2199
92fd8fd1 2200 /* Try to read receiver status if the link appears to be up */
93f62dad 2201 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2202 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2203 return;
2204 }
2205
92fd8fd1 2206 /* Now read the DPCD to see if it's actually running */
26d61aad 2207 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2208 intel_dp_link_down(intel_dp);
2209 return;
2210 }
2211
a60f0e38
JB		 2212 /* Try to read the source of the interrupt */
2213 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2214 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2215 /* Clear interrupt source */
2216 intel_dp_aux_native_write_1(intel_dp,
2217 DP_DEVICE_SERVICE_IRQ_VECTOR,
2218 sink_irq_vector);
2219
2220 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2221 intel_dp_handle_test_request(intel_dp);
2222 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2223 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2224 }
2225
93f62dad 2226 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2227 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2228 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2229 intel_dp_start_link_train(intel_dp);
2230 intel_dp_complete_link_train(intel_dp);
2231 }
a4fc5ed6 2232}
a4fc5ed6 2233
07d3dc18 2234/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2235static enum drm_connector_status
26d61aad 2236intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2237{
07d3dc18
AJ		 2238 uint8_t *dpcd = intel_dp->dpcd;
2239 bool hpd;
2240 uint8_t type;
2241
2242 if (!intel_dp_get_dpcd(intel_dp))
2243 return connector_status_disconnected;
2244
2245 /* if there's no downstream port, we're done */
2246 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2247 return connector_status_connected;
2248
2249 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2250 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2251 if (hpd) {
da131a46 2252 uint8_t reg;
07d3dc18 2253 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
da131a46 2254 &reg, 1))
07d3dc18 2255 return connector_status_unknown;
da131a46
AJ		 2256 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2257 : connector_status_disconnected;
07d3dc18
AJ		 2258 }
2259
2260 /* If no HPD, poke DDC gently */
2261 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2262 return connector_status_connected;
07d3dc18
AJ		 2263
2264 /* Well we tried, say unknown for unreliable port types */
2265 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2266 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2267 return connector_status_unknown;
2268
2269 /* Anything else is out of spec, warn and ignore */
2270 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2271 return connector_status_disconnected;
71ba9000
AJ		 2272}
2273
5eb08b69 2274static enum drm_connector_status
a9756bb5 2275ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2276{
5eb08b69
ZW		 2277 enum drm_connector_status status;
2278
fe16d949
CW		 2279 /* Can't disconnect eDP, but you can close the lid... */
2280 if (is_edp(intel_dp)) {
2281 status = intel_panel_detect(intel_dp->base.base.dev);
2282 if (status == connector_status_unknown)
2283 status = connector_status_connected;
2284 return status;
2285 }
01cb9ea6 2286
26d61aad 2287 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2288}
2289
a4fc5ed6 2290static enum drm_connector_status
a9756bb5 2291g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2292{
4ef69c7a 2293 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2294 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2295 uint32_t bit;
5eb08b69 2296
ea5b213a 2297 switch (intel_dp->output_reg) {
a4fc5ed6 2298 case DP_B:
10f76a38 2299 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2300 break;
2301 case DP_C:
10f76a38 2302 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2303 break;
2304 case DP_D:
10f76a38 2305 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2306 break;
2307 default:
2308 return connector_status_unknown;
2309 }
2310
10f76a38 2311 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2312 return connector_status_disconnected;
2313
26d61aad 2314 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2315}
2316
8c241fef
KP		 2317static struct edid *
2318intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2319{
2320 struct intel_dp *intel_dp = intel_attached_dp(connector);
2321 struct edid *edid;
d6f24d0f
JB		 2322 int size;
2323
2324 if (is_edp(intel_dp)) {
2325 if (!intel_dp->edid)
2326 return NULL;
2327
2328 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2329 edid = kmalloc(size, GFP_KERNEL);
2330 if (!edid)
2331 return NULL;
2332
2333 memcpy(edid, intel_dp->edid, size);
2334 return edid;
2335 }
8c241fef 2336
8c241fef 2337 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2338 return edid;
2339}
2340
2341static int
2342intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2343{
2344 struct intel_dp *intel_dp = intel_attached_dp(connector);
2345 int ret;
2346
d6f24d0f
JB		 2347 if (is_edp(intel_dp)) {
2348 drm_mode_connector_update_edid_property(connector,
2349 intel_dp->edid);
2350 ret = drm_add_edid_modes(connector, intel_dp->edid);
2351 drm_edid_to_eld(connector,
2352 intel_dp->edid);
d6f24d0f
JB		 2353 return intel_dp->edid_mode_count;
2354 }
2355
8c241fef 2356 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2357 return ret;
2358}
2359
2360
a9756bb5
ZW		 2361/**
2362 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2363 *
2364 * \return true if DP port is connected.
2365 * \return false if DP port is disconnected.
2366 */
2367static enum drm_connector_status
2368intel_dp_detect(struct drm_connector *connector, bool force)
2369{
2370 struct intel_dp *intel_dp = intel_attached_dp(connector);
2371 struct drm_device *dev = intel_dp->base.base.dev;
2372 enum drm_connector_status status;
2373 struct edid *edid = NULL;
2374
2375 intel_dp->has_audio = false;
2376
2377 if (HAS_PCH_SPLIT(dev))
2378 status = ironlake_dp_detect(intel_dp);
2379 else
2380 status = g4x_dp_detect(intel_dp);
1b9be9d0 2381
ac66ae83
AJ		 2382 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2383 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2384 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2385 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2386
a9756bb5
ZW		 2387 if (status != connector_status_connected)
2388 return status;
2389
0d198328
AJ		 2390 intel_dp_probe_oui(intel_dp);
2391
c3e5f67b
DV		 2392 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2393 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2394 } else {
8c241fef 2395 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2396 if (edid) {
2397 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2398 kfree(edid);
2399 }
a9756bb5
ZW		 2400 }
2401
2402 return connector_status_connected;
a4fc5ed6
KP		 2403}
2404
2405static int intel_dp_get_modes(struct drm_connector *connector)
2406{
df0e9248 2407 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2408 struct intel_connector *intel_connector = to_intel_connector(connector);
4ef69c7a 2409 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658 2410 int ret;
a4fc5ed6
KP		 2411
2412 /* We should parse the EDID data and find out if it has an audio sink
2413 */
2414
8c241fef 2415 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2416 if (ret)
32f9d658
ZW		 2417 return ret;
2418
f8779fda 2419 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2420 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2421 struct drm_display_mode *mode;
dd06f90e
JN		 2422 mode = drm_mode_duplicate(dev,
2423 intel_connector->panel.fixed_mode);
f8779fda 2424 if (mode) {
32f9d658
ZW		 2425 drm_mode_probed_add(connector, mode);
2426 return 1;
2427 }
2428 }
2429 return 0;
a4fc5ed6
KP		 2430}
2431
1aad7ac0
CW		 2432static bool
2433intel_dp_detect_audio(struct drm_connector *connector)
2434{
2435 struct intel_dp *intel_dp = intel_attached_dp(connector);
2436 struct edid *edid;
2437 bool has_audio = false;
2438
8c241fef 2439 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2440 if (edid) {
2441 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2442 kfree(edid);
2443 }
2444
2445 return has_audio;
2446}
2447
f684960e
CW		 2448static int
2449intel_dp_set_property(struct drm_connector *connector,
2450 struct drm_property *property,
2451 uint64_t val)
2452{
e953fd7b 2453 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2454 struct intel_dp *intel_dp = intel_attached_dp(connector);
2455 int ret;
2456
2457 ret = drm_connector_property_set_value(connector, property, val);
2458 if (ret)
2459 return ret;
2460
3f43c48d 2461 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2462 int i = val;
2463 bool has_audio;
2464
2465 if (i == intel_dp->force_audio)
f684960e
CW		 2466 return 0;
2467
1aad7ac0 2468 intel_dp->force_audio = i;
f684960e 2469
c3e5f67b 2470 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2471 has_audio = intel_dp_detect_audio(connector);
2472 else
c3e5f67b 2473 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2474
2475 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2476 return 0;
2477
1aad7ac0 2478 intel_dp->has_audio = has_audio;
f684960e
CW		 2479 goto done;
2480 }
2481
e953fd7b
CW		 2482 if (property == dev_priv->broadcast_rgb_property) {
2483 if (val == !!intel_dp->color_range)
2484 return 0;
2485
2486 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2487 goto done;
2488 }
2489
f684960e
CW		 2490 return -EINVAL;
2491
2492done:
2493 if (intel_dp->base.base.crtc) {
2494 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2495 intel_set_mode(crtc, &crtc->mode,
2496 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2497 }
2498
2499 return 0;
2500}
2501
a4fc5ed6 2502static void
0206e353 2503intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2504{
aaa6fd2a 2505 struct drm_device *dev = connector->dev;
be3cd5e3 2506 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2507 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2508
1d508706 2509 if (is_edp(intel_dp)) {
aaa6fd2a 2510 intel_panel_destroy_backlight(dev);
1d508706
JN		 2511 intel_panel_fini(&intel_connector->panel);
2512 }
aaa6fd2a 2513
a4fc5ed6
KP		 2514 drm_sysfs_connector_remove(connector);
2515 drm_connector_cleanup(connector);
55f78c43 2516 kfree(connector);
a4fc5ed6
KP		 2517}
2518
24d05927
DV		 2519static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2520{
2521 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2522
2523 i2c_del_adapter(&intel_dp->adapter);
2524 drm_encoder_cleanup(encoder);
bd943159 2525 if (is_edp(intel_dp)) {
d6f24d0f 2526 kfree(intel_dp->edid);
bd943159
KP		 2527 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2528 ironlake_panel_vdd_off_sync(intel_dp);
2529 }
24d05927
DV		 2530 kfree(intel_dp);
2531}
2532
a4fc5ed6 2533static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2534 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2535 .mode_set = intel_dp_mode_set,
1f703855 2536 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2537};
2538
a7902ac5
PZ		 2539static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2540 .mode_fixup = intel_dp_mode_fixup,
2541 .mode_set = intel_ddi_mode_set,
2542 .disable = intel_encoder_noop,
2543};
2544
a4fc5ed6 2545static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2546 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2547 .detect = intel_dp_detect,
2548 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2549 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2550 .destroy = intel_dp_destroy,
2551};
2552
2553static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2554 .get_modes = intel_dp_get_modes,
2555 .mode_valid = intel_dp_mode_valid,
df0e9248 2556 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2557};
2558
a4fc5ed6 2559static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2560 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2561};
2562
995b6762 2563static void
21d40d37 2564intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2565{
ea5b213a 2566 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2567
885a5014 2568 intel_dp_check_link_status(intel_dp);
c8110e52 2569}
6207937d 2570
e3421a18
ZW		 2571/* Return which DP Port should be selected for Transcoder DP control */
2572int
0206e353 2573intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2574{
2575 struct drm_device *dev = crtc->dev;
6c2b7c12 2576 struct intel_encoder *encoder;
e3421a18 2577
6c2b7c12
DV		 2578 for_each_encoder_on_crtc(dev, crtc, encoder) {
2579 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2580
417e822d
KP		 2581 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2582 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2583 return intel_dp->output_reg;
e3421a18 2584 }
ea5b213a 2585
e3421a18
ZW		 2586 return -1;
2587}
2588
36e83a18 2589/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2590bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2591{
2592 struct drm_i915_private *dev_priv = dev->dev_private;
2593 struct child_device_config *p_child;
2594 int i;
2595
2596 if (!dev_priv->child_dev_num)
2597 return false;
2598
2599 for (i = 0; i < dev_priv->child_dev_num; i++) {
2600 p_child = dev_priv->child_dev + i;
2601
2602 if (p_child->dvo_port == PORT_IDPD &&
2603 p_child->device_type == DEVICE_TYPE_eDP)
2604 return true;
2605 }
2606 return false;
2607}
2608
f684960e
CW		 2609static void
2610intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2611{
3f43c48d 2612 intel_attach_force_audio_property(connector);
e953fd7b 2613 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2614}
2615
a4fc5ed6 2616void
ab9d7c30 2617intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2618{
2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620 struct drm_connector *connector;
ea5b213a 2621 struct intel_dp *intel_dp;
21d40d37 2622 struct intel_encoder *intel_encoder;
55f78c43 2623 struct intel_connector *intel_connector;
f8779fda 2624 struct drm_display_mode *fixed_mode = NULL;
5eb08b69 2625 const char *name = NULL;
b329530c 2626 int type;
a4fc5ed6 2627
ea5b213a
CW		 2628 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2629 if (!intel_dp)
a4fc5ed6
KP		 2630 return;
2631
3d3dc149 2632 intel_dp->output_reg = output_reg;
ab9d7c30 2633 intel_dp->port = port;
0767935e
DV		 2634 /* Preserve the current hw state. */
2635 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2636
55f78c43
ZW		 2637 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2638 if (!intel_connector) {
ea5b213a 2639 kfree(intel_dp);
55f78c43
ZW		 2640 return;
2641 }
ea5b213a 2642 intel_encoder = &intel_dp->base;
dd06f90e 2643 intel_dp->attached_connector = intel_connector;
55f78c43 2644
ea5b213a 2645 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2646 if (intel_dpd_is_edp(dev))
ea5b213a 2647 intel_dp->is_pch_edp = true;
b329530c 2648
19c03924
GB		 2649 /*
2650 * FIXME : We need to initialize built-in panels before external panels.
2651 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2652 */
2653 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2654 type = DRM_MODE_CONNECTOR_eDP;
2655 intel_encoder->type = INTEL_OUTPUT_EDP;
2656 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2657 type = DRM_MODE_CONNECTOR_eDP;
2658 intel_encoder->type = INTEL_OUTPUT_EDP;
2659 } else {
2660 type = DRM_MODE_CONNECTOR_DisplayPort;
2661 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2662 }
2663
55f78c43 2664 connector = &intel_connector->base;
b329530c 2665 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2666 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2667
eb1f8e4f
DA		 2668 connector->polled = DRM_CONNECTOR_POLL_HPD;
2669
66a9278e 2670 intel_encoder->cloneable = false;
f8aed700 2671
66a9278e
DV		 2672 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2673 ironlake_panel_vdd_work);
6251ec0a 2674
27f8227b 2675 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2676
a4fc5ed6
KP		 2677 connector->interlace_allowed = true;
2678 connector->doublescan_allowed = 0;
2679
4ef69c7a 2680 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2681 DRM_MODE_ENCODER_TMDS);
a7902ac5
PZ		 2682
2683 if (IS_HASWELL(dev))
2684 drm_encoder_helper_add(&intel_encoder->base,
2685 &intel_dp_helper_funcs_hsw);
2686 else
2687 drm_encoder_helper_add(&intel_encoder->base,
2688 &intel_dp_helper_funcs);
a4fc5ed6 2689
df0e9248 2690 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2691 drm_sysfs_connector_add(connector);
2692
a7902ac5
PZ		 2693 if (IS_HASWELL(dev)) {
2694 intel_encoder->enable = intel_enable_ddi;
2695 intel_encoder->pre_enable = intel_ddi_pre_enable;
2696 intel_encoder->disable = intel_disable_ddi;
2697 intel_encoder->post_disable = intel_ddi_post_disable;
2698 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2699 } else {
2700 intel_encoder->enable = intel_enable_dp;
2701 intel_encoder->pre_enable = intel_pre_enable_dp;
2702 intel_encoder->disable = intel_disable_dp;
2703 intel_encoder->post_disable = intel_post_disable_dp;
2704 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2705 }
19d8fe15 2706 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2707
a4fc5ed6 2708 /* Set up the DDC bus. */
ab9d7c30
PZ		 2709 switch (port) {
2710 case PORT_A:
2711 name = "DPDDC-A";
2712 break;
2713 case PORT_B:
2714 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2715 name = "DPDDC-B";
2716 break;
2717 case PORT_C:
2718 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2719 name = "DPDDC-C";
2720 break;
2721 case PORT_D:
2722 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2723 name = "DPDDC-D";
2724 break;
2725 default:
2726 WARN(1, "Invalid port %c\n", port_name(port));
2727 break;
5eb08b69
ZW		 2728 }
2729
89667383
JB		 2730 /* Cache some DPCD data in the eDP case */
2731 if (is_edp(intel_dp)) {
f01eca2e
KP		 2732 struct edp_power_seq cur, vbt;
2733 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2734
2735 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2736 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2737 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2738
bfa3384a
JB		 2739 if (!pp_on || !pp_off || !pp_div) {
2740 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2741 intel_dp_encoder_destroy(&intel_dp->base.base);
2742 intel_dp_destroy(&intel_connector->base);
2743 return;
2744 }
2745
f01eca2e
KP		 2746 /* Pull timing values out of registers */
2747 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2748 PANEL_POWER_UP_DELAY_SHIFT;
2749
2750 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2751 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2752
f01eca2e
KP		 2753 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2754 PANEL_LIGHT_OFF_DELAY_SHIFT;
2755
2756 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2757 PANEL_POWER_DOWN_DELAY_SHIFT;
2758
2759 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2760 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2761
2762 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2763 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2764
2765 vbt = dev_priv->edp.pps;
2766
2767 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2768 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2769
2770#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2771
2772 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2773 intel_dp->backlight_on_delay = get_delay(t8);
2774 intel_dp->backlight_off_delay = get_delay(t9);
2775 intel_dp->panel_power_down_delay = get_delay(t10);
2776 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2777
2778 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2779 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2780 intel_dp->panel_power_cycle_delay);
2781
2782 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2783 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
c1f05264
DA		 2784 }
2785
2786 intel_dp_i2c_init(intel_dp, intel_connector, name);
2787
2788 if (is_edp(intel_dp)) {
2789 bool ret;
f8779fda 2790 struct drm_display_mode *scan;
c1f05264 2791 struct edid *edid;
5d613501
JB		 2792
2793 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2794 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2795 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2796
59f3e272 2797 if (ret) {
7183dc29
JB		 2798 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2799 dev_priv->no_aux_handshake =
2800 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2801 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2802 } else {
3d3dc149 2803 /* if this fails, presume the device is a ghost */
48898b03 2804 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2805 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2806 intel_dp_destroy(&intel_connector->base);
3d3dc149 2807 return;
89667383 2808 }
89667383 2809
d6f24d0f
JB		 2810 ironlake_edp_panel_vdd_on(intel_dp);
2811 edid = drm_get_edid(connector, &intel_dp->adapter);
2812 if (edid) {
2813 drm_mode_connector_update_edid_property(connector,
2814 edid);
2815 intel_dp->edid_mode_count =
2816 drm_add_edid_modes(connector, edid);
2817 drm_edid_to_eld(connector, edid);
2818 intel_dp->edid = edid;
2819 }
f8779fda
JN		 2820
2821 /* prefer fixed mode from EDID if available */
2822 list_for_each_entry(scan, &connector->probed_modes, head) {
2823 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2824 fixed_mode = drm_mode_duplicate(dev, scan);
2825 break;
2826 }
2827 }
2828
2829 /* fallback to VBT if available for eDP */
2830 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2831 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2832 if (fixed_mode)
2833 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2834 }
f8779fda 2835
d6f24d0f
JB		 2836 ironlake_edp_panel_vdd_off(intel_dp, false);
2837 }
552fb0b7 2838
21d40d37 2839 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2840
1d508706 2841 if (is_edp(intel_dp)) {
dd06f90e 2842 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2843 intel_panel_setup_backlight(connector);
1d508706 2844 }
32f9d658 2845
f684960e
CW		 2846 intel_dp_add_properties(intel_dp, connector);
2847
a4fc5ed6
KP		 2848 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2849 * 0xd. Failure to do so will result in spurious interrupts being
2850 * generated on the port when a cable is not attached.
2851 */
2852 if (IS_G4X(dev) && !IS_GM45(dev)) {
2853 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2854 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2855 }
2856}
Linux 6.x block layer and io_uring tree(s)