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DRM/i915: Restore sdvo_flags after dtd->mode->dtd Roundrtrip.
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
a4fc5ed6
KP		 31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
34#include "drm_crtc_helper.h"
d6f24d0f 35#include "drm_edid.h"
a4fc5ed6
KP		 36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
a4fc5ed6 39
edb39244 40#define DP_RECEIVER_CAP_SIZE 0xf
a4fc5ed6
KP		 41#define DP_LINK_STATUS_SIZE 6
42#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43
cfcb0fc9
JB		 44/**
45 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
46 * @intel_dp: DP struct
47 *
48 * If a CPU or PCH DP output is attached to an eDP panel, this function
49 * will return true, and false otherwise.
50 */
51static bool is_edp(struct intel_dp *intel_dp)
52{
53 return intel_dp->base.type == INTEL_OUTPUT_EDP;
54}
55
56/**
57 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
58 * @intel_dp: DP struct
59 *
60 * Returns true if the given DP struct corresponds to a PCH DP port attached
61 * to an eDP panel, false otherwise. Helpful for determining whether we
62 * may need FDI resources for a given DP output or not.
63 */
64static bool is_pch_edp(struct intel_dp *intel_dp)
65{
66 return intel_dp->is_pch_edp;
67}
68
1c95822a
AJ		 69/**
70 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
71 * @intel_dp: DP struct
72 *
73 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 */
75static bool is_cpu_edp(struct intel_dp *intel_dp)
76{
77 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
78}
79
ea5b213a
CW		 80static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
81{
4ef69c7a 82 return container_of(encoder, struct intel_dp, base.base);
ea5b213a 83}
a4fc5ed6 84
df0e9248
CW		 85static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
86{
87 return container_of(intel_attached_encoder(connector),
88 struct intel_dp, base);
89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
33a34e4e
JB		 110static void intel_dp_start_link_train(struct intel_dp *intel_dp);
111static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
ea5b213a 112static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 113
32f9d658 114void
0206e353 115intel_edp_link_config(struct intel_encoder *intel_encoder,
ea5b213a 116 int *lane_num, int *link_bw)
32f9d658 117{
ea5b213a 118 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
32f9d658 119
ea5b213a
CW		 120 *lane_num = intel_dp->lane_count;
121 if (intel_dp->link_bw == DP_LINK_BW_1_62)
32f9d658 122 *link_bw = 162000;
ea5b213a 123 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
32f9d658
ZW		 124 *link_bw = 270000;
125}
126
94bf2ced
DV		 127int
128intel_edp_target_clock(struct intel_encoder *intel_encoder,
129 struct drm_display_mode *mode)
130{
131 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
132
133 if (intel_dp->panel_fixed_mode)
134 return intel_dp->panel_fixed_mode->clock;
135 else
136 return mode->clock;
137}
138
a4fc5ed6 139static int
ea5b213a 140intel_dp_max_lane_count(struct intel_dp *intel_dp)
a4fc5ed6 141{
9a10f401
KP		 142 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
143 switch (max_lane_count) {
144 case 1: case 2: case 4:
145 break;
146 default:
147 max_lane_count = 4;
a4fc5ed6
KP		 148 }
149 return max_lane_count;
150}
151
152static int
ea5b213a 153intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 154{
7183dc29 155 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 156
157 switch (max_link_bw) {
158 case DP_LINK_BW_1_62:
159 case DP_LINK_BW_2_7:
160 break;
161 default:
162 max_link_bw = DP_LINK_BW_1_62;
163 break;
164 }
165 return max_link_bw;
166}
167
168static int
169intel_dp_link_clock(uint8_t link_bw)
170{
171 if (link_bw == DP_LINK_BW_2_7)
172 return 270000;
173 else
174 return 162000;
175}
176
cd9dde44
AJ		 177/*
178 * The units on the numbers in the next two are... bizarre. Examples will
179 * make it clearer; this one parallels an example in the eDP spec.
180 *
181 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
182 *
183 * 270000 * 1 * 8 / 10 == 216000
184 *
185 * The actual data capacity of that configuration is 2.16Gbit/s, so the
186 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
187 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
188 * 119000. At 18bpp that's 2142000 kilobits per second.
189 *
190 * Thus the strange-looking division by 10 in intel_dp_link_required, to
191 * get the result in decakilobits instead of kilobits.
192 */
193
a4fc5ed6 194static int
c898261c 195intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 196{
cd9dde44 197 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 198}
199
fe27d53e
DA		 200static int
201intel_dp_max_data_rate(int max_link_clock, int max_lanes)
202{
203 return (max_link_clock * max_lanes * 8) / 10;
204}
205
c4867936
DV		 206static bool
207intel_dp_adjust_dithering(struct intel_dp *intel_dp,
208 struct drm_display_mode *mode,
cb1793ce 209 bool adjust_mode)
c4867936
DV		 210{
211 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
212 int max_lanes = intel_dp_max_lane_count(intel_dp);
213 int max_rate, mode_rate;
214
215 mode_rate = intel_dp_link_required(mode->clock, 24);
216 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
217
218 if (mode_rate > max_rate) {
219 mode_rate = intel_dp_link_required(mode->clock, 18);
220 if (mode_rate > max_rate)
221 return false;
222
cb1793ce
DV		 223 if (adjust_mode)
224 mode->private_flags
c4867936
DV		 225 |= INTEL_MODE_DP_FORCE_6BPC;
226
227 return true;
228 }
229
230 return true;
231}
232
a4fc5ed6
KP		 233static int
234intel_dp_mode_valid(struct drm_connector *connector,
235 struct drm_display_mode *mode)
236{
df0e9248 237 struct intel_dp *intel_dp = intel_attached_dp(connector);
a4fc5ed6 238
d15456de
KP		 239 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
240 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
7de56f43
ZY		 241 return MODE_PANEL;
242
d15456de 243 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
7de56f43
ZY		 244 return MODE_PANEL;
245 }
246
cb1793ce 247 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
c4867936 248 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 249
250 if (mode->clock < 10000)
251 return MODE_CLOCK_LOW;
252
0af78a2b
DV		 253 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
254 return MODE_H_ILLEGAL;
255
a4fc5ed6
KP		 256 return MODE_OK;
257}
258
259static uint32_t
260pack_aux(uint8_t *src, int src_bytes)
261{
262 int i;
263 uint32_t v = 0;
264
265 if (src_bytes > 4)
266 src_bytes = 4;
267 for (i = 0; i < src_bytes; i++)
268 v |= ((uint32_t) src[i]) << ((3-i) * 8);
269 return v;
270}
271
272static void
273unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
274{
275 int i;
276 if (dst_bytes > 4)
277 dst_bytes = 4;
278 for (i = 0; i < dst_bytes; i++)
279 dst[i] = src >> ((3-i) * 8);
280}
281
fb0f8fbf
KP		 282/* hrawclock is 1/4 the FSB frequency */
283static int
284intel_hrawclk(struct drm_device *dev)
285{
286 struct drm_i915_private *dev_priv = dev->dev_private;
287 uint32_t clkcfg;
288
289 clkcfg = I915_READ(CLKCFG);
290 switch (clkcfg & CLKCFG_FSB_MASK) {
291 case CLKCFG_FSB_400:
292 return 100;
293 case CLKCFG_FSB_533:
294 return 133;
295 case CLKCFG_FSB_667:
296 return 166;
297 case CLKCFG_FSB_800:
298 return 200;
299 case CLKCFG_FSB_1067:
300 return 266;
301 case CLKCFG_FSB_1333:
302 return 333;
303 /* these two are just a guess; one of them might be right */
304 case CLKCFG_FSB_1600:
305 case CLKCFG_FSB_1600_ALT:
306 return 400;
307 default:
308 return 133;
309 }
310}
311
ebf33b18
KP		 312static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
313{
314 struct drm_device *dev = intel_dp->base.base.dev;
315 struct drm_i915_private *dev_priv = dev->dev_private;
316
317 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
318}
319
320static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
321{
322 struct drm_device *dev = intel_dp->base.base.dev;
323 struct drm_i915_private *dev_priv = dev->dev_private;
324
325 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
326}
327
9b984dae
KP		 328static void
329intel_dp_check_edp(struct intel_dp *intel_dp)
330{
331 struct drm_device *dev = intel_dp->base.base.dev;
332 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 333
9b984dae
KP		 334 if (!is_edp(intel_dp))
335 return;
ebf33b18 336 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 337 WARN(1, "eDP powered off while attempting aux channel communication.\n");
338 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
ebf33b18 339 I915_READ(PCH_PP_STATUS),
9b984dae
KP		 340 I915_READ(PCH_PP_CONTROL));
341 }
342}
343
a4fc5ed6 344static int
ea5b213a 345intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 346 uint8_t *send, int send_bytes,
347 uint8_t *recv, int recv_size)
348{
ea5b213a 349 uint32_t output_reg = intel_dp->output_reg;
4ef69c7a 350 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 351 struct drm_i915_private *dev_priv = dev->dev_private;
352 uint32_t ch_ctl = output_reg + 0x10;
353 uint32_t ch_data = ch_ctl + 4;
354 int i;
355 int recv_bytes;
a4fc5ed6 356 uint32_t status;
fb0f8fbf 357 uint32_t aux_clock_divider;
6b4e0a93 358 int try, precharge;
a4fc5ed6 359
9b984dae 360 intel_dp_check_edp(intel_dp);
a4fc5ed6 361 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 362 * and would like to run at 2MHz. So, take the
363 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 364 *
365 * Note that PCH attached eDP panels should use a 125MHz input
366 * clock divider.
a4fc5ed6 367 */
1c95822a 368 if (is_cpu_edp(intel_dp)) {
1a2eb460
KP		 369 if (IS_GEN6(dev) || IS_GEN7(dev))
370 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 371 else
372 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
373 } else if (HAS_PCH_SPLIT(dev))
6919132e 374 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
5eb08b69
ZW		 375 else
376 aux_clock_divider = intel_hrawclk(dev) / 2;
377
6b4e0a93
DV		 378 if (IS_GEN6(dev))
379 precharge = 3;
380 else
381 precharge = 5;
382
11bee43e
JB		 383 /* Try to wait for any previous AUX channel activity */
384 for (try = 0; try < 3; try++) {
385 status = I915_READ(ch_ctl);
386 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
387 break;
388 msleep(1);
389 }
390
391 if (try == 3) {
392 WARN(1, "dp_aux_ch not started status 0x%08x\n",
393 I915_READ(ch_ctl));
4f7f7b7e
CW		 394 return -EBUSY;
395 }
396
fb0f8fbf
KP		 397 /* Must try at least 3 times according to DP spec */
398 for (try = 0; try < 5; try++) {
399 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 400 for (i = 0; i < send_bytes; i += 4)
401 I915_WRITE(ch_data + i,
402 pack_aux(send + i, send_bytes - i));
0206e353 403
fb0f8fbf 404 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 405 I915_WRITE(ch_ctl,
406 DP_AUX_CH_CTL_SEND_BUSY |
407 DP_AUX_CH_CTL_TIME_OUT_400us |
408 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
409 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
410 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
411 DP_AUX_CH_CTL_DONE |
412 DP_AUX_CH_CTL_TIME_OUT_ERROR |
413 DP_AUX_CH_CTL_RECEIVE_ERROR);
fb0f8fbf 414 for (;;) {
fb0f8fbf
KP		 415 status = I915_READ(ch_ctl);
416 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
417 break;
4f7f7b7e 418 udelay(100);
fb0f8fbf 419 }
0206e353 420
fb0f8fbf 421 /* Clear done status and any errors */
4f7f7b7e
CW		 422 I915_WRITE(ch_ctl,
423 status |
424 DP_AUX_CH_CTL_DONE |
425 DP_AUX_CH_CTL_TIME_OUT_ERROR |
426 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 427
428 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
429 DP_AUX_CH_CTL_RECEIVE_ERROR))
430 continue;
4f7f7b7e 431 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 432 break;
433 }
434
a4fc5ed6 435 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 436 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
a5b3da54 437 return -EBUSY;
a4fc5ed6
KP		 438 }
439
440 /* Check for timeout or receive error.
441 * Timeouts occur when the sink is not connected
442 */
a5b3da54 443 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 444 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
a5b3da54
KP		 445 return -EIO;
446 }
1ae8c0a5
KP		 447
448 /* Timeouts occur when the device isn't connected, so they're
449 * "normal" -- don't fill the kernel log with these */
a5b3da54 450 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 451 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
a5b3da54 452 return -ETIMEDOUT;
a4fc5ed6
KP		 453 }
454
455 /* Unload any bytes sent back from the other side */
456 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
457 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 458 if (recv_bytes > recv_size)
459 recv_bytes = recv_size;
0206e353 460
4f7f7b7e
CW		 461 for (i = 0; i < recv_bytes; i += 4)
462 unpack_aux(I915_READ(ch_data + i),
463 recv + i, recv_bytes - i);
a4fc5ed6
KP		 464
465 return recv_bytes;
466}
467
468/* Write data to the aux channel in native mode */
469static int
ea5b213a 470intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 471 uint16_t address, uint8_t *send, int send_bytes)
472{
473 int ret;
474 uint8_t msg[20];
475 int msg_bytes;
476 uint8_t ack;
477
9b984dae 478 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 479 if (send_bytes > 16)
480 return -1;
481 msg[0] = AUX_NATIVE_WRITE << 4;
482 msg[1] = address >> 8;
eebc863e 483 msg[2] = address & 0xff;
a4fc5ed6
KP		 484 msg[3] = send_bytes - 1;
485 memcpy(&msg[4], send, send_bytes);
486 msg_bytes = send_bytes + 4;
487 for (;;) {
ea5b213a 488 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 489 if (ret < 0)
490 return ret;
491 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
492 break;
493 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
494 udelay(100);
495 else
a5b3da54 496 return -EIO;
a4fc5ed6
KP		 497 }
498 return send_bytes;
499}
500
501/* Write a single byte to the aux channel in native mode */
502static int
ea5b213a 503intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 504 uint16_t address, uint8_t byte)
505{
ea5b213a 506 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 507}
508
509/* read bytes from a native aux channel */
510static int
ea5b213a 511intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 512 uint16_t address, uint8_t *recv, int recv_bytes)
513{
514 uint8_t msg[4];
515 int msg_bytes;
516 uint8_t reply[20];
517 int reply_bytes;
518 uint8_t ack;
519 int ret;
520
9b984dae 521 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 522 msg[0] = AUX_NATIVE_READ << 4;
523 msg[1] = address >> 8;
524 msg[2] = address & 0xff;
525 msg[3] = recv_bytes - 1;
526
527 msg_bytes = 4;
528 reply_bytes = recv_bytes + 1;
529
530 for (;;) {
ea5b213a 531 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 532 reply, reply_bytes);
a5b3da54
KP		 533 if (ret == 0)
534 return -EPROTO;
535 if (ret < 0)
a4fc5ed6
KP		 536 return ret;
537 ack = reply[0];
538 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
539 memcpy(recv, reply + 1, ret - 1);
540 return ret - 1;
541 }
542 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
543 udelay(100);
544 else
a5b3da54 545 return -EIO;
a4fc5ed6
KP		 546 }
547}
548
549static int
ab2c0672
DA		 550intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
551 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 552{
ab2c0672 553 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 554 struct intel_dp *intel_dp = container_of(adapter,
555 struct intel_dp,
556 adapter);
ab2c0672
DA		 557 uint16_t address = algo_data->address;
558 uint8_t msg[5];
559 uint8_t reply[2];
8316f337 560 unsigned retry;
ab2c0672
DA		 561 int msg_bytes;
562 int reply_bytes;
563 int ret;
564
9b984dae 565 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 566 /* Set up the command byte */
567 if (mode & MODE_I2C_READ)
568 msg[0] = AUX_I2C_READ << 4;
569 else
570 msg[0] = AUX_I2C_WRITE << 4;
571
572 if (!(mode & MODE_I2C_STOP))
573 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 574
ab2c0672
DA		 575 msg[1] = address >> 8;
576 msg[2] = address;
577
578 switch (mode) {
579 case MODE_I2C_WRITE:
580 msg[3] = 0;
581 msg[4] = write_byte;
582 msg_bytes = 5;
583 reply_bytes = 1;
584 break;
585 case MODE_I2C_READ:
586 msg[3] = 0;
587 msg_bytes = 4;
588 reply_bytes = 2;
589 break;
590 default:
591 msg_bytes = 3;
592 reply_bytes = 1;
593 break;
594 }
595
8316f337
DF		 596 for (retry = 0; retry < 5; retry++) {
597 ret = intel_dp_aux_ch(intel_dp,
598 msg, msg_bytes,
599 reply, reply_bytes);
ab2c0672 600 if (ret < 0) {
3ff99164 601 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 602 return ret;
603 }
8316f337
DF		 604
605 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
606 case AUX_NATIVE_REPLY_ACK:
607 /* I2C-over-AUX Reply field is only valid
608 * when paired with AUX ACK.
609 */
610 break;
611 case AUX_NATIVE_REPLY_NACK:
612 DRM_DEBUG_KMS("aux_ch native nack\n");
613 return -EREMOTEIO;
614 case AUX_NATIVE_REPLY_DEFER:
615 udelay(100);
616 continue;
617 default:
618 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
619 reply[0]);
620 return -EREMOTEIO;
621 }
622
ab2c0672
DA		 623 switch (reply[0] & AUX_I2C_REPLY_MASK) {
624 case AUX_I2C_REPLY_ACK:
625 if (mode == MODE_I2C_READ) {
626 *read_byte = reply[1];
627 }
628 return reply_bytes - 1;
629 case AUX_I2C_REPLY_NACK:
8316f337 630 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 631 return -EREMOTEIO;
632 case AUX_I2C_REPLY_DEFER:
8316f337 633 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 634 udelay(100);
635 break;
636 default:
8316f337 637 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 638 return -EREMOTEIO;
639 }
640 }
8316f337
DF		 641
642 DRM_ERROR("too many retries, giving up\n");
643 return -EREMOTEIO;
a4fc5ed6
KP		 644}
645
0b5c541b 646static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
bd943159 647static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
0b5c541b 648
a4fc5ed6 649static int
ea5b213a 650intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 651 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 652{
0b5c541b
KP		 653 int ret;
654
d54e9d28 655 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 656 intel_dp->algo.running = false;
657 intel_dp->algo.address = 0;
658 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
659
0206e353 660 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 661 intel_dp->adapter.owner = THIS_MODULE;
662 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 663 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 664 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
665 intel_dp->adapter.algo_data = &intel_dp->algo;
666 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
667
0b5c541b
KP		 668 ironlake_edp_panel_vdd_on(intel_dp);
669 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 670 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 671 return ret;
a4fc5ed6
KP		 672}
673
674static bool
e811f5ae
LP		 675intel_dp_mode_fixup(struct drm_encoder *encoder,
676 const struct drm_display_mode *mode,
a4fc5ed6
KP		 677 struct drm_display_mode *adjusted_mode)
678{
0d3a1bee 679 struct drm_device *dev = encoder->dev;
ea5b213a 680 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
a4fc5ed6 681 int lane_count, clock;
ea5b213a
CW		 682 int max_lane_count = intel_dp_max_lane_count(intel_dp);
683 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 684 int bpp, mode_rate;
a4fc5ed6
KP		 685 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
686
d15456de
KP		 687 if (is_edp(intel_dp) && intel_dp->panel_fixed_mode) {
688 intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
1d8e1c75
CW		 689 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
690 mode, adjusted_mode);
0d3a1bee
ZY		 691 }
692
cb1793ce 693 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 694 return false;
695
083f9560
DV		 696 DRM_DEBUG_KMS("DP link computation with max lane count %i "
697 "max bw %02x pixel clock %iKHz\n",
71244653 698 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 699
cb1793ce 700 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
c4867936
DV		 701 return false;
702
703 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
71244653 704 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
c4867936 705
2514bc51
JB		 706 for (clock = 0; clock <= max_clock; clock++) {
707 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
fe27d53e 708 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
a4fc5ed6 709
083f9560 710 if (mode_rate <= link_avail) {
ea5b213a
CW		 711 intel_dp->link_bw = bws[clock];
712 intel_dp->lane_count = lane_count;
713 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
083f9560
DV		 714 DRM_DEBUG_KMS("DP link bw %02x lane "
715 "count %d clock %d bpp %d\n",
ea5b213a 716 intel_dp->link_bw, intel_dp->lane_count,
083f9560
DV		 717 adjusted_mode->clock, bpp);
718 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
719 mode_rate, link_avail);
a4fc5ed6
KP		 720 return true;
721 }
722 }
723 }
fe27d53e 724
a4fc5ed6
KP		 725 return false;
726}
727
728struct intel_dp_m_n {
729 uint32_t tu;
730 uint32_t gmch_m;
731 uint32_t gmch_n;
732 uint32_t link_m;
733 uint32_t link_n;
734};
735
736static void
737intel_reduce_ratio(uint32_t *num, uint32_t *den)
738{
739 while (*num > 0xffffff || *den > 0xffffff) {
740 *num >>= 1;
741 *den >>= 1;
742 }
743}
744
745static void
36e83a18 746intel_dp_compute_m_n(int bpp,
a4fc5ed6
KP		 747 int nlanes,
748 int pixel_clock,
749 int link_clock,
750 struct intel_dp_m_n *m_n)
751{
752 m_n->tu = 64;
36e83a18 753 m_n->gmch_m = (pixel_clock * bpp) >> 3;
a4fc5ed6
KP		 754 m_n->gmch_n = link_clock * nlanes;
755 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
756 m_n->link_m = pixel_clock;
757 m_n->link_n = link_clock;
758 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
759}
760
761void
762intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
763 struct drm_display_mode *adjusted_mode)
764{
765 struct drm_device *dev = crtc->dev;
6c2b7c12 766 struct intel_encoder *encoder;
a4fc5ed6
KP		 767 struct drm_i915_private *dev_priv = dev->dev_private;
768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
858fa035 769 int lane_count = 4;
a4fc5ed6 770 struct intel_dp_m_n m_n;
9db4a9c7 771 int pipe = intel_crtc->pipe;
a4fc5ed6
KP		 772
773 /*
21d40d37 774 * Find the lane count in the intel_encoder private
a4fc5ed6 775 */
6c2b7c12
DV		 776 for_each_encoder_on_crtc(dev, crtc, encoder) {
777 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
a4fc5ed6 778
9a10f401
KP		 779 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
780 intel_dp->base.type == INTEL_OUTPUT_EDP)
781 {
ea5b213a 782 lane_count = intel_dp->lane_count;
51190667 783 break;
a4fc5ed6
KP		 784 }
785 }
786
787 /*
788 * Compute the GMCH and Link ratios. The '3' here is
789 * the number of bytes_per_pixel post-LUT, which we always
790 * set up for 8-bits of R/G/B, or 3 bytes total.
791 */
858fa035 792 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
a4fc5ed6
KP		 793 mode->clock, adjusted_mode->clock, &m_n);
794
c619eed4 795 if (HAS_PCH_SPLIT(dev)) {
9db4a9c7
JB		 796 I915_WRITE(TRANSDATA_M1(pipe),
797 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
798 m_n.gmch_m);
799 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
800 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
801 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
a4fc5ed6 802 } else {
9db4a9c7
JB		 803 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
804 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
805 m_n.gmch_m);
806 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
807 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
808 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
a4fc5ed6
KP		 809 }
810}
811
812static void
813intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
814 struct drm_display_mode *adjusted_mode)
815{
e3421a18 816 struct drm_device *dev = encoder->dev;
417e822d 817 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 818 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4ef69c7a 819 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a4fc5ed6
KP		 820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
821
417e822d 822 /*
1a2eb460 823 * There are four kinds of DP registers:
417e822d
KP		 824 *
825 * IBX PCH
1a2eb460
KP		 826 * SNB CPU
827 * IVB CPU
417e822d
KP		 828 * CPT PCH
829 *
830 * IBX PCH and CPU are the same for almost everything,
831 * except that the CPU DP PLL is configured in this
832 * register
833 *
834 * CPT PCH is quite different, having many bits moved
835 * to the TRANS_DP_CTL register instead. That
836 * configuration happens (oddly) in ironlake_pch_enable
837 */
9c9e7927 838
417e822d
KP		 839 /* Preserve the BIOS-computed detected bit. This is
840 * supposed to be read-only.
841 */
842 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 843
417e822d 844 /* Handle DP bits in common between all three register formats */
417e822d 845 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 846
ea5b213a 847 switch (intel_dp->lane_count) {
a4fc5ed6 848 case 1:
ea5b213a 849 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 850 break;
851 case 2:
ea5b213a 852 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 853 break;
854 case 4:
ea5b213a 855 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 856 break;
857 }
e0dac65e
WF		 858 if (intel_dp->has_audio) {
859 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
860 pipe_name(intel_crtc->pipe));
ea5b213a 861 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 862 intel_write_eld(encoder, adjusted_mode);
863 }
ea5b213a
CW		 864 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
865 intel_dp->link_configuration[0] = intel_dp->link_bw;
866 intel_dp->link_configuration[1] = intel_dp->lane_count;
a2cab1b2 867 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
a4fc5ed6 868 /*
9962c925 869 * Check for DPCD version > 1.1 and enhanced framing support
a4fc5ed6 870 */
7183dc29
JB		 871 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
872 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
ea5b213a 873 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
a4fc5ed6
KP		 874 }
875
417e822d 876 /* Split out the IBX/CPU vs CPT settings */
32f9d658 877
1a2eb460
KP		 878 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
879 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
880 intel_dp->DP |= DP_SYNC_HS_HIGH;
881 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
882 intel_dp->DP |= DP_SYNC_VS_HIGH;
883 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
884
885 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
886 intel_dp->DP |= DP_ENHANCED_FRAMING;
887
888 intel_dp->DP |= intel_crtc->pipe << 29;
889
890 /* don't miss out required setting for eDP */
1a2eb460
KP		 891 if (adjusted_mode->clock < 200000)
892 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
893 else
894 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
895 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
417e822d
KP		 896 intel_dp->DP |= intel_dp->color_range;
897
898 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
899 intel_dp->DP |= DP_SYNC_HS_HIGH;
900 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
901 intel_dp->DP |= DP_SYNC_VS_HIGH;
902 intel_dp->DP |= DP_LINK_TRAIN_OFF;
903
904 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
905 intel_dp->DP |= DP_ENHANCED_FRAMING;
906
907 if (intel_crtc->pipe == 1)
908 intel_dp->DP |= DP_PIPEB_SELECT;
909
910 if (is_cpu_edp(intel_dp)) {
911 /* don't miss out required setting for eDP */
417e822d
KP		 912 if (adjusted_mode->clock < 200000)
913 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
914 else
915 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
916 }
917 } else {
918 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 919 }
a4fc5ed6
KP		 920}
921
99ea7127
KP		 922#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
923#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
924
925#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
926#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
927
928#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
929#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
930
931static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
932 u32 mask,
933 u32 value)
bd943159 934{
99ea7127
KP		 935 struct drm_device *dev = intel_dp->base.base.dev;
936 struct drm_i915_private *dev_priv = dev->dev_private;
32ce697c 937
99ea7127
KP		 938 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
939 mask, value,
940 I915_READ(PCH_PP_STATUS),
941 I915_READ(PCH_PP_CONTROL));
32ce697c 942
99ea7127
KP		 943 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
944 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
945 I915_READ(PCH_PP_STATUS),
946 I915_READ(PCH_PP_CONTROL));
32ce697c 947 }
99ea7127 948}
32ce697c 949
99ea7127
KP		 950static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
951{
952 DRM_DEBUG_KMS("Wait for panel power on\n");
953 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 954}
955
99ea7127
KP		 956static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
957{
958 DRM_DEBUG_KMS("Wait for panel power off time\n");
959 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
960}
961
962static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
963{
964 DRM_DEBUG_KMS("Wait for panel power cycle\n");
965 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
966}
967
968
832dd3c1
KP		 969/* Read the current pp_control value, unlocking the register if it
970 * is locked
971 */
972
973static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
974{
975 u32 control = I915_READ(PCH_PP_CONTROL);
976
977 control &= ~PANEL_UNLOCK_MASK;
978 control |= PANEL_UNLOCK_REGS;
979 return control;
bd943159
KP		 980}
981
5d613501
JB		 982static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
983{
984 struct drm_device *dev = intel_dp->base.base.dev;
985 struct drm_i915_private *dev_priv = dev->dev_private;
986 u32 pp;
987
97af61f5
KP		 988 if (!is_edp(intel_dp))
989 return;
f01eca2e 990 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 991
bd943159
KP		 992 WARN(intel_dp->want_panel_vdd,
993 "eDP VDD already requested on\n");
994
995 intel_dp->want_panel_vdd = true;
99ea7127 996
bd943159
KP		 997 if (ironlake_edp_have_panel_vdd(intel_dp)) {
998 DRM_DEBUG_KMS("eDP VDD already on\n");
999 return;
1000 }
1001
99ea7127
KP		 1002 if (!ironlake_edp_have_panel_power(intel_dp))
1003 ironlake_wait_panel_power_cycle(intel_dp);
1004
832dd3c1 1005 pp = ironlake_get_pp_control(dev_priv);
5d613501
JB		 1006 pp |= EDP_FORCE_VDD;
1007 I915_WRITE(PCH_PP_CONTROL, pp);
1008 POSTING_READ(PCH_PP_CONTROL);
f01eca2e
KP		 1009 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1010 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
ebf33b18
KP		 1011
1012 /*
1013 * If the panel wasn't on, delay before accessing aux channel
1014 */
1015 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1016 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1017 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1018 }
5d613501
JB		 1019}
1020
bd943159 1021static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501
JB		 1022{
1023 struct drm_device *dev = intel_dp->base.base.dev;
1024 struct drm_i915_private *dev_priv = dev->dev_private;
1025 u32 pp;
1026
bd943159 1027 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
832dd3c1 1028 pp = ironlake_get_pp_control(dev_priv);
bd943159
KP		 1029 pp &= ~EDP_FORCE_VDD;
1030 I915_WRITE(PCH_PP_CONTROL, pp);
1031 POSTING_READ(PCH_PP_CONTROL);
1032
1033 /* Make sure sequencer is idle before allowing subsequent activity */
1034 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1035 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
99ea7127
KP		 1036
1037 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1038 }
1039}
5d613501 1040
bd943159
KP		 1041static void ironlake_panel_vdd_work(struct work_struct *__work)
1042{
1043 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1044 struct intel_dp, panel_vdd_work);
1045 struct drm_device *dev = intel_dp->base.base.dev;
1046
627f7675 1047 mutex_lock(&dev->mode_config.mutex);
bd943159 1048 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1049 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1050}
1051
1052static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1053{
97af61f5
KP		 1054 if (!is_edp(intel_dp))
1055 return;
5d613501 1056
bd943159
KP		 1057 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1058 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1059
bd943159
KP		 1060 intel_dp->want_panel_vdd = false;
1061
1062 if (sync) {
1063 ironlake_panel_vdd_off_sync(intel_dp);
1064 } else {
1065 /*
1066 * Queue the timer to fire a long
1067 * time from now (relative to the power down delay)
1068 * to keep the panel power up across a sequence of operations
1069 */
1070 schedule_delayed_work(&intel_dp->panel_vdd_work,
1071 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1072 }
5d613501
JB		 1073}
1074
86a3073e 1075static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1076{
01cb9ea6 1077 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1078 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1079 u32 pp;
9934c132 1080
97af61f5 1081 if (!is_edp(intel_dp))
bd943159 1082 return;
99ea7127
KP		 1083
1084 DRM_DEBUG_KMS("Turn eDP power on\n");
1085
1086 if (ironlake_edp_have_panel_power(intel_dp)) {
1087 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1088 return;
99ea7127 1089 }
9934c132 1090
99ea7127 1091 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1092
99ea7127 1093 pp = ironlake_get_pp_control(dev_priv);
05ce1a49
KP		 1094 if (IS_GEN5(dev)) {
1095 /* ILK workaround: disable reset around power sequence */
1096 pp &= ~PANEL_POWER_RESET;
1097 I915_WRITE(PCH_PP_CONTROL, pp);
1098 POSTING_READ(PCH_PP_CONTROL);
1099 }
37c6c9b0 1100
1c0ae80a 1101 pp |= POWER_TARGET_ON;
99ea7127
KP		 1102 if (!IS_GEN5(dev))
1103 pp |= PANEL_POWER_RESET;
1104
9934c132 1105 I915_WRITE(PCH_PP_CONTROL, pp);
01cb9ea6 1106 POSTING_READ(PCH_PP_CONTROL);
9934c132 1107
99ea7127 1108 ironlake_wait_panel_on(intel_dp);
9934c132 1109
05ce1a49
KP		 1110 if (IS_GEN5(dev)) {
1111 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1112 I915_WRITE(PCH_PP_CONTROL, pp);
1113 POSTING_READ(PCH_PP_CONTROL);
1114 }
9934c132
JB		 1115}
1116
99ea7127 1117static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1118{
99ea7127 1119 struct drm_device *dev = intel_dp->base.base.dev;
9934c132 1120 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1121 u32 pp;
9934c132 1122
97af61f5
KP		 1123 if (!is_edp(intel_dp))
1124 return;
37c6c9b0 1125
99ea7127 1126 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1127
6cb49835 1128 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1129
99ea7127 1130 pp = ironlake_get_pp_control(dev_priv);
35a38556
DV		 1131 /* We need to switch off panel power _and_ force vdd, for otherwise some
1132 * panels get very unhappy and cease to work. */
1133 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
99ea7127
KP		 1134 I915_WRITE(PCH_PP_CONTROL, pp);
1135 POSTING_READ(PCH_PP_CONTROL);
9934c132 1136
35a38556
DV		 1137 intel_dp->want_panel_vdd = false;
1138
99ea7127 1139 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1140}
1141
86a3073e 1142static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1143{
f01eca2e 1144 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1145 struct drm_i915_private *dev_priv = dev->dev_private;
1146 u32 pp;
1147
f01eca2e
KP		 1148 if (!is_edp(intel_dp))
1149 return;
1150
28c97730 1151 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1152 /*
1153 * If we enable the backlight right away following a panel power
1154 * on, we may see slight flicker as the panel syncs with the eDP
1155 * link. So delay a bit to make sure the image is solid before
1156 * allowing it to appear.
1157 */
f01eca2e 1158 msleep(intel_dp->backlight_on_delay);
832dd3c1 1159 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1160 pp |= EDP_BLC_ENABLE;
1161 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e 1162 POSTING_READ(PCH_PP_CONTROL);
32f9d658
ZW		 1163}
1164
86a3073e 1165static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1166{
f01eca2e 1167 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 1168 struct drm_i915_private *dev_priv = dev->dev_private;
1169 u32 pp;
1170
f01eca2e
KP		 1171 if (!is_edp(intel_dp))
1172 return;
1173
28c97730 1174 DRM_DEBUG_KMS("\n");
832dd3c1 1175 pp = ironlake_get_pp_control(dev_priv);
32f9d658
ZW		 1176 pp &= ~EDP_BLC_ENABLE;
1177 I915_WRITE(PCH_PP_CONTROL, pp);
f01eca2e
KP		 1178 POSTING_READ(PCH_PP_CONTROL);
1179 msleep(intel_dp->backlight_off_delay);
32f9d658 1180}
a4fc5ed6 1181
2bd2ad64 1182static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1183{
2bd2ad64
DV		 1184 struct drm_device *dev = intel_dp->base.base.dev;
1185 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1186 struct drm_i915_private *dev_priv = dev->dev_private;
1187 u32 dpa_ctl;
1188
2bd2ad64
DV		 1189 assert_pipe_disabled(dev_priv,
1190 to_intel_crtc(crtc)->pipe);
1191
d240f20f
JB		 1192 DRM_DEBUG_KMS("\n");
1193 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1194 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1195 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1196
1197 /* We don't adjust intel_dp->DP while tearing down the link, to
1198 * facilitate link retraining (e.g. after hotplug). Hence clear all
1199 * enable bits here to ensure that we don't enable too much. */
1200 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1201 intel_dp->DP |= DP_PLL_ENABLE;
1202 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1203 POSTING_READ(DP_A);
1204 udelay(200);
d240f20f
JB		 1205}
1206
2bd2ad64 1207static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1208{
2bd2ad64
DV		 1209 struct drm_device *dev = intel_dp->base.base.dev;
1210 struct drm_crtc *crtc = intel_dp->base.base.crtc;
d240f20f
JB		 1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212 u32 dpa_ctl;
1213
2bd2ad64
DV		 1214 assert_pipe_disabled(dev_priv,
1215 to_intel_crtc(crtc)->pipe);
1216
d240f20f 1217 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1218 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1219 "dp pll off, should be on\n");
1220 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1221
1222 /* We can't rely on the value tracked for the DP register in
1223 * intel_dp->DP because link_down must not change that (otherwise link
1224 * re-training will fail. */
298b0b39 1225 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1226 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1227 POSTING_READ(DP_A);
d240f20f
JB		 1228 udelay(200);
1229}
1230
c7ad3810
JB		 1231/* If the sink supports it, try to set the power state appropriately */
1232static void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1233{
1234 int ret, i;
1235
1236 /* Should have a valid DPCD by this point */
1237 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1238 return;
1239
1240 if (mode != DRM_MODE_DPMS_ON) {
1241 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1242 DP_SET_POWER_D3);
1243 if (ret != 1)
1244 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1245 } else {
1246 /*
1247 * When turning on, we need to retry for 1ms to give the sink
1248 * time to wake up.
1249 */
1250 for (i = 0; i < 3; i++) {
1251 ret = intel_dp_aux_native_write_1(intel_dp,
1252 DP_SET_POWER,
1253 DP_SET_POWER_D0);
1254 if (ret == 1)
1255 break;
1256 msleep(1);
1257 }
1258 }
1259}
1260
19d8fe15
DV		 1261static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1262 enum pipe *pipe)
d240f20f 1263{
19d8fe15
DV		 1264 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1265 struct drm_device *dev = encoder->base.dev;
1266 struct drm_i915_private *dev_priv = dev->dev_private;
1267 u32 tmp = I915_READ(intel_dp->output_reg);
1268
1269 if (!(tmp & DP_PORT_EN))
1270 return false;
1271
1272 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1273 *pipe = PORT_TO_PIPE_CPT(tmp);
1274 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1275 *pipe = PORT_TO_PIPE(tmp);
1276 } else {
1277 u32 trans_sel;
1278 u32 trans_dp;
1279 int i;
1280
1281 switch (intel_dp->output_reg) {
1282 case PCH_DP_B:
1283 trans_sel = TRANS_DP_PORT_SEL_B;
1284 break;
1285 case PCH_DP_C:
1286 trans_sel = TRANS_DP_PORT_SEL_C;
1287 break;
1288 case PCH_DP_D:
1289 trans_sel = TRANS_DP_PORT_SEL_D;
1290 break;
1291 default:
1292 return true;
1293 }
1294
1295 for_each_pipe(i) {
1296 trans_dp = I915_READ(TRANS_DP_CTL(i));
1297 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1298 *pipe = i;
1299 return true;
1300 }
1301 }
1302 }
1303
1304 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
d240f20f 1305
19d8fe15
DV		 1306 return true;
1307}
1308
e8cb4558 1309static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1310{
e8cb4558 1311 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1312
1313 /* Make sure the panel is off before trying to change the mode. But also
1314 * ensure that we have vdd while we switch off the panel. */
1315 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1316 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1317 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1318 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1319
1320 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1321 if (!is_cpu_edp(intel_dp))
1322 intel_dp_link_down(intel_dp);
d240f20f
JB		 1323}
1324
2bd2ad64
DV		 1325static void intel_post_disable_dp(struct intel_encoder *encoder)
1326{
1327 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1328
3739850b
DV		 1329 if (is_cpu_edp(intel_dp)) {
1330 intel_dp_link_down(intel_dp);
2bd2ad64 1331 ironlake_edp_pll_off(intel_dp);
3739850b 1332 }
2bd2ad64
DV		 1333}
1334
e8cb4558 1335static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1336{
e8cb4558
DV		 1337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1338 struct drm_device *dev = encoder->base.dev;
1339 struct drm_i915_private *dev_priv = dev->dev_private;
1340 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1341
0c33d8d7
DV		 1342 if (WARN_ON(dp_reg & DP_PORT_EN))
1343 return;
1344
97af61f5 1345 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1346 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
0c33d8d7
DV		 1347 intel_dp_start_link_train(intel_dp);
1348 ironlake_edp_panel_on(intel_dp);
1349 ironlake_edp_panel_vdd_off(intel_dp, true);
1350 intel_dp_complete_link_train(intel_dp);
f01eca2e 1351 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1352}
1353
2bd2ad64 1354static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1355{
2bd2ad64 1356 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
0a91ca29 1357
2bd2ad64
DV		 1358 if (is_cpu_edp(intel_dp))
1359 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1360}
1361
1362/*
df0c237d
JB		 1363 * Native read with retry for link status and receiver capability reads for
1364 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1365 */
1366static bool
df0c237d
JB		 1367intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1368 uint8_t *recv, int recv_bytes)
a4fc5ed6 1369{
61da5fab
JB		 1370 int ret, i;
1371
df0c237d
JB		 1372 /*
1373 * Sinks are *supposed* to come up within 1ms from an off state,
1374 * but we're also supposed to retry 3 times per the spec.
1375 */
61da5fab 1376 for (i = 0; i < 3; i++) {
df0c237d
JB		 1377 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1378 recv_bytes);
1379 if (ret == recv_bytes)
61da5fab
JB		 1380 return true;
1381 msleep(1);
1382 }
a4fc5ed6 1383
61da5fab 1384 return false;
a4fc5ed6
KP		 1385}
1386
1387/*
1388 * Fetch AUX CH registers 0x202 - 0x207 which contain
1389 * link status information
1390 */
1391static bool
93f62dad 1392intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1393{
df0c237d
JB		 1394 return intel_dp_aux_native_read_retry(intel_dp,
1395 DP_LANE0_1_STATUS,
93f62dad 1396 link_status,
df0c237d 1397 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1398}
1399
1400static uint8_t
1401intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1402 int r)
1403{
1404 return link_status[r - DP_LANE0_1_STATUS];
1405}
1406
a4fc5ed6 1407static uint8_t
93f62dad 1408intel_get_adjust_request_voltage(uint8_t adjust_request[2],
a4fc5ed6
KP		 1409 int lane)
1410{
a4fc5ed6
KP		 1411 int s = ((lane & 1) ?
1412 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1413 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
93f62dad 1414 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1415
1416 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1417}
1418
1419static uint8_t
93f62dad 1420intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
a4fc5ed6
KP		 1421 int lane)
1422{
a4fc5ed6
KP		 1423 int s = ((lane & 1) ?
1424 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1425 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
93f62dad 1426 uint8_t l = adjust_request[lane>>1];
a4fc5ed6
KP		 1427
1428 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1429}
1430
1431
1432#if 0
1433static char *voltage_names[] = {
1434 "0.4V", "0.6V", "0.8V", "1.2V"
1435};
1436static char *pre_emph_names[] = {
1437 "0dB", "3.5dB", "6dB", "9.5dB"
1438};
1439static char *link_train_names[] = {
1440 "pattern 1", "pattern 2", "idle", "off"
1441};
1442#endif
1443
1444/*
1445 * These are source-specific values; current Intel hardware supports
1446 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1447 */
a4fc5ed6
KP		 1448
1449static uint8_t
1a2eb460 1450intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1451{
1a2eb460
KP		 1452 struct drm_device *dev = intel_dp->base.base.dev;
1453
1454 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1455 return DP_TRAIN_VOLTAGE_SWING_800;
1456 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1457 return DP_TRAIN_VOLTAGE_SWING_1200;
1458 else
1459 return DP_TRAIN_VOLTAGE_SWING_800;
1460}
1461
1462static uint8_t
1463intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1464{
1465 struct drm_device *dev = intel_dp->base.base.dev;
1466
1467 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1468 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1469 case DP_TRAIN_VOLTAGE_SWING_400:
1470 return DP_TRAIN_PRE_EMPHASIS_6;
1471 case DP_TRAIN_VOLTAGE_SWING_600:
1472 case DP_TRAIN_VOLTAGE_SWING_800:
1473 return DP_TRAIN_PRE_EMPHASIS_3_5;
1474 default:
1475 return DP_TRAIN_PRE_EMPHASIS_0;
1476 }
1477 } else {
1478 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1479 case DP_TRAIN_VOLTAGE_SWING_400:
1480 return DP_TRAIN_PRE_EMPHASIS_6;
1481 case DP_TRAIN_VOLTAGE_SWING_600:
1482 return DP_TRAIN_PRE_EMPHASIS_6;
1483 case DP_TRAIN_VOLTAGE_SWING_800:
1484 return DP_TRAIN_PRE_EMPHASIS_3_5;
1485 case DP_TRAIN_VOLTAGE_SWING_1200:
1486 default:
1487 return DP_TRAIN_PRE_EMPHASIS_0;
1488 }
a4fc5ed6
KP		 1489 }
1490}
1491
1492static void
93f62dad 1493intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1494{
1495 uint8_t v = 0;
1496 uint8_t p = 0;
1497 int lane;
93f62dad 1498 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1a2eb460
KP		 1499 uint8_t voltage_max;
1500 uint8_t preemph_max;
a4fc5ed6 1501
33a34e4e 1502 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad
KP		 1503 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1504 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
a4fc5ed6
KP		 1505
1506 if (this_v > v)
1507 v = this_v;
1508 if (this_p > p)
1509 p = this_p;
1510 }
1511
1a2eb460 1512 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1513 if (v >= voltage_max)
1514 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1515
1a2eb460
KP		 1516 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1517 if (p >= preemph_max)
1518 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1519
1520 for (lane = 0; lane < 4; lane++)
33a34e4e 1521 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1522}
1523
1524static uint32_t
93f62dad 1525intel_dp_signal_levels(uint8_t train_set)
a4fc5ed6 1526{
3cf2efb1 1527 uint32_t signal_levels = 0;
a4fc5ed6 1528
3cf2efb1 1529 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1530 case DP_TRAIN_VOLTAGE_SWING_400:
1531 default:
1532 signal_levels |= DP_VOLTAGE_0_4;
1533 break;
1534 case DP_TRAIN_VOLTAGE_SWING_600:
1535 signal_levels |= DP_VOLTAGE_0_6;
1536 break;
1537 case DP_TRAIN_VOLTAGE_SWING_800:
1538 signal_levels |= DP_VOLTAGE_0_8;
1539 break;
1540 case DP_TRAIN_VOLTAGE_SWING_1200:
1541 signal_levels |= DP_VOLTAGE_1_2;
1542 break;
1543 }
3cf2efb1 1544 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1545 case DP_TRAIN_PRE_EMPHASIS_0:
1546 default:
1547 signal_levels |= DP_PRE_EMPHASIS_0;
1548 break;
1549 case DP_TRAIN_PRE_EMPHASIS_3_5:
1550 signal_levels |= DP_PRE_EMPHASIS_3_5;
1551 break;
1552 case DP_TRAIN_PRE_EMPHASIS_6:
1553 signal_levels |= DP_PRE_EMPHASIS_6;
1554 break;
1555 case DP_TRAIN_PRE_EMPHASIS_9_5:
1556 signal_levels |= DP_PRE_EMPHASIS_9_5;
1557 break;
1558 }
1559 return signal_levels;
1560}
1561
e3421a18
ZW		 1562/* Gen6's DP voltage swing and pre-emphasis control */
1563static uint32_t
1564intel_gen6_edp_signal_levels(uint8_t train_set)
1565{
3c5a62b5
YL		 1566 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1567 DP_TRAIN_PRE_EMPHASIS_MASK);
1568 switch (signal_levels) {
e3421a18 1569 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1570 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1571 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1572 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1573 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1574 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1575 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1576 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1577 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1578 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1579 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1580 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1581 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1582 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1583 default:
3c5a62b5
YL		 1584 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1585 "0x%x\n", signal_levels);
1586 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1587 }
1588}
1589
1a2eb460
KP		 1590/* Gen7's DP voltage swing and pre-emphasis control */
1591static uint32_t
1592intel_gen7_edp_signal_levels(uint8_t train_set)
1593{
1594 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1595 DP_TRAIN_PRE_EMPHASIS_MASK);
1596 switch (signal_levels) {
1597 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1598 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1599 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1600 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1601 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1602 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1603
1604 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1605 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1606 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1607 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1608
1609 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1610 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1611 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1612 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1613
1614 default:
1615 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1616 "0x%x\n", signal_levels);
1617 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1618 }
1619}
1620
a4fc5ed6
KP		 1621static uint8_t
1622intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1623 int lane)
1624{
a4fc5ed6 1625 int s = (lane & 1) * 4;
93f62dad 1626 uint8_t l = link_status[lane>>1];
a4fc5ed6
KP		 1627
1628 return (l >> s) & 0xf;
1629}
1630
1631/* Check for clock recovery is done on all channels */
1632static bool
1633intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1634{
1635 int lane;
1636 uint8_t lane_status;
1637
1638 for (lane = 0; lane < lane_count; lane++) {
1639 lane_status = intel_get_lane_status(link_status, lane);
1640 if ((lane_status & DP_LANE_CR_DONE) == 0)
1641 return false;
1642 }
1643 return true;
1644}
1645
1646/* Check to see if channel eq is done on all channels */
1647#define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1648 DP_LANE_CHANNEL_EQ_DONE|\
1649 DP_LANE_SYMBOL_LOCKED)
1650static bool
93f62dad 1651intel_channel_eq_ok(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1652{
1653 uint8_t lane_align;
1654 uint8_t lane_status;
1655 int lane;
1656
93f62dad 1657 lane_align = intel_dp_link_status(link_status,
a4fc5ed6
KP		 1658 DP_LANE_ALIGN_STATUS_UPDATED);
1659 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1660 return false;
33a34e4e 1661 for (lane = 0; lane < intel_dp->lane_count; lane++) {
93f62dad 1662 lane_status = intel_get_lane_status(link_status, lane);
a4fc5ed6
KP		 1663 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1664 return false;
1665 }
1666 return true;
1667}
1668
1669static bool
ea5b213a 1670intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1671 uint32_t dp_reg_value,
58e10eb9 1672 uint8_t dp_train_pat)
a4fc5ed6 1673{
4ef69c7a 1674 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1675 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6
KP		 1676 int ret;
1677
47ea7542
PZ		 1678 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1679 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1680
1681 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1682 case DP_TRAINING_PATTERN_DISABLE:
1683 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1684 break;
1685 case DP_TRAINING_PATTERN_1:
1686 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1687 break;
1688 case DP_TRAINING_PATTERN_2:
1689 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1690 break;
1691 case DP_TRAINING_PATTERN_3:
1692 DRM_ERROR("DP training pattern 3 not supported\n");
1693 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1694 break;
1695 }
1696
1697 } else {
1698 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1699
1700 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1701 case DP_TRAINING_PATTERN_DISABLE:
1702 dp_reg_value |= DP_LINK_TRAIN_OFF;
1703 break;
1704 case DP_TRAINING_PATTERN_1:
1705 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1706 break;
1707 case DP_TRAINING_PATTERN_2:
1708 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1709 break;
1710 case DP_TRAINING_PATTERN_3:
1711 DRM_ERROR("DP training pattern 3 not supported\n");
1712 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1713 break;
1714 }
1715 }
1716
ea5b213a
CW		 1717 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1718 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1719
ea5b213a 1720 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1721 DP_TRAINING_PATTERN_SET,
1722 dp_train_pat);
1723
47ea7542
PZ		 1724 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1725 DP_TRAINING_PATTERN_DISABLE) {
1726 ret = intel_dp_aux_native_write(intel_dp,
1727 DP_TRAINING_LANE0_SET,
1728 intel_dp->train_set,
1729 intel_dp->lane_count);
1730 if (ret != intel_dp->lane_count)
1731 return false;
1732 }
a4fc5ed6
KP		 1733
1734 return true;
1735}
1736
33a34e4e 1737/* Enable corresponding port and start training pattern 1 */
a4fc5ed6 1738static void
33a34e4e 1739intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1740{
4ef69c7a 1741 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6
KP		 1742 int i;
1743 uint8_t voltage;
1744 bool clock_recovery = false;
cdb0e95b 1745 int voltage_tries, loop_tries;
ea5b213a 1746 uint32_t DP = intel_dp->DP;
a4fc5ed6 1747
3cf2efb1
CW		 1748 /* Write the link configuration data */
1749 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1750 intel_dp->link_configuration,
1751 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1752
1753 DP |= DP_PORT_EN;
1a2eb460 1754
33a34e4e 1755 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1756 voltage = 0xff;
cdb0e95b
KP		 1757 voltage_tries = 0;
1758 loop_tries = 0;
a4fc5ed6
KP		 1759 clock_recovery = false;
1760 for (;;) {
33a34e4e 1761 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1762 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1763 uint32_t signal_levels;
417e822d 1764
1a2eb460
KP		 1765
1766 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1767 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1768 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1769 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1770 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1771 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1772 } else {
93f62dad
KP		 1773 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1774 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", signal_levels);
e3421a18
ZW		 1775 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1776 }
a4fc5ed6 1777
47ea7542 1778 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1779 DP_TRAINING_PATTERN_1 |
1780 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1781 break;
a4fc5ed6
KP		 1782 /* Set training pattern 1 */
1783
3cf2efb1 1784 udelay(100);
93f62dad
KP		 1785 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1786 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1787 break;
93f62dad 1788 }
a4fc5ed6 1789
93f62dad
KP		 1790 if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1791 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1792 clock_recovery = true;
1793 break;
1794 }
1795
1796 /* Check to see if we've tried the max voltage */
1797 for (i = 0; i < intel_dp->lane_count; i++)
1798 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1799 break;
0d710688 1800 if (i == intel_dp->lane_count && voltage_tries == 5) {
24773670 1801 if (++loop_tries == 5) {
cdb0e95b
KP		 1802 DRM_DEBUG_KMS("too many full retries, give up\n");
1803 break;
1804 }
1805 memset(intel_dp->train_set, 0, 4);
1806 voltage_tries = 0;
1807 continue;
1808 }
a4fc5ed6 1809
3cf2efb1 1810 /* Check to see if we've tried the same voltage 5 times */
24773670
CW		 1811 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1812 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
cdb0e95b 1813 voltage_tries = 0;
24773670
CW		 1814 } else
1815 ++voltage_tries;
a4fc5ed6 1816
3cf2efb1 1817 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1818 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1819 }
1820
33a34e4e
JB		 1821 intel_dp->DP = DP;
1822}
1823
1824static void
1825intel_dp_complete_link_train(struct intel_dp *intel_dp)
1826{
4ef69c7a 1827 struct drm_device *dev = intel_dp->base.base.dev;
33a34e4e 1828 bool channel_eq = false;
37f80975 1829 int tries, cr_tries;
33a34e4e
JB		 1830 uint32_t DP = intel_dp->DP;
1831
a4fc5ed6
KP		 1832 /* channel equalization */
1833 tries = 0;
37f80975 1834 cr_tries = 0;
a4fc5ed6
KP		 1835 channel_eq = false;
1836 for (;;) {
33a34e4e 1837 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
e3421a18 1838 uint32_t signal_levels;
93f62dad 1839 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1840
37f80975
JB		 1841 if (cr_tries > 5) {
1842 DRM_ERROR("failed to train DP, aborting\n");
1843 intel_dp_link_down(intel_dp);
1844 break;
1845 }
1846
1a2eb460
KP		 1847 if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
1848 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1849 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1850 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
33a34e4e 1851 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1852 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1853 } else {
93f62dad 1854 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
e3421a18
ZW		 1855 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1856 }
1857
a4fc5ed6 1858 /* channel eq pattern */
47ea7542 1859 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1860 DP_TRAINING_PATTERN_2 |
1861 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1862 break;
1863
3cf2efb1 1864 udelay(400);
93f62dad 1865 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1866 break;
a4fc5ed6 1867
37f80975 1868 /* Make sure clock is still ok */
93f62dad 1869 if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1870 intel_dp_start_link_train(intel_dp);
1871 cr_tries++;
1872 continue;
1873 }
1874
93f62dad 1875 if (intel_channel_eq_ok(intel_dp, link_status)) {
3cf2efb1
CW		 1876 channel_eq = true;
1877 break;
1878 }
a4fc5ed6 1879
37f80975
JB		 1880 /* Try 5 times, then try clock recovery if that fails */
1881 if (tries > 5) {
1882 intel_dp_link_down(intel_dp);
1883 intel_dp_start_link_train(intel_dp);
1884 tries = 0;
1885 cr_tries++;
1886 continue;
1887 }
a4fc5ed6 1888
3cf2efb1 1889 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1890 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1891 ++tries;
869184a6 1892 }
3cf2efb1 1893
47ea7542 1894 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1895}
1896
1897static void
ea5b213a 1898intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1899{
4ef69c7a 1900 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 1901 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1902 uint32_t DP = intel_dp->DP;
a4fc5ed6 1903
0c33d8d7 1904 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 1905 return;
1906
28c97730 1907 DRM_DEBUG_KMS("\n");
32f9d658 1908
1a2eb460 1909 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1910 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1911 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1912 } else {
1913 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1914 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1915 }
fe255d00 1916 POSTING_READ(intel_dp->output_reg);
5eb08b69 1917
fe255d00 1918 msleep(17);
5eb08b69 1919
493a7081 1920 if (HAS_PCH_IBX(dev) &&
1b39d6f3 1921 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
31acbcc4
CW		 1922 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1923
5bddd17f
EA		 1924 /* Hardware workaround: leaving our transcoder select
1925 * set to transcoder B while it's off will prevent the
1926 * corresponding HDMI output on transcoder A.
1927 *
1928 * Combine this with another hardware workaround:
1929 * transcoder select bit can only be cleared while the
1930 * port is enabled.
1931 */
1932 DP &= ~DP_PIPEB_SELECT;
1933 I915_WRITE(intel_dp->output_reg, DP);
1934
1935 /* Changes to enable or select take place the vblank
1936 * after being written.
1937 */
31acbcc4
CW		 1938 if (crtc == NULL) {
1939 /* We can arrive here never having been attached
1940 * to a CRTC, for instance, due to inheriting
1941 * random state from the BIOS.
1942 *
1943 * If the pipe is not running, play safe and
1944 * wait for the clocks to stabilise before
1945 * continuing.
1946 */
1947 POSTING_READ(intel_dp->output_reg);
1948 msleep(50);
1949 } else
1950 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
5bddd17f
EA		 1951 }
1952
832afda6 1953 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 1954 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1955 POSTING_READ(intel_dp->output_reg);
f01eca2e 1956 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 1957}
1958
26d61aad
KP		 1959static bool
1960intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 1961{
92fd8fd1 1962 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 1963 sizeof(intel_dp->dpcd)) == 0)
1964 return false; /* aux transfer failed */
92fd8fd1 1965
edb39244
AJ		 1966 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
1967 return false; /* DPCD not present */
1968
1969 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1970 DP_DWN_STRM_PORT_PRESENT))
1971 return true; /* native DP sink */
1972
1973 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
1974 return true; /* no per-port downstream info */
1975
1976 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
1977 intel_dp->downstream_ports,
1978 DP_MAX_DOWNSTREAM_PORTS) == 0)
1979 return false; /* downstream port status fetch failed */
1980
1981 return true;
92fd8fd1
KP		 1982}
1983
0d198328
AJ		 1984static void
1985intel_dp_probe_oui(struct intel_dp *intel_dp)
1986{
1987 u8 buf[3];
1988
1989 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
1990 return;
1991
351cfc34
DV		 1992 ironlake_edp_panel_vdd_on(intel_dp);
1993
0d198328
AJ		 1994 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
1995 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
1996 buf[0], buf[1], buf[2]);
1997
1998 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
1999 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2000 buf[0], buf[1], buf[2]);
351cfc34
DV		 2001
2002 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2003}
2004
a60f0e38
JB		 2005static bool
2006intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2007{
2008 int ret;
2009
2010 ret = intel_dp_aux_native_read_retry(intel_dp,
2011 DP_DEVICE_SERVICE_IRQ_VECTOR,
2012 sink_irq_vector, 1);
2013 if (!ret)
2014 return false;
2015
2016 return true;
2017}
2018
2019static void
2020intel_dp_handle_test_request(struct intel_dp *intel_dp)
2021{
2022 /* NAK by default */
2023 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2024}
2025
a4fc5ed6
KP		 2026/*
2027 * According to DP spec
2028 * 5.1.2:
2029 * 1. Read DPCD
2030 * 2. Configure link according to Receiver Capabilities
2031 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2032 * 4. Check link status on receipt of hot-plug interrupt
2033 */
2034
2035static void
ea5b213a 2036intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2037{
a60f0e38 2038 u8 sink_irq_vector;
93f62dad 2039 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2040
24e804ba 2041 if (!intel_dp->base.connectors_active)
d2b996ac 2042 return;
59cd09e1 2043
24e804ba 2044 if (WARN_ON(!intel_dp->base.base.crtc))
a4fc5ed6
KP		 2045 return;
2046
92fd8fd1 2047 /* Try to read receiver status if the link appears to be up */
93f62dad 2048 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2049 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2050 return;
2051 }
2052
92fd8fd1 2053 /* Now read the DPCD to see if it's actually running */
26d61aad 2054 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2055 intel_dp_link_down(intel_dp);
2056 return;
2057 }
2058
a60f0e38
JB		 2059 /* Try to read the source of the interrupt */
2060 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2061 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2062 /* Clear interrupt source */
2063 intel_dp_aux_native_write_1(intel_dp,
2064 DP_DEVICE_SERVICE_IRQ_VECTOR,
2065 sink_irq_vector);
2066
2067 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2068 intel_dp_handle_test_request(intel_dp);
2069 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2070 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2071 }
2072
93f62dad 2073 if (!intel_channel_eq_ok(intel_dp, link_status)) {
92fd8fd1
KP		 2074 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2075 drm_get_encoder_name(&intel_dp->base.base));
33a34e4e
JB		 2076 intel_dp_start_link_train(intel_dp);
2077 intel_dp_complete_link_train(intel_dp);
2078 }
a4fc5ed6 2079}
a4fc5ed6 2080
caf9ab24 2081/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2082static enum drm_connector_status
26d61aad 2083intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2084{
caf9ab24
AJ		 2085 uint8_t *dpcd = intel_dp->dpcd;
2086 bool hpd;
2087 uint8_t type;
2088
2089 if (!intel_dp_get_dpcd(intel_dp))
2090 return connector_status_disconnected;
2091
2092 /* if there's no downstream port, we're done */
2093 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2094 return connector_status_connected;
2095
2096 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2097 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2098 if (hpd) {
23235177 2099 uint8_t reg;
caf9ab24 2100 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2101 &reg, 1))
caf9ab24 2102 return connector_status_unknown;
23235177
AJ		 2103 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2104 : connector_status_disconnected;
caf9ab24
AJ		 2105 }
2106
2107 /* If no HPD, poke DDC gently */
2108 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2109 return connector_status_connected;
caf9ab24
AJ		 2110
2111 /* Well we tried, say unknown for unreliable port types */
2112 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2113 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2114 return connector_status_unknown;
2115
2116 /* Anything else is out of spec, warn and ignore */
2117 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2118 return connector_status_disconnected;
71ba9000
AJ		 2119}
2120
5eb08b69 2121static enum drm_connector_status
a9756bb5 2122ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2123{
5eb08b69
ZW		 2124 enum drm_connector_status status;
2125
fe16d949
CW		 2126 /* Can't disconnect eDP, but you can close the lid... */
2127 if (is_edp(intel_dp)) {
2128 status = intel_panel_detect(intel_dp->base.base.dev);
2129 if (status == connector_status_unknown)
2130 status = connector_status_connected;
2131 return status;
2132 }
01cb9ea6 2133
26d61aad 2134 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2135}
2136
a4fc5ed6 2137static enum drm_connector_status
a9756bb5 2138g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2139{
4ef69c7a 2140 struct drm_device *dev = intel_dp->base.base.dev;
a4fc5ed6 2141 struct drm_i915_private *dev_priv = dev->dev_private;
10f76a38 2142 uint32_t bit;
5eb08b69 2143
ea5b213a 2144 switch (intel_dp->output_reg) {
a4fc5ed6 2145 case DP_B:
10f76a38 2146 bit = DPB_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2147 break;
2148 case DP_C:
10f76a38 2149 bit = DPC_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2150 break;
2151 case DP_D:
10f76a38 2152 bit = DPD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2153 break;
2154 default:
2155 return connector_status_unknown;
2156 }
2157
10f76a38 2158 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2159 return connector_status_disconnected;
2160
26d61aad 2161 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2162}
2163
8c241fef
KP		 2164static struct edid *
2165intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2166{
2167 struct intel_dp *intel_dp = intel_attached_dp(connector);
2168 struct edid *edid;
d6f24d0f
JB		 2169 int size;
2170
2171 if (is_edp(intel_dp)) {
2172 if (!intel_dp->edid)
2173 return NULL;
2174
2175 size = (intel_dp->edid->extensions + 1) * EDID_LENGTH;
2176 edid = kmalloc(size, GFP_KERNEL);
2177 if (!edid)
2178 return NULL;
2179
2180 memcpy(edid, intel_dp->edid, size);
2181 return edid;
2182 }
8c241fef 2183
8c241fef 2184 edid = drm_get_edid(connector, adapter);
8c241fef
KP		 2185 return edid;
2186}
2187
2188static int
2189intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2190{
2191 struct intel_dp *intel_dp = intel_attached_dp(connector);
2192 int ret;
2193
d6f24d0f
JB		 2194 if (is_edp(intel_dp)) {
2195 drm_mode_connector_update_edid_property(connector,
2196 intel_dp->edid);
2197 ret = drm_add_edid_modes(connector, intel_dp->edid);
2198 drm_edid_to_eld(connector,
2199 intel_dp->edid);
d6f24d0f
JB		 2200 return intel_dp->edid_mode_count;
2201 }
2202
8c241fef 2203 ret = intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2204 return ret;
2205}
2206
2207
a9756bb5
ZW		 2208/**
2209 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2210 *
2211 * \return true if DP port is connected.
2212 * \return false if DP port is disconnected.
2213 */
2214static enum drm_connector_status
2215intel_dp_detect(struct drm_connector *connector, bool force)
2216{
2217 struct intel_dp *intel_dp = intel_attached_dp(connector);
2218 struct drm_device *dev = intel_dp->base.base.dev;
2219 enum drm_connector_status status;
2220 struct edid *edid = NULL;
2221
2222 intel_dp->has_audio = false;
2223
2224 if (HAS_PCH_SPLIT(dev))
2225 status = ironlake_dp_detect(intel_dp);
2226 else
2227 status = g4x_dp_detect(intel_dp);
1b9be9d0 2228
ac66ae83
AJ		 2229 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2230 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2231 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2232 intel_dp->dpcd[6], intel_dp->dpcd[7]);
1b9be9d0 2233
a9756bb5
ZW		 2234 if (status != connector_status_connected)
2235 return status;
2236
0d198328
AJ		 2237 intel_dp_probe_oui(intel_dp);
2238
c3e5f67b
DV		 2239 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2240 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2241 } else {
8c241fef 2242 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2243 if (edid) {
2244 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2245 kfree(edid);
2246 }
a9756bb5
ZW		 2247 }
2248
2249 return connector_status_connected;
a4fc5ed6
KP		 2250}
2251
2252static int intel_dp_get_modes(struct drm_connector *connector)
2253{
df0e9248 2254 struct intel_dp *intel_dp = intel_attached_dp(connector);
4ef69c7a 2255 struct drm_device *dev = intel_dp->base.base.dev;
32f9d658
ZW		 2256 struct drm_i915_private *dev_priv = dev->dev_private;
2257 int ret;
a4fc5ed6
KP		 2258
2259 /* We should parse the EDID data and find out if it has an audio sink
2260 */
2261
8c241fef 2262 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
b9efc480 2263 if (ret) {
d15456de 2264 if (is_edp(intel_dp) && !intel_dp->panel_fixed_mode) {
b9efc480
ZY		 2265 struct drm_display_mode *newmode;
2266 list_for_each_entry(newmode, &connector->probed_modes,
2267 head) {
d15456de
KP		 2268 if ((newmode->type & DRM_MODE_TYPE_PREFERRED)) {
2269 intel_dp->panel_fixed_mode =
b9efc480
ZY		 2270 drm_mode_duplicate(dev, newmode);
2271 break;
2272 }
2273 }
2274 }
32f9d658 2275 return ret;
b9efc480 2276 }
32f9d658
ZW		 2277
2278 /* if eDP has no EDID, try to use fixed panel mode from VBT */
4d926461 2279 if (is_edp(intel_dp)) {
47f0eb22 2280 /* initialize panel mode from VBT if available for eDP */
d15456de
KP		 2281 if (intel_dp->panel_fixed_mode == NULL && dev_priv->lfp_lvds_vbt_mode != NULL) {
2282 intel_dp->panel_fixed_mode =
47f0eb22 2283 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
d15456de
KP		 2284 if (intel_dp->panel_fixed_mode) {
2285 intel_dp->panel_fixed_mode->type |=
47f0eb22
KP		 2286 DRM_MODE_TYPE_PREFERRED;
2287 }
2288 }
d15456de 2289 if (intel_dp->panel_fixed_mode) {
32f9d658 2290 struct drm_display_mode *mode;
d15456de 2291 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
32f9d658
ZW		 2292 drm_mode_probed_add(connector, mode);
2293 return 1;
2294 }
2295 }
2296 return 0;
a4fc5ed6
KP		 2297}
2298
1aad7ac0
CW		 2299static bool
2300intel_dp_detect_audio(struct drm_connector *connector)
2301{
2302 struct intel_dp *intel_dp = intel_attached_dp(connector);
2303 struct edid *edid;
2304 bool has_audio = false;
2305
8c241fef 2306 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2307 if (edid) {
2308 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2309 kfree(edid);
2310 }
2311
2312 return has_audio;
2313}
2314
f684960e
CW		 2315static int
2316intel_dp_set_property(struct drm_connector *connector,
2317 struct drm_property *property,
2318 uint64_t val)
2319{
e953fd7b 2320 struct drm_i915_private *dev_priv = connector->dev->dev_private;
f684960e
CW		 2321 struct intel_dp *intel_dp = intel_attached_dp(connector);
2322 int ret;
2323
2324 ret = drm_connector_property_set_value(connector, property, val);
2325 if (ret)
2326 return ret;
2327
3f43c48d 2328 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2329 int i = val;
2330 bool has_audio;
2331
2332 if (i == intel_dp->force_audio)
f684960e
CW		 2333 return 0;
2334
1aad7ac0 2335 intel_dp->force_audio = i;
f684960e 2336
c3e5f67b 2337 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2338 has_audio = intel_dp_detect_audio(connector);
2339 else
c3e5f67b 2340 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2341
2342 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2343 return 0;
2344
1aad7ac0 2345 intel_dp->has_audio = has_audio;
f684960e
CW		 2346 goto done;
2347 }
2348
e953fd7b
CW		 2349 if (property == dev_priv->broadcast_rgb_property) {
2350 if (val == !!intel_dp->color_range)
2351 return 0;
2352
2353 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2354 goto done;
2355 }
2356
f684960e
CW		 2357 return -EINVAL;
2358
2359done:
2360 if (intel_dp->base.base.crtc) {
2361 struct drm_crtc *crtc = intel_dp->base.base.crtc;
a6778b3c
DV		 2362 intel_set_mode(crtc, &crtc->mode,
2363 crtc->x, crtc->y, crtc->fb);
f684960e
CW		 2364 }
2365
2366 return 0;
2367}
2368
a4fc5ed6 2369static void
0206e353 2370intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2371{
aaa6fd2a 2372 struct drm_device *dev = connector->dev;
be3cd5e3 2373 struct intel_dp *intel_dp = intel_attached_dp(connector);
aaa6fd2a 2374
be3cd5e3 2375 if (is_edp(intel_dp))
aaa6fd2a
MG		 2376 intel_panel_destroy_backlight(dev);
2377
a4fc5ed6
KP		 2378 drm_sysfs_connector_remove(connector);
2379 drm_connector_cleanup(connector);
55f78c43 2380 kfree(connector);
a4fc5ed6
KP		 2381}
2382
24d05927
DV		 2383static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2384{
2385 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2386
2387 i2c_del_adapter(&intel_dp->adapter);
2388 drm_encoder_cleanup(encoder);
bd943159 2389 if (is_edp(intel_dp)) {
d6f24d0f 2390 kfree(intel_dp->edid);
bd943159
KP		 2391 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2392 ironlake_panel_vdd_off_sync(intel_dp);
2393 }
24d05927
DV		 2394 kfree(intel_dp);
2395}
2396
a4fc5ed6 2397static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2398 .mode_fixup = intel_dp_mode_fixup,
a4fc5ed6 2399 .mode_set = intel_dp_mode_set,
1f703855 2400 .disable = intel_encoder_noop,
a4fc5ed6
KP		 2401};
2402
2403static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2404 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2405 .detect = intel_dp_detect,
2406 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2407 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2408 .destroy = intel_dp_destroy,
2409};
2410
2411static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2412 .get_modes = intel_dp_get_modes,
2413 .mode_valid = intel_dp_mode_valid,
df0e9248 2414 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2415};
2416
a4fc5ed6 2417static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2418 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2419};
2420
995b6762 2421static void
21d40d37 2422intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2423{
ea5b213a 2424 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
c8110e52 2425
885a5014 2426 intel_dp_check_link_status(intel_dp);
c8110e52 2427}
6207937d 2428
e3421a18
ZW		 2429/* Return which DP Port should be selected for Transcoder DP control */
2430int
0206e353 2431intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2432{
2433 struct drm_device *dev = crtc->dev;
6c2b7c12 2434 struct intel_encoder *encoder;
e3421a18 2435
6c2b7c12
DV		 2436 for_each_encoder_on_crtc(dev, crtc, encoder) {
2437 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
e3421a18 2438
417e822d
KP		 2439 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2440 intel_dp->base.type == INTEL_OUTPUT_EDP)
ea5b213a 2441 return intel_dp->output_reg;
e3421a18 2442 }
ea5b213a 2443
e3421a18
ZW		 2444 return -1;
2445}
2446
36e83a18 2447/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2448bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2449{
2450 struct drm_i915_private *dev_priv = dev->dev_private;
2451 struct child_device_config *p_child;
2452 int i;
2453
2454 if (!dev_priv->child_dev_num)
2455 return false;
2456
2457 for (i = 0; i < dev_priv->child_dev_num; i++) {
2458 p_child = dev_priv->child_dev + i;
2459
2460 if (p_child->dvo_port == PORT_IDPD &&
2461 p_child->device_type == DEVICE_TYPE_eDP)
2462 return true;
2463 }
2464 return false;
2465}
2466
f684960e
CW		 2467static void
2468intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2469{
3f43c48d 2470 intel_attach_force_audio_property(connector);
e953fd7b 2471 intel_attach_broadcast_rgb_property(connector);
f684960e
CW		 2472}
2473
a4fc5ed6 2474void
ab9d7c30 2475intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
a4fc5ed6
KP		 2476{
2477 struct drm_i915_private *dev_priv = dev->dev_private;
2478 struct drm_connector *connector;
ea5b213a 2479 struct intel_dp *intel_dp;
21d40d37 2480 struct intel_encoder *intel_encoder;
55f78c43 2481 struct intel_connector *intel_connector;
5eb08b69 2482 const char *name = NULL;
b329530c 2483 int type;
a4fc5ed6 2484
ea5b213a
CW		 2485 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2486 if (!intel_dp)
a4fc5ed6
KP		 2487 return;
2488
3d3dc149 2489 intel_dp->output_reg = output_reg;
ab9d7c30 2490 intel_dp->port = port;
0767935e
DV		 2491 /* Preserve the current hw state. */
2492 intel_dp->DP = I915_READ(intel_dp->output_reg);
3d3dc149 2493
55f78c43
ZW		 2494 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2495 if (!intel_connector) {
ea5b213a 2496 kfree(intel_dp);
55f78c43
ZW		 2497 return;
2498 }
ea5b213a 2499 intel_encoder = &intel_dp->base;
55f78c43 2500
ea5b213a 2501 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
b329530c 2502 if (intel_dpd_is_edp(dev))
ea5b213a 2503 intel_dp->is_pch_edp = true;
b329530c 2504
cfcb0fc9 2505 if (output_reg == DP_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2506 type = DRM_MODE_CONNECTOR_eDP;
2507 intel_encoder->type = INTEL_OUTPUT_EDP;
2508 } else {
2509 type = DRM_MODE_CONNECTOR_DisplayPort;
2510 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2511 }
2512
55f78c43 2513 connector = &intel_connector->base;
b329530c 2514 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2515 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2516
eb1f8e4f
DA		 2517 connector->polled = DRM_CONNECTOR_POLL_HPD;
2518
66a9278e 2519 intel_encoder->cloneable = false;
f8aed700 2520
66a9278e
DV		 2521 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2522 ironlake_panel_vdd_work);
6251ec0a 2523
27f8227b 2524 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
ee7b9f93 2525
a4fc5ed6
KP		 2526 connector->interlace_allowed = true;
2527 connector->doublescan_allowed = 0;
2528
4ef69c7a 2529 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
a4fc5ed6 2530 DRM_MODE_ENCODER_TMDS);
4ef69c7a 2531 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
a4fc5ed6 2532
df0e9248 2533 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2534 drm_sysfs_connector_add(connector);
2535
e8cb4558 2536 intel_encoder->enable = intel_enable_dp;
2bd2ad64 2537 intel_encoder->pre_enable = intel_pre_enable_dp;
e8cb4558 2538 intel_encoder->disable = intel_disable_dp;
2bd2ad64 2539 intel_encoder->post_disable = intel_post_disable_dp;
19d8fe15
DV		 2540 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2541 intel_connector->get_hw_state = intel_connector_get_hw_state;
e8cb4558 2542
a4fc5ed6 2543 /* Set up the DDC bus. */
ab9d7c30
PZ		 2544 switch (port) {
2545 case PORT_A:
2546 name = "DPDDC-A";
2547 break;
2548 case PORT_B:
2549 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2550 name = "DPDDC-B";
2551 break;
2552 case PORT_C:
2553 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2554 name = "DPDDC-C";
2555 break;
2556 case PORT_D:
2557 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2558 name = "DPDDC-D";
2559 break;
2560 default:
2561 WARN(1, "Invalid port %c\n", port_name(port));
2562 break;
5eb08b69
ZW		 2563 }
2564
89667383
JB		 2565 /* Cache some DPCD data in the eDP case */
2566 if (is_edp(intel_dp)) {
f01eca2e
KP		 2567 struct edp_power_seq cur, vbt;
2568 u32 pp_on, pp_off, pp_div;
5d613501
JB		 2569
2570 pp_on = I915_READ(PCH_PP_ON_DELAYS);
f01eca2e 2571 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
5d613501 2572 pp_div = I915_READ(PCH_PP_DIVISOR);
89667383 2573
bfa3384a
JB		 2574 if (!pp_on || !pp_off || !pp_div) {
2575 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2576 intel_dp_encoder_destroy(&intel_dp->base.base);
2577 intel_dp_destroy(&intel_connector->base);
2578 return;
2579 }
2580
f01eca2e
KP		 2581 /* Pull timing values out of registers */
2582 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2583 PANEL_POWER_UP_DELAY_SHIFT;
2584
2585 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2586 PANEL_LIGHT_ON_DELAY_SHIFT;
f2e8b18a 2587
f01eca2e
KP		 2588 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2589 PANEL_LIGHT_OFF_DELAY_SHIFT;
2590
2591 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2592 PANEL_POWER_DOWN_DELAY_SHIFT;
2593
2594 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2595 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2596
2597 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2598 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2599
2600 vbt = dev_priv->edp.pps;
2601
2602 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2603 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2604
2605#define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2606
2607 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2608 intel_dp->backlight_on_delay = get_delay(t8);
2609 intel_dp->backlight_off_delay = get_delay(t9);
2610 intel_dp->panel_power_down_delay = get_delay(t10);
2611 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2612
2613 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2614 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2615 intel_dp->panel_power_cycle_delay);
2616
2617 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2618 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
c1f05264
DA		 2619 }
2620
2621 intel_dp_i2c_init(intel_dp, intel_connector, name);
2622
2623 if (is_edp(intel_dp)) {
2624 bool ret;
2625 struct edid *edid;
5d613501
JB		 2626
2627 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2628 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2629 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2630
59f3e272 2631 if (ret) {
7183dc29
JB		 2632 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2633 dev_priv->no_aux_handshake =
2634 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2635 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2636 } else {
3d3dc149 2637 /* if this fails, presume the device is a ghost */
48898b03 2638 DRM_INFO("failed to retrieve link info, disabling eDP\n");
3d3dc149 2639 intel_dp_encoder_destroy(&intel_dp->base.base);
48898b03 2640 intel_dp_destroy(&intel_connector->base);
3d3dc149 2641 return;
89667383 2642 }
89667383 2643
d6f24d0f
JB		 2644 ironlake_edp_panel_vdd_on(intel_dp);
2645 edid = drm_get_edid(connector, &intel_dp->adapter);
2646 if (edid) {
2647 drm_mode_connector_update_edid_property(connector,
2648 edid);
2649 intel_dp->edid_mode_count =
2650 drm_add_edid_modes(connector, edid);
2651 drm_edid_to_eld(connector, edid);
2652 intel_dp->edid = edid;
2653 }
2654 ironlake_edp_panel_vdd_off(intel_dp, false);
2655 }
552fb0b7 2656
21d40d37 2657 intel_encoder->hot_plug = intel_dp_hot_plug;
a4fc5ed6 2658
4d926461 2659 if (is_edp(intel_dp)) {
aaa6fd2a
MG		 2660 dev_priv->int_edp_connector = connector;
2661 intel_panel_setup_backlight(dev);
32f9d658
ZW		 2662 }
2663
f684960e
CW		 2664 intel_dp_add_properties(intel_dp, connector);
2665
a4fc5ed6
KP		 2666 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2667 * 0xd. Failure to do so will result in spurious interrupts being
2668 * generated on the port when a cable is not attached.
2669 */
2670 if (IS_G4X(dev) && !IS_GM45(dev)) {
2671 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2672 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2673 }
2674}
Linux 6.x block layer and io_uring tree(s)