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drm/i915: Fix edp vdd locking
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
1e0560e0 114static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
e39b999a
VS		 303 lockdep_assert_held(&dev_priv->pps_mutex);
304
bf13e81b
JN		 305 /* modeset should have pipe */
306 if (crtc)
307 return to_intel_crtc(crtc)->pipe;
308
309 /* init time, try to find a pipe with this port selected */
310 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
311 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
312 PANEL_PORT_SELECT_MASK;
ad933b56 313 if (port_sel == PANEL_PORT_SELECT_VLV(port))
bf13e81b
JN		 314 return pipe;
315 }
316
317 /* shrug */
318 return PIPE_A;
319}
320
321static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
322{
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324
325 if (HAS_PCH_SPLIT(dev))
326 return PCH_PP_CONTROL;
327 else
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
329}
330
331static u32 _pp_stat_reg(struct intel_dp *intel_dp)
332{
333 struct drm_device *dev = intel_dp_to_dev(intel_dp);
334
335 if (HAS_PCH_SPLIT(dev))
336 return PCH_PP_STATUS;
337 else
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
339}
340
01527b31
CT		 341/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343static int edp_notify_handler(struct notifier_block *this, unsigned long code,
344 void *unused)
345{
346 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
347 edp_notifier);
348 struct drm_device *dev = intel_dp_to_dev(intel_dp);
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 u32 pp_div;
351 u32 pp_ctrl_reg, pp_div_reg;
01527b31
CT		 352
353 if (!is_edp(intel_dp) || code != SYS_RESTART)
354 return 0;
355
e39b999a
VS		 356 mutex_lock(&dev_priv->pps_mutex);
357
01527b31 358 if (IS_VALLEYVIEW(dev)) {
e39b999a
VS		 359 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
360
01527b31
CT		 361 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
362 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
363 pp_div = I915_READ(pp_div_reg);
364 pp_div &= PP_REFERENCE_DIVIDER_MASK;
365
366 /* 0x1F write to PP_DIV_REG sets max cycle delay */
367 I915_WRITE(pp_div_reg, pp_div | 0x1F);
368 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
369 msleep(intel_dp->panel_power_cycle_delay);
370 }
371
e39b999a
VS		 372 mutex_unlock(&dev_priv->pps_mutex);
373
01527b31
CT		 374 return 0;
375}
376
4be73780 377static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 378{
30add22d 379 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 380 struct drm_i915_private *dev_priv = dev->dev_private;
381
e39b999a
VS		 382 lockdep_assert_held(&dev_priv->pps_mutex);
383
bf13e81b 384 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 385}
386
4be73780 387static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 388{
30add22d 389 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 390 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 391 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
392 struct intel_encoder *intel_encoder = &intel_dig_port->base;
393 enum intel_display_power_domain power_domain;
ebf33b18 394
e39b999a
VS		 395 lockdep_assert_held(&dev_priv->pps_mutex);
396
bb4932c4
ID		 397 power_domain = intel_display_port_power_domain(intel_encoder);
398 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 399 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 400}
401
9b984dae
KP		 402static void
403intel_dp_check_edp(struct intel_dp *intel_dp)
404{
30add22d 405 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 406 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 407
9b984dae
KP		 408 if (!is_edp(intel_dp))
409 return;
453c5420 410
4be73780 411 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 412 WARN(1, "eDP powered off while attempting aux channel communication.\n");
413 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 414 I915_READ(_pp_stat_reg(intel_dp)),
415 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 416 }
417}
418
9ee32fea
DV		 419static uint32_t
420intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
421{
422 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
423 struct drm_device *dev = intel_dig_port->base.base.dev;
424 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 425 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 426 uint32_t status;
427 bool done;
428
ef04f00d 429#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 430 if (has_aux_irq)
b18ac466 431 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 432 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 433 else
434 done = wait_for_atomic(C, 10) == 0;
435 if (!done)
436 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
437 has_aux_irq);
438#undef C
439
440 return status;
441}
442
ec5b01dd 443static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 444{
174edf1f
PZ		 445 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
446 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 447
ec5b01dd
DL		 448 /*
449 * The clock divider is based off the hrawclk, and would like to run at
450 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 451 */
ec5b01dd
DL		 452 return index ? 0 : intel_hrawclk(dev) / 2;
453}
454
455static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
456{
457 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
458 struct drm_device *dev = intel_dig_port->base.base.dev;
459
460 if (index)
461 return 0;
462
463 if (intel_dig_port->port == PORT_A) {
464 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 465 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 466 else
b84a1cf8 467 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 468 } else {
469 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
470 }
471}
472
473static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
474{
475 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
476 struct drm_device *dev = intel_dig_port->base.base.dev;
477 struct drm_i915_private *dev_priv = dev->dev_private;
478
479 if (intel_dig_port->port == PORT_A) {
480 if (index)
481 return 0;
482 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 483 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
484 /* Workaround for non-ULT HSW */
bc86625a
CW		 485 switch (index) {
486 case 0: return 63;
487 case 1: return 72;
488 default: return 0;
489 }
ec5b01dd 490 } else {
bc86625a 491 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 492 }
b84a1cf8
RV		 493}
494
ec5b01dd
DL		 495static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
496{
497 return index ? 0 : 100;
498}
499
5ed12a19
DL		 500static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
501 bool has_aux_irq,
502 int send_bytes,
503 uint32_t aux_clock_divider)
504{
505 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
506 struct drm_device *dev = intel_dig_port->base.base.dev;
507 uint32_t precharge, timeout;
508
509 if (IS_GEN6(dev))
510 precharge = 3;
511 else
512 precharge = 5;
513
514 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
515 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
516 else
517 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
518
519 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 520 DP_AUX_CH_CTL_DONE |
5ed12a19 521 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 522 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 523 timeout |
788d4433 524 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 525 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
526 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 527 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 528}
529
b84a1cf8
RV		 530static int
531intel_dp_aux_ch(struct intel_dp *intel_dp,
532 uint8_t *send, int send_bytes,
533 uint8_t *recv, int recv_size)
534{
535 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
536 struct drm_device *dev = intel_dig_port->base.base.dev;
537 struct drm_i915_private *dev_priv = dev->dev_private;
538 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
539 uint32_t ch_data = ch_ctl + 4;
bc86625a 540 uint32_t aux_clock_divider;
b84a1cf8
RV		 541 int i, ret, recv_bytes;
542 uint32_t status;
5ed12a19 543 int try, clock = 0;
4e6b788c 544 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 545 bool vdd;
546
e39b999a
VS		 547 mutex_lock(&dev_priv->pps_mutex);
548
72c3500a
VS		 549 /*
550 * We will be called with VDD already enabled for dpcd/edid/oui reads.
551 * In such cases we want to leave VDD enabled and it's up to upper layers
552 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
553 * ourselves.
554 */
1e0560e0 555 vdd = edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 556
557 /* dp aux is extremely sensitive to irq latency, hence request the
558 * lowest possible wakeup latency and so prevent the cpu from going into
559 * deep sleep states.
560 */
561 pm_qos_update_request(&dev_priv->pm_qos, 0);
562
563 intel_dp_check_edp(intel_dp);
5eb08b69 564
c67a470b
PZ		 565 intel_aux_display_runtime_get(dev_priv);
566
11bee43e
JB		 567 /* Try to wait for any previous AUX channel activity */
568 for (try = 0; try < 3; try++) {
ef04f00d 569 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 570 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
571 break;
572 msleep(1);
573 }
574
575 if (try == 3) {
576 WARN(1, "dp_aux_ch not started status 0x%08x\n",
577 I915_READ(ch_ctl));
9ee32fea
DV		 578 ret = -EBUSY;
579 goto out;
4f7f7b7e
CW		 580 }
581
46a5ae9f
PZ		 582 /* Only 5 data registers! */
583 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
584 ret = -E2BIG;
585 goto out;
586 }
587
ec5b01dd 588 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 589 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
590 has_aux_irq,
591 send_bytes,
592 aux_clock_divider);
5ed12a19 593
bc86625a
CW		 594 /* Must try at least 3 times according to DP spec */
595 for (try = 0; try < 5; try++) {
596 /* Load the send data into the aux channel data registers */
597 for (i = 0; i < send_bytes; i += 4)
598 I915_WRITE(ch_data + i,
599 pack_aux(send + i, send_bytes - i));
600
601 /* Send the command and wait for it to complete */
5ed12a19 602 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 603
604 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
605
606 /* Clear done status and any errors */
607 I915_WRITE(ch_ctl,
608 status |
609 DP_AUX_CH_CTL_DONE |
610 DP_AUX_CH_CTL_TIME_OUT_ERROR |
611 DP_AUX_CH_CTL_RECEIVE_ERROR);
612
613 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
614 DP_AUX_CH_CTL_RECEIVE_ERROR))
615 continue;
616 if (status & DP_AUX_CH_CTL_DONE)
617 break;
618 }
4f7f7b7e 619 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 620 break;
621 }
622
a4fc5ed6 623 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 624 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 625 ret = -EBUSY;
626 goto out;
a4fc5ed6
KP		 627 }
628
629 /* Check for timeout or receive error.
630 * Timeouts occur when the sink is not connected
631 */
a5b3da54 632 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 633 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 634 ret = -EIO;
635 goto out;
a5b3da54 636 }
1ae8c0a5
KP		 637
638 /* Timeouts occur when the device isn't connected, so they're
639 * "normal" -- don't fill the kernel log with these */
a5b3da54 640 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 641 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 642 ret = -ETIMEDOUT;
643 goto out;
a4fc5ed6
KP		 644 }
645
646 /* Unload any bytes sent back from the other side */
647 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
648 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 649 if (recv_bytes > recv_size)
650 recv_bytes = recv_size;
0206e353 651
4f7f7b7e
CW		 652 for (i = 0; i < recv_bytes; i += 4)
653 unpack_aux(I915_READ(ch_data + i),
654 recv + i, recv_bytes - i);
a4fc5ed6 655
9ee32fea
DV		 656 ret = recv_bytes;
657out:
658 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 659 intel_aux_display_runtime_put(dev_priv);
9ee32fea 660
884f19e9
JN		 661 if (vdd)
662 edp_panel_vdd_off(intel_dp, false);
663
e39b999a
VS		 664 mutex_unlock(&dev_priv->pps_mutex);
665
9ee32fea 666 return ret;
a4fc5ed6
KP		 667}
668
a6c8aff0
JN		 669#define BARE_ADDRESS_SIZE 3
670#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 671static ssize_t
672intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 673{
9d1a1031
JN		 674 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
675 uint8_t txbuf[20], rxbuf[20];
676 size_t txsize, rxsize;
a4fc5ed6 677 int ret;
a4fc5ed6 678
9d1a1031
JN		 679 txbuf[0] = msg->request << 4;
680 txbuf[1] = msg->address >> 8;
681 txbuf[2] = msg->address & 0xff;
682 txbuf[3] = msg->size - 1;
46a5ae9f 683
9d1a1031
JN		 684 switch (msg->request & ~DP_AUX_I2C_MOT) {
685 case DP_AUX_NATIVE_WRITE:
686 case DP_AUX_I2C_WRITE:
a6c8aff0 687 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 688 rxsize = 1;
f51a44b9 689
9d1a1031
JN		 690 if (WARN_ON(txsize > 20))
691 return -E2BIG;
a4fc5ed6 692
9d1a1031 693 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 694
9d1a1031
JN		 695 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
696 if (ret > 0) {
697 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 698
9d1a1031
JN		 699 /* Return payload size. */
700 ret = msg->size;
701 }
702 break;
46a5ae9f 703
9d1a1031
JN		 704 case DP_AUX_NATIVE_READ:
705 case DP_AUX_I2C_READ:
a6c8aff0 706 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 707 rxsize = msg->size + 1;
a4fc5ed6 708
9d1a1031
JN		 709 if (WARN_ON(rxsize > 20))
710 return -E2BIG;
a4fc5ed6 711
9d1a1031
JN		 712 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
713 if (ret > 0) {
714 msg->reply = rxbuf[0] >> 4;
715 /*
716 * Assume happy day, and copy the data. The caller is
717 * expected to check msg->reply before touching it.
718 *
719 * Return payload size.
720 */
721 ret--;
722 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 723 }
9d1a1031
JN		 724 break;
725
726 default:
727 ret = -EINVAL;
728 break;
a4fc5ed6 729 }
f51a44b9 730
9d1a1031 731 return ret;
a4fc5ed6
KP		 732}
733
9d1a1031
JN		 734static void
735intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
736{
737 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 738 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
739 enum port port = intel_dig_port->port;
0b99836f 740 const char *name = NULL;
ab2c0672
DA		 741 int ret;
742
33ad6626
JN		 743 switch (port) {
744 case PORT_A:
745 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 746 name = "DPDDC-A";
ab2c0672 747 break;
33ad6626
JN		 748 case PORT_B:
749 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 750 name = "DPDDC-B";
ab2c0672 751 break;
33ad6626
JN		 752 case PORT_C:
753 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 754 name = "DPDDC-C";
ab2c0672 755 break;
33ad6626
JN		 756 case PORT_D:
757 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 758 name = "DPDDC-D";
33ad6626
JN		 759 break;
760 default:
761 BUG();
ab2c0672
DA		 762 }
763
33ad6626
JN		 764 if (!HAS_DDI(dev))
765 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 766
0b99836f 767 intel_dp->aux.name = name;
9d1a1031
JN		 768 intel_dp->aux.dev = dev->dev;
769 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 770
0b99836f
JN		 771 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
772 connector->base.kdev->kobj.name);
8316f337 773
4f71d0cb 774 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 775 if (ret < 0) {
4f71d0cb 776 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 777 name, ret);
778 return;
ab2c0672 779 }
8a5e6aeb 780
0b99836f
JN		 781 ret = sysfs_create_link(&connector->base.kdev->kobj,
782 &intel_dp->aux.ddc.dev.kobj,
783 intel_dp->aux.ddc.dev.kobj.name);
784 if (ret < 0) {
785 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 786 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 787 }
a4fc5ed6
KP		 788}
789
80f65de3
ID		 790static void
791intel_dp_connector_unregister(struct intel_connector *intel_connector)
792{
793 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
794
0e32b39c
DA		 795 if (!intel_connector->mst_port)
796 sysfs_remove_link(&intel_connector->base.kdev->kobj,
797 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 798 intel_connector_unregister(intel_connector);
799}
800
0e50338c
DV		 801static void
802hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
803{
804 switch (link_bw) {
805 case DP_LINK_BW_1_62:
806 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
807 break;
808 case DP_LINK_BW_2_7:
809 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
810 break;
811 case DP_LINK_BW_5_4:
812 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
813 break;
814 }
815}
816
c6bb3538
DV		 817static void
818intel_dp_set_clock(struct intel_encoder *encoder,
819 struct intel_crtc_config *pipe_config, int link_bw)
820{
821 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 822 const struct dp_link_dpll *divisor = NULL;
823 int i, count = 0;
c6bb3538
DV		 824
825 if (IS_G4X(dev)) {
9dd4ffdf
CML		 826 divisor = gen4_dpll;
827 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 828 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 829 divisor = pch_dpll;
830 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 831 } else if (IS_CHERRYVIEW(dev)) {
832 divisor = chv_dpll;
833 count = ARRAY_SIZE(chv_dpll);
c6bb3538 834 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 835 divisor = vlv_dpll;
836 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 837 }
9dd4ffdf
CML		 838
839 if (divisor && count) {
840 for (i = 0; i < count; i++) {
841 if (link_bw == divisor[i].link_bw) {
842 pipe_config->dpll = divisor[i].dpll;
843 pipe_config->clock_set = true;
844 break;
845 }
846 }
c6bb3538
DV		 847 }
848}
849
00c09d70 850bool
5bfe2ac0
DV		 851intel_dp_compute_config(struct intel_encoder *encoder,
852 struct intel_crtc_config *pipe_config)
a4fc5ed6 853{
5bfe2ac0 854 struct drm_device *dev = encoder->base.dev;
36008365 855 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 856 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 857 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 858 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 859 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 860 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 861 int lane_count, clock;
56071a20 862 int min_lane_count = 1;
eeb6324d 863 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 864 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 865 int min_clock = 0;
06ea66b6 866 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 867 int bpp, mode_rate;
06ea66b6 868 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 869 int link_avail, link_clock;
a4fc5ed6 870
bc7d38a4 871 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 872 pipe_config->has_pch_encoder = true;
873
03afc4a2 874 pipe_config->has_dp_encoder = true;
f769cd24 875 pipe_config->has_drrs = false;
9ed109a7 876 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 877
dd06f90e
JN		 878 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
879 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
880 adjusted_mode);
2dd24552
JB		 881 if (!HAS_PCH_SPLIT(dev))
882 intel_gmch_panel_fitting(intel_crtc, pipe_config,
883 intel_connector->panel.fitting_mode);
884 else
b074cec8
JB		 885 intel_pch_panel_fitting(intel_crtc, pipe_config,
886 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 887 }
888
cb1793ce 889 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 890 return false;
891
083f9560
DV		 892 DRM_DEBUG_KMS("DP link computation with max lane count %i "
893 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 894 max_lane_count, bws[max_clock],
895 adjusted_mode->crtc_clock);
083f9560 896
36008365
DV		 897 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
898 * bpc in between. */
3e7ca985 899 bpp = pipe_config->pipe_bpp;
56071a20
JN		 900 if (is_edp(intel_dp)) {
901 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
902 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
903 dev_priv->vbt.edp_bpp);
904 bpp = dev_priv->vbt.edp_bpp;
905 }
906
f4cdbc21
JN		 907 if (IS_BROADWELL(dev)) {
908 /* Yes, it's an ugly hack. */
909 min_lane_count = max_lane_count;
910 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
911 min_lane_count);
912 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 913 min_lane_count = min(dev_priv->vbt.edp_lanes,
914 max_lane_count);
915 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
916 min_lane_count);
917 }
918
919 if (dev_priv->vbt.edp_rate) {
920 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
921 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
922 bws[min_clock]);
923 }
7984211e 924 }
657445fe 925
36008365 926 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 927 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
928 bpp);
36008365 929
c6930992
DA		 930 for (clock = min_clock; clock <= max_clock; clock++) {
931 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 932 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
933 link_avail = intel_dp_max_data_rate(link_clock,
934 lane_count);
935
936 if (mode_rate <= link_avail) {
937 goto found;
938 }
939 }
940 }
941 }
c4867936 942
36008365 943 return false;
3685a8f3 944
36008365 945found:
55bc60db
VS		 946 if (intel_dp->color_range_auto) {
947 /*
948 * See:
949 * CEA-861-E - 5.1 Default Encoding Parameters
950 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
951 */
18316c8c 952 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 953 intel_dp->color_range = DP_COLOR_RANGE_16_235;
954 else
955 intel_dp->color_range = 0;
956 }
957
3685a8f3 958 if (intel_dp->color_range)
50f3b016 959 pipe_config->limited_color_range = true;
a4fc5ed6 960
36008365
DV		 961 intel_dp->link_bw = bws[clock];
962 intel_dp->lane_count = lane_count;
657445fe 963 pipe_config->pipe_bpp = bpp;
ff9a6750 964 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 965
36008365
DV		 966 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
967 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 968 pipe_config->port_clock, bpp);
36008365
DV		 969 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
970 mode_rate, link_avail);
a4fc5ed6 971
03afc4a2 972 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 973 adjusted_mode->crtc_clock,
974 pipe_config->port_clock,
03afc4a2 975 &pipe_config->dp_m_n);
9d1a455b 976
439d7ac0
PB		 977 if (intel_connector->panel.downclock_mode != NULL &&
978 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 979 pipe_config->has_drrs = true;
439d7ac0
PB		 980 intel_link_compute_m_n(bpp, lane_count,
981 intel_connector->panel.downclock_mode->clock,
982 pipe_config->port_clock,
983 &pipe_config->dp_m2_n2);
984 }
985
ea155f32 986 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 987 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
988 else
989 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 990
03afc4a2 991 return true;
a4fc5ed6
KP		 992}
993
7c62a164 994static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 995{
7c62a164
DV		 996 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
997 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
998 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 999 struct drm_i915_private *dev_priv = dev->dev_private;
1000 u32 dpa_ctl;
1001
ff9a6750 1002 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 1003 dpa_ctl = I915_READ(DP_A);
1004 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1005
ff9a6750 1006 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 1007 /* For a long time we've carried around a ILK-DevA w/a for the
1008 * 160MHz clock. If we're really unlucky, it's still required.
1009 */
1010 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 1011 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 1012 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 1013 } else {
1014 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 1015 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 1016 }
1ce17038 1017
ea9b6006
DV		 1018 I915_WRITE(DP_A, dpa_ctl);
1019
1020 POSTING_READ(DP_A);
1021 udelay(500);
1022}
1023
8ac33ed3 1024static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1025{
b934223d 1026 struct drm_device *dev = encoder->base.dev;
417e822d 1027 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1028 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1029 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1030 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1031 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1032
417e822d 1033 /*
1a2eb460 1034 * There are four kinds of DP registers:
417e822d
KP		 1035 *
1036 * IBX PCH
1a2eb460
KP		 1037 * SNB CPU
1038 * IVB CPU
417e822d
KP		 1039 * CPT PCH
1040 *
1041 * IBX PCH and CPU are the same for almost everything,
1042 * except that the CPU DP PLL is configured in this
1043 * register
1044 *
1045 * CPT PCH is quite different, having many bits moved
1046 * to the TRANS_DP_CTL register instead. That
1047 * configuration happens (oddly) in ironlake_pch_enable
1048 */
9c9e7927 1049
417e822d
KP		 1050 /* Preserve the BIOS-computed detected bit. This is
1051 * supposed to be read-only.
1052 */
1053 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1054
417e822d 1055 /* Handle DP bits in common between all three register formats */
417e822d 1056 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1057 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1058
9ed109a7 1059 if (crtc->config.has_audio) {
e0dac65e 1060 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1061 pipe_name(crtc->pipe));
ea5b213a 1062 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1063 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1064 }
247d89f6 1065
417e822d 1066 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1067
bc7d38a4 1068 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1069 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1070 intel_dp->DP |= DP_SYNC_HS_HIGH;
1071 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1072 intel_dp->DP |= DP_SYNC_VS_HIGH;
1073 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1074
6aba5b6c 1075 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1076 intel_dp->DP |= DP_ENHANCED_FRAMING;
1077
7c62a164 1078 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1079 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1080 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1081 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1082
1083 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1084 intel_dp->DP |= DP_SYNC_HS_HIGH;
1085 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1086 intel_dp->DP |= DP_SYNC_VS_HIGH;
1087 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1088
6aba5b6c 1089 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1090 intel_dp->DP |= DP_ENHANCED_FRAMING;
1091
44f37d1f
CML		 1092 if (!IS_CHERRYVIEW(dev)) {
1093 if (crtc->pipe == 1)
1094 intel_dp->DP |= DP_PIPEB_SELECT;
1095 } else {
1096 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1097 }
417e822d
KP		 1098 } else {
1099 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1100 }
a4fc5ed6
KP		 1101}
1102
ffd6749d
PZ		 1103#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1104#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1105
1a5ef5b7
PZ		 1106#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1107#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1108
ffd6749d
PZ		 1109#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1110#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1111
4be73780 1112static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1113 u32 mask,
1114 u32 value)
bd943159 1115{
30add22d 1116 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1117 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1118 u32 pp_stat_reg, pp_ctrl_reg;
1119
e39b999a
VS		 1120 lockdep_assert_held(&dev_priv->pps_mutex);
1121
bf13e81b
JN		 1122 pp_stat_reg = _pp_stat_reg(intel_dp);
1123 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1124
99ea7127 1125 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1126 mask, value,
1127 I915_READ(pp_stat_reg),
1128 I915_READ(pp_ctrl_reg));
32ce697c 1129
453c5420 1130 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1131 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1132 I915_READ(pp_stat_reg),
1133 I915_READ(pp_ctrl_reg));
32ce697c 1134 }
54c136d4
CW		 1135
1136 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1137}
32ce697c 1138
4be73780 1139static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1140{
1141 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1142 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1143}
1144
4be73780 1145static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1146{
1147 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1148 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1149}
1150
4be73780 1151static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1152{
1153 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1154
1155 /* When we disable the VDD override bit last we have to do the manual
1156 * wait. */
1157 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1158 intel_dp->panel_power_cycle_delay);
1159
4be73780 1160 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1161}
1162
4be73780 1163static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1164{
1165 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1166 intel_dp->backlight_on_delay);
1167}
1168
4be73780 1169static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1170{
1171 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1172 intel_dp->backlight_off_delay);
1173}
99ea7127 1174
832dd3c1
KP		 1175/* Read the current pp_control value, unlocking the register if it
1176 * is locked
1177 */
1178
453c5420 1179static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1180{
453c5420
JB		 1181 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1182 struct drm_i915_private *dev_priv = dev->dev_private;
1183 u32 control;
832dd3c1 1184
e39b999a
VS		 1185 lockdep_assert_held(&dev_priv->pps_mutex);
1186
bf13e81b 1187 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1188 control &= ~PANEL_UNLOCK_MASK;
1189 control |= PANEL_UNLOCK_REGS;
1190 return control;
bd943159
KP		 1191}
1192
1e0560e0 1193static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1194{
30add22d 1195 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1196 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1197 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1198 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1199 enum intel_display_power_domain power_domain;
5d613501 1200 u32 pp;
453c5420 1201 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1202 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1203
e39b999a
VS		 1204 lockdep_assert_held(&dev_priv->pps_mutex);
1205
97af61f5 1206 if (!is_edp(intel_dp))
adddaaf4 1207 return false;
bd943159
KP		 1208
1209 intel_dp->want_panel_vdd = true;
99ea7127 1210
4be73780 1211 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1212 return need_to_disable;
b0665d57 1213
4e6e1a54
ID		 1214 power_domain = intel_display_port_power_domain(intel_encoder);
1215 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1216
b0665d57 1217 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1218
4be73780
DV		 1219 if (!edp_have_panel_power(intel_dp))
1220 wait_panel_power_cycle(intel_dp);
99ea7127 1221
453c5420 1222 pp = ironlake_get_pp_control(intel_dp);
5d613501 1223 pp |= EDP_FORCE_VDD;
ebf33b18 1224
bf13e81b
JN		 1225 pp_stat_reg = _pp_stat_reg(intel_dp);
1226 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1227
1228 I915_WRITE(pp_ctrl_reg, pp);
1229 POSTING_READ(pp_ctrl_reg);
1230 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1231 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1232 /*
1233 * If the panel wasn't on, delay before accessing aux channel
1234 */
4be73780 1235 if (!edp_have_panel_power(intel_dp)) {
bd943159 1236 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1237 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1238 }
adddaaf4
JN		 1239
1240 return need_to_disable;
1241}
1242
b80d6c78 1243void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4 1244{
e39b999a
VS		 1245 struct drm_i915_private *dev_priv =
1246 intel_dp_to_dev(intel_dp)->dev_private;
c695b6b6 1247 bool vdd;
adddaaf4 1248
c695b6b6
VS		 1249 if (!is_edp(intel_dp))
1250 return;
1251
e39b999a 1252 mutex_lock(&dev_priv->pps_mutex);
c695b6b6 1253 vdd = edp_panel_vdd_on(intel_dp);
e39b999a 1254 mutex_unlock(&dev_priv->pps_mutex);
c695b6b6
VS		 1255
1256 WARN(!vdd, "eDP VDD already requested on\n");
5d613501
JB		 1257}
1258
4be73780 1259static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1260{
30add22d 1261 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501 1262 struct drm_i915_private *dev_priv = dev->dev_private;
be2c9196
VS		 1263 struct intel_digital_port *intel_dig_port =
1264 dp_to_dig_port(intel_dp);
1265 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1266 enum intel_display_power_domain power_domain;
5d613501 1267 u32 pp;
453c5420 1268 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1269
e39b999a 1270 lockdep_assert_held(&dev_priv->pps_mutex);
a0e99e68 1271
15e899a0
VS		 1272 WARN_ON(intel_dp->want_panel_vdd);
1273
1274 if (!edp_have_panel_vdd(intel_dp))
be2c9196 1275 return;
4e6e1a54 1276
be2c9196 1277 DRM_DEBUG_KMS("Turning eDP VDD off\n");
b0665d57 1278
be2c9196
VS		 1279 pp = ironlake_get_pp_control(intel_dp);
1280 pp &= ~EDP_FORCE_VDD;
bd943159 1281
be2c9196
VS		 1282 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1283 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420 1284
be2c9196
VS		 1285 I915_WRITE(pp_ctrl_reg, pp);
1286 POSTING_READ(pp_ctrl_reg);
99ea7127 1287
be2c9196
VS		 1288 /* Make sure sequencer is idle before allowing subsequent activity */
1289 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1290 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c 1291
be2c9196
VS		 1292 if ((pp & POWER_TARGET_ON) == 0)
1293 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1294
be2c9196
VS		 1295 power_domain = intel_display_port_power_domain(intel_encoder);
1296 intel_display_power_put(dev_priv, power_domain);
bd943159 1297}
5d613501 1298
4be73780 1299static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1300{
1301 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1302 struct intel_dp, panel_vdd_work);
e39b999a
VS		 1303 struct drm_i915_private *dev_priv =
1304 intel_dp_to_dev(intel_dp)->dev_private;
bd943159 1305
e39b999a 1306 mutex_lock(&dev_priv->pps_mutex);
15e899a0
VS		 1307 if (!intel_dp->want_panel_vdd)
1308 edp_panel_vdd_off_sync(intel_dp);
e39b999a 1309 mutex_unlock(&dev_priv->pps_mutex);
bd943159
KP		 1310}
1311
aba86890
ID		 1312static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1313{
1314 unsigned long delay;
1315
1316 /*
1317 * Queue the timer to fire a long time from now (relative to the power
1318 * down delay) to keep the panel power up across a sequence of
1319 * operations.
1320 */
1321 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1322 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1323}
1324
4be73780 1325static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1326{
e39b999a
VS		 1327 struct drm_i915_private *dev_priv =
1328 intel_dp_to_dev(intel_dp)->dev_private;
1329
1330 lockdep_assert_held(&dev_priv->pps_mutex);
1331
97af61f5
KP		 1332 if (!is_edp(intel_dp))
1333 return;
5d613501 1334
bd943159 1335 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1336
bd943159
KP		 1337 intel_dp->want_panel_vdd = false;
1338
aba86890 1339 if (sync)
4be73780 1340 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1341 else
1342 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1343}
1344
1e0560e0
VS		 1345static void intel_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1346{
e39b999a
VS		 1347 struct drm_i915_private *dev_priv =
1348 intel_dp_to_dev(intel_dp)->dev_private;
1349
1350 if (!is_edp(intel_dp))
1351 return;
1352
1353 mutex_lock(&dev_priv->pps_mutex);
1e0560e0 1354 edp_panel_vdd_off(intel_dp, sync);
e39b999a 1355 mutex_unlock(&dev_priv->pps_mutex);
1e0560e0
VS		 1356}
1357
4be73780 1358void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1359{
30add22d 1360 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1361 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1362 u32 pp;
453c5420 1363 u32 pp_ctrl_reg;
9934c132 1364
97af61f5 1365 if (!is_edp(intel_dp))
bd943159 1366 return;
99ea7127
KP		 1367
1368 DRM_DEBUG_KMS("Turn eDP power on\n");
1369
e39b999a
VS		 1370 mutex_lock(&dev_priv->pps_mutex);
1371
4be73780 1372 if (edp_have_panel_power(intel_dp)) {
99ea7127 1373 DRM_DEBUG_KMS("eDP power already on\n");
e39b999a 1374 goto out;
99ea7127 1375 }
9934c132 1376
4be73780 1377 wait_panel_power_cycle(intel_dp);
37c6c9b0 1378
bf13e81b 1379 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1380 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1381 if (IS_GEN5(dev)) {
1382 /* ILK workaround: disable reset around power sequence */
1383 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1384 I915_WRITE(pp_ctrl_reg, pp);
1385 POSTING_READ(pp_ctrl_reg);
05ce1a49 1386 }
37c6c9b0 1387
1c0ae80a 1388 pp |= POWER_TARGET_ON;
99ea7127
KP		 1389 if (!IS_GEN5(dev))
1390 pp |= PANEL_POWER_RESET;
1391
453c5420
JB		 1392 I915_WRITE(pp_ctrl_reg, pp);
1393 POSTING_READ(pp_ctrl_reg);
9934c132 1394
4be73780 1395 wait_panel_on(intel_dp);
dce56b3c 1396 intel_dp->last_power_on = jiffies;
9934c132 1397
05ce1a49
KP		 1398 if (IS_GEN5(dev)) {
1399 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1400 I915_WRITE(pp_ctrl_reg, pp);
1401 POSTING_READ(pp_ctrl_reg);
05ce1a49 1402 }
e39b999a
VS		 1403
1404 out:
1405 mutex_unlock(&dev_priv->pps_mutex);
9934c132
JB		 1406}
1407
4be73780 1408void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1409{
4e6e1a54
ID		 1410 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1411 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1412 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1413 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1414 enum intel_display_power_domain power_domain;
99ea7127 1415 u32 pp;
453c5420 1416 u32 pp_ctrl_reg;
9934c132 1417
97af61f5
KP		 1418 if (!is_edp(intel_dp))
1419 return;
37c6c9b0 1420
99ea7127 1421 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1422
e39b999a
VS		 1423 mutex_lock(&dev_priv->pps_mutex);
1424
24f3e092
JN		 1425 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1426
453c5420 1427 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1428 /* We need to switch off panel power _and_ force vdd, for otherwise some
1429 * panels get very unhappy and cease to work. */
b3064154
PJ		 1430 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1431 EDP_BLC_ENABLE);
453c5420 1432
bf13e81b 1433 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1434
849e39f5
PZ		 1435 intel_dp->want_panel_vdd = false;
1436
453c5420
JB		 1437 I915_WRITE(pp_ctrl_reg, pp);
1438 POSTING_READ(pp_ctrl_reg);
9934c132 1439
dce56b3c 1440 intel_dp->last_power_cycle = jiffies;
4be73780 1441 wait_panel_off(intel_dp);
849e39f5
PZ		 1442
1443 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1444 power_domain = intel_display_port_power_domain(intel_encoder);
1445 intel_display_power_put(dev_priv, power_domain);
e39b999a
VS		 1446
1447 mutex_unlock(&dev_priv->pps_mutex);
9934c132
JB		 1448}
1449
1250d107
JN		 1450/* Enable backlight in the panel power control. */
1451static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1452{
da63a9f2
PZ		 1453 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1454 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1455 struct drm_i915_private *dev_priv = dev->dev_private;
1456 u32 pp;
453c5420 1457 u32 pp_ctrl_reg;
32f9d658 1458
01cb9ea6
JB		 1459 /*
1460 * If we enable the backlight right away following a panel power
1461 * on, we may see slight flicker as the panel syncs with the eDP
1462 * link. So delay a bit to make sure the image is solid before
1463 * allowing it to appear.
1464 */
4be73780 1465 wait_backlight_on(intel_dp);
e39b999a
VS		 1466
1467 mutex_lock(&dev_priv->pps_mutex);
1468
453c5420 1469 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1470 pp |= EDP_BLC_ENABLE;
453c5420 1471
bf13e81b 1472 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1473
1474 I915_WRITE(pp_ctrl_reg, pp);
1475 POSTING_READ(pp_ctrl_reg);
e39b999a
VS		 1476
1477 mutex_unlock(&dev_priv->pps_mutex);
32f9d658
ZW		 1478}
1479
1250d107
JN		 1480/* Enable backlight PWM and backlight PP control. */
1481void intel_edp_backlight_on(struct intel_dp *intel_dp)
1482{
1483 if (!is_edp(intel_dp))
1484 return;
1485
1486 DRM_DEBUG_KMS("\n");
1487
1488 intel_panel_enable_backlight(intel_dp->attached_connector);
1489 _intel_edp_backlight_on(intel_dp);
1490}
1491
1492/* Disable backlight in the panel power control. */
1493static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1494{
30add22d 1495 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497 u32 pp;
453c5420 1498 u32 pp_ctrl_reg;
32f9d658 1499
e39b999a
VS		 1500 if (!is_edp(intel_dp))
1501 return;
1502
1503 mutex_lock(&dev_priv->pps_mutex);
1504
453c5420 1505 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1506 pp &= ~EDP_BLC_ENABLE;
453c5420 1507
bf13e81b 1508 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1509
1510 I915_WRITE(pp_ctrl_reg, pp);
1511 POSTING_READ(pp_ctrl_reg);
f7d2323c 1512
e39b999a
VS		 1513 mutex_unlock(&dev_priv->pps_mutex);
1514
1515 intel_dp->last_backlight_off = jiffies;
f7d2323c 1516 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1517}
1518
1519/* Disable backlight PP control and backlight PWM. */
1520void intel_edp_backlight_off(struct intel_dp *intel_dp)
1521{
1522 if (!is_edp(intel_dp))
1523 return;
1524
1525 DRM_DEBUG_KMS("\n");
f7d2323c 1526
1250d107 1527 _intel_edp_backlight_off(intel_dp);
f7d2323c 1528 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1529}
a4fc5ed6 1530
73580fb7
JN		 1531/*
1532 * Hook for controlling the panel power control backlight through the bl_power
1533 * sysfs attribute. Take care to handle multiple calls.
1534 */
1535static void intel_edp_backlight_power(struct intel_connector *connector,
1536 bool enable)
1537{
e39b999a 1538 struct drm_i915_private *dev_priv = connector->base.dev->dev_private;
73580fb7 1539 struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
e39b999a
VS		 1540 bool is_enabled;
1541
1542 mutex_lock(&dev_priv->pps_mutex);
1543 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1544 mutex_unlock(&dev_priv->pps_mutex);
73580fb7
JN		 1545
1546 if (is_enabled == enable)
1547 return;
1548
23ba9373
JN		 1549 DRM_DEBUG_KMS("panel power control backlight %s\n",
1550 enable ? "enable" : "disable");
73580fb7
JN		 1551
1552 if (enable)
1553 _intel_edp_backlight_on(intel_dp);
1554 else
1555 _intel_edp_backlight_off(intel_dp);
1556}
1557
2bd2ad64 1558static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1559{
da63a9f2
PZ		 1560 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1561 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1562 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1563 struct drm_i915_private *dev_priv = dev->dev_private;
1564 u32 dpa_ctl;
1565
2bd2ad64
DV		 1566 assert_pipe_disabled(dev_priv,
1567 to_intel_crtc(crtc)->pipe);
1568
d240f20f
JB		 1569 DRM_DEBUG_KMS("\n");
1570 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1571 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1572 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1573
1574 /* We don't adjust intel_dp->DP while tearing down the link, to
1575 * facilitate link retraining (e.g. after hotplug). Hence clear all
1576 * enable bits here to ensure that we don't enable too much. */
1577 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1578 intel_dp->DP |= DP_PLL_ENABLE;
1579 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1580 POSTING_READ(DP_A);
1581 udelay(200);
d240f20f
JB		 1582}
1583
2bd2ad64 1584static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1585{
da63a9f2
PZ		 1586 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1587 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1588 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1589 struct drm_i915_private *dev_priv = dev->dev_private;
1590 u32 dpa_ctl;
1591
2bd2ad64
DV		 1592 assert_pipe_disabled(dev_priv,
1593 to_intel_crtc(crtc)->pipe);
1594
d240f20f 1595 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1596 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1597 "dp pll off, should be on\n");
1598 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1599
1600 /* We can't rely on the value tracked for the DP register in
1601 * intel_dp->DP because link_down must not change that (otherwise link
1602 * re-training will fail. */
298b0b39 1603 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1604 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1605 POSTING_READ(DP_A);
d240f20f
JB		 1606 udelay(200);
1607}
1608
c7ad3810 1609/* If the sink supports it, try to set the power state appropriately */
c19b0669 1610void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1611{
1612 int ret, i;
1613
1614 /* Should have a valid DPCD by this point */
1615 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1616 return;
1617
1618 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1619 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1620 DP_SET_POWER_D3);
c7ad3810
JB		 1621 } else {
1622 /*
1623 * When turning on, we need to retry for 1ms to give the sink
1624 * time to wake up.
1625 */
1626 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1627 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1628 DP_SET_POWER_D0);
c7ad3810
JB		 1629 if (ret == 1)
1630 break;
1631 msleep(1);
1632 }
1633 }
f9cac721
JN		 1634
1635 if (ret != 1)
1636 DRM_DEBUG_KMS("failed to %s sink power state\n",
1637 mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
c7ad3810
JB		 1638}
1639
19d8fe15
DV		 1640static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1641 enum pipe *pipe)
d240f20f 1642{
19d8fe15 1643 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1644 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1645 struct drm_device *dev = encoder->base.dev;
1646 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1647 enum intel_display_power_domain power_domain;
1648 u32 tmp;
1649
1650 power_domain = intel_display_port_power_domain(encoder);
1651 if (!intel_display_power_enabled(dev_priv, power_domain))
1652 return false;
1653
1654 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1655
1656 if (!(tmp & DP_PORT_EN))
1657 return false;
1658
bc7d38a4 1659 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1660 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1661 } else if (IS_CHERRYVIEW(dev)) {
1662 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1663 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1664 *pipe = PORT_TO_PIPE(tmp);
1665 } else {
1666 u32 trans_sel;
1667 u32 trans_dp;
1668 int i;
1669
1670 switch (intel_dp->output_reg) {
1671 case PCH_DP_B:
1672 trans_sel = TRANS_DP_PORT_SEL_B;
1673 break;
1674 case PCH_DP_C:
1675 trans_sel = TRANS_DP_PORT_SEL_C;
1676 break;
1677 case PCH_DP_D:
1678 trans_sel = TRANS_DP_PORT_SEL_D;
1679 break;
1680 default:
1681 return true;
1682 }
1683
055e393f 1684 for_each_pipe(dev_priv, i) {
19d8fe15
DV		 1685 trans_dp = I915_READ(TRANS_DP_CTL(i));
1686 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1687 *pipe = i;
1688 return true;
1689 }
1690 }
19d8fe15 1691
4a0833ec
DV		 1692 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1693 intel_dp->output_reg);
1694 }
d240f20f 1695
19d8fe15
DV		 1696 return true;
1697}
d240f20f 1698
045ac3b5
JB		 1699static void intel_dp_get_config(struct intel_encoder *encoder,
1700 struct intel_crtc_config *pipe_config)
1701{
1702 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1703 u32 tmp, flags = 0;
63000ef6
XZ		 1704 struct drm_device *dev = encoder->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 enum port port = dp_to_dig_port(intel_dp)->port;
1707 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1708 int dotclock;
045ac3b5 1709
9ed109a7
DV		 1710 tmp = I915_READ(intel_dp->output_reg);
1711 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1712 pipe_config->has_audio = true;
1713
63000ef6 1714 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1715 if (tmp & DP_SYNC_HS_HIGH)
1716 flags |= DRM_MODE_FLAG_PHSYNC;
1717 else
1718 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1719
63000ef6
XZ		 1720 if (tmp & DP_SYNC_VS_HIGH)
1721 flags |= DRM_MODE_FLAG_PVSYNC;
1722 else
1723 flags |= DRM_MODE_FLAG_NVSYNC;
1724 } else {
1725 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1726 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1727 flags |= DRM_MODE_FLAG_PHSYNC;
1728 else
1729 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1730
63000ef6
XZ		 1731 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1732 flags |= DRM_MODE_FLAG_PVSYNC;
1733 else
1734 flags |= DRM_MODE_FLAG_NVSYNC;
1735 }
045ac3b5
JB		 1736
1737 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1738
eb14cb74
VS		 1739 pipe_config->has_dp_encoder = true;
1740
1741 intel_dp_get_m_n(crtc, pipe_config);
1742
18442d08 1743 if (port == PORT_A) {
f1f644dc
JB		 1744 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1745 pipe_config->port_clock = 162000;
1746 else
1747 pipe_config->port_clock = 270000;
1748 }
18442d08
VS		 1749
1750 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1751 &pipe_config->dp_m_n);
1752
1753 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1754 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1755
241bfc38 1756 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1757
c6cd2ee2
JN		 1758 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1759 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1760 /*
1761 * This is a big fat ugly hack.
1762 *
1763 * Some machines in UEFI boot mode provide us a VBT that has 18
1764 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1765 * unknown we fail to light up. Yet the same BIOS boots up with
1766 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1767 * max, not what it tells us to use.
1768 *
1769 * Note: This will still be broken if the eDP panel is not lit
1770 * up by the BIOS, and thus we can't get the mode at module
1771 * load.
1772 */
1773 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1774 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1775 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1776 }
045ac3b5
JB		 1777}
1778
34eb7579 1779static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1780{
34eb7579 1781 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1782}
1783
2b28bb1b
RV		 1784static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1785{
1786 struct drm_i915_private *dev_priv = dev->dev_private;
1787
18b5992c 1788 if (!HAS_PSR(dev))
2b28bb1b
RV		 1789 return false;
1790
18b5992c 1791 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1792}
1793
1794static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1795 struct edp_vsc_psr *vsc_psr)
1796{
1797 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1798 struct drm_device *dev = dig_port->base.base.dev;
1799 struct drm_i915_private *dev_priv = dev->dev_private;
1800 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1801 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1802 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1803 uint32_t *data = (uint32_t *) vsc_psr;
1804 unsigned int i;
1805
1806 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1807 the video DIP being updated before program video DIP data buffer
1808 registers for DIP being updated. */
1809 I915_WRITE(ctl_reg, 0);
1810 POSTING_READ(ctl_reg);
1811
1812 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1813 if (i < sizeof(struct edp_vsc_psr))
1814 I915_WRITE(data_reg + i, *data++);
1815 else
1816 I915_WRITE(data_reg + i, 0);
1817 }
1818
1819 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1820 POSTING_READ(ctl_reg);
1821}
1822
1823static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1824{
1825 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1826 struct drm_i915_private *dev_priv = dev->dev_private;
1827 struct edp_vsc_psr psr_vsc;
1828
2b28bb1b
RV		 1829 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1830 memset(&psr_vsc, 0, sizeof(psr_vsc));
1831 psr_vsc.sdp_header.HB0 = 0;
1832 psr_vsc.sdp_header.HB1 = 0x7;
1833 psr_vsc.sdp_header.HB2 = 0x2;
1834 psr_vsc.sdp_header.HB3 = 0x8;
1835 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1836
1837 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1838 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1839 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1840}
1841
1842static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1843{
0e0ae652
RV		 1844 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1845 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1846 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1847 uint32_t aux_clock_divider;
2b28bb1b
RV		 1848 int precharge = 0x3;
1849 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1850 bool only_standby = false;
2b28bb1b 1851
ec5b01dd
DL		 1852 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1853
0e0ae652
RV		 1854 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1855 only_standby = true;
1856
2b28bb1b 1857 /* Enable PSR in sink */
0e0ae652 1858 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1859 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1860 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1861 else
9d1a1031
JN		 1862 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1863 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1864
1865 /* Setup AUX registers */
18b5992c
BW		 1866 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1867 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1868 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1869 DP_AUX_CH_CTL_TIME_OUT_400us |
1870 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1871 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1872 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1873}
1874
1875static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1876{
0e0ae652
RV		 1877 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1878 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 uint32_t max_sleep_time = 0x1f;
1881 uint32_t idle_frames = 1;
1882 uint32_t val = 0x0;
ed8546ac 1883 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1884 bool only_standby = false;
1885
1886 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1887 only_standby = true;
2b28bb1b 1888
0e0ae652 1889 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1890 val |= EDP_PSR_LINK_STANDBY;
1891 val |= EDP_PSR_TP2_TP3_TIME_0us;
1892 val |= EDP_PSR_TP1_TIME_0us;
1893 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1894 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1895 } else
1896 val |= EDP_PSR_LINK_DISABLE;
1897
18b5992c 1898 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1899 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1900 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1901 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1902 EDP_PSR_ENABLE);
1903}
1904
3f51e471
RV		 1905static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1906{
1907 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1908 struct drm_device *dev = dig_port->base.base.dev;
1909 struct drm_i915_private *dev_priv = dev->dev_private;
1910 struct drm_crtc *crtc = dig_port->base.base.crtc;
1911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1912
f0355c4a 1913 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1914 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1915 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1916
a031d709
RV		 1917 dev_priv->psr.source_ok = false;
1918
9ca15301 1919 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1920 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1921 return false;
1922 }
1923
d330a953 1924 if (!i915.enable_psr) {
105b7c11 1925 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1926 return false;
1927 }
1928
4c8c7000
RV		 1929 /* Below limitations aren't valid for Broadwell */
1930 if (IS_BROADWELL(dev))
1931 goto out;
1932
3f51e471
RV		 1933 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1934 S3D_ENABLE) {
1935 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1936 return false;
1937 }
1938
ca73b4f0 1939 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1940 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1941 return false;
1942 }
1943
4c8c7000 1944 out:
a031d709 1945 dev_priv->psr.source_ok = true;
3f51e471
RV		 1946 return true;
1947}
1948
3d739d92 1949static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1950{
7c8f8a70
RV		 1951 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1952 struct drm_device *dev = intel_dig_port->base.base.dev;
1953 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1954
3638379c
DV		 1955 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1956 WARN_ON(dev_priv->psr.active);
f0355c4a 1957 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1958
2b28bb1b
RV		 1959 /* Enable PSR on the panel */
1960 intel_edp_psr_enable_sink(intel_dp);
1961
1962 /* Enable PSR on the host */
1963 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1964
7c8f8a70 1965 dev_priv->psr.active = true;
2b28bb1b
RV		 1966}
1967
3d739d92
RV		 1968void intel_edp_psr_enable(struct intel_dp *intel_dp)
1969{
1970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1971 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1972
4704c573
RV		 1973 if (!HAS_PSR(dev)) {
1974 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1975 return;
1976 }
1977
34eb7579
RV		 1978 if (!is_edp_psr(intel_dp)) {
1979 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1980 return;
1981 }
1982
f0355c4a 1983 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1984 if (dev_priv->psr.enabled) {
1985 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1986 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1987 return;
1988 }
1989
9ca15301
DV		 1990 dev_priv->psr.busy_frontbuffer_bits = 0;
1991
16487254
RV		 1992 /* Setup PSR once */
1993 intel_edp_psr_setup(intel_dp);
1994
7c8f8a70 1995 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1996 dev_priv->psr.enabled = intel_dp;
f0355c4a 1997 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1998}
1999
2b28bb1b
RV		 2000void intel_edp_psr_disable(struct intel_dp *intel_dp)
2001{
2002 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2003 struct drm_i915_private *dev_priv = dev->dev_private;
2004
f0355c4a
DV		 2005 mutex_lock(&dev_priv->psr.lock);
2006 if (!dev_priv->psr.enabled) {
2007 mutex_unlock(&dev_priv->psr.lock);
2008 return;
2009 }
2010
3638379c
DV		 2011 if (dev_priv->psr.active) {
2012 I915_WRITE(EDP_PSR_CTL(dev),
2013 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
2014
2015 /* Wait till PSR is idle */
2016 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
2017 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
2018 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 2019
3638379c
DV		 2020 dev_priv->psr.active = false;
2021 } else {
2022 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
2023 }
7c8f8a70 2024
2807cf69 2025 dev_priv->psr.enabled = NULL;
f0355c4a 2026 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 2027
2028 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 2029}
2030
f02a326e 2031static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 2032{
2033 struct drm_i915_private *dev_priv =
2034 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 2035 struct intel_dp *intel_dp = dev_priv->psr.enabled;
2036
f0355c4a
DV		 2037 mutex_lock(&dev_priv->psr.lock);
2038 intel_dp = dev_priv->psr.enabled;
2039
2807cf69 2040 if (!intel_dp)
f0355c4a 2041 goto unlock;
2807cf69 2042
9ca15301
DV		 2043 /*
2044 * The delayed work can race with an invalidate hence we need to
2045 * recheck. Since psr_flush first clears this and then reschedules we
2046 * won't ever miss a flush when bailing out here.
2047 */
2048 if (dev_priv->psr.busy_frontbuffer_bits)
2049 goto unlock;
2050
2051 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 2052unlock:
2053 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 2054}
2055
9ca15301 2056static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 2057{
2058 struct drm_i915_private *dev_priv = dev->dev_private;
2059
3638379c
DV		 2060 if (dev_priv->psr.active) {
2061 u32 val = I915_READ(EDP_PSR_CTL(dev));
2062
2063 WARN_ON(!(val & EDP_PSR_ENABLE));
2064
2065 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
2066
2067 dev_priv->psr.active = false;
2068 }
7c8f8a70 2069
9ca15301
DV		 2070}
2071
2072void intel_edp_psr_invalidate(struct drm_device *dev,
2073 unsigned frontbuffer_bits)
2074{
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct drm_crtc *crtc;
2077 enum pipe pipe;
2078
9ca15301
DV		 2079 mutex_lock(&dev_priv->psr.lock);
2080 if (!dev_priv->psr.enabled) {
2081 mutex_unlock(&dev_priv->psr.lock);
2082 return;
2083 }
2084
2085 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2086 pipe = to_intel_crtc(crtc)->pipe;
2087
2088 intel_edp_psr_do_exit(dev);
2089
2090 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
2091
2092 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
2093 mutex_unlock(&dev_priv->psr.lock);
2094}
2095
2096void intel_edp_psr_flush(struct drm_device *dev,
2097 unsigned frontbuffer_bits)
2098{
2099 struct drm_i915_private *dev_priv = dev->dev_private;
2100 struct drm_crtc *crtc;
2101 enum pipe pipe;
2102
9ca15301
DV		 2103 mutex_lock(&dev_priv->psr.lock);
2104 if (!dev_priv->psr.enabled) {
2105 mutex_unlock(&dev_priv->psr.lock);
2106 return;
2107 }
2108
2109 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2110 pipe = to_intel_crtc(crtc)->pipe;
2111 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2112
2113 /*
2114 * On Haswell sprite plane updates don't result in a psr invalidating
2115 * signal in the hardware. Which means we need to manually fake this in
2116 * software for all flushes, not just when we've seen a preceding
2117 * invalidation through frontbuffer rendering.
2118 */
2119 if (IS_HASWELL(dev) &&
2120 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2121 intel_edp_psr_do_exit(dev);
2122
2123 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2124 schedule_delayed_work(&dev_priv->psr.work,
2125 msecs_to_jiffies(100));
f0355c4a 2126 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2127}
2128
2129void intel_edp_psr_init(struct drm_device *dev)
2130{
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132
7c8f8a70 2133 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2134 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2135}
2136
e8cb4558 2137static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2138{
e8cb4558 2139 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2140 enum port port = dp_to_dig_port(intel_dp)->port;
2141 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2142
2143 /* Make sure the panel is off before trying to change the mode. But also
2144 * ensure that we have vdd while we switch off the panel. */
24f3e092 2145 intel_edp_panel_vdd_on(intel_dp);
4be73780 2146 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2147 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2148 intel_edp_panel_off(intel_dp);
3739850b
DV		 2149
2150 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2151 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2152 intel_dp_link_down(intel_dp);
d240f20f
JB		 2153}
2154
49277c31 2155static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2156{
2bd2ad64 2157 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2158 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2159
49277c31
VS		 2160 if (port != PORT_A)
2161 return;
2162
2163 intel_dp_link_down(intel_dp);
2164 ironlake_edp_pll_off(intel_dp);
2165}
2166
2167static void vlv_post_disable_dp(struct intel_encoder *encoder)
2168{
2169 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2170
2171 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2172}
2173
580d3811
VS		 2174static void chv_post_disable_dp(struct intel_encoder *encoder)
2175{
2176 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2177 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2178 struct drm_device *dev = encoder->base.dev;
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 struct intel_crtc *intel_crtc =
2181 to_intel_crtc(encoder->base.crtc);
2182 enum dpio_channel ch = vlv_dport_to_channel(dport);
2183 enum pipe pipe = intel_crtc->pipe;
2184 u32 val;
2185
2186 intel_dp_link_down(intel_dp);
2187
2188 mutex_lock(&dev_priv->dpio_lock);
2189
2190 /* Propagate soft reset to data lane reset */
97fd4d5c 2191 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2192 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2193 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2194
97fd4d5c
VS		 2195 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2196 val |= CHV_PCS_REQ_SOFTRESET_EN;
2197 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2198
2199 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2200 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2201 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2202
2203 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2204 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2205 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2206
2207 mutex_unlock(&dev_priv->dpio_lock);
2208}
2209
e8cb4558 2210static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2211{
e8cb4558
DV		 2212 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2213 struct drm_device *dev = encoder->base.dev;
2214 struct drm_i915_private *dev_priv = dev->dev_private;
2215 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2216
0c33d8d7
DV		 2217 if (WARN_ON(dp_reg & DP_PORT_EN))
2218 return;
5d613501 2219
24f3e092 2220 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2221 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2222 intel_dp_start_link_train(intel_dp);
4be73780 2223 intel_edp_panel_on(intel_dp);
1e0560e0 2224 intel_edp_panel_vdd_off(intel_dp, true);
33a34e4e 2225 intel_dp_complete_link_train(intel_dp);
3ab9c637 2226 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2227}
89b667f8 2228
ecff4f3b
JN		 2229static void g4x_enable_dp(struct intel_encoder *encoder)
2230{
828f5c6e
JN		 2231 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2232
ecff4f3b 2233 intel_enable_dp(encoder);
4be73780 2234 intel_edp_backlight_on(intel_dp);
ab1f90f9 2235}
89b667f8 2236
ab1f90f9
JN		 2237static void vlv_enable_dp(struct intel_encoder *encoder)
2238{
828f5c6e
JN		 2239 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2240
4be73780 2241 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2242}
2243
ecff4f3b 2244static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2245{
2246 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2247 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2248
8ac33ed3
DV		 2249 intel_dp_prepare(encoder);
2250
d41f1efb
DV		 2251 /* Only ilk+ has port A */
2252 if (dport->port == PORT_A) {
2253 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2254 ironlake_edp_pll_on(intel_dp);
d41f1efb 2255 }
ab1f90f9
JN		 2256}
2257
2258static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2259{
2bd2ad64 2260 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2261 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2262 struct drm_device *dev = encoder->base.dev;
89b667f8 2263 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2264 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2265 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2266 int pipe = intel_crtc->pipe;
bf13e81b 2267 struct edp_power_seq power_seq;
ab1f90f9 2268 u32 val;
a4fc5ed6 2269
ab1f90f9 2270 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2271
ab3c759a 2272 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2273 val = 0;
2274 if (pipe)
2275 val |= (1<<21);
2276 else
2277 val &= ~(1<<21);
2278 val |= 0x001000c4;
ab3c759a
CML		 2279 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2280 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2281 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2282
ab1f90f9
JN		 2283 mutex_unlock(&dev_priv->dpio_lock);
2284
2cac613b
ID		 2285 if (is_edp(intel_dp)) {
2286 /* init power sequencer on this pipe and port */
e39b999a 2287 mutex_lock(&dev_priv->pps_mutex);
2cac613b
ID		 2288 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2289 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2290 &power_seq);
e39b999a 2291 mutex_unlock(&dev_priv->pps_mutex);
2cac613b 2292 }
bf13e81b 2293
ab1f90f9
JN		 2294 intel_enable_dp(encoder);
2295
e4607fcf 2296 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2297}
2298
ecff4f3b 2299static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2300{
2301 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2302 struct drm_device *dev = encoder->base.dev;
2303 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2304 struct intel_crtc *intel_crtc =
2305 to_intel_crtc(encoder->base.crtc);
e4607fcf 2306 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2307 int pipe = intel_crtc->pipe;
89b667f8 2308
8ac33ed3
DV		 2309 intel_dp_prepare(encoder);
2310
89b667f8 2311 /* Program Tx lane resets to default */
0980a60f 2312 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2313 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2314 DPIO_PCS_TX_LANE2_RESET |
2315 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2316 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2317 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2318 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2319 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2320 DPIO_PCS_CLK_SOFT_RESET);
2321
2322 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2323 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2324 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2325 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2326 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2327}
2328
e4a1d846
CML		 2329static void chv_pre_enable_dp(struct intel_encoder *encoder)
2330{
2331 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2332 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2333 struct drm_device *dev = encoder->base.dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct edp_power_seq power_seq;
2336 struct intel_crtc *intel_crtc =
2337 to_intel_crtc(encoder->base.crtc);
2338 enum dpio_channel ch = vlv_dport_to_channel(dport);
2339 int pipe = intel_crtc->pipe;
2340 int data, i;
949c1d43 2341 u32 val;
e4a1d846 2342
e4a1d846 2343 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2344
2345 /* Deassert soft data lane reset*/
97fd4d5c 2346 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2347 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2348 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2349
2350 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2351 val |= CHV_PCS_REQ_SOFTRESET_EN;
2352 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2353
2354 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2355 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2356 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2357
97fd4d5c 2358 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2359 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2360 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2361
2362 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2363 for (i = 0; i < 4; i++) {
2364 /* Set the latency optimal bit */
2365 data = (i == 1) ? 0x0 : 0x6;
2366 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2367 data << DPIO_FRC_LATENCY_SHFIT);
2368
2369 /* Set the upar bit */
2370 data = (i == 1) ? 0x0 : 0x1;
2371 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2372 data << DPIO_UPAR_SHIFT);
2373 }
2374
2375 /* Data lane stagger programming */
2376 /* FIXME: Fix up value only after power analysis */
2377
2378 mutex_unlock(&dev_priv->dpio_lock);
2379
2380 if (is_edp(intel_dp)) {
2381 /* init power sequencer on this pipe and port */
e39b999a 2382 mutex_lock(&dev_priv->pps_mutex);
e4a1d846
CML		 2383 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2384 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2385 &power_seq);
e39b999a 2386 mutex_unlock(&dev_priv->pps_mutex);
e4a1d846
CML		 2387 }
2388
2389 intel_enable_dp(encoder);
2390
2391 vlv_wait_port_ready(dev_priv, dport);
2392}
2393
9197c88b
VS		 2394static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2395{
2396 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2397 struct drm_device *dev = encoder->base.dev;
2398 struct drm_i915_private *dev_priv = dev->dev_private;
2399 struct intel_crtc *intel_crtc =
2400 to_intel_crtc(encoder->base.crtc);
2401 enum dpio_channel ch = vlv_dport_to_channel(dport);
2402 enum pipe pipe = intel_crtc->pipe;
2403 u32 val;
2404
625695f8
VS		 2405 intel_dp_prepare(encoder);
2406
9197c88b
VS		 2407 mutex_lock(&dev_priv->dpio_lock);
2408
b9e5ac3c
VS		 2409 /* program left/right clock distribution */
2410 if (pipe != PIPE_B) {
2411 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2412 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2413 if (ch == DPIO_CH0)
2414 val |= CHV_BUFLEFTENA1_FORCE;
2415 if (ch == DPIO_CH1)
2416 val |= CHV_BUFRIGHTENA1_FORCE;
2417 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2418 } else {
2419 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2420 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2421 if (ch == DPIO_CH0)
2422 val |= CHV_BUFLEFTENA2_FORCE;
2423 if (ch == DPIO_CH1)
2424 val |= CHV_BUFRIGHTENA2_FORCE;
2425 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2426 }
2427
9197c88b
VS		 2428 /* program clock channel usage */
2429 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2430 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2431 if (pipe != PIPE_B)
2432 val &= ~CHV_PCS_USEDCLKCHANNEL;
2433 else
2434 val |= CHV_PCS_USEDCLKCHANNEL;
2435 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2436
2437 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2438 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2439 if (pipe != PIPE_B)
2440 val &= ~CHV_PCS_USEDCLKCHANNEL;
2441 else
2442 val |= CHV_PCS_USEDCLKCHANNEL;
2443 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2444
2445 /*
2446 * This a a bit weird since generally CL
2447 * matches the pipe, but here we need to
2448 * pick the CL based on the port.
2449 */
2450 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2451 if (pipe != PIPE_B)
2452 val &= ~CHV_CMN_USEDCLKCHANNEL;
2453 else
2454 val |= CHV_CMN_USEDCLKCHANNEL;
2455 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2456
2457 mutex_unlock(&dev_priv->dpio_lock);
2458}
2459
a4fc5ed6 2460/*
df0c237d
JB		 2461 * Native read with retry for link status and receiver capability reads for
2462 * cases where the sink may still be asleep.
9d1a1031
JN		 2463 *
2464 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2465 * supposed to retry 3 times per the spec.
a4fc5ed6 2466 */
9d1a1031
JN		 2467static ssize_t
2468intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2469 void *buffer, size_t size)
a4fc5ed6 2470{
9d1a1031
JN		 2471 ssize_t ret;
2472 int i;
61da5fab 2473
61da5fab 2474 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2475 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2476 if (ret == size)
2477 return ret;
61da5fab
JB		 2478 msleep(1);
2479 }
a4fc5ed6 2480
9d1a1031 2481 return ret;
a4fc5ed6
KP		 2482}
2483
2484/*
2485 * Fetch AUX CH registers 0x202 - 0x207 which contain
2486 * link status information
2487 */
2488static bool
93f62dad 2489intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2490{
9d1a1031
JN		 2491 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2492 DP_LANE0_1_STATUS,
2493 link_status,
2494 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2495}
2496
1100244e 2497/* These are source-specific values. */
a4fc5ed6 2498static uint8_t
1a2eb460 2499intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2500{
30add22d 2501 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2502 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2503
9576c27f 2504 if (IS_VALLEYVIEW(dev))
bd60018a 2505 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
bc7d38a4 2506 else if (IS_GEN7(dev) && port == PORT_A)
bd60018a 2507 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
bc7d38a4 2508 else if (HAS_PCH_CPT(dev) && port != PORT_A)
bd60018a 2509 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
1a2eb460 2510 else
bd60018a 2511 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
1a2eb460
KP		 2512}
2513
2514static uint8_t
2515intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2516{
30add22d 2517 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2518 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2519
9576c27f 2520 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722 2521 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2522 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2523 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2524 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2525 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2526 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2527 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
d6c0d722 2529 default:
bd60018a 2530 return DP_TRAIN_PRE_EMPH_LEVEL_0;
d6c0d722 2531 }
e2fa6fba
P		 2532 } else if (IS_VALLEYVIEW(dev)) {
2533 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2534 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2535 return DP_TRAIN_PRE_EMPH_LEVEL_3;
2536 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2537 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2538 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2539 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2540 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba 2541 default:
bd60018a 2542 return DP_TRAIN_PRE_EMPH_LEVEL_0;
e2fa6fba 2543 }
bc7d38a4 2544 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460 2545 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2546 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2547 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2548 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2549 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2550 return DP_TRAIN_PRE_EMPH_LEVEL_1;
1a2eb460 2551 default:
bd60018a 2552 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460
KP		 2553 }
2554 } else {
2555 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a
SJ		 2556 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
2557 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2558 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
2559 return DP_TRAIN_PRE_EMPH_LEVEL_2;
2560 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
2561 return DP_TRAIN_PRE_EMPH_LEVEL_1;
2562 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
1a2eb460 2563 default:
bd60018a 2564 return DP_TRAIN_PRE_EMPH_LEVEL_0;
1a2eb460 2565 }
a4fc5ed6
KP		 2566 }
2567}
2568
e2fa6fba
P		 2569static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2570{
2571 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2572 struct drm_i915_private *dev_priv = dev->dev_private;
2573 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2574 struct intel_crtc *intel_crtc =
2575 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2576 unsigned long demph_reg_value, preemph_reg_value,
2577 uniqtranscale_reg_value;
2578 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2579 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2580 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2581
2582 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2583 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e2fa6fba
P		 2584 preemph_reg_value = 0x0004000;
2585 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2586 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2587 demph_reg_value = 0x2B405555;
2588 uniqtranscale_reg_value = 0x552AB83A;
2589 break;
bd60018a 2590 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2591 demph_reg_value = 0x2B404040;
2592 uniqtranscale_reg_value = 0x5548B83A;
2593 break;
bd60018a 2594 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2595 demph_reg_value = 0x2B245555;
2596 uniqtranscale_reg_value = 0x5560B83A;
2597 break;
bd60018a 2598 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e2fa6fba
P		 2599 demph_reg_value = 0x2B405555;
2600 uniqtranscale_reg_value = 0x5598DA3A;
2601 break;
2602 default:
2603 return 0;
2604 }
2605 break;
bd60018a 2606 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e2fa6fba
P		 2607 preemph_reg_value = 0x0002000;
2608 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2609 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2610 demph_reg_value = 0x2B404040;
2611 uniqtranscale_reg_value = 0x5552B83A;
2612 break;
bd60018a 2613 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2614 demph_reg_value = 0x2B404848;
2615 uniqtranscale_reg_value = 0x5580B83A;
2616 break;
bd60018a 2617 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e2fa6fba
P		 2618 demph_reg_value = 0x2B404040;
2619 uniqtranscale_reg_value = 0x55ADDA3A;
2620 break;
2621 default:
2622 return 0;
2623 }
2624 break;
bd60018a 2625 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e2fa6fba
P		 2626 preemph_reg_value = 0x0000000;
2627 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2628 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2629 demph_reg_value = 0x2B305555;
2630 uniqtranscale_reg_value = 0x5570B83A;
2631 break;
bd60018a 2632 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e2fa6fba
P		 2633 demph_reg_value = 0x2B2B4040;
2634 uniqtranscale_reg_value = 0x55ADDA3A;
2635 break;
2636 default:
2637 return 0;
2638 }
2639 break;
bd60018a 2640 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e2fa6fba
P		 2641 preemph_reg_value = 0x0006000;
2642 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2643 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e2fa6fba
P		 2644 demph_reg_value = 0x1B405555;
2645 uniqtranscale_reg_value = 0x55ADDA3A;
2646 break;
2647 default:
2648 return 0;
2649 }
2650 break;
2651 default:
2652 return 0;
2653 }
2654
0980a60f 2655 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2656 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2657 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2658 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2659 uniqtranscale_reg_value);
ab3c759a
CML		 2660 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2661 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2662 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2663 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2664 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2665
2666 return 0;
2667}
2668
e4a1d846
CML		 2669static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2670{
2671 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2674 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2675 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2676 uint8_t train_set = intel_dp->train_set[0];
2677 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2678 enum pipe pipe = intel_crtc->pipe;
2679 int i;
e4a1d846
CML		 2680
2681 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2682 case DP_TRAIN_PRE_EMPH_LEVEL_0:
e4a1d846 2683 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2684 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2685 deemph_reg_value = 128;
2686 margin_reg_value = 52;
2687 break;
bd60018a 2688 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2689 deemph_reg_value = 128;
2690 margin_reg_value = 77;
2691 break;
bd60018a 2692 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2693 deemph_reg_value = 128;
2694 margin_reg_value = 102;
2695 break;
bd60018a 2696 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
e4a1d846
CML		 2697 deemph_reg_value = 128;
2698 margin_reg_value = 154;
2699 /* FIXME extra to set for 1200 */
2700 break;
2701 default:
2702 return 0;
2703 }
2704 break;
bd60018a 2705 case DP_TRAIN_PRE_EMPH_LEVEL_1:
e4a1d846 2706 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2707 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2708 deemph_reg_value = 85;
2709 margin_reg_value = 78;
2710 break;
bd60018a 2711 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2712 deemph_reg_value = 85;
2713 margin_reg_value = 116;
2714 break;
bd60018a 2715 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
e4a1d846
CML		 2716 deemph_reg_value = 85;
2717 margin_reg_value = 154;
2718 break;
2719 default:
2720 return 0;
2721 }
2722 break;
bd60018a 2723 case DP_TRAIN_PRE_EMPH_LEVEL_2:
e4a1d846 2724 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2725 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2726 deemph_reg_value = 64;
2727 margin_reg_value = 104;
2728 break;
bd60018a 2729 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
e4a1d846
CML		 2730 deemph_reg_value = 64;
2731 margin_reg_value = 154;
2732 break;
2733 default:
2734 return 0;
2735 }
2736 break;
bd60018a 2737 case DP_TRAIN_PRE_EMPH_LEVEL_3:
e4a1d846 2738 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2739 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
e4a1d846
CML		 2740 deemph_reg_value = 43;
2741 margin_reg_value = 154;
2742 break;
2743 default:
2744 return 0;
2745 }
2746 break;
2747 default:
2748 return 0;
2749 }
2750
2751 mutex_lock(&dev_priv->dpio_lock);
2752
2753 /* Clear calc init */
1966e59e
VS		 2754 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2755 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2756 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2757
2758 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2759 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2760 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2761
2762 /* Program swing deemph */
f72df8db
VS		 2763 for (i = 0; i < 4; i++) {
2764 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2765 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2766 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2767 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2768 }
e4a1d846
CML		 2769
2770 /* Program swing margin */
f72df8db
VS		 2771 for (i = 0; i < 4; i++) {
2772 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2773 val &= ~DPIO_SWING_MARGIN000_MASK;
2774 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2775 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2776 }
e4a1d846
CML		 2777
2778 /* Disable unique transition scale */
f72df8db
VS		 2779 for (i = 0; i < 4; i++) {
2780 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2781 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2782 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2783 }
e4a1d846
CML		 2784
2785 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
bd60018a 2786 == DP_TRAIN_PRE_EMPH_LEVEL_0) &&
e4a1d846 2787 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
bd60018a 2788 == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
e4a1d846
CML		 2789
2790 /*
2791 * The document said it needs to set bit 27 for ch0 and bit 26
2792 * for ch1. Might be a typo in the doc.
2793 * For now, for this unique transition scale selection, set bit
2794 * 27 for ch0 and ch1.
2795 */
f72df8db
VS		 2796 for (i = 0; i < 4; i++) {
2797 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2798 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2799 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2800 }
e4a1d846 2801
f72df8db
VS		 2802 for (i = 0; i < 4; i++) {
2803 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2804 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2805 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2806 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2807 }
e4a1d846
CML		 2808 }
2809
2810 /* Start swing calculation */
1966e59e
VS		 2811 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2812 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2813 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2814
2815 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2816 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2817 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2818
2819 /* LRC Bypass */
2820 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2821 val |= DPIO_LRC_BYPASS;
2822 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2823
2824 mutex_unlock(&dev_priv->dpio_lock);
2825
2826 return 0;
2827}
2828
a4fc5ed6 2829static void
0301b3ac
JN		 2830intel_get_adjust_train(struct intel_dp *intel_dp,
2831 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2832{
2833 uint8_t v = 0;
2834 uint8_t p = 0;
2835 int lane;
1a2eb460
KP		 2836 uint8_t voltage_max;
2837 uint8_t preemph_max;
a4fc5ed6 2838
33a34e4e 2839 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2840 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2841 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2842
2843 if (this_v > v)
2844 v = this_v;
2845 if (this_p > p)
2846 p = this_p;
2847 }
2848
1a2eb460 2849 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2850 if (v >= voltage_max)
2851 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2852
1a2eb460
KP		 2853 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2854 if (p >= preemph_max)
2855 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2856
2857 for (lane = 0; lane < 4; lane++)
33a34e4e 2858 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2859}
2860
2861static uint32_t
f0a3424e 2862intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2863{
3cf2efb1 2864 uint32_t signal_levels = 0;
a4fc5ed6 2865
3cf2efb1 2866 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
bd60018a 2867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
a4fc5ed6
KP		 2868 default:
2869 signal_levels |= DP_VOLTAGE_0_4;
2870 break;
bd60018a 2871 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
a4fc5ed6
KP		 2872 signal_levels |= DP_VOLTAGE_0_6;
2873 break;
bd60018a 2874 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
a4fc5ed6
KP		 2875 signal_levels |= DP_VOLTAGE_0_8;
2876 break;
bd60018a 2877 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
a4fc5ed6
KP		 2878 signal_levels |= DP_VOLTAGE_1_2;
2879 break;
2880 }
3cf2efb1 2881 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
bd60018a 2882 case DP_TRAIN_PRE_EMPH_LEVEL_0:
a4fc5ed6
KP		 2883 default:
2884 signal_levels |= DP_PRE_EMPHASIS_0;
2885 break;
bd60018a 2886 case DP_TRAIN_PRE_EMPH_LEVEL_1:
a4fc5ed6
KP		 2887 signal_levels |= DP_PRE_EMPHASIS_3_5;
2888 break;
bd60018a 2889 case DP_TRAIN_PRE_EMPH_LEVEL_2:
a4fc5ed6
KP		 2890 signal_levels |= DP_PRE_EMPHASIS_6;
2891 break;
bd60018a 2892 case DP_TRAIN_PRE_EMPH_LEVEL_3:
a4fc5ed6
KP		 2893 signal_levels |= DP_PRE_EMPHASIS_9_5;
2894 break;
2895 }
2896 return signal_levels;
2897}
2898
e3421a18
ZW		 2899/* Gen6's DP voltage swing and pre-emphasis control */
2900static uint32_t
2901intel_gen6_edp_signal_levels(uint8_t train_set)
2902{
3c5a62b5
YL		 2903 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2904 DP_TRAIN_PRE_EMPHASIS_MASK);
2905 switch (signal_levels) {
bd60018a
SJ		 2906 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2907 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 2908 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
bd60018a 2909 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 2910 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
bd60018a
SJ		 2911 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
2912 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3c5a62b5 2913 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
bd60018a
SJ		 2914 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
2915 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3c5a62b5 2916 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
bd60018a
SJ		 2917 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
2918 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3c5a62b5 2919 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2920 default:
3c5a62b5
YL		 2921 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2922 "0x%x\n", signal_levels);
2923 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2924 }
2925}
2926
1a2eb460
KP		 2927/* Gen7's DP voltage swing and pre-emphasis control */
2928static uint32_t
2929intel_gen7_edp_signal_levels(uint8_t train_set)
2930{
2931 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2932 DP_TRAIN_PRE_EMPHASIS_MASK);
2933 switch (signal_levels) {
bd60018a 2934 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 2935 return EDP_LINK_TRAIN_400MV_0DB_IVB;
bd60018a 2936 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460 2937 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
bd60018a 2938 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1a2eb460
KP		 2939 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2940
bd60018a 2941 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 2942 return EDP_LINK_TRAIN_600MV_0DB_IVB;
bd60018a 2943 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 2944 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2945
bd60018a 2946 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1a2eb460 2947 return EDP_LINK_TRAIN_800MV_0DB_IVB;
bd60018a 2948 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1a2eb460
KP		 2949 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2950
2951 default:
2952 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2953 "0x%x\n", signal_levels);
2954 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2955 }
2956}
2957
d6c0d722
PZ		 2958/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2959static uint32_t
f0a3424e 2960intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2961{
d6c0d722
PZ		 2962 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2963 DP_TRAIN_PRE_EMPHASIS_MASK);
2964 switch (signal_levels) {
bd60018a 2965 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 2966 return DDI_BUF_TRANS_SELECT(0);
bd60018a 2967 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 2968 return DDI_BUF_TRANS_SELECT(1);
bd60018a 2969 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 2970 return DDI_BUF_TRANS_SELECT(2);
bd60018a 2971 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
c5fe6a06 2972 return DDI_BUF_TRANS_SELECT(3);
a4fc5ed6 2973
bd60018a 2974 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 2975 return DDI_BUF_TRANS_SELECT(4);
bd60018a 2976 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 2977 return DDI_BUF_TRANS_SELECT(5);
bd60018a 2978 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
c5fe6a06 2979 return DDI_BUF_TRANS_SELECT(6);
a4fc5ed6 2980
bd60018a 2981 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
c5fe6a06 2982 return DDI_BUF_TRANS_SELECT(7);
bd60018a 2983 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
c5fe6a06 2984 return DDI_BUF_TRANS_SELECT(8);
d6c0d722
PZ		 2985 default:
2986 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2987 "0x%x\n", signal_levels);
c5fe6a06 2988 return DDI_BUF_TRANS_SELECT(0);
a4fc5ed6 2989 }
a4fc5ed6
KP		 2990}
2991
f0a3424e
PZ		 2992/* Properly updates "DP" with the correct signal levels. */
2993static void
2994intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2995{
2996 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2997 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2998 struct drm_device *dev = intel_dig_port->base.base.dev;
2999 uint32_t signal_levels, mask;
3000 uint8_t train_set = intel_dp->train_set[0];
3001
9576c27f 3002 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 3003 signal_levels = intel_hsw_signal_levels(train_set);
3004 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 3005 } else if (IS_CHERRYVIEW(dev)) {
3006 signal_levels = intel_chv_signal_levels(intel_dp);
3007 mask = 0;
e2fa6fba
P		 3008 } else if (IS_VALLEYVIEW(dev)) {
3009 signal_levels = intel_vlv_signal_levels(intel_dp);
3010 mask = 0;
bc7d38a4 3011 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 3012 signal_levels = intel_gen7_edp_signal_levels(train_set);
3013 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 3014 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 3015 signal_levels = intel_gen6_edp_signal_levels(train_set);
3016 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3017 } else {
3018 signal_levels = intel_gen4_signal_levels(train_set);
3019 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3020 }
3021
3022 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3023
3024 *DP = (*DP & ~mask) | signal_levels;
3025}
3026
a4fc5ed6 3027static bool
ea5b213a 3028intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 3029 uint32_t *DP,
58e10eb9 3030 uint8_t dp_train_pat)
a4fc5ed6 3031{
174edf1f
PZ		 3032 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3033 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3034 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3035 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 3036 uint8_t buf[sizeof(intel_dp->train_set) + 1];
3037 int ret, len;
a4fc5ed6 3038
22b8bf17 3039 if (HAS_DDI(dev)) {
3ab9c637 3040 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 3041
3042 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
3043 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
3044 else
3045 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
3046
3047 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3048 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3049 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 3050 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3051
3052 break;
3053 case DP_TRAINING_PATTERN_1:
3054 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3055 break;
3056 case DP_TRAINING_PATTERN_2:
3057 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3058 break;
3059 case DP_TRAINING_PATTERN_3:
3060 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3061 break;
3062 }
174edf1f 3063 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 3064
bc7d38a4 3065 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 3066 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 3067
3068 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3069 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3070 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 3071 break;
3072 case DP_TRAINING_PATTERN_1:
70aff66c 3073 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 3074 break;
3075 case DP_TRAINING_PATTERN_2:
70aff66c 3076 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3077 break;
3078 case DP_TRAINING_PATTERN_3:
3079 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 3080 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 3081 break;
3082 }
3083
3084 } else {
aad3d14d
VS		 3085 if (IS_CHERRYVIEW(dev))
3086 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
3087 else
3088 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 3089
3090 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
3091 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 3092 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 3093 break;
3094 case DP_TRAINING_PATTERN_1:
70aff66c 3095 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 3096 break;
3097 case DP_TRAINING_PATTERN_2:
70aff66c 3098 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 3099 break;
3100 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 3101 if (IS_CHERRYVIEW(dev)) {
3102 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
3103 } else {
3104 DRM_ERROR("DP training pattern 3 not supported\n");
3105 *DP |= DP_LINK_TRAIN_PAT_2;
3106 }
47ea7542
PZ		 3107 break;
3108 }
3109 }
3110
70aff66c 3111 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3112 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3113
2cdfe6c8
JN		 3114 buf[0] = dp_train_pat;
3115 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3116 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3117 /* don't write DP_TRAINING_LANEx_SET on disable */
3118 len = 1;
3119 } else {
3120 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3121 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3122 len = intel_dp->lane_count + 1;
47ea7542 3123 }
a4fc5ed6 3124
9d1a1031
JN		 3125 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3126 buf, len);
2cdfe6c8
JN		 3127
3128 return ret == len;
a4fc5ed6
KP		 3129}
3130
70aff66c
JN		 3131static bool
3132intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3133 uint8_t dp_train_pat)
3134{
953d22e8 3135 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3136 intel_dp_set_signal_levels(intel_dp, DP);
3137 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3138}
3139
3140static bool
3141intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3142 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3143{
3144 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3145 struct drm_device *dev = intel_dig_port->base.base.dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int ret;
3148
3149 intel_get_adjust_train(intel_dp, link_status);
3150 intel_dp_set_signal_levels(intel_dp, DP);
3151
3152 I915_WRITE(intel_dp->output_reg, *DP);
3153 POSTING_READ(intel_dp->output_reg);
3154
9d1a1031
JN		 3155 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3156 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3157
3158 return ret == intel_dp->lane_count;
3159}
3160
3ab9c637
ID		 3161static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3162{
3163 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3164 struct drm_device *dev = intel_dig_port->base.base.dev;
3165 struct drm_i915_private *dev_priv = dev->dev_private;
3166 enum port port = intel_dig_port->port;
3167 uint32_t val;
3168
3169 if (!HAS_DDI(dev))
3170 return;
3171
3172 val = I915_READ(DP_TP_CTL(port));
3173 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3174 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3175 I915_WRITE(DP_TP_CTL(port), val);
3176
3177 /*
3178 * On PORT_A we can have only eDP in SST mode. There the only reason
3179 * we need to set idle transmission mode is to work around a HW issue
3180 * where we enable the pipe while not in idle link-training mode.
3181 * In this case there is requirement to wait for a minimum number of
3182 * idle patterns to be sent.
3183 */
3184 if (port == PORT_A)
3185 return;
3186
3187 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3188 1))
3189 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3190}
3191
33a34e4e 3192/* Enable corresponding port and start training pattern 1 */
c19b0669 3193void
33a34e4e 3194intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3195{
da63a9f2 3196 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3197 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3198 int i;
3199 uint8_t voltage;
cdb0e95b 3200 int voltage_tries, loop_tries;
ea5b213a 3201 uint32_t DP = intel_dp->DP;
6aba5b6c 3202 uint8_t link_config[2];
a4fc5ed6 3203
affa9354 3204 if (HAS_DDI(dev))
c19b0669
PZ		 3205 intel_ddi_prepare_link_retrain(encoder);
3206
3cf2efb1 3207 /* Write the link configuration data */
6aba5b6c
JN		 3208 link_config[0] = intel_dp->link_bw;
3209 link_config[1] = intel_dp->lane_count;
3210 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3211 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3212 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3213
3214 link_config[0] = 0;
3215 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3216 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3217
3218 DP |= DP_PORT_EN;
1a2eb460 3219
70aff66c
JN		 3220 /* clock recovery */
3221 if (!intel_dp_reset_link_train(intel_dp, &DP,
3222 DP_TRAINING_PATTERN_1 |
3223 DP_LINK_SCRAMBLING_DISABLE)) {
3224 DRM_ERROR("failed to enable link training\n");
3225 return;
3226 }
3227
a4fc5ed6 3228 voltage = 0xff;
cdb0e95b
KP		 3229 voltage_tries = 0;
3230 loop_tries = 0;
a4fc5ed6 3231 for (;;) {
70aff66c 3232 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3233
a7c9655f 3234 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3235 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3236 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3237 break;
93f62dad 3238 }
a4fc5ed6 3239
01916270 3240 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3241 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3242 break;
3243 }
3244
3245 /* Check to see if we've tried the max voltage */
3246 for (i = 0; i < intel_dp->lane_count; i++)
3247 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3248 break;
3b4f819d 3249 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3250 ++loop_tries;
3251 if (loop_tries == 5) {
3def84b3 3252 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3253 break;
3254 }
70aff66c
JN		 3255 intel_dp_reset_link_train(intel_dp, &DP,
3256 DP_TRAINING_PATTERN_1 |
3257 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3258 voltage_tries = 0;
3259 continue;
3260 }
a4fc5ed6 3261
3cf2efb1 3262 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3263 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3264 ++voltage_tries;
b06fbda3 3265 if (voltage_tries == 5) {
3def84b3 3266 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3267 break;
3268 }
3269 } else
3270 voltage_tries = 0;
3271 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3272
70aff66c
JN		 3273 /* Update training set as requested by target */
3274 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3275 DRM_ERROR("failed to update link training\n");
3276 break;
3277 }
a4fc5ed6
KP		 3278 }
3279
33a34e4e
JB		 3280 intel_dp->DP = DP;
3281}
3282
c19b0669 3283void
33a34e4e
JB		 3284intel_dp_complete_link_train(struct intel_dp *intel_dp)
3285{
33a34e4e 3286 bool channel_eq = false;
37f80975 3287 int tries, cr_tries;
33a34e4e 3288 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3289 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3290
3291 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3292 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3293 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3294
a4fc5ed6 3295 /* channel equalization */
70aff66c 3296 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3297 training_pattern |
70aff66c
JN		 3298 DP_LINK_SCRAMBLING_DISABLE)) {
3299 DRM_ERROR("failed to start channel equalization\n");
3300 return;
3301 }
3302
a4fc5ed6 3303 tries = 0;
37f80975 3304 cr_tries = 0;
a4fc5ed6
KP		 3305 channel_eq = false;
3306 for (;;) {
70aff66c 3307 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3308
37f80975
JB		 3309 if (cr_tries > 5) {
3310 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3311 break;
3312 }
3313
a7c9655f 3314 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3315 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3316 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3317 break;
70aff66c 3318 }
a4fc5ed6 3319
37f80975 3320 /* Make sure clock is still ok */
01916270 3321 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3322 intel_dp_start_link_train(intel_dp);
70aff66c 3323 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3324 training_pattern |
70aff66c 3325 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3326 cr_tries++;
3327 continue;
3328 }
3329
1ffdff13 3330 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3331 channel_eq = true;
3332 break;
3333 }
a4fc5ed6 3334
37f80975
JB		 3335 /* Try 5 times, then try clock recovery if that fails */
3336 if (tries > 5) {
3337 intel_dp_link_down(intel_dp);
3338 intel_dp_start_link_train(intel_dp);
70aff66c 3339 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3340 training_pattern |
70aff66c 3341 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3342 tries = 0;
3343 cr_tries++;
3344 continue;
3345 }
a4fc5ed6 3346
70aff66c
JN		 3347 /* Update training set as requested by target */
3348 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3349 DRM_ERROR("failed to update link training\n");
3350 break;
3351 }
3cf2efb1 3352 ++tries;
869184a6 3353 }
3cf2efb1 3354
3ab9c637
ID		 3355 intel_dp_set_idle_link_train(intel_dp);
3356
3357 intel_dp->DP = DP;
3358
d6c0d722 3359 if (channel_eq)
07f42258 3360 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3361
3ab9c637
ID		 3362}
3363
3364void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3365{
70aff66c 3366 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3367 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3368}
3369
3370static void
ea5b213a 3371intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3372{
da63a9f2 3373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3374 enum port port = intel_dig_port->port;
da63a9f2 3375 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3376 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3377 struct intel_crtc *intel_crtc =
3378 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3379 uint32_t DP = intel_dp->DP;
a4fc5ed6 3380
bc76e320 3381 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3382 return;
3383
0c33d8d7 3384 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3385 return;
3386
28c97730 3387 DRM_DEBUG_KMS("\n");
32f9d658 3388
bc7d38a4 3389 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3390 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3391 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3392 } else {
aad3d14d
VS		 3393 if (IS_CHERRYVIEW(dev))
3394 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3395 else
3396 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3397 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3398 }
fe255d00 3399 POSTING_READ(intel_dp->output_reg);
5eb08b69 3400
493a7081 3401 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3402 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3403 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3404
5bddd17f
EA		 3405 /* Hardware workaround: leaving our transcoder select
3406 * set to transcoder B while it's off will prevent the
3407 * corresponding HDMI output on transcoder A.
3408 *
3409 * Combine this with another hardware workaround:
3410 * transcoder select bit can only be cleared while the
3411 * port is enabled.
3412 */
3413 DP &= ~DP_PIPEB_SELECT;
3414 I915_WRITE(intel_dp->output_reg, DP);
3415
3416 /* Changes to enable or select take place the vblank
3417 * after being written.
3418 */
ff50afe9
DV		 3419 if (WARN_ON(crtc == NULL)) {
3420 /* We should never try to disable a port without a crtc
3421 * attached. For paranoia keep the code around for a
3422 * bit. */
31acbcc4
CW		 3423 POSTING_READ(intel_dp->output_reg);
3424 msleep(50);
3425 } else
ab527efc 3426 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3427 }
3428
832afda6 3429 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3430 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3431 POSTING_READ(intel_dp->output_reg);
f01eca2e 3432 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3433}
3434
26d61aad
KP		 3435static bool
3436intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3437{
a031d709
RV		 3438 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3439 struct drm_device *dev = dig_port->base.base.dev;
3440 struct drm_i915_private *dev_priv = dev->dev_private;
3441
9d1a1031
JN		 3442 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3443 sizeof(intel_dp->dpcd)) < 0)
edb39244 3444 return false; /* aux transfer failed */
92fd8fd1 3445
a8e98153 3446 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
577c7a50 3447
edb39244
AJ		 3448 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3449 return false; /* DPCD not present */
3450
2293bb5c
SK		 3451 /* Check if the panel supports PSR */
3452 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3453 if (is_edp(intel_dp)) {
9d1a1031
JN		 3454 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3455 intel_dp->psr_dpcd,
3456 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3457 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3458 dev_priv->psr.sink_support = true;
50003939 3459 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3460 }
50003939
JN		 3461 }
3462
06ea66b6
TP		 3463 /* Training Pattern 3 support */
3464 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3465 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3466 intel_dp->use_tps3 = true;
3467 DRM_DEBUG_KMS("Displayport TPS3 supported");
3468 } else
3469 intel_dp->use_tps3 = false;
3470
edb39244
AJ		 3471 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3472 DP_DWN_STRM_PORT_PRESENT))
3473 return true; /* native DP sink */
3474
3475 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3476 return true; /* no per-port downstream info */
3477
9d1a1031
JN		 3478 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3479 intel_dp->downstream_ports,
3480 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3481 return false; /* downstream port status fetch failed */
3482
3483 return true;
92fd8fd1
KP		 3484}
3485
0d198328
AJ		 3486static void
3487intel_dp_probe_oui(struct intel_dp *intel_dp)
3488{
3489 u8 buf[3];
3490
3491 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3492 return;
3493
24f3e092 3494 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3495
9d1a1031 3496 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3497 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3498 buf[0], buf[1], buf[2]);
3499
9d1a1031 3500 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3501 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3502 buf[0], buf[1], buf[2]);
351cfc34 3503
1e0560e0 3504 intel_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3505}
3506
0e32b39c
DA		 3507static bool
3508intel_dp_probe_mst(struct intel_dp *intel_dp)
3509{
3510 u8 buf[1];
3511
3512 if (!intel_dp->can_mst)
3513 return false;
3514
3515 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3516 return false;
3517
d337a341 3518 intel_edp_panel_vdd_on(intel_dp);
0e32b39c
DA		 3519 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3520 if (buf[0] & DP_MST_CAP) {
3521 DRM_DEBUG_KMS("Sink is MST capable\n");
3522 intel_dp->is_mst = true;
3523 } else {
3524 DRM_DEBUG_KMS("Sink is not MST capable\n");
3525 intel_dp->is_mst = false;
3526 }
3527 }
1e0560e0 3528 intel_edp_panel_vdd_off(intel_dp, false);
0e32b39c
DA		 3529
3530 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3531 return intel_dp->is_mst;
3532}
3533
d2e216d0
RV		 3534int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3535{
3536 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3537 struct drm_device *dev = intel_dig_port->base.base.dev;
3538 struct intel_crtc *intel_crtc =
3539 to_intel_crtc(intel_dig_port->base.base.crtc);
3540 u8 buf[1];
3541
9d1a1031 3542 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3543 return -EAGAIN;
3544
3545 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3546 return -ENOTTY;
3547
9d1a1031
JN		 3548 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3549 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3550 return -EAGAIN;
3551
3552 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3553 intel_wait_for_vblank(dev, intel_crtc->pipe);
3554 intel_wait_for_vblank(dev, intel_crtc->pipe);
3555
9d1a1031 3556 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3557 return -EAGAIN;
3558
9d1a1031 3559 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3560 return 0;
3561}
3562
a60f0e38
JB		 3563static bool
3564intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3565{
9d1a1031
JN		 3566 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3567 DP_DEVICE_SERVICE_IRQ_VECTOR,
3568 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3569}
3570
0e32b39c
DA		 3571static bool
3572intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3573{
3574 int ret;
3575
3576 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3577 DP_SINK_COUNT_ESI,
3578 sink_irq_vector, 14);
3579 if (ret != 14)
3580 return false;
3581
3582 return true;
3583}
3584
a60f0e38
JB		 3585static void
3586intel_dp_handle_test_request(struct intel_dp *intel_dp)
3587{
3588 /* NAK by default */
9d1a1031 3589 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3590}
3591
0e32b39c
DA		 3592static int
3593intel_dp_check_mst_status(struct intel_dp *intel_dp)
3594{
3595 bool bret;
3596
3597 if (intel_dp->is_mst) {
3598 u8 esi[16] = { 0 };
3599 int ret = 0;
3600 int retry;
3601 bool handled;
3602 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3603go_again:
3604 if (bret == true) {
3605
3606 /* check link status - esi[10] = 0x200c */
3607 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3608 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3609 intel_dp_start_link_train(intel_dp);
3610 intel_dp_complete_link_train(intel_dp);
3611 intel_dp_stop_link_train(intel_dp);
3612 }
3613
3614 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3615 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3616
3617 if (handled) {
3618 for (retry = 0; retry < 3; retry++) {
3619 int wret;
3620 wret = drm_dp_dpcd_write(&intel_dp->aux,
3621 DP_SINK_COUNT_ESI+1,
3622 &esi[1], 3);
3623 if (wret == 3) {
3624 break;
3625 }
3626 }
3627
3628 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3629 if (bret == true) {
3630 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3631 goto go_again;
3632 }
3633 } else
3634 ret = 0;
3635
3636 return ret;
3637 } else {
3638 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3639 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3640 intel_dp->is_mst = false;
3641 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3642 /* send a hotplug event */
3643 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3644 }
3645 }
3646 return -EINVAL;
3647}
3648
a4fc5ed6
KP		 3649/*
3650 * According to DP spec
3651 * 5.1.2:
3652 * 1. Read DPCD
3653 * 2. Configure link according to Receiver Capabilities
3654 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3655 * 4. Check link status on receipt of hot-plug interrupt
3656 */
00c09d70 3657void
ea5b213a 3658intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3659{
5b215bcf 3660 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3661 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3662 u8 sink_irq_vector;
93f62dad 3663 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3664
5b215bcf
DA		 3665 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3666
da63a9f2 3667 if (!intel_encoder->connectors_active)
d2b996ac 3668 return;
59cd09e1 3669
da63a9f2 3670 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3671 return;
3672
1a125d8a
ID		 3673 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3674 return;
3675
92fd8fd1 3676 /* Try to read receiver status if the link appears to be up */
93f62dad 3677 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3678 return;
3679 }
3680
92fd8fd1 3681 /* Now read the DPCD to see if it's actually running */
26d61aad 3682 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3683 return;
3684 }
3685
a60f0e38
JB		 3686 /* Try to read the source of the interrupt */
3687 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3688 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3689 /* Clear interrupt source */
9d1a1031
JN		 3690 drm_dp_dpcd_writeb(&intel_dp->aux,
3691 DP_DEVICE_SERVICE_IRQ_VECTOR,
3692 sink_irq_vector);
a60f0e38
JB		 3693
3694 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3695 intel_dp_handle_test_request(intel_dp);
3696 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3697 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3698 }
3699
1ffdff13 3700 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3701 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3702 intel_encoder->base.name);
33a34e4e
JB		 3703 intel_dp_start_link_train(intel_dp);
3704 intel_dp_complete_link_train(intel_dp);
3ab9c637 3705 intel_dp_stop_link_train(intel_dp);
33a34e4e 3706 }
a4fc5ed6 3707}
a4fc5ed6 3708
caf9ab24 3709/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3710static enum drm_connector_status
26d61aad 3711intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3712{
caf9ab24 3713 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3714 uint8_t type;
3715
3716 if (!intel_dp_get_dpcd(intel_dp))
3717 return connector_status_disconnected;
3718
3719 /* if there's no downstream port, we're done */
3720 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3721 return connector_status_connected;
caf9ab24
AJ		 3722
3723 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3724 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3725 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3726 uint8_t reg;
9d1a1031
JN		 3727
3728 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3729 &reg, 1) < 0)
caf9ab24 3730 return connector_status_unknown;
9d1a1031 3731
23235177
AJ		 3732 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3733 : connector_status_disconnected;
caf9ab24
AJ		 3734 }
3735
3736 /* If no HPD, poke DDC gently */
0b99836f 3737 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3738 return connector_status_connected;
caf9ab24
AJ		 3739
3740 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3741 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3742 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3743 if (type == DP_DS_PORT_TYPE_VGA ||
3744 type == DP_DS_PORT_TYPE_NON_EDID)
3745 return connector_status_unknown;
3746 } else {
3747 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3748 DP_DWN_STRM_PORT_TYPE_MASK;
3749 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3750 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3751 return connector_status_unknown;
3752 }
caf9ab24
AJ		 3753
3754 /* Anything else is out of spec, warn and ignore */
3755 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3756 return connector_status_disconnected;
71ba9000
AJ		 3757}
3758
d410b56d
CW		 3759static enum drm_connector_status
3760edp_detect(struct intel_dp *intel_dp)
3761{
3762 struct drm_device *dev = intel_dp_to_dev(intel_dp);
3763 enum drm_connector_status status;
3764
3765 status = intel_panel_detect(dev);
3766 if (status == connector_status_unknown)
3767 status = connector_status_connected;
3768
3769 return status;
3770}
3771
5eb08b69 3772static enum drm_connector_status
a9756bb5 3773ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3774{
30add22d 3775 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
01cb9ea6 3778
1b469639
DL		 3779 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3780 return connector_status_disconnected;
3781
26d61aad 3782 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3783}
3784
a4fc5ed6 3785static enum drm_connector_status
a9756bb5 3786g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3787{
30add22d 3788 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3789 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3790 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3791 uint32_t bit;
5eb08b69 3792
232a6ee9
TP		 3793 if (IS_VALLEYVIEW(dev)) {
3794 switch (intel_dig_port->port) {
3795 case PORT_B:
3796 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3797 break;
3798 case PORT_C:
3799 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3800 break;
3801 case PORT_D:
3802 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3803 break;
3804 default:
3805 return connector_status_unknown;
3806 }
3807 } else {
3808 switch (intel_dig_port->port) {
3809 case PORT_B:
3810 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3811 break;
3812 case PORT_C:
3813 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3814 break;
3815 case PORT_D:
3816 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3817 break;
3818 default:
3819 return connector_status_unknown;
3820 }
a4fc5ed6
KP		 3821 }
3822
10f76a38 3823 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3824 return connector_status_disconnected;
3825
26d61aad 3826 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3827}
3828
8c241fef 3829static struct edid *
beb60608 3830intel_dp_get_edid(struct intel_dp *intel_dp)
8c241fef 3831{
beb60608 3832 struct intel_connector *intel_connector = intel_dp->attached_connector;
d6f24d0f 3833
9cd300e0
JN		 3834 /* use cached edid if we have one */
3835 if (intel_connector->edid) {
9cd300e0
JN		 3836 /* invalid edid */
3837 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3838 return NULL;
3839
55e9edeb 3840 return drm_edid_duplicate(intel_connector->edid);
beb60608
CW		 3841 } else
3842 return drm_get_edid(&intel_connector->base,
3843 &intel_dp->aux.ddc);
3844}
8c241fef 3845
beb60608
CW		 3846static void
3847intel_dp_set_edid(struct intel_dp *intel_dp)
3848{
3849 struct intel_connector *intel_connector = intel_dp->attached_connector;
3850 struct edid *edid;
3851
3852 edid = intel_dp_get_edid(intel_dp);
3853 intel_connector->detect_edid = edid;
3854
3855 if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
3856 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
3857 else
3858 intel_dp->has_audio = drm_detect_monitor_audio(edid);
8c241fef
KP		 3859}
3860
beb60608
CW		 3861static void
3862intel_dp_unset_edid(struct intel_dp *intel_dp)
8c241fef 3863{
beb60608 3864 struct intel_connector *intel_connector = intel_dp->attached_connector;
8c241fef 3865
beb60608
CW		 3866 kfree(intel_connector->detect_edid);
3867 intel_connector->detect_edid = NULL;
9cd300e0 3868
beb60608
CW		 3869 intel_dp->has_audio = false;
3870}
d6f24d0f 3871
beb60608
CW		 3872static enum intel_display_power_domain
3873intel_dp_power_get(struct intel_dp *dp)
3874{
3875 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
3876 enum intel_display_power_domain power_domain;
3877
3878 power_domain = intel_display_port_power_domain(encoder);
3879 intel_display_power_get(to_i915(encoder->base.dev), power_domain);
3880
3881 return power_domain;
3882}
3883
3884static void
3885intel_dp_power_put(struct intel_dp *dp,
3886 enum intel_display_power_domain power_domain)
3887{
3888 struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
3889 intel_display_power_put(to_i915(encoder->base.dev), power_domain);
8c241fef
KP		 3890}
3891
a9756bb5
ZW		 3892static enum drm_connector_status
3893intel_dp_detect(struct drm_connector *connector, bool force)
3894{
3895 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3896 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3897 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3898 struct drm_device *dev = connector->dev;
a9756bb5 3899 enum drm_connector_status status;
671dedd2 3900 enum intel_display_power_domain power_domain;
0e32b39c 3901 bool ret;
a9756bb5 3902
164c8598 3903 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3904 connector->base.id, connector->name);
beb60608 3905 intel_dp_unset_edid(intel_dp);
164c8598 3906
0e32b39c
DA		 3907 if (intel_dp->is_mst) {
3908 /* MST devices are disconnected from a monitor POV */
3909 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3910 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
beb60608 3911 return connector_status_disconnected;
0e32b39c
DA		 3912 }
3913
beb60608 3914 power_domain = intel_dp_power_get(intel_dp);
a9756bb5 3915
d410b56d
CW		 3916 /* Can't disconnect eDP, but you can close the lid... */
3917 if (is_edp(intel_dp))
3918 status = edp_detect(intel_dp);
3919 else if (HAS_PCH_SPLIT(dev))
a9756bb5
ZW		 3920 status = ironlake_dp_detect(intel_dp);
3921 else
3922 status = g4x_dp_detect(intel_dp);
3923 if (status != connector_status_connected)
c8c8fb33 3924 goto out;
a9756bb5 3925
0d198328
AJ		 3926 intel_dp_probe_oui(intel_dp);
3927
0e32b39c
DA		 3928 ret = intel_dp_probe_mst(intel_dp);
3929 if (ret) {
3930 /* if we are in MST mode then this connector
3931 won't appear connected or have anything with EDID on it */
3932 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3933 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3934 status = connector_status_disconnected;
3935 goto out;
3936 }
3937
beb60608 3938 intel_dp_set_edid(intel_dp);
a9756bb5 3939
d63885da
PZ		 3940 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3941 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3942 status = connector_status_connected;
3943
3944out:
beb60608 3945 intel_dp_power_put(intel_dp, power_domain);
c8c8fb33 3946 return status;
a4fc5ed6
KP		 3947}
3948
beb60608
CW		 3949static void
3950intel_dp_force(struct drm_connector *connector)
a4fc5ed6 3951{
df0e9248 3952 struct intel_dp *intel_dp = intel_attached_dp(connector);
beb60608 3953 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
671dedd2 3954 enum intel_display_power_domain power_domain;
a4fc5ed6 3955
beb60608
CW		 3956 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3957 connector->base.id, connector->name);
3958 intel_dp_unset_edid(intel_dp);
a4fc5ed6 3959
beb60608
CW		 3960 if (connector->status != connector_status_connected)
3961 return;
671dedd2 3962
beb60608
CW		 3963 power_domain = intel_dp_power_get(intel_dp);
3964
3965 intel_dp_set_edid(intel_dp);
3966
3967 intel_dp_power_put(intel_dp, power_domain);
3968
3969 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3970 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3971}
3972
3973static int intel_dp_get_modes(struct drm_connector *connector)
3974{
3975 struct intel_connector *intel_connector = to_intel_connector(connector);
3976 struct edid *edid;
3977
3978 edid = intel_connector->detect_edid;
3979 if (edid) {
3980 int ret = intel_connector_update_modes(connector, edid);
3981 if (ret)
3982 return ret;
3983 }
32f9d658 3984
f8779fda 3985 /* if eDP has no EDID, fall back to fixed mode */
beb60608
CW		 3986 if (is_edp(intel_attached_dp(connector)) &&
3987 intel_connector->panel.fixed_mode) {
f8779fda 3988 struct drm_display_mode *mode;
beb60608
CW		 3989
3990 mode = drm_mode_duplicate(connector->dev,
dd06f90e 3991 intel_connector->panel.fixed_mode);
f8779fda 3992 if (mode) {
32f9d658
ZW		 3993 drm_mode_probed_add(connector, mode);
3994 return 1;
3995 }
3996 }
beb60608 3997
32f9d658 3998 return 0;
a4fc5ed6
KP		 3999}
4000
1aad7ac0
CW		 4001static bool
4002intel_dp_detect_audio(struct drm_connector *connector)
4003{
1aad7ac0 4004 bool has_audio = false;
beb60608 4005 struct edid *edid;
1aad7ac0 4006
beb60608
CW		 4007 edid = to_intel_connector(connector)->detect_edid;
4008 if (edid)
1aad7ac0 4009 has_audio = drm_detect_monitor_audio(edid);
671dedd2 4010
1aad7ac0
CW		 4011 return has_audio;
4012}
4013
f684960e
CW		 4014static int
4015intel_dp_set_property(struct drm_connector *connector,
4016 struct drm_property *property,
4017 uint64_t val)
4018{
e953fd7b 4019 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 4020 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 4021 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4022 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 4023 int ret;
4024
662595df 4025 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 4026 if (ret)
4027 return ret;
4028
3f43c48d 4029 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 4030 int i = val;
4031 bool has_audio;
4032
4033 if (i == intel_dp->force_audio)
f684960e
CW		 4034 return 0;
4035
1aad7ac0 4036 intel_dp->force_audio = i;
f684960e 4037
c3e5f67b 4038 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 4039 has_audio = intel_dp_detect_audio(connector);
4040 else
c3e5f67b 4041 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 4042
4043 if (has_audio == intel_dp->has_audio)
f684960e
CW		 4044 return 0;
4045
1aad7ac0 4046 intel_dp->has_audio = has_audio;
f684960e
CW		 4047 goto done;
4048 }
4049
e953fd7b 4050 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 4051 bool old_auto = intel_dp->color_range_auto;
4052 uint32_t old_range = intel_dp->color_range;
4053
55bc60db
VS		 4054 switch (val) {
4055 case INTEL_BROADCAST_RGB_AUTO:
4056 intel_dp->color_range_auto = true;
4057 break;
4058 case INTEL_BROADCAST_RGB_FULL:
4059 intel_dp->color_range_auto = false;
4060 intel_dp->color_range = 0;
4061 break;
4062 case INTEL_BROADCAST_RGB_LIMITED:
4063 intel_dp->color_range_auto = false;
4064 intel_dp->color_range = DP_COLOR_RANGE_16_235;
4065 break;
4066 default:
4067 return -EINVAL;
4068 }
ae4edb80
DV		 4069
4070 if (old_auto == intel_dp->color_range_auto &&
4071 old_range == intel_dp->color_range)
4072 return 0;
4073
e953fd7b
CW		 4074 goto done;
4075 }
4076
53b41837
YN		 4077 if (is_edp(intel_dp) &&
4078 property == connector->dev->mode_config.scaling_mode_property) {
4079 if (val == DRM_MODE_SCALE_NONE) {
4080 DRM_DEBUG_KMS("no scaling not supported\n");
4081 return -EINVAL;
4082 }
4083
4084 if (intel_connector->panel.fitting_mode == val) {
4085 /* the eDP scaling property is not changed */
4086 return 0;
4087 }
4088 intel_connector->panel.fitting_mode = val;
4089
4090 goto done;
4091 }
4092
f684960e
CW		 4093 return -EINVAL;
4094
4095done:
c0c36b94
CW		 4096 if (intel_encoder->base.crtc)
4097 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 4098
4099 return 0;
4100}
4101
a4fc5ed6 4102static void
73845adf 4103intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 4104{
1d508706 4105 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 4106
beb60608
CW		 4107 intel_dp_unset_edid(intel_attached_dp(connector));
4108
9cd300e0
JN		 4109 if (!IS_ERR_OR_NULL(intel_connector->edid))
4110 kfree(intel_connector->edid);
4111
acd8db10
PZ		 4112 /* Can't call is_edp() since the encoder may have been destroyed
4113 * already. */
4114 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 4115 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 4116
a4fc5ed6 4117 drm_connector_cleanup(connector);
55f78c43 4118 kfree(connector);
a4fc5ed6
KP		 4119}
4120
00c09d70 4121void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4122{
da63a9f2
PZ		 4123 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4124 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 4125 struct drm_device *dev = intel_dp_to_dev(intel_dp);
e39b999a 4126 struct drm_i915_private *dev_priv = dev->dev_private;
24d05927 4127
4f71d0cb 4128 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4129 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4130 drm_encoder_cleanup(encoder);
bd943159
KP		 4131 if (is_edp(intel_dp)) {
4132 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
e39b999a 4133 mutex_lock(&dev_priv->pps_mutex);
4be73780 4134 edp_panel_vdd_off_sync(intel_dp);
e39b999a 4135 mutex_unlock(&dev_priv->pps_mutex);
01527b31
CT		 4136 if (intel_dp->edp_notifier.notifier_call) {
4137 unregister_reboot_notifier(&intel_dp->edp_notifier);
4138 intel_dp->edp_notifier.notifier_call = NULL;
4139 }
bd943159 4140 }
da63a9f2 4141 kfree(intel_dig_port);
24d05927
DV		 4142}
4143
07f9cd0b
ID		 4144static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4145{
4146 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
e39b999a
VS		 4147 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4148 struct drm_i915_private *dev_priv = dev->dev_private;
07f9cd0b
ID		 4149
4150 if (!is_edp(intel_dp))
4151 return;
4152
e39b999a 4153 mutex_lock(&dev_priv->pps_mutex);
07f9cd0b 4154 edp_panel_vdd_off_sync(intel_dp);
e39b999a 4155 mutex_unlock(&dev_priv->pps_mutex);
07f9cd0b
ID		 4156}
4157
6d93c0c4
ID		 4158static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4159{
4160 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4161}
4162
a4fc5ed6 4163static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4164 .dpms = intel_connector_dpms,
a4fc5ed6 4165 .detect = intel_dp_detect,
beb60608 4166 .force = intel_dp_force,
a4fc5ed6 4167 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4168 .set_property = intel_dp_set_property,
73845adf 4169 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4170};
4171
4172static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4173 .get_modes = intel_dp_get_modes,
4174 .mode_valid = intel_dp_mode_valid,
df0e9248 4175 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4176};
4177
a4fc5ed6 4178static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4179 .reset = intel_dp_encoder_reset,
24d05927 4180 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4181};
4182
0e32b39c 4183void
21d40d37 4184intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4185{
0e32b39c 4186 return;
c8110e52 4187}
6207937d 4188
13cf5504
DA		 4189bool
4190intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4191{
4192 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4193 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4194 struct drm_device *dev = intel_dig_port->base.base.dev;
4195 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4196 enum intel_display_power_domain power_domain;
4197 bool ret = true;
4198
0e32b39c
DA		 4199 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4200 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4201
26fbb774
VS		 4202 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4203 port_name(intel_dig_port->port),
0e32b39c 4204 long_hpd ? "long" : "short");
13cf5504 4205
1c767b33
ID		 4206 power_domain = intel_display_port_power_domain(intel_encoder);
4207 intel_display_power_get(dev_priv, power_domain);
4208
0e32b39c
DA		 4209 if (long_hpd) {
4210 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4211 goto mst_fail;
4212
4213 if (!intel_dp_get_dpcd(intel_dp)) {
4214 goto mst_fail;
4215 }
4216
4217 intel_dp_probe_oui(intel_dp);
4218
4219 if (!intel_dp_probe_mst(intel_dp))
4220 goto mst_fail;
4221
4222 } else {
4223 if (intel_dp->is_mst) {
1c767b33 4224 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4225 goto mst_fail;
4226 }
4227
4228 if (!intel_dp->is_mst) {
4229 /*
4230 * we'll check the link status via the normal hot plug path later -
4231 * but for short hpds we should check it now
4232 */
5b215bcf 4233 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4234 intel_dp_check_link_status(intel_dp);
5b215bcf 4235 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4236 }
4237 }
1c767b33
ID		 4238 ret = false;
4239 goto put_power;
0e32b39c
DA		 4240mst_fail:
4241 /* if we were in MST mode, and device is not there get out of MST mode */
4242 if (intel_dp->is_mst) {
4243 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4244 intel_dp->is_mst = false;
4245 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4246 }
1c767b33
ID		 4247put_power:
4248 intel_display_power_put(dev_priv, power_domain);
4249
4250 return ret;
13cf5504
DA		 4251}
4252
e3421a18
ZW		 4253/* Return which DP Port should be selected for Transcoder DP control */
4254int
0206e353 4255intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4256{
4257 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4258 struct intel_encoder *intel_encoder;
4259 struct intel_dp *intel_dp;
e3421a18 4260
fa90ecef
PZ		 4261 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4262 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4263
fa90ecef
PZ		 4264 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4265 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4266 return intel_dp->output_reg;
e3421a18 4267 }
ea5b213a 4268
e3421a18
ZW		 4269 return -1;
4270}
4271
36e83a18 4272/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4273bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4274{
4275 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4276 union child_device_config *p_child;
36e83a18 4277 int i;
5d8a7752
VS		 4278 static const short port_mapping[] = {
4279 [PORT_B] = PORT_IDPB,
4280 [PORT_C] = PORT_IDPC,
4281 [PORT_D] = PORT_IDPD,
4282 };
36e83a18 4283
3b32a35b
VS		 4284 if (port == PORT_A)
4285 return true;
4286
41aa3448 4287 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4288 return false;
4289
41aa3448
RV		 4290 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4291 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4292
5d8a7752 4293 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4294 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4295 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4296 return true;
4297 }
4298 return false;
4299}
4300
0e32b39c 4301void
f684960e
CW		 4302intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4303{
53b41837
YN		 4304 struct intel_connector *intel_connector = to_intel_connector(connector);
4305
3f43c48d 4306 intel_attach_force_audio_property(connector);
e953fd7b 4307 intel_attach_broadcast_rgb_property(connector);
55bc60db 4308 intel_dp->color_range_auto = true;
53b41837
YN		 4309
4310 if (is_edp(intel_dp)) {
4311 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4312 drm_object_attach_property(
4313 &connector->base,
53b41837 4314 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4315 DRM_MODE_SCALE_ASPECT);
4316 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4317 }
f684960e
CW		 4318}
4319
dada1a9f
ID		 4320static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4321{
4322 intel_dp->last_power_cycle = jiffies;
4323 intel_dp->last_power_on = jiffies;
4324 intel_dp->last_backlight_off = jiffies;
4325}
4326
67a54566
DV		 4327static void
4328intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4329 struct intel_dp *intel_dp,
4330 struct edp_power_seq *out)
67a54566
DV		 4331{
4332 struct drm_i915_private *dev_priv = dev->dev_private;
4333 struct edp_power_seq cur, vbt, spec, final;
4334 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4335 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420 4336
e39b999a
VS		 4337 lockdep_assert_held(&dev_priv->pps_mutex);
4338
453c5420 4339 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4340 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4341 pp_on_reg = PCH_PP_ON_DELAYS;
4342 pp_off_reg = PCH_PP_OFF_DELAYS;
4343 pp_div_reg = PCH_PP_DIVISOR;
4344 } else {
bf13e81b
JN		 4345 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4346
4347 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4348 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4349 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4350 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4351 }
67a54566
DV		 4352
4353 /* Workaround: Need to write PP_CONTROL with the unlock key as
4354 * the very first thing. */
453c5420 4355 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4356 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4357
453c5420
JB		 4358 pp_on = I915_READ(pp_on_reg);
4359 pp_off = I915_READ(pp_off_reg);
4360 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4361
4362 /* Pull timing values out of registers */
4363 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4364 PANEL_POWER_UP_DELAY_SHIFT;
4365
4366 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4367 PANEL_LIGHT_ON_DELAY_SHIFT;
4368
4369 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4370 PANEL_LIGHT_OFF_DELAY_SHIFT;
4371
4372 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4373 PANEL_POWER_DOWN_DELAY_SHIFT;
4374
4375 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4376 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4377
4378 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4379 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4380
41aa3448 4381 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4382
4383 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4384 * our hw here, which are all in 100usec. */
4385 spec.t1_t3 = 210 * 10;
4386 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4387 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4388 spec.t10 = 500 * 10;
4389 /* This one is special and actually in units of 100ms, but zero
4390 * based in the hw (so we need to add 100 ms). But the sw vbt
4391 * table multiplies it with 1000 to make it in units of 100usec,
4392 * too. */
4393 spec.t11_t12 = (510 + 100) * 10;
4394
4395 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4396 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4397
4398 /* Use the max of the register settings and vbt. If both are
4399 * unset, fall back to the spec limits. */
4400#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4401 spec.field : \
4402 max(cur.field, vbt.field))
4403 assign_final(t1_t3);
4404 assign_final(t8);
4405 assign_final(t9);
4406 assign_final(t10);
4407 assign_final(t11_t12);
4408#undef assign_final
4409
4410#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4411 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4412 intel_dp->backlight_on_delay = get_delay(t8);
4413 intel_dp->backlight_off_delay = get_delay(t9);
4414 intel_dp->panel_power_down_delay = get_delay(t10);
4415 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4416#undef get_delay
4417
f30d26e4
JN		 4418 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4419 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4420 intel_dp->panel_power_cycle_delay);
4421
4422 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4423 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4424
4425 if (out)
4426 *out = final;
4427}
4428
4429static void
4430intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4431 struct intel_dp *intel_dp,
4432 struct edp_power_seq *seq)
4433{
4434 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4435 u32 pp_on, pp_off, pp_div, port_sel = 0;
4436 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4437 int pp_on_reg, pp_off_reg, pp_div_reg;
ad933b56 4438 enum port port = dp_to_dig_port(intel_dp)->port;
453c5420 4439
e39b999a
VS		 4440 lockdep_assert_held(&dev_priv->pps_mutex);
4441
453c5420
JB		 4442 if (HAS_PCH_SPLIT(dev)) {
4443 pp_on_reg = PCH_PP_ON_DELAYS;
4444 pp_off_reg = PCH_PP_OFF_DELAYS;
4445 pp_div_reg = PCH_PP_DIVISOR;
4446 } else {
bf13e81b
JN		 4447 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4448
4449 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4450 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4451 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4452 }
4453
b2f19d1a
PZ		 4454 /*
4455 * And finally store the new values in the power sequencer. The
4456 * backlight delays are set to 1 because we do manual waits on them. For
4457 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4458 * we'll end up waiting for the backlight off delay twice: once when we
4459 * do the manual sleep, and once when we disable the panel and wait for
4460 * the PP_STATUS bit to become zero.
4461 */
f30d26e4 4462 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4463 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4464 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4465 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4466 /* Compute the divisor for the pp clock, simply match the Bspec
4467 * formula. */
453c5420 4468 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4469 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4470 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4471
4472 /* Haswell doesn't have any port selection bits for the panel
4473 * power sequencer any more. */
bc7d38a4 4474 if (IS_VALLEYVIEW(dev)) {
ad933b56 4475 port_sel = PANEL_PORT_SELECT_VLV(port);
bc7d38a4 4476 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
ad933b56 4477 if (port == PORT_A)
a24c144c 4478 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4479 else
a24c144c 4480 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4481 }
4482
453c5420
JB		 4483 pp_on |= port_sel;
4484
4485 I915_WRITE(pp_on_reg, pp_on);
4486 I915_WRITE(pp_off_reg, pp_off);
4487 I915_WRITE(pp_div_reg, pp_div);
67a54566 4488
67a54566 4489 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4490 I915_READ(pp_on_reg),
4491 I915_READ(pp_off_reg),
4492 I915_READ(pp_div_reg));
f684960e
CW		 4493}
4494
439d7ac0
PB		 4495void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4496{
4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 struct intel_encoder *encoder;
4499 struct intel_dp *intel_dp = NULL;
4500 struct intel_crtc_config *config = NULL;
4501 struct intel_crtc *intel_crtc = NULL;
4502 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4503 u32 reg, val;
4504 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4505
4506 if (refresh_rate <= 0) {
4507 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4508 return;
4509 }
4510
4511 if (intel_connector == NULL) {
4512 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4513 return;
4514 }
4515
1fcc9d1c
DV		 4516 /*
4517 * FIXME: This needs proper synchronization with psr state. But really
4518 * hard to tell without seeing the user of this function of this code.
4519 * Check locking and ordering once that lands.
4520 */
439d7ac0
PB		 4521 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4522 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4523 return;
4524 }
4525
4526 encoder = intel_attached_encoder(&intel_connector->base);
4527 intel_dp = enc_to_intel_dp(&encoder->base);
4528 intel_crtc = encoder->new_crtc;
4529
4530 if (!intel_crtc) {
4531 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4532 return;
4533 }
4534
4535 config = &intel_crtc->config;
4536
4537 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4538 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4539 return;
4540 }
4541
4542 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4543 index = DRRS_LOW_RR;
4544
4545 if (index == intel_dp->drrs_state.refresh_rate_type) {
4546 DRM_DEBUG_KMS(
4547 "DRRS requested for previously set RR...ignoring\n");
4548 return;
4549 }
4550
4551 if (!intel_crtc->active) {
4552 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4553 return;
4554 }
4555
4556 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4557 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4558 val = I915_READ(reg);
4559 if (index > DRRS_HIGH_RR) {
4560 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4561 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4562 } else {
4563 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4564 }
4565 I915_WRITE(reg, val);
4566 }
4567
4568 /*
4569 * mutex taken to ensure that there is no race between differnt
4570 * drrs calls trying to update refresh rate. This scenario may occur
4571 * in future when idleness detection based DRRS in kernel and
4572 * possible calls from user space to set differnt RR are made.
4573 */
4574
4575 mutex_lock(&intel_dp->drrs_state.mutex);
4576
4577 intel_dp->drrs_state.refresh_rate_type = index;
4578
4579 mutex_unlock(&intel_dp->drrs_state.mutex);
4580
4581 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4582}
4583
4f9db5b5
PB		 4584static struct drm_display_mode *
4585intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4586 struct intel_connector *intel_connector,
4587 struct drm_display_mode *fixed_mode)
4588{
4589 struct drm_connector *connector = &intel_connector->base;
4590 struct intel_dp *intel_dp = &intel_dig_port->dp;
4591 struct drm_device *dev = intel_dig_port->base.base.dev;
4592 struct drm_i915_private *dev_priv = dev->dev_private;
4593 struct drm_display_mode *downclock_mode = NULL;
4594
4595 if (INTEL_INFO(dev)->gen <= 6) {
4596 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4597 return NULL;
4598 }
4599
4600 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4601 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4602 return NULL;
4603 }
4604
4605 downclock_mode = intel_find_panel_downclock
4606 (dev, fixed_mode, connector);
4607
4608 if (!downclock_mode) {
4079b8d1 4609 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4610 return NULL;
4611 }
4612
439d7ac0
PB		 4613 dev_priv->drrs.connector = intel_connector;
4614
4615 mutex_init(&intel_dp->drrs_state.mutex);
4616
4f9db5b5
PB		 4617 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4618
4619 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4620 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4621 return downclock_mode;
4622}
4623
aba86890
ID		 4624void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4625{
4626 struct drm_device *dev = intel_encoder->base.dev;
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628 struct intel_dp *intel_dp;
4629 enum intel_display_power_domain power_domain;
4630
4631 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4632 return;
4633
e39b999a
VS		 4634 mutex_lock(&dev_priv->pps_mutex);
4635
aba86890
ID		 4636 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4637 if (!edp_have_panel_vdd(intel_dp))
e39b999a 4638 goto out;
aba86890
ID		 4639 /*
4640 * The VDD bit needs a power domain reference, so if the bit is
4641 * already enabled when we boot or resume, grab this reference and
4642 * schedule a vdd off, so we don't hold on to the reference
4643 * indefinitely.
4644 */
4645 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4646 power_domain = intel_display_port_power_domain(intel_encoder);
4647 intel_display_power_get(dev_priv, power_domain);
4648
4649 edp_panel_vdd_schedule_off(intel_dp);
e39b999a
VS		 4650 out:
4651 mutex_unlock(&dev_priv->pps_mutex);
aba86890
ID		 4652}
4653
ed92f0b2 4654static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4655 struct intel_connector *intel_connector,
4656 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4657{
4658 struct drm_connector *connector = &intel_connector->base;
4659 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4660 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4661 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4662 struct drm_i915_private *dev_priv = dev->dev_private;
4663 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4664 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4665 bool has_dpcd;
4666 struct drm_display_mode *scan;
4667 struct edid *edid;
4668
4f9db5b5
PB		 4669 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4670
ed92f0b2
PZ		 4671 if (!is_edp(intel_dp))
4672 return true;
4673
aba86890 4674 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4675
ed92f0b2 4676 /* Cache DPCD and EDID for edp. */
24f3e092 4677 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4678 has_dpcd = intel_dp_get_dpcd(intel_dp);
1e0560e0 4679 intel_edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4680
4681 if (has_dpcd) {
4682 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4683 dev_priv->no_aux_handshake =
4684 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4685 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4686 } else {
4687 /* if this fails, presume the device is a ghost */
4688 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4689 return false;
4690 }
4691
4692 /* We now know it's not a ghost, init power sequence regs. */
e39b999a 4693 mutex_lock(&dev_priv->pps_mutex);
0095e6dc 4694 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
e39b999a 4695 mutex_unlock(&dev_priv->pps_mutex);
ed92f0b2 4696
060c8778 4697 mutex_lock(&dev->mode_config.mutex);
0b99836f 4698 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4699 if (edid) {
4700 if (drm_add_edid_modes(connector, edid)) {
4701 drm_mode_connector_update_edid_property(connector,
4702 edid);
4703 drm_edid_to_eld(connector, edid);
4704 } else {
4705 kfree(edid);
4706 edid = ERR_PTR(-EINVAL);
4707 }
4708 } else {
4709 edid = ERR_PTR(-ENOENT);
4710 }
4711 intel_connector->edid = edid;
4712
4713 /* prefer fixed mode from EDID if available */
4714 list_for_each_entry(scan, &connector->probed_modes, head) {
4715 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4716 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4717 downclock_mode = intel_dp_drrs_init(
4718 intel_dig_port,
4719 intel_connector, fixed_mode);
ed92f0b2
PZ		 4720 break;
4721 }
4722 }
4723
4724 /* fallback to VBT if available for eDP */
4725 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4726 fixed_mode = drm_mode_duplicate(dev,
4727 dev_priv->vbt.lfp_lvds_vbt_mode);
4728 if (fixed_mode)
4729 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4730 }
060c8778 4731 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4732
01527b31
CT		 4733 if (IS_VALLEYVIEW(dev)) {
4734 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4735 register_reboot_notifier(&intel_dp->edp_notifier);
4736 }
4737
4f9db5b5 4738 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
73580fb7 4739 intel_connector->panel.backlight_power = intel_edp_backlight_power;
ed92f0b2
PZ		 4740 intel_panel_setup_backlight(connector);
4741
4742 return true;
4743}
4744
16c25533 4745bool
f0fec3f2
PZ		 4746intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4747 struct intel_connector *intel_connector)
a4fc5ed6 4748{
f0fec3f2
PZ		 4749 struct drm_connector *connector = &intel_connector->base;
4750 struct intel_dp *intel_dp = &intel_dig_port->dp;
4751 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4752 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4753 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4754 enum port port = intel_dig_port->port;
0095e6dc 4755 struct edp_power_seq power_seq = { 0 };
0b99836f 4756 int type;
a4fc5ed6 4757
ec5b01dd
DL		 4758 /* intel_dp vfuncs */
4759 if (IS_VALLEYVIEW(dev))
4760 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4761 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4762 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4763 else if (HAS_PCH_SPLIT(dev))
4764 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4765 else
4766 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4767
153b1100
DL		 4768 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4769
0767935e
DV		 4770 /* Preserve the current hw state. */
4771 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4772 intel_dp->attached_connector = intel_connector;
3d3dc149 4773
3b32a35b 4774 if (intel_dp_is_edp(dev, port))
b329530c 4775 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4776 else
4777 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4778
f7d24902
ID		 4779 /*
4780 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4781 * for DP the encoder type can be set by the caller to
4782 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4783 */
4784 if (type == DRM_MODE_CONNECTOR_eDP)
4785 intel_encoder->type = INTEL_OUTPUT_EDP;
4786
e7281eab
ID		 4787 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4788 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4789 port_name(port));
4790
b329530c 4791 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4792 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4793
a4fc5ed6
KP		 4794 connector->interlace_allowed = true;
4795 connector->doublescan_allowed = 0;
4796
f0fec3f2 4797 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4798 edp_panel_vdd_work);
a4fc5ed6 4799
df0e9248 4800 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4801 drm_connector_register(connector);
a4fc5ed6 4802
affa9354 4803 if (HAS_DDI(dev))
bcbc889b
PZ		 4804 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4805 else
4806 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4807 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4808
0b99836f 4809 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4810 switch (port) {
4811 case PORT_A:
1d843f9d 4812 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4813 break;
4814 case PORT_B:
1d843f9d 4815 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4816 break;
4817 case PORT_C:
1d843f9d 4818 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4819 break;
4820 case PORT_D:
1d843f9d 4821 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4822 break;
4823 default:
ad1c0b19 4824 BUG();
5eb08b69
ZW		 4825 }
4826
dada1a9f 4827 if (is_edp(intel_dp)) {
e39b999a 4828 mutex_lock(&dev_priv->pps_mutex);
dada1a9f 4829 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4830 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
e39b999a 4831 mutex_unlock(&dev_priv->pps_mutex);
dada1a9f 4832 }
0095e6dc 4833
9d1a1031 4834 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4835
0e32b39c
DA		 4836 /* init MST on ports that can support it */
4837 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4838 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4839 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4840 }
4841 }
4842
0095e6dc 4843 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4844 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4845 if (is_edp(intel_dp)) {
4846 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
e39b999a 4847 mutex_lock(&dev_priv->pps_mutex);
4be73780 4848 edp_panel_vdd_off_sync(intel_dp);
e39b999a 4849 mutex_unlock(&dev_priv->pps_mutex);
15b1d171 4850 }
34ea3d38 4851 drm_connector_unregister(connector);
b2f246a8 4852 drm_connector_cleanup(connector);
16c25533 4853 return false;
b2f246a8 4854 }
32f9d658 4855
f684960e
CW		 4856 intel_dp_add_properties(intel_dp, connector);
4857
a4fc5ed6
KP		 4858 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4859 * 0xd. Failure to do so will result in spurious interrupts being
4860 * generated on the port when a cable is not attached.
4861 */
4862 if (IS_G4X(dev) && !IS_GM45(dev)) {
4863 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4864 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4865 }
16c25533
PZ		 4866
4867 return true;
a4fc5ed6 4868}
f0fec3f2
PZ		 4869
4870void
4871intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4872{
13cf5504 4873 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4874 struct intel_digital_port *intel_dig_port;
4875 struct intel_encoder *intel_encoder;
4876 struct drm_encoder *encoder;
4877 struct intel_connector *intel_connector;
4878
b14c5679 4879 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4880 if (!intel_dig_port)
4881 return;
4882
b14c5679 4883 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4884 if (!intel_connector) {
4885 kfree(intel_dig_port);
4886 return;
4887 }
4888
4889 intel_encoder = &intel_dig_port->base;
4890 encoder = &intel_encoder->base;
4891
4892 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4893 DRM_MODE_ENCODER_TMDS);
4894
5bfe2ac0 4895 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4896 intel_encoder->disable = intel_disable_dp;
00c09d70 4897 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4898 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 4899 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 4900 if (IS_CHERRYVIEW(dev)) {
9197c88b 4901 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4902 intel_encoder->pre_enable = chv_pre_enable_dp;
4903 intel_encoder->enable = vlv_enable_dp;
580d3811 4904 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4905 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4906 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4907 intel_encoder->pre_enable = vlv_pre_enable_dp;
4908 intel_encoder->enable = vlv_enable_dp;
49277c31 4909 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4910 } else {
ecff4f3b
JN		 4911 intel_encoder->pre_enable = g4x_pre_enable_dp;
4912 intel_encoder->enable = g4x_enable_dp;
49277c31 4913 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4914 }
f0fec3f2 4915
174edf1f 4916 intel_dig_port->port = port;
f0fec3f2
PZ		 4917 intel_dig_port->dp.output_reg = output_reg;
4918
00c09d70 4919 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4920 if (IS_CHERRYVIEW(dev)) {
4921 if (port == PORT_D)
4922 intel_encoder->crtc_mask = 1 << 2;
4923 else
4924 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4925 } else {
4926 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4927 }
bc079e8b 4928 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4929 intel_encoder->hot_plug = intel_dp_hot_plug;
4930
13cf5504
DA		 4931 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4932 dev_priv->hpd_irq_port[port] = intel_dig_port;
4933
15b1d171
PZ		 4934 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4935 drm_encoder_cleanup(encoder);
4936 kfree(intel_dig_port);
b2f246a8 4937 kfree(intel_connector);
15b1d171 4938 }
f0fec3f2 4939}
0e32b39c
DA		 4940
4941void intel_dp_mst_suspend(struct drm_device *dev)
4942{
4943 struct drm_i915_private *dev_priv = dev->dev_private;
4944 int i;
4945
4946 /* disable MST */
4947 for (i = 0; i < I915_MAX_PORTS; i++) {
4948 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4949 if (!intel_dig_port)
4950 continue;
4951
4952 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4953 if (!intel_dig_port->dp.can_mst)
4954 continue;
4955 if (intel_dig_port->dp.is_mst)
4956 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4957 }
4958 }
4959}
4960
4961void intel_dp_mst_resume(struct drm_device *dev)
4962{
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4964 int i;
4965
4966 for (i = 0; i < I915_MAX_PORTS; i++) {
4967 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4968 if (!intel_dig_port)
4969 continue;
4970 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4971 int ret;
4972
4973 if (!intel_dig_port->dp.can_mst)
4974 continue;
4975
4976 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4977 if (ret != 0) {
4978 intel_dp_check_mst_status(&intel_dig_port->dp);
4979 }
4980 }
4981 }
4982}
Linux 6.x block layer and io_uring tree(s)