projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: invert {ilk, snb}_gt_irq_handler check
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
68b4d824 55static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 56{
68b4d824
ID		 57 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
58
59 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 60}
61
df0e9248
CW		 62static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
63{
fa90ecef 64 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 65}
66
ea5b213a 67static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 68
a4fc5ed6 69static int
ea5b213a 70intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 71{
7183dc29 72 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 73
74 switch (max_link_bw) {
75 case DP_LINK_BW_1_62:
76 case DP_LINK_BW_2_7:
77 break;
78 default:
79 max_link_bw = DP_LINK_BW_1_62;
80 break;
81 }
82 return max_link_bw;
83}
84
cd9dde44
AJ		 85/*
86 * The units on the numbers in the next two are... bizarre. Examples will
87 * make it clearer; this one parallels an example in the eDP spec.
88 *
89 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
90 *
91 * 270000 * 1 * 8 / 10 == 216000
92 *
93 * The actual data capacity of that configuration is 2.16Gbit/s, so the
94 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
95 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
96 * 119000. At 18bpp that's 2142000 kilobits per second.
97 *
98 * Thus the strange-looking division by 10 in intel_dp_link_required, to
99 * get the result in decakilobits instead of kilobits.
100 */
101
a4fc5ed6 102static int
c898261c 103intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 104{
cd9dde44 105 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 106}
107
fe27d53e
DA		 108static int
109intel_dp_max_data_rate(int max_link_clock, int max_lanes)
110{
111 return (max_link_clock * max_lanes * 8) / 10;
112}
113
a4fc5ed6
KP		 114static int
115intel_dp_mode_valid(struct drm_connector *connector,
116 struct drm_display_mode *mode)
117{
df0e9248 118 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 119 struct intel_connector *intel_connector = to_intel_connector(connector);
120 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 121 int target_clock = mode->clock;
122 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 123
dd06f90e
JN		 124 if (is_edp(intel_dp) && fixed_mode) {
125 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 126 return MODE_PANEL;
127
dd06f90e 128 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 129 return MODE_PANEL;
03afc4a2
DV		 130
131 target_clock = fixed_mode->clock;
7de56f43
ZY		 132 }
133
36008365
DV		 134 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
135 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
136
137 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
138 mode_rate = intel_dp_link_required(target_clock, 18);
139
140 if (mode_rate > max_rate)
c4867936 141 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 142
143 if (mode->clock < 10000)
144 return MODE_CLOCK_LOW;
145
0af78a2b
DV		 146 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
147 return MODE_H_ILLEGAL;
148
a4fc5ed6
KP		 149 return MODE_OK;
150}
151
152static uint32_t
153pack_aux(uint8_t *src, int src_bytes)
154{
155 int i;
156 uint32_t v = 0;
157
158 if (src_bytes > 4)
159 src_bytes = 4;
160 for (i = 0; i < src_bytes; i++)
161 v |= ((uint32_t) src[i]) << ((3-i) * 8);
162 return v;
163}
164
165static void
166unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
167{
168 int i;
169 if (dst_bytes > 4)
170 dst_bytes = 4;
171 for (i = 0; i < dst_bytes; i++)
172 dst[i] = src >> ((3-i) * 8);
173}
174
fb0f8fbf
KP		 175/* hrawclock is 1/4 the FSB frequency */
176static int
177intel_hrawclk(struct drm_device *dev)
178{
179 struct drm_i915_private *dev_priv = dev->dev_private;
180 uint32_t clkcfg;
181
9473c8f4
VP		 182 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
183 if (IS_VALLEYVIEW(dev))
184 return 200;
185
fb0f8fbf
KP		 186 clkcfg = I915_READ(CLKCFG);
187 switch (clkcfg & CLKCFG_FSB_MASK) {
188 case CLKCFG_FSB_400:
189 return 100;
190 case CLKCFG_FSB_533:
191 return 133;
192 case CLKCFG_FSB_667:
193 return 166;
194 case CLKCFG_FSB_800:
195 return 200;
196 case CLKCFG_FSB_1067:
197 return 266;
198 case CLKCFG_FSB_1333:
199 return 333;
200 /* these two are just a guess; one of them might be right */
201 case CLKCFG_FSB_1600:
202 case CLKCFG_FSB_1600_ALT:
203 return 400;
204 default:
205 return 133;
206 }
207}
208
ebf33b18
KP		 209static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
210{
30add22d 211 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 212 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 213 u32 pp_stat_reg;
ebf33b18 214
453c5420
JB		 215 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
216 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 217}
218
219static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
220{
30add22d 221 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 222 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 223 u32 pp_ctrl_reg;
ebf33b18 224
453c5420
JB		 225 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
226 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 227}
228
9b984dae
KP		 229static void
230intel_dp_check_edp(struct intel_dp *intel_dp)
231{
30add22d 232 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 233 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 234 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 235
9b984dae
KP		 236 if (!is_edp(intel_dp))
237 return;
453c5420
JB		 238
239 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
240 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
241
ebf33b18 242 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 243 WARN(1, "eDP powered off while attempting aux channel communication.\n");
244 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 245 I915_READ(pp_stat_reg),
246 I915_READ(pp_ctrl_reg));
9b984dae
KP		 247 }
248}
249
9ee32fea
DV		 250static uint32_t
251intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
252{
253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
254 struct drm_device *dev = intel_dig_port->base.base.dev;
255 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 256 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 257 uint32_t status;
258 bool done;
259
ef04f00d 260#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 261 if (has_aux_irq)
b18ac466 262 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 263 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 264 else
265 done = wait_for_atomic(C, 10) == 0;
266 if (!done)
267 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
268 has_aux_irq);
269#undef C
270
271 return status;
272}
273
b84a1cf8 274static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp)
a4fc5ed6 275{
174edf1f
PZ		 276 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
277 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 278 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 279
a4fc5ed6 280 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 281 * and would like to run at 2MHz. So, take the
282 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 283 *
284 * Note that PCH attached eDP panels should use a 125MHz input
285 * clock divider.
a4fc5ed6 286 */
a62d0834 287 if (IS_VALLEYVIEW(dev)) {
b84a1cf8 288 return 100;
a62d0834 289 } else if (intel_dig_port->port == PORT_A) {
affa9354 290 if (HAS_DDI(dev))
b84a1cf8 291 return DIV_ROUND_CLOSEST(
b2b877ff 292 intel_ddi_get_cdclk_freq(dev_priv), 2000);
9473c8f4 293 else if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 294 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 295 else
b84a1cf8 296 return 225; /* eDP input clock at 450Mhz */
2c55c336
JN		 297 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
298 /* Workaround for non-ULT HSW */
b84a1cf8 299 return 74;
2c55c336 300 } else if (HAS_PCH_SPLIT(dev)) {
b84a1cf8 301 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 302 } else {
b84a1cf8 303 return intel_hrawclk(dev) / 2;
2c55c336 304 }
b84a1cf8
RV		 305}
306
307static int
308intel_dp_aux_ch(struct intel_dp *intel_dp,
309 uint8_t *send, int send_bytes,
310 uint8_t *recv, int recv_size)
311{
312 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
313 struct drm_device *dev = intel_dig_port->base.base.dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
316 uint32_t ch_data = ch_ctl + 4;
317 int i, ret, recv_bytes;
318 uint32_t status;
319 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp);
320 int try, precharge;
321 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
322
323 /* dp aux is extremely sensitive to irq latency, hence request the
324 * lowest possible wakeup latency and so prevent the cpu from going into
325 * deep sleep states.
326 */
327 pm_qos_update_request(&dev_priv->pm_qos, 0);
328
329 intel_dp_check_edp(intel_dp);
5eb08b69 330
6b4e0a93
DV		 331 if (IS_GEN6(dev))
332 precharge = 3;
333 else
334 precharge = 5;
335
11bee43e
JB		 336 /* Try to wait for any previous AUX channel activity */
337 for (try = 0; try < 3; try++) {
ef04f00d 338 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 339 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
340 break;
341 msleep(1);
342 }
343
344 if (try == 3) {
345 WARN(1, "dp_aux_ch not started status 0x%08x\n",
346 I915_READ(ch_ctl));
9ee32fea
DV		 347 ret = -EBUSY;
348 goto out;
4f7f7b7e
CW		 349 }
350
fb0f8fbf
KP		 351 /* Must try at least 3 times according to DP spec */
352 for (try = 0; try < 5; try++) {
353 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 354 for (i = 0; i < send_bytes; i += 4)
355 I915_WRITE(ch_data + i,
356 pack_aux(send + i, send_bytes - i));
0206e353 357
fb0f8fbf 358 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 359 I915_WRITE(ch_ctl,
360 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 361 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 362 DP_AUX_CH_CTL_TIME_OUT_400us |
363 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
364 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
365 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
366 DP_AUX_CH_CTL_DONE |
367 DP_AUX_CH_CTL_TIME_OUT_ERROR |
368 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 369
370 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 371
fb0f8fbf 372 /* Clear done status and any errors */
4f7f7b7e
CW		 373 I915_WRITE(ch_ctl,
374 status |
375 DP_AUX_CH_CTL_DONE |
376 DP_AUX_CH_CTL_TIME_OUT_ERROR |
377 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 378
379 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
380 DP_AUX_CH_CTL_RECEIVE_ERROR))
381 continue;
4f7f7b7e 382 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 383 break;
384 }
385
a4fc5ed6 386 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 387 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 388 ret = -EBUSY;
389 goto out;
a4fc5ed6
KP		 390 }
391
392 /* Check for timeout or receive error.
393 * Timeouts occur when the sink is not connected
394 */
a5b3da54 395 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 396 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 397 ret = -EIO;
398 goto out;
a5b3da54 399 }
1ae8c0a5
KP		 400
401 /* Timeouts occur when the device isn't connected, so they're
402 * "normal" -- don't fill the kernel log with these */
a5b3da54 403 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 404 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 405 ret = -ETIMEDOUT;
406 goto out;
a4fc5ed6
KP		 407 }
408
409 /* Unload any bytes sent back from the other side */
410 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
411 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 412 if (recv_bytes > recv_size)
413 recv_bytes = recv_size;
0206e353 414
4f7f7b7e
CW		 415 for (i = 0; i < recv_bytes; i += 4)
416 unpack_aux(I915_READ(ch_data + i),
417 recv + i, recv_bytes - i);
a4fc5ed6 418
9ee32fea
DV		 419 ret = recv_bytes;
420out:
421 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
422
423 return ret;
a4fc5ed6
KP		 424}
425
426/* Write data to the aux channel in native mode */
427static int
ea5b213a 428intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 429 uint16_t address, uint8_t *send, int send_bytes)
430{
431 int ret;
432 uint8_t msg[20];
433 int msg_bytes;
434 uint8_t ack;
435
9b984dae 436 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 437 if (send_bytes > 16)
438 return -1;
439 msg[0] = AUX_NATIVE_WRITE << 4;
440 msg[1] = address >> 8;
eebc863e 441 msg[2] = address & 0xff;
a4fc5ed6
KP		 442 msg[3] = send_bytes - 1;
443 memcpy(&msg[4], send, send_bytes);
444 msg_bytes = send_bytes + 4;
445 for (;;) {
ea5b213a 446 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 447 if (ret < 0)
448 return ret;
449 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
450 break;
451 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
452 udelay(100);
453 else
a5b3da54 454 return -EIO;
a4fc5ed6
KP		 455 }
456 return send_bytes;
457}
458
459/* Write a single byte to the aux channel in native mode */
460static int
ea5b213a 461intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 462 uint16_t address, uint8_t byte)
463{
ea5b213a 464 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 465}
466
467/* read bytes from a native aux channel */
468static int
ea5b213a 469intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 470 uint16_t address, uint8_t *recv, int recv_bytes)
471{
472 uint8_t msg[4];
473 int msg_bytes;
474 uint8_t reply[20];
475 int reply_bytes;
476 uint8_t ack;
477 int ret;
478
9b984dae 479 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 480 msg[0] = AUX_NATIVE_READ << 4;
481 msg[1] = address >> 8;
482 msg[2] = address & 0xff;
483 msg[3] = recv_bytes - 1;
484
485 msg_bytes = 4;
486 reply_bytes = recv_bytes + 1;
487
488 for (;;) {
ea5b213a 489 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 490 reply, reply_bytes);
a5b3da54
KP		 491 if (ret == 0)
492 return -EPROTO;
493 if (ret < 0)
a4fc5ed6
KP		 494 return ret;
495 ack = reply[0];
496 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
497 memcpy(recv, reply + 1, ret - 1);
498 return ret - 1;
499 }
500 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
501 udelay(100);
502 else
a5b3da54 503 return -EIO;
a4fc5ed6
KP		 504 }
505}
506
507static int
ab2c0672
DA		 508intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
509 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 510{
ab2c0672 511 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 512 struct intel_dp *intel_dp = container_of(adapter,
513 struct intel_dp,
514 adapter);
ab2c0672
DA		 515 uint16_t address = algo_data->address;
516 uint8_t msg[5];
517 uint8_t reply[2];
8316f337 518 unsigned retry;
ab2c0672
DA		 519 int msg_bytes;
520 int reply_bytes;
521 int ret;
522
9b984dae 523 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 524 /* Set up the command byte */
525 if (mode & MODE_I2C_READ)
526 msg[0] = AUX_I2C_READ << 4;
527 else
528 msg[0] = AUX_I2C_WRITE << 4;
529
530 if (!(mode & MODE_I2C_STOP))
531 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 532
ab2c0672
DA		 533 msg[1] = address >> 8;
534 msg[2] = address;
535
536 switch (mode) {
537 case MODE_I2C_WRITE:
538 msg[3] = 0;
539 msg[4] = write_byte;
540 msg_bytes = 5;
541 reply_bytes = 1;
542 break;
543 case MODE_I2C_READ:
544 msg[3] = 0;
545 msg_bytes = 4;
546 reply_bytes = 2;
547 break;
548 default:
549 msg_bytes = 3;
550 reply_bytes = 1;
551 break;
552 }
553
8316f337
DF		 554 for (retry = 0; retry < 5; retry++) {
555 ret = intel_dp_aux_ch(intel_dp,
556 msg, msg_bytes,
557 reply, reply_bytes);
ab2c0672 558 if (ret < 0) {
3ff99164 559 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 560 return ret;
561 }
8316f337
DF		 562
563 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
564 case AUX_NATIVE_REPLY_ACK:
565 /* I2C-over-AUX Reply field is only valid
566 * when paired with AUX ACK.
567 */
568 break;
569 case AUX_NATIVE_REPLY_NACK:
570 DRM_DEBUG_KMS("aux_ch native nack\n");
571 return -EREMOTEIO;
572 case AUX_NATIVE_REPLY_DEFER:
573 udelay(100);
574 continue;
575 default:
576 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
577 reply[0]);
578 return -EREMOTEIO;
579 }
580
ab2c0672
DA		 581 switch (reply[0] & AUX_I2C_REPLY_MASK) {
582 case AUX_I2C_REPLY_ACK:
583 if (mode == MODE_I2C_READ) {
584 *read_byte = reply[1];
585 }
586 return reply_bytes - 1;
587 case AUX_I2C_REPLY_NACK:
8316f337 588 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 589 return -EREMOTEIO;
590 case AUX_I2C_REPLY_DEFER:
8316f337 591 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 592 udelay(100);
593 break;
594 default:
8316f337 595 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 596 return -EREMOTEIO;
597 }
598 }
8316f337
DF		 599
600 DRM_ERROR("too many retries, giving up\n");
601 return -EREMOTEIO;
a4fc5ed6
KP		 602}
603
604static int
ea5b213a 605intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 606 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 607{
0b5c541b
KP		 608 int ret;
609
d54e9d28 610 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 611 intel_dp->algo.running = false;
612 intel_dp->algo.address = 0;
613 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
614
0206e353 615 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 616 intel_dp->adapter.owner = THIS_MODULE;
617 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 618 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 619 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
620 intel_dp->adapter.algo_data = &intel_dp->algo;
621 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
622
0b5c541b
KP		 623 ironlake_edp_panel_vdd_on(intel_dp);
624 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 625 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 626 return ret;
a4fc5ed6
KP		 627}
628
c6bb3538
DV		 629static void
630intel_dp_set_clock(struct intel_encoder *encoder,
631 struct intel_crtc_config *pipe_config, int link_bw)
632{
633 struct drm_device *dev = encoder->base.dev;
634
635 if (IS_G4X(dev)) {
636 if (link_bw == DP_LINK_BW_1_62) {
637 pipe_config->dpll.p1 = 2;
638 pipe_config->dpll.p2 = 10;
639 pipe_config->dpll.n = 2;
640 pipe_config->dpll.m1 = 23;
641 pipe_config->dpll.m2 = 8;
642 } else {
643 pipe_config->dpll.p1 = 1;
644 pipe_config->dpll.p2 = 10;
645 pipe_config->dpll.n = 1;
646 pipe_config->dpll.m1 = 14;
647 pipe_config->dpll.m2 = 2;
648 }
649 pipe_config->clock_set = true;
650 } else if (IS_HASWELL(dev)) {
651 /* Haswell has special-purpose DP DDI clocks. */
652 } else if (HAS_PCH_SPLIT(dev)) {
653 if (link_bw == DP_LINK_BW_1_62) {
654 pipe_config->dpll.n = 1;
655 pipe_config->dpll.p1 = 2;
656 pipe_config->dpll.p2 = 10;
657 pipe_config->dpll.m1 = 12;
658 pipe_config->dpll.m2 = 9;
659 } else {
660 pipe_config->dpll.n = 2;
661 pipe_config->dpll.p1 = 1;
662 pipe_config->dpll.p2 = 10;
663 pipe_config->dpll.m1 = 14;
664 pipe_config->dpll.m2 = 8;
665 }
666 pipe_config->clock_set = true;
667 } else if (IS_VALLEYVIEW(dev)) {
668 /* FIXME: Need to figure out optimized DP clocks for vlv. */
669 }
670}
671
00c09d70 672bool
5bfe2ac0
DV		 673intel_dp_compute_config(struct intel_encoder *encoder,
674 struct intel_crtc_config *pipe_config)
a4fc5ed6 675{
5bfe2ac0 676 struct drm_device *dev = encoder->base.dev;
36008365 677 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 678 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 679 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 680 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 681 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 682 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 683 int lane_count, clock;
397fe157 684 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 685 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 686 int bpp, mode_rate;
a4fc5ed6 687 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
ff9a6750 688 int link_avail, link_clock;
a4fc5ed6 689
bc7d38a4 690 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 691 pipe_config->has_pch_encoder = true;
692
03afc4a2 693 pipe_config->has_dp_encoder = true;
a4fc5ed6 694
dd06f90e
JN		 695 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
696 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
697 adjusted_mode);
2dd24552
JB		 698 if (!HAS_PCH_SPLIT(dev))
699 intel_gmch_panel_fitting(intel_crtc, pipe_config,
700 intel_connector->panel.fitting_mode);
701 else
b074cec8
JB		 702 intel_pch_panel_fitting(intel_crtc, pipe_config,
703 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 704 }
705
cb1793ce 706 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 707 return false;
708
083f9560
DV		 709 DRM_DEBUG_KMS("DP link computation with max lane count %i "
710 "max bw %02x pixel clock %iKHz\n",
71244653 711 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 712
36008365
DV		 713 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
714 * bpc in between. */
3e7ca985 715 bpp = pipe_config->pipe_bpp;
7984211e
ID		 716 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp) {
717 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
718 dev_priv->vbt.edp_bpp);
e1b73cba 719 bpp = min_t(int, bpp, dev_priv->vbt.edp_bpp);
7984211e 720 }
657445fe 721
36008365 722 for (; bpp >= 6*3; bpp -= 2*3) {
ff9a6750 723 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
36008365
DV		 724
725 for (clock = 0; clock <= max_clock; clock++) {
726 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
727 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
728 link_avail = intel_dp_max_data_rate(link_clock,
729 lane_count);
730
731 if (mode_rate <= link_avail) {
732 goto found;
733 }
734 }
735 }
736 }
c4867936 737
36008365 738 return false;
3685a8f3 739
36008365 740found:
55bc60db
VS		 741 if (intel_dp->color_range_auto) {
742 /*
743 * See:
744 * CEA-861-E - 5.1 Default Encoding Parameters
745 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
746 */
18316c8c 747 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 748 intel_dp->color_range = DP_COLOR_RANGE_16_235;
749 else
750 intel_dp->color_range = 0;
751 }
752
3685a8f3 753 if (intel_dp->color_range)
50f3b016 754 pipe_config->limited_color_range = true;
a4fc5ed6 755
36008365
DV		 756 intel_dp->link_bw = bws[clock];
757 intel_dp->lane_count = lane_count;
657445fe 758 pipe_config->pipe_bpp = bpp;
ff9a6750 759 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 760
36008365
DV		 761 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
762 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 763 pipe_config->port_clock, bpp);
36008365
DV		 764 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
765 mode_rate, link_avail);
a4fc5ed6 766
03afc4a2 767 intel_link_compute_m_n(bpp, lane_count,
ff9a6750 768 adjusted_mode->clock, pipe_config->port_clock,
03afc4a2 769 &pipe_config->dp_m_n);
9d1a455b 770
c6bb3538
DV		 771 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
772
03afc4a2 773 return true;
a4fc5ed6
KP		 774}
775
247d89f6
PZ		 776void intel_dp_init_link_config(struct intel_dp *intel_dp)
777{
778 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
779 intel_dp->link_configuration[0] = intel_dp->link_bw;
780 intel_dp->link_configuration[1] = intel_dp->lane_count;
781 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
782 /*
783 * Check for DPCD version > 1.1 and enhanced framing support
784 */
785 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
786 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
787 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
788 }
789}
790
7c62a164 791static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 792{
7c62a164
DV		 793 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
794 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
795 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 796 struct drm_i915_private *dev_priv = dev->dev_private;
797 u32 dpa_ctl;
798
ff9a6750 799 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 800 dpa_ctl = I915_READ(DP_A);
801 dpa_ctl &= ~DP_PLL_FREQ_MASK;
802
ff9a6750 803 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 804 /* For a long time we've carried around a ILK-DevA w/a for the
805 * 160MHz clock. If we're really unlucky, it's still required.
806 */
807 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 808 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 809 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 810 } else {
811 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 812 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 813 }
1ce17038 814
ea9b6006
DV		 815 I915_WRITE(DP_A, dpa_ctl);
816
817 POSTING_READ(DP_A);
818 udelay(500);
819}
820
a4fc5ed6
KP		 821static void
822intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
823 struct drm_display_mode *adjusted_mode)
824{
e3421a18 825 struct drm_device *dev = encoder->dev;
417e822d 826 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 827 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
bc7d38a4 828 enum port port = dp_to_dig_port(intel_dp)->port;
7c62a164 829 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
a4fc5ed6 830
417e822d 831 /*
1a2eb460 832 * There are four kinds of DP registers:
417e822d
KP		 833 *
834 * IBX PCH
1a2eb460
KP		 835 * SNB CPU
836 * IVB CPU
417e822d
KP		 837 * CPT PCH
838 *
839 * IBX PCH and CPU are the same for almost everything,
840 * except that the CPU DP PLL is configured in this
841 * register
842 *
843 * CPT PCH is quite different, having many bits moved
844 * to the TRANS_DP_CTL register instead. That
845 * configuration happens (oddly) in ironlake_pch_enable
846 */
9c9e7927 847
417e822d
KP		 848 /* Preserve the BIOS-computed detected bit. This is
849 * supposed to be read-only.
850 */
851 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 852
417e822d 853 /* Handle DP bits in common between all three register formats */
417e822d 854 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 855 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 856
e0dac65e
WF		 857 if (intel_dp->has_audio) {
858 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 859 pipe_name(crtc->pipe));
ea5b213a 860 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 861 intel_write_eld(encoder, adjusted_mode);
862 }
247d89f6
PZ		 863
864 intel_dp_init_link_config(intel_dp);
a4fc5ed6 865
417e822d 866 /* Split out the IBX/CPU vs CPT settings */
32f9d658 867
bc7d38a4 868 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 869 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
870 intel_dp->DP |= DP_SYNC_HS_HIGH;
871 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
872 intel_dp->DP |= DP_SYNC_VS_HIGH;
873 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
874
875 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
876 intel_dp->DP |= DP_ENHANCED_FRAMING;
877
7c62a164 878 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 879 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 880 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 881 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 882
883 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
884 intel_dp->DP |= DP_SYNC_HS_HIGH;
885 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
886 intel_dp->DP |= DP_SYNC_VS_HIGH;
887 intel_dp->DP |= DP_LINK_TRAIN_OFF;
888
889 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
890 intel_dp->DP |= DP_ENHANCED_FRAMING;
891
7c62a164 892 if (crtc->pipe == 1)
417e822d 893 intel_dp->DP |= DP_PIPEB_SELECT;
417e822d
KP		 894 } else {
895 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 896 }
ea9b6006 897
bc7d38a4 898 if (port == PORT_A && !IS_VALLEYVIEW(dev))
7c62a164 899 ironlake_set_pll_cpu_edp(intel_dp);
a4fc5ed6
KP		 900}
901
99ea7127
KP		 902#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
903#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
904
905#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
906#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
907
908#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
909#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
910
911static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
912 u32 mask,
913 u32 value)
bd943159 914{
30add22d 915 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 916 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 917 u32 pp_stat_reg, pp_ctrl_reg;
918
919 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
920 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 921
99ea7127 922 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 923 mask, value,
924 I915_READ(pp_stat_reg),
925 I915_READ(pp_ctrl_reg));
32ce697c 926
453c5420 927 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 928 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 929 I915_READ(pp_stat_reg),
930 I915_READ(pp_ctrl_reg));
32ce697c 931 }
99ea7127 932}
32ce697c 933
99ea7127
KP		 934static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
935{
936 DRM_DEBUG_KMS("Wait for panel power on\n");
937 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 938}
939
99ea7127
KP		 940static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
941{
942 DRM_DEBUG_KMS("Wait for panel power off time\n");
943 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
944}
945
946static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
947{
948 DRM_DEBUG_KMS("Wait for panel power cycle\n");
949 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
950}
951
952
832dd3c1
KP		 953/* Read the current pp_control value, unlocking the register if it
954 * is locked
955 */
956
453c5420 957static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 958{
453c5420
JB		 959 struct drm_device *dev = intel_dp_to_dev(intel_dp);
960 struct drm_i915_private *dev_priv = dev->dev_private;
961 u32 control;
962 u32 pp_ctrl_reg;
963
964 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
965 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 966
967 control &= ~PANEL_UNLOCK_MASK;
968 control |= PANEL_UNLOCK_REGS;
969 return control;
bd943159
KP		 970}
971
82a4d9c0 972void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 973{
30add22d 974 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 975 struct drm_i915_private *dev_priv = dev->dev_private;
976 u32 pp;
453c5420 977 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 978
97af61f5
KP		 979 if (!is_edp(intel_dp))
980 return;
f01eca2e 981 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 982
bd943159
KP		 983 WARN(intel_dp->want_panel_vdd,
984 "eDP VDD already requested on\n");
985
986 intel_dp->want_panel_vdd = true;
99ea7127 987
bd943159
KP		 988 if (ironlake_edp_have_panel_vdd(intel_dp)) {
989 DRM_DEBUG_KMS("eDP VDD already on\n");
990 return;
991 }
992
99ea7127
KP		 993 if (!ironlake_edp_have_panel_power(intel_dp))
994 ironlake_wait_panel_power_cycle(intel_dp);
995
453c5420 996 pp = ironlake_get_pp_control(intel_dp);
5d613501 997 pp |= EDP_FORCE_VDD;
ebf33b18 998
453c5420
JB		 999 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1000 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1001
1002 I915_WRITE(pp_ctrl_reg, pp);
1003 POSTING_READ(pp_ctrl_reg);
1004 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1005 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1006 /*
1007 * If the panel wasn't on, delay before accessing aux channel
1008 */
1009 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1010 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1011 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1012 }
5d613501
JB		 1013}
1014
bd943159 1015static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1016{
30add22d 1017 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1018 struct drm_i915_private *dev_priv = dev->dev_private;
1019 u32 pp;
453c5420 1020 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1021
a0e99e68
DV		 1022 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1023
bd943159 1024 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1025 pp = ironlake_get_pp_control(intel_dp);
bd943159 1026 pp &= ~EDP_FORCE_VDD;
bd943159 1027
453c5420
JB		 1028 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1029 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1030
1031 I915_WRITE(pp_ctrl_reg, pp);
1032 POSTING_READ(pp_ctrl_reg);
99ea7127 1033
453c5420
JB		 1034 /* Make sure sequencer is idle before allowing subsequent activity */
1035 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1036 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1037 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1038 }
1039}
5d613501 1040
bd943159
KP		 1041static void ironlake_panel_vdd_work(struct work_struct *__work)
1042{
1043 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1044 struct intel_dp, panel_vdd_work);
30add22d 1045 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1046
627f7675 1047 mutex_lock(&dev->mode_config.mutex);
bd943159 1048 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1049 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1050}
1051
82a4d9c0 1052void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1053{
97af61f5
KP		 1054 if (!is_edp(intel_dp))
1055 return;
5d613501 1056
bd943159
KP		 1057 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1058 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1059
bd943159
KP		 1060 intel_dp->want_panel_vdd = false;
1061
1062 if (sync) {
1063 ironlake_panel_vdd_off_sync(intel_dp);
1064 } else {
1065 /*
1066 * Queue the timer to fire a long
1067 * time from now (relative to the power down delay)
1068 * to keep the panel power up across a sequence of operations
1069 */
1070 schedule_delayed_work(&intel_dp->panel_vdd_work,
1071 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1072 }
5d613501
JB		 1073}
1074
82a4d9c0 1075void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1076{
30add22d 1077 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1078 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1079 u32 pp;
453c5420 1080 u32 pp_ctrl_reg;
9934c132 1081
97af61f5 1082 if (!is_edp(intel_dp))
bd943159 1083 return;
99ea7127
KP		 1084
1085 DRM_DEBUG_KMS("Turn eDP power on\n");
1086
1087 if (ironlake_edp_have_panel_power(intel_dp)) {
1088 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1089 return;
99ea7127 1090 }
9934c132 1091
99ea7127 1092 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1093
453c5420 1094 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1095 if (IS_GEN5(dev)) {
1096 /* ILK workaround: disable reset around power sequence */
1097 pp &= ~PANEL_POWER_RESET;
1098 I915_WRITE(PCH_PP_CONTROL, pp);
1099 POSTING_READ(PCH_PP_CONTROL);
1100 }
37c6c9b0 1101
1c0ae80a 1102 pp |= POWER_TARGET_ON;
99ea7127
KP		 1103 if (!IS_GEN5(dev))
1104 pp |= PANEL_POWER_RESET;
1105
453c5420
JB		 1106 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1107
1108 I915_WRITE(pp_ctrl_reg, pp);
1109 POSTING_READ(pp_ctrl_reg);
9934c132 1110
99ea7127 1111 ironlake_wait_panel_on(intel_dp);
9934c132 1112
05ce1a49
KP		 1113 if (IS_GEN5(dev)) {
1114 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1115 I915_WRITE(PCH_PP_CONTROL, pp);
1116 POSTING_READ(PCH_PP_CONTROL);
1117 }
9934c132
JB		 1118}
1119
82a4d9c0 1120void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1121{
30add22d 1122 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1123 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1124 u32 pp;
453c5420 1125 u32 pp_ctrl_reg;
9934c132 1126
97af61f5
KP		 1127 if (!is_edp(intel_dp))
1128 return;
37c6c9b0 1129
99ea7127 1130 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1131
6cb49835 1132 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1133
453c5420 1134 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1135 /* We need to switch off panel power _and_ force vdd, for otherwise some
1136 * panels get very unhappy and cease to work. */
1137 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1138
1139 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1140
1141 I915_WRITE(pp_ctrl_reg, pp);
1142 POSTING_READ(pp_ctrl_reg);
9934c132 1143
35a38556
DV		 1144 intel_dp->want_panel_vdd = false;
1145
99ea7127 1146 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1147}
1148
d6c50ff8 1149void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1150{
da63a9f2
PZ		 1151 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1152 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1153 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1154 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1155 u32 pp;
453c5420 1156 u32 pp_ctrl_reg;
32f9d658 1157
f01eca2e
KP		 1158 if (!is_edp(intel_dp))
1159 return;
1160
28c97730 1161 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1162 /*
1163 * If we enable the backlight right away following a panel power
1164 * on, we may see slight flicker as the panel syncs with the eDP
1165 * link. So delay a bit to make sure the image is solid before
1166 * allowing it to appear.
1167 */
f01eca2e 1168 msleep(intel_dp->backlight_on_delay);
453c5420 1169 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1170 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1171
1172 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1173
1174 I915_WRITE(pp_ctrl_reg, pp);
1175 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1176
1177 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1178}
1179
d6c50ff8 1180void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1181{
30add22d 1182 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1183 struct drm_i915_private *dev_priv = dev->dev_private;
1184 u32 pp;
453c5420 1185 u32 pp_ctrl_reg;
32f9d658 1186
f01eca2e
KP		 1187 if (!is_edp(intel_dp))
1188 return;
1189
035aa3de
DV		 1190 intel_panel_disable_backlight(dev);
1191
28c97730 1192 DRM_DEBUG_KMS("\n");
453c5420 1193 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1194 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1195
1196 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1197
1198 I915_WRITE(pp_ctrl_reg, pp);
1199 POSTING_READ(pp_ctrl_reg);
f01eca2e 1200 msleep(intel_dp->backlight_off_delay);
32f9d658 1201}
a4fc5ed6 1202
2bd2ad64 1203static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1204{
da63a9f2
PZ		 1205 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1206 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1207 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1208 struct drm_i915_private *dev_priv = dev->dev_private;
1209 u32 dpa_ctl;
1210
2bd2ad64
DV		 1211 assert_pipe_disabled(dev_priv,
1212 to_intel_crtc(crtc)->pipe);
1213
d240f20f
JB		 1214 DRM_DEBUG_KMS("\n");
1215 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1216 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1217 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1218
1219 /* We don't adjust intel_dp->DP while tearing down the link, to
1220 * facilitate link retraining (e.g. after hotplug). Hence clear all
1221 * enable bits here to ensure that we don't enable too much. */
1222 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1223 intel_dp->DP |= DP_PLL_ENABLE;
1224 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1225 POSTING_READ(DP_A);
1226 udelay(200);
d240f20f
JB		 1227}
1228
2bd2ad64 1229static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1230{
da63a9f2
PZ		 1231 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1232 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1233 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1234 struct drm_i915_private *dev_priv = dev->dev_private;
1235 u32 dpa_ctl;
1236
2bd2ad64
DV		 1237 assert_pipe_disabled(dev_priv,
1238 to_intel_crtc(crtc)->pipe);
1239
d240f20f 1240 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1241 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1242 "dp pll off, should be on\n");
1243 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1244
1245 /* We can't rely on the value tracked for the DP register in
1246 * intel_dp->DP because link_down must not change that (otherwise link
1247 * re-training will fail. */
298b0b39 1248 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1249 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1250 POSTING_READ(DP_A);
d240f20f
JB		 1251 udelay(200);
1252}
1253
c7ad3810 1254/* If the sink supports it, try to set the power state appropriately */
c19b0669 1255void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1256{
1257 int ret, i;
1258
1259 /* Should have a valid DPCD by this point */
1260 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1261 return;
1262
1263 if (mode != DRM_MODE_DPMS_ON) {
1264 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1265 DP_SET_POWER_D3);
1266 if (ret != 1)
1267 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1268 } else {
1269 /*
1270 * When turning on, we need to retry for 1ms to give the sink
1271 * time to wake up.
1272 */
1273 for (i = 0; i < 3; i++) {
1274 ret = intel_dp_aux_native_write_1(intel_dp,
1275 DP_SET_POWER,
1276 DP_SET_POWER_D0);
1277 if (ret == 1)
1278 break;
1279 msleep(1);
1280 }
1281 }
1282}
1283
19d8fe15
DV		 1284static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1285 enum pipe *pipe)
d240f20f 1286{
19d8fe15 1287 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1288 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1289 struct drm_device *dev = encoder->base.dev;
1290 struct drm_i915_private *dev_priv = dev->dev_private;
1291 u32 tmp = I915_READ(intel_dp->output_reg);
1292
1293 if (!(tmp & DP_PORT_EN))
1294 return false;
1295
bc7d38a4 1296 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1297 *pipe = PORT_TO_PIPE_CPT(tmp);
bc7d38a4 1298 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1299 *pipe = PORT_TO_PIPE(tmp);
1300 } else {
1301 u32 trans_sel;
1302 u32 trans_dp;
1303 int i;
1304
1305 switch (intel_dp->output_reg) {
1306 case PCH_DP_B:
1307 trans_sel = TRANS_DP_PORT_SEL_B;
1308 break;
1309 case PCH_DP_C:
1310 trans_sel = TRANS_DP_PORT_SEL_C;
1311 break;
1312 case PCH_DP_D:
1313 trans_sel = TRANS_DP_PORT_SEL_D;
1314 break;
1315 default:
1316 return true;
1317 }
1318
1319 for_each_pipe(i) {
1320 trans_dp = I915_READ(TRANS_DP_CTL(i));
1321 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1322 *pipe = i;
1323 return true;
1324 }
1325 }
19d8fe15 1326
4a0833ec
DV		 1327 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1328 intel_dp->output_reg);
1329 }
d240f20f 1330
19d8fe15
DV		 1331 return true;
1332}
d240f20f 1333
045ac3b5
JB		 1334static void intel_dp_get_config(struct intel_encoder *encoder,
1335 struct intel_crtc_config *pipe_config)
1336{
1337 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1338 u32 tmp, flags = 0;
63000ef6
XZ		 1339 struct drm_device *dev = encoder->base.dev;
1340 struct drm_i915_private *dev_priv = dev->dev_private;
1341 enum port port = dp_to_dig_port(intel_dp)->port;
1342 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
045ac3b5 1343
63000ef6
XZ		 1344 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
1345 tmp = I915_READ(intel_dp->output_reg);
1346 if (tmp & DP_SYNC_HS_HIGH)
1347 flags |= DRM_MODE_FLAG_PHSYNC;
1348 else
1349 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1350
63000ef6
XZ		 1351 if (tmp & DP_SYNC_VS_HIGH)
1352 flags |= DRM_MODE_FLAG_PVSYNC;
1353 else
1354 flags |= DRM_MODE_FLAG_NVSYNC;
1355 } else {
1356 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1357 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1358 flags |= DRM_MODE_FLAG_PHSYNC;
1359 else
1360 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1361
63000ef6
XZ		 1362 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1363 flags |= DRM_MODE_FLAG_PVSYNC;
1364 else
1365 flags |= DRM_MODE_FLAG_NVSYNC;
1366 }
045ac3b5
JB		 1367
1368 pipe_config->adjusted_mode.flags |= flags;
f1f644dc
JB		 1369
1370 if (dp_to_dig_port(intel_dp)->port == PORT_A) {
1371 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1372 pipe_config->port_clock = 162000;
1373 else
1374 pipe_config->port_clock = 270000;
1375 }
045ac3b5
JB		 1376}
1377
2293bb5c
SK		 1378static bool is_edp_psr(struct intel_dp *intel_dp)
1379{
1380 return is_edp(intel_dp) &&
1381 intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1382}
1383
2b28bb1b
RV		 1384static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1385{
1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387
1388 if (!IS_HASWELL(dev))
1389 return false;
1390
1391 return I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
1392}
1393
1394static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1395 struct edp_vsc_psr *vsc_psr)
1396{
1397 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1398 struct drm_device *dev = dig_port->base.base.dev;
1399 struct drm_i915_private *dev_priv = dev->dev_private;
1400 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1401 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1402 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1403 uint32_t *data = (uint32_t *) vsc_psr;
1404 unsigned int i;
1405
1406 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1407 the video DIP being updated before program video DIP data buffer
1408 registers for DIP being updated. */
1409 I915_WRITE(ctl_reg, 0);
1410 POSTING_READ(ctl_reg);
1411
1412 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1413 if (i < sizeof(struct edp_vsc_psr))
1414 I915_WRITE(data_reg + i, *data++);
1415 else
1416 I915_WRITE(data_reg + i, 0);
1417 }
1418
1419 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1420 POSTING_READ(ctl_reg);
1421}
1422
1423static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1424{
1425 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1426 struct drm_i915_private *dev_priv = dev->dev_private;
1427 struct edp_vsc_psr psr_vsc;
1428
1429 if (intel_dp->psr_setup_done)
1430 return;
1431
1432 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1433 memset(&psr_vsc, 0, sizeof(psr_vsc));
1434 psr_vsc.sdp_header.HB0 = 0;
1435 psr_vsc.sdp_header.HB1 = 0x7;
1436 psr_vsc.sdp_header.HB2 = 0x2;
1437 psr_vsc.sdp_header.HB3 = 0x8;
1438 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1439
1440 /* Avoid continuous PSR exit by masking memup and hpd */
1441 I915_WRITE(EDP_PSR_DEBUG_CTL, EDP_PSR_DEBUG_MASK_MEMUP |
1442 EDP_PSR_DEBUG_MASK_HPD);
1443
1444 intel_dp->psr_setup_done = true;
1445}
1446
1447static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1448{
1449 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1450 struct drm_i915_private *dev_priv = dev->dev_private;
1451 uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp);
1452 int precharge = 0x3;
1453 int msg_size = 5; /* Header(4) + Message(1) */
1454
1455 /* Enable PSR in sink */
1456 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1457 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1458 DP_PSR_ENABLE &
1459 ~DP_PSR_MAIN_LINK_ACTIVE);
1460 else
1461 intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
1462 DP_PSR_ENABLE |
1463 DP_PSR_MAIN_LINK_ACTIVE);
1464
1465 /* Setup AUX registers */
1466 I915_WRITE(EDP_PSR_AUX_DATA1, EDP_PSR_DPCD_COMMAND);
1467 I915_WRITE(EDP_PSR_AUX_DATA2, EDP_PSR_DPCD_NORMAL_OPERATION);
1468 I915_WRITE(EDP_PSR_AUX_CTL,
1469 DP_AUX_CH_CTL_TIME_OUT_400us |
1470 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1471 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1472 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1473}
1474
1475static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1476{
1477 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1478 struct drm_i915_private *dev_priv = dev->dev_private;
1479 uint32_t max_sleep_time = 0x1f;
1480 uint32_t idle_frames = 1;
1481 uint32_t val = 0x0;
1482
1483 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1484 val |= EDP_PSR_LINK_STANDBY;
1485 val |= EDP_PSR_TP2_TP3_TIME_0us;
1486 val |= EDP_PSR_TP1_TIME_0us;
1487 val |= EDP_PSR_SKIP_AUX_EXIT;
1488 } else
1489 val |= EDP_PSR_LINK_DISABLE;
1490
1491 I915_WRITE(EDP_PSR_CTL, val |
1492 EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES |
1493 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1494 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1495 EDP_PSR_ENABLE);
1496}
1497
3f51e471
RV		 1498static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1499{
1500 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1501 struct drm_device *dev = dig_port->base.base.dev;
1502 struct drm_i915_private *dev_priv = dev->dev_private;
1503 struct drm_crtc *crtc = dig_port->base.base.crtc;
1504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1505 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
1506 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1507
1508 if (!IS_HASWELL(dev)) {
1509 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1510 dev_priv->no_psr_reason = PSR_NO_SOURCE;
1511 return false;
1512 }
1513
1514 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1515 (dig_port->port != PORT_A)) {
1516 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
1517 dev_priv->no_psr_reason = PSR_HSW_NOT_DDIA;
1518 return false;
1519 }
1520
1521 if (!is_edp_psr(intel_dp)) {
1522 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1523 dev_priv->no_psr_reason = PSR_NO_SINK;
1524 return false;
1525 }
1526
105b7c11
RV		 1527 if (!i915_enable_psr) {
1528 DRM_DEBUG_KMS("PSR disable by flag\n");
1529 dev_priv->no_psr_reason = PSR_MODULE_PARAM;
1530 return false;
1531 }
1532
3f51e471
RV		 1533 if (!intel_crtc->active || !crtc->fb || !crtc->mode.clock) {
1534 DRM_DEBUG_KMS("crtc not active for PSR\n");
1535 dev_priv->no_psr_reason = PSR_CRTC_NOT_ACTIVE;
1536 return false;
1537 }
1538
1539 if (obj->tiling_mode != I915_TILING_X ||
1540 obj->fence_reg == I915_FENCE_REG_NONE) {
1541 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
1542 dev_priv->no_psr_reason = PSR_NOT_TILED;
1543 return false;
1544 }
1545
1546 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1547 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
1548 dev_priv->no_psr_reason = PSR_SPRITE_ENABLED;
1549 return false;
1550 }
1551
1552 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1553 S3D_ENABLE) {
1554 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
1555 dev_priv->no_psr_reason = PSR_S3D_ENABLED;
1556 return false;
1557 }
1558
1559 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) {
1560 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
1561 dev_priv->no_psr_reason = PSR_INTERLACED_ENABLED;
1562 return false;
1563 }
1564
1565 return true;
1566}
1567
3d739d92 1568static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b
RV		 1569{
1570 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1571
3f51e471
RV		 1572 if (!intel_edp_psr_match_conditions(intel_dp) ||
1573 intel_edp_is_psr_enabled(dev))
2b28bb1b
RV		 1574 return;
1575
1576 /* Setup PSR once */
1577 intel_edp_psr_setup(intel_dp);
1578
1579 /* Enable PSR on the panel */
1580 intel_edp_psr_enable_sink(intel_dp);
1581
1582 /* Enable PSR on the host */
1583 intel_edp_psr_enable_source(intel_dp);
1584}
1585
3d739d92
RV		 1586void intel_edp_psr_enable(struct intel_dp *intel_dp)
1587{
1588 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1589
1590 if (intel_edp_psr_match_conditions(intel_dp) &&
1591 !intel_edp_is_psr_enabled(dev))
1592 intel_edp_psr_do_enable(intel_dp);
1593}
1594
2b28bb1b
RV		 1595void intel_edp_psr_disable(struct intel_dp *intel_dp)
1596{
1597 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1598 struct drm_i915_private *dev_priv = dev->dev_private;
1599
1600 if (!intel_edp_is_psr_enabled(dev))
1601 return;
1602
1603 I915_WRITE(EDP_PSR_CTL, I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
1604
1605 /* Wait till PSR is idle */
1606 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
1607 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1608 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1609}
1610
3d739d92
RV		 1611void intel_edp_psr_update(struct drm_device *dev)
1612{
1613 struct intel_encoder *encoder;
1614 struct intel_dp *intel_dp = NULL;
1615
1616 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1617 if (encoder->type == INTEL_OUTPUT_EDP) {
1618 intel_dp = enc_to_intel_dp(&encoder->base);
1619
1620 if (!is_edp_psr(intel_dp))
1621 return;
1622
1623 if (!intel_edp_psr_match_conditions(intel_dp))
1624 intel_edp_psr_disable(intel_dp);
1625 else
1626 if (!intel_edp_is_psr_enabled(dev))
1627 intel_edp_psr_do_enable(intel_dp);
1628 }
1629}
1630
e8cb4558 1631static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1632{
e8cb4558 1633 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 1634 enum port port = dp_to_dig_port(intel_dp)->port;
1635 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 1636
1637 /* Make sure the panel is off before trying to change the mode. But also
1638 * ensure that we have vdd while we switch off the panel. */
1639 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1640 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1641 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1642 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1643
1644 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 1645 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 1646 intel_dp_link_down(intel_dp);
d240f20f
JB		 1647}
1648
2bd2ad64 1649static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1650{
2bd2ad64 1651 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 1652 enum port port = dp_to_dig_port(intel_dp)->port;
b2634017 1653 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1654
982a3866 1655 if (port == PORT_A || IS_VALLEYVIEW(dev)) {
3739850b 1656 intel_dp_link_down(intel_dp);
b2634017
JB		 1657 if (!IS_VALLEYVIEW(dev))
1658 ironlake_edp_pll_off(intel_dp);
3739850b 1659 }
2bd2ad64
DV		 1660}
1661
e8cb4558 1662static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1663{
e8cb4558
DV		 1664 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1665 struct drm_device *dev = encoder->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1668
0c33d8d7
DV		 1669 if (WARN_ON(dp_reg & DP_PORT_EN))
1670 return;
5d613501 1671
97af61f5 1672 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1673 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1674 intel_dp_start_link_train(intel_dp);
97af61f5 1675 ironlake_edp_panel_on(intel_dp);
bd943159 1676 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1677 intel_dp_complete_link_train(intel_dp);
3ab9c637 1678 intel_dp_stop_link_train(intel_dp);
f01eca2e 1679 ironlake_edp_backlight_on(intel_dp);
89b667f8
JB		 1680
1681 if (IS_VALLEYVIEW(dev)) {
1682 struct intel_digital_port *dport =
1683 enc_to_dig_port(&encoder->base);
1684 int channel = vlv_dport_to_channel(dport);
1685
1686 vlv_wait_port_ready(dev_priv, channel);
1687 }
d240f20f
JB		 1688}
1689
2bd2ad64 1690static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1691{
2bd2ad64 1692 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1693 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 1694 struct drm_device *dev = encoder->base.dev;
89b667f8 1695 struct drm_i915_private *dev_priv = dev->dev_private;
a4fc5ed6 1696
bc7d38a4 1697 if (dport->port == PORT_A && !IS_VALLEYVIEW(dev))
2bd2ad64 1698 ironlake_edp_pll_on(intel_dp);
89b667f8
JB		 1699
1700 if (IS_VALLEYVIEW(dev)) {
89b667f8
JB		 1701 struct intel_crtc *intel_crtc =
1702 to_intel_crtc(encoder->base.crtc);
1703 int port = vlv_dport_to_channel(dport);
1704 int pipe = intel_crtc->pipe;
1705 u32 val;
1706
ae99258f 1707 val = vlv_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
89b667f8
JB		 1708 val = 0;
1709 if (pipe)
1710 val |= (1<<21);
1711 else
1712 val &= ~(1<<21);
1713 val |= 0x001000c4;
ae99258f 1714 vlv_dpio_write(dev_priv, DPIO_DATA_CHANNEL(port), val);
89b667f8 1715
ae99258f 1716 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF0(port),
89b667f8 1717 0x00760018);
ae99258f 1718 vlv_dpio_write(dev_priv, DPIO_PCS_CLOCKBUF8(port),
89b667f8
JB		 1719 0x00400888);
1720 }
1721}
1722
1723static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
1724{
1725 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1726 struct drm_device *dev = encoder->base.dev;
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728 int port = vlv_dport_to_channel(dport);
1729
1730 if (!IS_VALLEYVIEW(dev))
1731 return;
1732
89b667f8 1733 /* Program Tx lane resets to default */
ae99258f 1734 vlv_dpio_write(dev_priv, DPIO_PCS_TX(port),
89b667f8
JB		 1735 DPIO_PCS_TX_LANE2_RESET |
1736 DPIO_PCS_TX_LANE1_RESET);
ae99258f 1737 vlv_dpio_write(dev_priv, DPIO_PCS_CLK(port),
89b667f8
JB		 1738 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1739 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1740 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1741 DPIO_PCS_CLK_SOFT_RESET);
1742
1743 /* Fix up inter-pair skew failure */
ae99258f
JN		 1744 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER1(port), 0x00750f00);
1745 vlv_dpio_write(dev_priv, DPIO_TX_CTL(port), 0x00001500);
1746 vlv_dpio_write(dev_priv, DPIO_TX_LANE(port), 0x40400000);
a4fc5ed6
KP		 1747}
1748
1749/*
df0c237d
JB		 1750 * Native read with retry for link status and receiver capability reads for
1751 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1752 */
1753static bool
df0c237d
JB		 1754intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1755 uint8_t *recv, int recv_bytes)
a4fc5ed6 1756{
61da5fab
JB		 1757 int ret, i;
1758
df0c237d
JB		 1759 /*
1760 * Sinks are *supposed* to come up within 1ms from an off state,
1761 * but we're also supposed to retry 3 times per the spec.
1762 */
61da5fab 1763 for (i = 0; i < 3; i++) {
df0c237d
JB		 1764 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1765 recv_bytes);
1766 if (ret == recv_bytes)
61da5fab
JB		 1767 return true;
1768 msleep(1);
1769 }
a4fc5ed6 1770
61da5fab 1771 return false;
a4fc5ed6
KP		 1772}
1773
1774/*
1775 * Fetch AUX CH registers 0x202 - 0x207 which contain
1776 * link status information
1777 */
1778static bool
93f62dad 1779intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1780{
df0c237d
JB		 1781 return intel_dp_aux_native_read_retry(intel_dp,
1782 DP_LANE0_1_STATUS,
93f62dad 1783 link_status,
df0c237d 1784 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1785}
1786
a4fc5ed6
KP		 1787#if 0
1788static char *voltage_names[] = {
1789 "0.4V", "0.6V", "0.8V", "1.2V"
1790};
1791static char *pre_emph_names[] = {
1792 "0dB", "3.5dB", "6dB", "9.5dB"
1793};
1794static char *link_train_names[] = {
1795 "pattern 1", "pattern 2", "idle", "off"
1796};
1797#endif
1798
1799/*
1800 * These are source-specific values; current Intel hardware supports
1801 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1802 */
a4fc5ed6
KP		 1803
1804static uint8_t
1a2eb460 1805intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1806{
30add22d 1807 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1808 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1809
e2fa6fba
P		 1810 if (IS_VALLEYVIEW(dev))
1811 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 1812 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 1813 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 1814 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 1815 return DP_TRAIN_VOLTAGE_SWING_1200;
1816 else
1817 return DP_TRAIN_VOLTAGE_SWING_800;
1818}
1819
1820static uint8_t
1821intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1822{
30add22d 1823 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 1824 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 1825
22b8bf17 1826 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1827 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1828 case DP_TRAIN_VOLTAGE_SWING_400:
1829 return DP_TRAIN_PRE_EMPHASIS_9_5;
1830 case DP_TRAIN_VOLTAGE_SWING_600:
1831 return DP_TRAIN_PRE_EMPHASIS_6;
1832 case DP_TRAIN_VOLTAGE_SWING_800:
1833 return DP_TRAIN_PRE_EMPHASIS_3_5;
1834 case DP_TRAIN_VOLTAGE_SWING_1200:
1835 default:
1836 return DP_TRAIN_PRE_EMPHASIS_0;
1837 }
e2fa6fba
P		 1838 } else if (IS_VALLEYVIEW(dev)) {
1839 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1840 case DP_TRAIN_VOLTAGE_SWING_400:
1841 return DP_TRAIN_PRE_EMPHASIS_9_5;
1842 case DP_TRAIN_VOLTAGE_SWING_600:
1843 return DP_TRAIN_PRE_EMPHASIS_6;
1844 case DP_TRAIN_VOLTAGE_SWING_800:
1845 return DP_TRAIN_PRE_EMPHASIS_3_5;
1846 case DP_TRAIN_VOLTAGE_SWING_1200:
1847 default:
1848 return DP_TRAIN_PRE_EMPHASIS_0;
1849 }
bc7d38a4 1850 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 1851 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1852 case DP_TRAIN_VOLTAGE_SWING_400:
1853 return DP_TRAIN_PRE_EMPHASIS_6;
1854 case DP_TRAIN_VOLTAGE_SWING_600:
1855 case DP_TRAIN_VOLTAGE_SWING_800:
1856 return DP_TRAIN_PRE_EMPHASIS_3_5;
1857 default:
1858 return DP_TRAIN_PRE_EMPHASIS_0;
1859 }
1860 } else {
1861 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1862 case DP_TRAIN_VOLTAGE_SWING_400:
1863 return DP_TRAIN_PRE_EMPHASIS_6;
1864 case DP_TRAIN_VOLTAGE_SWING_600:
1865 return DP_TRAIN_PRE_EMPHASIS_6;
1866 case DP_TRAIN_VOLTAGE_SWING_800:
1867 return DP_TRAIN_PRE_EMPHASIS_3_5;
1868 case DP_TRAIN_VOLTAGE_SWING_1200:
1869 default:
1870 return DP_TRAIN_PRE_EMPHASIS_0;
1871 }
a4fc5ed6
KP		 1872 }
1873}
1874
e2fa6fba
P		 1875static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
1876{
1877 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1878 struct drm_i915_private *dev_priv = dev->dev_private;
1879 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1880 unsigned long demph_reg_value, preemph_reg_value,
1881 uniqtranscale_reg_value;
1882 uint8_t train_set = intel_dp->train_set[0];
cece5d58 1883 int port = vlv_dport_to_channel(dport);
e2fa6fba
P		 1884
1885 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1886 case DP_TRAIN_PRE_EMPHASIS_0:
1887 preemph_reg_value = 0x0004000;
1888 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1889 case DP_TRAIN_VOLTAGE_SWING_400:
1890 demph_reg_value = 0x2B405555;
1891 uniqtranscale_reg_value = 0x552AB83A;
1892 break;
1893 case DP_TRAIN_VOLTAGE_SWING_600:
1894 demph_reg_value = 0x2B404040;
1895 uniqtranscale_reg_value = 0x5548B83A;
1896 break;
1897 case DP_TRAIN_VOLTAGE_SWING_800:
1898 demph_reg_value = 0x2B245555;
1899 uniqtranscale_reg_value = 0x5560B83A;
1900 break;
1901 case DP_TRAIN_VOLTAGE_SWING_1200:
1902 demph_reg_value = 0x2B405555;
1903 uniqtranscale_reg_value = 0x5598DA3A;
1904 break;
1905 default:
1906 return 0;
1907 }
1908 break;
1909 case DP_TRAIN_PRE_EMPHASIS_3_5:
1910 preemph_reg_value = 0x0002000;
1911 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1912 case DP_TRAIN_VOLTAGE_SWING_400:
1913 demph_reg_value = 0x2B404040;
1914 uniqtranscale_reg_value = 0x5552B83A;
1915 break;
1916 case DP_TRAIN_VOLTAGE_SWING_600:
1917 demph_reg_value = 0x2B404848;
1918 uniqtranscale_reg_value = 0x5580B83A;
1919 break;
1920 case DP_TRAIN_VOLTAGE_SWING_800:
1921 demph_reg_value = 0x2B404040;
1922 uniqtranscale_reg_value = 0x55ADDA3A;
1923 break;
1924 default:
1925 return 0;
1926 }
1927 break;
1928 case DP_TRAIN_PRE_EMPHASIS_6:
1929 preemph_reg_value = 0x0000000;
1930 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1931 case DP_TRAIN_VOLTAGE_SWING_400:
1932 demph_reg_value = 0x2B305555;
1933 uniqtranscale_reg_value = 0x5570B83A;
1934 break;
1935 case DP_TRAIN_VOLTAGE_SWING_600:
1936 demph_reg_value = 0x2B2B4040;
1937 uniqtranscale_reg_value = 0x55ADDA3A;
1938 break;
1939 default:
1940 return 0;
1941 }
1942 break;
1943 case DP_TRAIN_PRE_EMPHASIS_9_5:
1944 preemph_reg_value = 0x0006000;
1945 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1946 case DP_TRAIN_VOLTAGE_SWING_400:
1947 demph_reg_value = 0x1B405555;
1948 uniqtranscale_reg_value = 0x55ADDA3A;
1949 break;
1950 default:
1951 return 0;
1952 }
1953 break;
1954 default:
1955 return 0;
1956 }
1957
ae99258f
JN		 1958 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x00000000);
1959 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL4(port), demph_reg_value);
1960 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL2(port),
e2fa6fba 1961 uniqtranscale_reg_value);
ae99258f
JN		 1962 vlv_dpio_write(dev_priv, DPIO_TX_SWING_CTL3(port), 0x0C782040);
1963 vlv_dpio_write(dev_priv, DPIO_PCS_STAGGER0(port), 0x00030000);
1964 vlv_dpio_write(dev_priv, DPIO_PCS_CTL_OVER1(port), preemph_reg_value);
1965 vlv_dpio_write(dev_priv, DPIO_TX_OCALINIT(port), 0x80000000);
e2fa6fba
P		 1966
1967 return 0;
1968}
1969
a4fc5ed6 1970static void
93f62dad 1971intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1972{
1973 uint8_t v = 0;
1974 uint8_t p = 0;
1975 int lane;
1a2eb460
KP		 1976 uint8_t voltage_max;
1977 uint8_t preemph_max;
a4fc5ed6 1978
33a34e4e 1979 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1980 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1981 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1982
1983 if (this_v > v)
1984 v = this_v;
1985 if (this_p > p)
1986 p = this_p;
1987 }
1988
1a2eb460 1989 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1990 if (v >= voltage_max)
1991 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1992
1a2eb460
KP		 1993 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1994 if (p >= preemph_max)
1995 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1996
1997 for (lane = 0; lane < 4; lane++)
33a34e4e 1998 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1999}
2000
2001static uint32_t
f0a3424e 2002intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2003{
3cf2efb1 2004 uint32_t signal_levels = 0;
a4fc5ed6 2005
3cf2efb1 2006 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2007 case DP_TRAIN_VOLTAGE_SWING_400:
2008 default:
2009 signal_levels |= DP_VOLTAGE_0_4;
2010 break;
2011 case DP_TRAIN_VOLTAGE_SWING_600:
2012 signal_levels |= DP_VOLTAGE_0_6;
2013 break;
2014 case DP_TRAIN_VOLTAGE_SWING_800:
2015 signal_levels |= DP_VOLTAGE_0_8;
2016 break;
2017 case DP_TRAIN_VOLTAGE_SWING_1200:
2018 signal_levels |= DP_VOLTAGE_1_2;
2019 break;
2020 }
3cf2efb1 2021 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2022 case DP_TRAIN_PRE_EMPHASIS_0:
2023 default:
2024 signal_levels |= DP_PRE_EMPHASIS_0;
2025 break;
2026 case DP_TRAIN_PRE_EMPHASIS_3_5:
2027 signal_levels |= DP_PRE_EMPHASIS_3_5;
2028 break;
2029 case DP_TRAIN_PRE_EMPHASIS_6:
2030 signal_levels |= DP_PRE_EMPHASIS_6;
2031 break;
2032 case DP_TRAIN_PRE_EMPHASIS_9_5:
2033 signal_levels |= DP_PRE_EMPHASIS_9_5;
2034 break;
2035 }
2036 return signal_levels;
2037}
2038
e3421a18
ZW		 2039/* Gen6's DP voltage swing and pre-emphasis control */
2040static uint32_t
2041intel_gen6_edp_signal_levels(uint8_t train_set)
2042{
3c5a62b5
YL		 2043 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2044 DP_TRAIN_PRE_EMPHASIS_MASK);
2045 switch (signal_levels) {
e3421a18 2046 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2047 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2048 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2049 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2050 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2051 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2052 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2053 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2054 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2055 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2056 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2057 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2058 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2059 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2060 default:
3c5a62b5
YL		 2061 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2062 "0x%x\n", signal_levels);
2063 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2064 }
2065}
2066
1a2eb460
KP		 2067/* Gen7's DP voltage swing and pre-emphasis control */
2068static uint32_t
2069intel_gen7_edp_signal_levels(uint8_t train_set)
2070{
2071 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2072 DP_TRAIN_PRE_EMPHASIS_MASK);
2073 switch (signal_levels) {
2074 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2075 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2076 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2077 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2078 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2079 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2080
2081 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2082 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2083 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2084 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2085
2086 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2087 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2088 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2089 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2090
2091 default:
2092 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2093 "0x%x\n", signal_levels);
2094 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2095 }
2096}
2097
d6c0d722
PZ		 2098/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2099static uint32_t
f0a3424e 2100intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2101{
d6c0d722
PZ		 2102 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2103 DP_TRAIN_PRE_EMPHASIS_MASK);
2104 switch (signal_levels) {
2105 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2106 return DDI_BUF_EMP_400MV_0DB_HSW;
2107 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2108 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2109 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2110 return DDI_BUF_EMP_400MV_6DB_HSW;
2111 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2112 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2113
d6c0d722
PZ		 2114 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2115 return DDI_BUF_EMP_600MV_0DB_HSW;
2116 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2117 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2118 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2119 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2120
d6c0d722
PZ		 2121 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2122 return DDI_BUF_EMP_800MV_0DB_HSW;
2123 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2124 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2125 default:
2126 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2127 "0x%x\n", signal_levels);
2128 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2129 }
a4fc5ed6
KP		 2130}
2131
f0a3424e
PZ		 2132/* Properly updates "DP" with the correct signal levels. */
2133static void
2134intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2135{
2136 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2137 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2138 struct drm_device *dev = intel_dig_port->base.base.dev;
2139 uint32_t signal_levels, mask;
2140 uint8_t train_set = intel_dp->train_set[0];
2141
22b8bf17 2142 if (HAS_DDI(dev)) {
f0a3424e
PZ		 2143 signal_levels = intel_hsw_signal_levels(train_set);
2144 mask = DDI_BUF_EMP_MASK;
e2fa6fba
P		 2145 } else if (IS_VALLEYVIEW(dev)) {
2146 signal_levels = intel_vlv_signal_levels(intel_dp);
2147 mask = 0;
bc7d38a4 2148 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2149 signal_levels = intel_gen7_edp_signal_levels(train_set);
2150 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2151 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2152 signal_levels = intel_gen6_edp_signal_levels(train_set);
2153 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2154 } else {
2155 signal_levels = intel_gen4_signal_levels(train_set);
2156 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2157 }
2158
2159 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2160
2161 *DP = (*DP & ~mask) | signal_levels;
2162}
2163
a4fc5ed6 2164static bool
ea5b213a 2165intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 2166 uint32_t dp_reg_value,
58e10eb9 2167 uint8_t dp_train_pat)
a4fc5ed6 2168{
174edf1f
PZ		 2169 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2170 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2171 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2172 enum port port = intel_dig_port->port;
a4fc5ed6
KP		 2173 int ret;
2174
22b8bf17 2175 if (HAS_DDI(dev)) {
3ab9c637 2176 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2177
2178 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2179 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2180 else
2181 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2182
2183 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2184 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2185 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2186 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2187
2188 break;
2189 case DP_TRAINING_PATTERN_1:
2190 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2191 break;
2192 case DP_TRAINING_PATTERN_2:
2193 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2194 break;
2195 case DP_TRAINING_PATTERN_3:
2196 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2197 break;
2198 }
174edf1f 2199 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2200
bc7d38a4 2201 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
47ea7542
PZ		 2202 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
2203
2204 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2205 case DP_TRAINING_PATTERN_DISABLE:
2206 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
2207 break;
2208 case DP_TRAINING_PATTERN_1:
2209 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
2210 break;
2211 case DP_TRAINING_PATTERN_2:
2212 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2213 break;
2214 case DP_TRAINING_PATTERN_3:
2215 DRM_ERROR("DP training pattern 3 not supported\n");
2216 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
2217 break;
2218 }
2219
2220 } else {
2221 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
2222
2223 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2224 case DP_TRAINING_PATTERN_DISABLE:
2225 dp_reg_value |= DP_LINK_TRAIN_OFF;
2226 break;
2227 case DP_TRAINING_PATTERN_1:
2228 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
2229 break;
2230 case DP_TRAINING_PATTERN_2:
2231 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2232 break;
2233 case DP_TRAINING_PATTERN_3:
2234 DRM_ERROR("DP training pattern 3 not supported\n");
2235 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
2236 break;
2237 }
2238 }
2239
ea5b213a
CW		 2240 I915_WRITE(intel_dp->output_reg, dp_reg_value);
2241 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 2242
ea5b213a 2243 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 2244 DP_TRAINING_PATTERN_SET,
2245 dp_train_pat);
2246
47ea7542
PZ		 2247 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
2248 DP_TRAINING_PATTERN_DISABLE) {
2249 ret = intel_dp_aux_native_write(intel_dp,
2250 DP_TRAINING_LANE0_SET,
2251 intel_dp->train_set,
2252 intel_dp->lane_count);
2253 if (ret != intel_dp->lane_count)
2254 return false;
2255 }
a4fc5ed6
KP		 2256
2257 return true;
2258}
2259
3ab9c637
ID		 2260static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2261{
2262 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2263 struct drm_device *dev = intel_dig_port->base.base.dev;
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265 enum port port = intel_dig_port->port;
2266 uint32_t val;
2267
2268 if (!HAS_DDI(dev))
2269 return;
2270
2271 val = I915_READ(DP_TP_CTL(port));
2272 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2273 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2274 I915_WRITE(DP_TP_CTL(port), val);
2275
2276 /*
2277 * On PORT_A we can have only eDP in SST mode. There the only reason
2278 * we need to set idle transmission mode is to work around a HW issue
2279 * where we enable the pipe while not in idle link-training mode.
2280 * In this case there is requirement to wait for a minimum number of
2281 * idle patterns to be sent.
2282 */
2283 if (port == PORT_A)
2284 return;
2285
2286 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2287 1))
2288 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2289}
2290
33a34e4e 2291/* Enable corresponding port and start training pattern 1 */
c19b0669 2292void
33a34e4e 2293intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 2294{
da63a9f2 2295 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 2296 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 2297 int i;
2298 uint8_t voltage;
2299 bool clock_recovery = false;
cdb0e95b 2300 int voltage_tries, loop_tries;
ea5b213a 2301 uint32_t DP = intel_dp->DP;
a4fc5ed6 2302
affa9354 2303 if (HAS_DDI(dev))
c19b0669
PZ		 2304 intel_ddi_prepare_link_retrain(encoder);
2305
3cf2efb1
CW		 2306 /* Write the link configuration data */
2307 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
2308 intel_dp->link_configuration,
2309 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 2310
2311 DP |= DP_PORT_EN;
1a2eb460 2312
33a34e4e 2313 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 2314 voltage = 0xff;
cdb0e95b
KP		 2315 voltage_tries = 0;
2316 loop_tries = 0;
a4fc5ed6
KP		 2317 clock_recovery = false;
2318 for (;;) {
33a34e4e 2319 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 2320 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 2321
2322 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 2323
a7c9655f 2324 /* Set training pattern 1 */
47ea7542 2325 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2326 DP_TRAINING_PATTERN_1 |
2327 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 2328 break;
a4fc5ed6 2329
a7c9655f 2330 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 2331 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2332 DRM_ERROR("failed to get link status\n");
a4fc5ed6 2333 break;
93f62dad 2334 }
a4fc5ed6 2335
01916270 2336 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 2337 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 2338 clock_recovery = true;
2339 break;
2340 }
2341
2342 /* Check to see if we've tried the max voltage */
2343 for (i = 0; i < intel_dp->lane_count; i++)
2344 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 2345 break;
3b4f819d 2346 if (i == intel_dp->lane_count) {
b06fbda3
DV		 2347 ++loop_tries;
2348 if (loop_tries == 5) {
cdb0e95b
KP		 2349 DRM_DEBUG_KMS("too many full retries, give up\n");
2350 break;
2351 }
2352 memset(intel_dp->train_set, 0, 4);
2353 voltage_tries = 0;
2354 continue;
2355 }
a4fc5ed6 2356
3cf2efb1 2357 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 2358 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 2359 ++voltage_tries;
b06fbda3
DV		 2360 if (voltage_tries == 5) {
2361 DRM_DEBUG_KMS("too many voltage retries, give up\n");
2362 break;
2363 }
2364 } else
2365 voltage_tries = 0;
2366 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 2367
3cf2efb1 2368 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2369 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 2370 }
2371
33a34e4e
JB		 2372 intel_dp->DP = DP;
2373}
2374
c19b0669 2375void
33a34e4e
JB		 2376intel_dp_complete_link_train(struct intel_dp *intel_dp)
2377{
33a34e4e 2378 bool channel_eq = false;
37f80975 2379 int tries, cr_tries;
33a34e4e
JB		 2380 uint32_t DP = intel_dp->DP;
2381
a4fc5ed6
KP		 2382 /* channel equalization */
2383 tries = 0;
37f80975 2384 cr_tries = 0;
a4fc5ed6
KP		 2385 channel_eq = false;
2386 for (;;) {
93f62dad 2387 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 2388
37f80975
JB		 2389 if (cr_tries > 5) {
2390 DRM_ERROR("failed to train DP, aborting\n");
2391 intel_dp_link_down(intel_dp);
2392 break;
2393 }
2394
f0a3424e 2395 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 2396
a4fc5ed6 2397 /* channel eq pattern */
47ea7542 2398 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 2399 DP_TRAINING_PATTERN_2 |
2400 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 2401 break;
2402
a7c9655f 2403 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 2404 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 2405 break;
a4fc5ed6 2406
37f80975 2407 /* Make sure clock is still ok */
01916270 2408 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 2409 intel_dp_start_link_train(intel_dp);
2410 cr_tries++;
2411 continue;
2412 }
2413
1ffdff13 2414 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 2415 channel_eq = true;
2416 break;
2417 }
a4fc5ed6 2418
37f80975
JB		 2419 /* Try 5 times, then try clock recovery if that fails */
2420 if (tries > 5) {
2421 intel_dp_link_down(intel_dp);
2422 intel_dp_start_link_train(intel_dp);
2423 tries = 0;
2424 cr_tries++;
2425 continue;
2426 }
a4fc5ed6 2427
3cf2efb1 2428 /* Compute new intel_dp->train_set as requested by target */
93f62dad 2429 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 2430 ++tries;
869184a6 2431 }
3cf2efb1 2432
3ab9c637
ID		 2433 intel_dp_set_idle_link_train(intel_dp);
2434
2435 intel_dp->DP = DP;
2436
d6c0d722 2437 if (channel_eq)
07f42258 2438 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 2439
3ab9c637
ID		 2440}
2441
2442void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2443{
2444 intel_dp_set_link_train(intel_dp, intel_dp->DP,
2445 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 2446}
2447
2448static void
ea5b213a 2449intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 2450{
da63a9f2 2451 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2452 enum port port = intel_dig_port->port;
da63a9f2 2453 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2454 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 2455 struct intel_crtc *intel_crtc =
2456 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 2457 uint32_t DP = intel_dp->DP;
a4fc5ed6 2458
c19b0669
PZ		 2459 /*
2460 * DDI code has a strict mode set sequence and we should try to respect
2461 * it, otherwise we might hang the machine in many different ways. So we
2462 * really should be disabling the port only on a complete crtc_disable
2463 * sequence. This function is just called under two conditions on DDI
2464 * code:
2465 * - Link train failed while doing crtc_enable, and on this case we
2466 * really should respect the mode set sequence and wait for a
2467 * crtc_disable.
2468 * - Someone turned the monitor off and intel_dp_check_link_status
2469 * called us. We don't need to disable the whole port on this case, so
2470 * when someone turns the monitor on again,
2471 * intel_ddi_prepare_link_retrain will take care of redoing the link
2472 * train.
2473 */
affa9354 2474 if (HAS_DDI(dev))
c19b0669
PZ		 2475 return;
2476
0c33d8d7 2477 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 2478 return;
2479
28c97730 2480 DRM_DEBUG_KMS("\n");
32f9d658 2481
bc7d38a4 2482 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 2483 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 2484 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 2485 } else {
2486 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 2487 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 2488 }
fe255d00 2489 POSTING_READ(intel_dp->output_reg);
5eb08b69 2490
ab527efc
DV		 2491 /* We don't really know why we're doing this */
2492 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2493
493a7081 2494 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2495 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2496 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2497
5bddd17f
EA		 2498 /* Hardware workaround: leaving our transcoder select
2499 * set to transcoder B while it's off will prevent the
2500 * corresponding HDMI output on transcoder A.
2501 *
2502 * Combine this with another hardware workaround:
2503 * transcoder select bit can only be cleared while the
2504 * port is enabled.
2505 */
2506 DP &= ~DP_PIPEB_SELECT;
2507 I915_WRITE(intel_dp->output_reg, DP);
2508
2509 /* Changes to enable or select take place the vblank
2510 * after being written.
2511 */
ff50afe9
DV		 2512 if (WARN_ON(crtc == NULL)) {
2513 /* We should never try to disable a port without a crtc
2514 * attached. For paranoia keep the code around for a
2515 * bit. */
31acbcc4
CW		 2516 POSTING_READ(intel_dp->output_reg);
2517 msleep(50);
2518 } else
ab527efc 2519 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2520 }
2521
832afda6 2522 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2523 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2524 POSTING_READ(intel_dp->output_reg);
f01eca2e 2525 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2526}
2527
26d61aad
KP		 2528static bool
2529intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2530{
577c7a50
DL		 2531 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2532
92fd8fd1 2533 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2534 sizeof(intel_dp->dpcd)) == 0)
2535 return false; /* aux transfer failed */
92fd8fd1 2536
577c7a50
DL		 2537 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2538 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2539 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2540
edb39244
AJ		 2541 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2542 return false; /* DPCD not present */
2543
2293bb5c
SK		 2544 /* Check if the panel supports PSR */
2545 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2546 intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
2547 intel_dp->psr_dpcd,
2548 sizeof(intel_dp->psr_dpcd));
2549 if (is_edp_psr(intel_dp))
2550 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
edb39244
AJ		 2551 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2552 DP_DWN_STRM_PORT_PRESENT))
2553 return true; /* native DP sink */
2554
2555 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2556 return true; /* no per-port downstream info */
2557
2558 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2559 intel_dp->downstream_ports,
2560 DP_MAX_DOWNSTREAM_PORTS) == 0)
2561 return false; /* downstream port status fetch failed */
2562
2563 return true;
92fd8fd1
KP		 2564}
2565
0d198328
AJ		 2566static void
2567intel_dp_probe_oui(struct intel_dp *intel_dp)
2568{
2569 u8 buf[3];
2570
2571 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2572 return;
2573
351cfc34
DV		 2574 ironlake_edp_panel_vdd_on(intel_dp);
2575
0d198328
AJ		 2576 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2577 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2578 buf[0], buf[1], buf[2]);
2579
2580 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2581 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2582 buf[0], buf[1], buf[2]);
351cfc34
DV		 2583
2584 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2585}
2586
a60f0e38
JB		 2587static bool
2588intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2589{
2590 int ret;
2591
2592 ret = intel_dp_aux_native_read_retry(intel_dp,
2593 DP_DEVICE_SERVICE_IRQ_VECTOR,
2594 sink_irq_vector, 1);
2595 if (!ret)
2596 return false;
2597
2598 return true;
2599}
2600
2601static void
2602intel_dp_handle_test_request(struct intel_dp *intel_dp)
2603{
2604 /* NAK by default */
9324cf7f 2605 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2606}
2607
a4fc5ed6
KP		 2608/*
2609 * According to DP spec
2610 * 5.1.2:
2611 * 1. Read DPCD
2612 * 2. Configure link according to Receiver Capabilities
2613 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2614 * 4. Check link status on receipt of hot-plug interrupt
2615 */
2616
00c09d70 2617void
ea5b213a 2618intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2619{
da63a9f2 2620 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2621 u8 sink_irq_vector;
93f62dad 2622 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2623
da63a9f2 2624 if (!intel_encoder->connectors_active)
d2b996ac 2625 return;
59cd09e1 2626
da63a9f2 2627 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2628 return;
2629
92fd8fd1 2630 /* Try to read receiver status if the link appears to be up */
93f62dad 2631 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2632 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2633 return;
2634 }
2635
92fd8fd1 2636 /* Now read the DPCD to see if it's actually running */
26d61aad 2637 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2638 intel_dp_link_down(intel_dp);
2639 return;
2640 }
2641
a60f0e38
JB		 2642 /* Try to read the source of the interrupt */
2643 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2644 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2645 /* Clear interrupt source */
2646 intel_dp_aux_native_write_1(intel_dp,
2647 DP_DEVICE_SERVICE_IRQ_VECTOR,
2648 sink_irq_vector);
2649
2650 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2651 intel_dp_handle_test_request(intel_dp);
2652 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2653 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2654 }
2655
1ffdff13 2656 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2657 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2658 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2659 intel_dp_start_link_train(intel_dp);
2660 intel_dp_complete_link_train(intel_dp);
3ab9c637 2661 intel_dp_stop_link_train(intel_dp);
33a34e4e 2662 }
a4fc5ed6 2663}
a4fc5ed6 2664
caf9ab24 2665/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2666static enum drm_connector_status
26d61aad 2667intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2668{
caf9ab24
AJ		 2669 uint8_t *dpcd = intel_dp->dpcd;
2670 bool hpd;
2671 uint8_t type;
2672
2673 if (!intel_dp_get_dpcd(intel_dp))
2674 return connector_status_disconnected;
2675
2676 /* if there's no downstream port, we're done */
2677 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2678 return connector_status_connected;
caf9ab24
AJ		 2679
2680 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2681 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2682 if (hpd) {
23235177 2683 uint8_t reg;
caf9ab24 2684 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2685 &reg, 1))
caf9ab24 2686 return connector_status_unknown;
23235177
AJ		 2687 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2688 : connector_status_disconnected;
caf9ab24
AJ		 2689 }
2690
2691 /* If no HPD, poke DDC gently */
2692 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2693 return connector_status_connected;
caf9ab24
AJ		 2694
2695 /* Well we tried, say unknown for unreliable port types */
2696 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2697 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2698 return connector_status_unknown;
2699
2700 /* Anything else is out of spec, warn and ignore */
2701 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2702 return connector_status_disconnected;
71ba9000
AJ		 2703}
2704
5eb08b69 2705static enum drm_connector_status
a9756bb5 2706ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2707{
30add22d 2708 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2709 struct drm_i915_private *dev_priv = dev->dev_private;
2710 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2711 enum drm_connector_status status;
2712
fe16d949
CW		 2713 /* Can't disconnect eDP, but you can close the lid... */
2714 if (is_edp(intel_dp)) {
30add22d 2715 status = intel_panel_detect(dev);
fe16d949
CW		 2716 if (status == connector_status_unknown)
2717 status = connector_status_connected;
2718 return status;
2719 }
01cb9ea6 2720
1b469639
DL		 2721 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2722 return connector_status_disconnected;
2723
26d61aad 2724 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2725}
2726
a4fc5ed6 2727static enum drm_connector_status
a9756bb5 2728g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2729{
30add22d 2730 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2731 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2732 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2733 uint32_t bit;
5eb08b69 2734
35aad75f
JB		 2735 /* Can't disconnect eDP, but you can close the lid... */
2736 if (is_edp(intel_dp)) {
2737 enum drm_connector_status status;
2738
2739 status = intel_panel_detect(dev);
2740 if (status == connector_status_unknown)
2741 status = connector_status_connected;
2742 return status;
2743 }
2744
34f2be46
VS		 2745 switch (intel_dig_port->port) {
2746 case PORT_B:
26739f12 2747 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2748 break;
34f2be46 2749 case PORT_C:
26739f12 2750 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2751 break;
34f2be46 2752 case PORT_D:
26739f12 2753 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2754 break;
2755 default:
2756 return connector_status_unknown;
2757 }
2758
10f76a38 2759 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2760 return connector_status_disconnected;
2761
26d61aad 2762 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2763}
2764
8c241fef
KP		 2765static struct edid *
2766intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2767{
9cd300e0 2768 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2769
9cd300e0
JN		 2770 /* use cached edid if we have one */
2771 if (intel_connector->edid) {
2772 struct edid *edid;
2773 int size;
2774
2775 /* invalid edid */
2776 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2777 return NULL;
2778
9cd300e0 2779 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
edbe1581 2780 edid = kmemdup(intel_connector->edid, size, GFP_KERNEL);
d6f24d0f
JB		 2781 if (!edid)
2782 return NULL;
2783
d6f24d0f
JB		 2784 return edid;
2785 }
8c241fef 2786
9cd300e0 2787 return drm_get_edid(connector, adapter);
8c241fef
KP		 2788}
2789
2790static int
2791intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2792{
9cd300e0 2793 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2794
9cd300e0
JN		 2795 /* use cached edid if we have one */
2796 if (intel_connector->edid) {
2797 /* invalid edid */
2798 if (IS_ERR(intel_connector->edid))
2799 return 0;
2800
2801 return intel_connector_update_modes(connector,
2802 intel_connector->edid);
d6f24d0f
JB		 2803 }
2804
9cd300e0 2805 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2806}
2807
a9756bb5
ZW		 2808static enum drm_connector_status
2809intel_dp_detect(struct drm_connector *connector, bool force)
2810{
2811 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2812 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2813 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2814 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2815 enum drm_connector_status status;
2816 struct edid *edid = NULL;
2817
2818 intel_dp->has_audio = false;
2819
2820 if (HAS_PCH_SPLIT(dev))
2821 status = ironlake_dp_detect(intel_dp);
2822 else
2823 status = g4x_dp_detect(intel_dp);
1b9be9d0 2824
a9756bb5
ZW		 2825 if (status != connector_status_connected)
2826 return status;
2827
0d198328
AJ		 2828 intel_dp_probe_oui(intel_dp);
2829
c3e5f67b
DV		 2830 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2831 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2832 } else {
8c241fef 2833 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2834 if (edid) {
2835 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2836 kfree(edid);
2837 }
a9756bb5
ZW		 2838 }
2839
d63885da
PZ		 2840 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2841 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2842 return connector_status_connected;
a4fc5ed6
KP		 2843}
2844
2845static int intel_dp_get_modes(struct drm_connector *connector)
2846{
df0e9248 2847 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2848 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2849 struct drm_device *dev = connector->dev;
32f9d658 2850 int ret;
a4fc5ed6
KP		 2851
2852 /* We should parse the EDID data and find out if it has an audio sink
2853 */
2854
8c241fef 2855 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2856 if (ret)
32f9d658
ZW		 2857 return ret;
2858
f8779fda 2859 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2860 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2861 struct drm_display_mode *mode;
dd06f90e
JN		 2862 mode = drm_mode_duplicate(dev,
2863 intel_connector->panel.fixed_mode);
f8779fda 2864 if (mode) {
32f9d658
ZW		 2865 drm_mode_probed_add(connector, mode);
2866 return 1;
2867 }
2868 }
2869 return 0;
a4fc5ed6
KP		 2870}
2871
1aad7ac0
CW		 2872static bool
2873intel_dp_detect_audio(struct drm_connector *connector)
2874{
2875 struct intel_dp *intel_dp = intel_attached_dp(connector);
2876 struct edid *edid;
2877 bool has_audio = false;
2878
8c241fef 2879 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2880 if (edid) {
2881 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2882 kfree(edid);
2883 }
2884
2885 return has_audio;
2886}
2887
f684960e
CW		 2888static int
2889intel_dp_set_property(struct drm_connector *connector,
2890 struct drm_property *property,
2891 uint64_t val)
2892{
e953fd7b 2893 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2894 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2895 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2896 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2897 int ret;
2898
662595df 2899 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2900 if (ret)
2901 return ret;
2902
3f43c48d 2903 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2904 int i = val;
2905 bool has_audio;
2906
2907 if (i == intel_dp->force_audio)
f684960e
CW		 2908 return 0;
2909
1aad7ac0 2910 intel_dp->force_audio = i;
f684960e 2911
c3e5f67b 2912 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2913 has_audio = intel_dp_detect_audio(connector);
2914 else
c3e5f67b 2915 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2916
2917 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2918 return 0;
2919
1aad7ac0 2920 intel_dp->has_audio = has_audio;
f684960e
CW		 2921 goto done;
2922 }
2923
e953fd7b 2924 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2925 bool old_auto = intel_dp->color_range_auto;
2926 uint32_t old_range = intel_dp->color_range;
2927
55bc60db
VS		 2928 switch (val) {
2929 case INTEL_BROADCAST_RGB_AUTO:
2930 intel_dp->color_range_auto = true;
2931 break;
2932 case INTEL_BROADCAST_RGB_FULL:
2933 intel_dp->color_range_auto = false;
2934 intel_dp->color_range = 0;
2935 break;
2936 case INTEL_BROADCAST_RGB_LIMITED:
2937 intel_dp->color_range_auto = false;
2938 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2939 break;
2940 default:
2941 return -EINVAL;
2942 }
ae4edb80
DV		 2943
2944 if (old_auto == intel_dp->color_range_auto &&
2945 old_range == intel_dp->color_range)
2946 return 0;
2947
e953fd7b
CW		 2948 goto done;
2949 }
2950
53b41837
YN		 2951 if (is_edp(intel_dp) &&
2952 property == connector->dev->mode_config.scaling_mode_property) {
2953 if (val == DRM_MODE_SCALE_NONE) {
2954 DRM_DEBUG_KMS("no scaling not supported\n");
2955 return -EINVAL;
2956 }
2957
2958 if (intel_connector->panel.fitting_mode == val) {
2959 /* the eDP scaling property is not changed */
2960 return 0;
2961 }
2962 intel_connector->panel.fitting_mode = val;
2963
2964 goto done;
2965 }
2966
f684960e
CW		 2967 return -EINVAL;
2968
2969done:
c0c36b94
CW		 2970 if (intel_encoder->base.crtc)
2971 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2972
2973 return 0;
2974}
2975
a4fc5ed6 2976static void
73845adf 2977intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 2978{
1d508706 2979 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2980
9cd300e0
JN		 2981 if (!IS_ERR_OR_NULL(intel_connector->edid))
2982 kfree(intel_connector->edid);
2983
acd8db10
PZ		 2984 /* Can't call is_edp() since the encoder may have been destroyed
2985 * already. */
2986 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 2987 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 2988
a4fc5ed6
KP		 2989 drm_sysfs_connector_remove(connector);
2990 drm_connector_cleanup(connector);
55f78c43 2991 kfree(connector);
a4fc5ed6
KP		 2992}
2993
00c09d70 2994void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2995{
da63a9f2
PZ		 2996 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2997 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 2998 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927
DV		 2999
3000 i2c_del_adapter(&intel_dp->adapter);
3001 drm_encoder_cleanup(encoder);
bd943159
KP		 3002 if (is_edp(intel_dp)) {
3003 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
bd173813 3004 mutex_lock(&dev->mode_config.mutex);
bd943159 3005 ironlake_panel_vdd_off_sync(intel_dp);
bd173813 3006 mutex_unlock(&dev->mode_config.mutex);
bd943159 3007 }
da63a9f2 3008 kfree(intel_dig_port);
24d05927
DV		 3009}
3010
a4fc5ed6 3011static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 3012 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 3013};
3014
3015static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 3016 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 3017 .detect = intel_dp_detect,
3018 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 3019 .set_property = intel_dp_set_property,
73845adf 3020 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 3021};
3022
3023static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3024 .get_modes = intel_dp_get_modes,
3025 .mode_valid = intel_dp_mode_valid,
df0e9248 3026 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 3027};
3028
a4fc5ed6 3029static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 3030 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 3031};
3032
995b6762 3033static void
21d40d37 3034intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 3035{
fa90ecef 3036 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 3037
885a5014 3038 intel_dp_check_link_status(intel_dp);
c8110e52 3039}
6207937d 3040
e3421a18
ZW		 3041/* Return which DP Port should be selected for Transcoder DP control */
3042int
0206e353 3043intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 3044{
3045 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 3046 struct intel_encoder *intel_encoder;
3047 struct intel_dp *intel_dp;
e3421a18 3048
fa90ecef
PZ		 3049 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3050 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 3051
fa90ecef
PZ		 3052 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3053 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 3054 return intel_dp->output_reg;
e3421a18 3055 }
ea5b213a 3056
e3421a18
ZW		 3057 return -1;
3058}
3059
36e83a18 3060/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 3061bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 3062{
3063 struct drm_i915_private *dev_priv = dev->dev_private;
3064 struct child_device_config *p_child;
3065 int i;
3066
41aa3448 3067 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 3068 return false;
3069
41aa3448
RV		 3070 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3071 p_child = dev_priv->vbt.child_dev + i;
36e83a18
ZY		 3072
3073 if (p_child->dvo_port == PORT_IDPD &&
3074 p_child->device_type == DEVICE_TYPE_eDP)
3075 return true;
3076 }
3077 return false;
3078}
3079
f684960e
CW		 3080static void
3081intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3082{
53b41837
YN		 3083 struct intel_connector *intel_connector = to_intel_connector(connector);
3084
3f43c48d 3085 intel_attach_force_audio_property(connector);
e953fd7b 3086 intel_attach_broadcast_rgb_property(connector);
55bc60db 3087 intel_dp->color_range_auto = true;
53b41837
YN		 3088
3089 if (is_edp(intel_dp)) {
3090 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 3091 drm_object_attach_property(
3092 &connector->base,
53b41837 3093 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 3094 DRM_MODE_SCALE_ASPECT);
3095 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 3096 }
f684960e
CW		 3097}
3098
67a54566
DV		 3099static void
3100intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 3101 struct intel_dp *intel_dp,
3102 struct edp_power_seq *out)
67a54566
DV		 3103{
3104 struct drm_i915_private *dev_priv = dev->dev_private;
3105 struct edp_power_seq cur, vbt, spec, final;
3106 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 3107 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3108
3109 if (HAS_PCH_SPLIT(dev)) {
3110 pp_control_reg = PCH_PP_CONTROL;
3111 pp_on_reg = PCH_PP_ON_DELAYS;
3112 pp_off_reg = PCH_PP_OFF_DELAYS;
3113 pp_div_reg = PCH_PP_DIVISOR;
3114 } else {
3115 pp_control_reg = PIPEA_PP_CONTROL;
3116 pp_on_reg = PIPEA_PP_ON_DELAYS;
3117 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3118 pp_div_reg = PIPEA_PP_DIVISOR;
3119 }
67a54566
DV		 3120
3121 /* Workaround: Need to write PP_CONTROL with the unlock key as
3122 * the very first thing. */
453c5420
JB		 3123 pp = ironlake_get_pp_control(intel_dp);
3124 I915_WRITE(pp_control_reg, pp);
67a54566 3125
453c5420
JB		 3126 pp_on = I915_READ(pp_on_reg);
3127 pp_off = I915_READ(pp_off_reg);
3128 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 3129
3130 /* Pull timing values out of registers */
3131 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3132 PANEL_POWER_UP_DELAY_SHIFT;
3133
3134 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3135 PANEL_LIGHT_ON_DELAY_SHIFT;
3136
3137 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3138 PANEL_LIGHT_OFF_DELAY_SHIFT;
3139
3140 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3141 PANEL_POWER_DOWN_DELAY_SHIFT;
3142
3143 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3144 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3145
3146 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3147 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3148
41aa3448 3149 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 3150
3151 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3152 * our hw here, which are all in 100usec. */
3153 spec.t1_t3 = 210 * 10;
3154 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3155 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3156 spec.t10 = 500 * 10;
3157 /* This one is special and actually in units of 100ms, but zero
3158 * based in the hw (so we need to add 100 ms). But the sw vbt
3159 * table multiplies it with 1000 to make it in units of 100usec,
3160 * too. */
3161 spec.t11_t12 = (510 + 100) * 10;
3162
3163 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3164 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3165
3166 /* Use the max of the register settings and vbt. If both are
3167 * unset, fall back to the spec limits. */
3168#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3169 spec.field : \
3170 max(cur.field, vbt.field))
3171 assign_final(t1_t3);
3172 assign_final(t8);
3173 assign_final(t9);
3174 assign_final(t10);
3175 assign_final(t11_t12);
3176#undef assign_final
3177
3178#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3179 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3180 intel_dp->backlight_on_delay = get_delay(t8);
3181 intel_dp->backlight_off_delay = get_delay(t9);
3182 intel_dp->panel_power_down_delay = get_delay(t10);
3183 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3184#undef get_delay
3185
f30d26e4
JN		 3186 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3187 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3188 intel_dp->panel_power_cycle_delay);
3189
3190 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3191 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3192
3193 if (out)
3194 *out = final;
3195}
3196
3197static void
3198intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3199 struct intel_dp *intel_dp,
3200 struct edp_power_seq *seq)
3201{
3202 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 3203 u32 pp_on, pp_off, pp_div, port_sel = 0;
3204 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3205 int pp_on_reg, pp_off_reg, pp_div_reg;
3206
3207 if (HAS_PCH_SPLIT(dev)) {
3208 pp_on_reg = PCH_PP_ON_DELAYS;
3209 pp_off_reg = PCH_PP_OFF_DELAYS;
3210 pp_div_reg = PCH_PP_DIVISOR;
3211 } else {
3212 pp_on_reg = PIPEA_PP_ON_DELAYS;
3213 pp_off_reg = PIPEA_PP_OFF_DELAYS;
3214 pp_div_reg = PIPEA_PP_DIVISOR;
3215 }
3216
67a54566 3217 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 3218 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3219 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
3220 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3221 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 3222 /* Compute the divisor for the pp clock, simply match the Bspec
3223 * formula. */
453c5420 3224 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 3225 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 3226 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3227
3228 /* Haswell doesn't have any port selection bits for the panel
3229 * power sequencer any more. */
bc7d38a4
ID		 3230 if (IS_VALLEYVIEW(dev)) {
3231 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
3232 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3233 if (dp_to_dig_port(intel_dp)->port == PORT_A)
453c5420 3234 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 3235 else
453c5420 3236 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 3237 }
3238
453c5420
JB		 3239 pp_on |= port_sel;
3240
3241 I915_WRITE(pp_on_reg, pp_on);
3242 I915_WRITE(pp_off_reg, pp_off);
3243 I915_WRITE(pp_div_reg, pp_div);
67a54566 3244
67a54566 3245 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 3246 I915_READ(pp_on_reg),
3247 I915_READ(pp_off_reg),
3248 I915_READ(pp_div_reg));
f684960e
CW		 3249}
3250
ed92f0b2
PZ		 3251static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3252 struct intel_connector *intel_connector)
3253{
3254 struct drm_connector *connector = &intel_connector->base;
3255 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3256 struct drm_device *dev = intel_dig_port->base.base.dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 struct drm_display_mode *fixed_mode = NULL;
3259 struct edp_power_seq power_seq = { 0 };
3260 bool has_dpcd;
3261 struct drm_display_mode *scan;
3262 struct edid *edid;
3263
3264 if (!is_edp(intel_dp))
3265 return true;
3266
3267 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3268
3269 /* Cache DPCD and EDID for edp. */
3270 ironlake_edp_panel_vdd_on(intel_dp);
3271 has_dpcd = intel_dp_get_dpcd(intel_dp);
3272 ironlake_edp_panel_vdd_off(intel_dp, false);
3273
3274 if (has_dpcd) {
3275 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3276 dev_priv->no_aux_handshake =
3277 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3278 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3279 } else {
3280 /* if this fails, presume the device is a ghost */
3281 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 3282 return false;
3283 }
3284
3285 /* We now know it's not a ghost, init power sequence regs. */
3286 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
3287 &power_seq);
3288
3289 ironlake_edp_panel_vdd_on(intel_dp);
3290 edid = drm_get_edid(connector, &intel_dp->adapter);
3291 if (edid) {
3292 if (drm_add_edid_modes(connector, edid)) {
3293 drm_mode_connector_update_edid_property(connector,
3294 edid);
3295 drm_edid_to_eld(connector, edid);
3296 } else {
3297 kfree(edid);
3298 edid = ERR_PTR(-EINVAL);
3299 }
3300 } else {
3301 edid = ERR_PTR(-ENOENT);
3302 }
3303 intel_connector->edid = edid;
3304
3305 /* prefer fixed mode from EDID if available */
3306 list_for_each_entry(scan, &connector->probed_modes, head) {
3307 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
3308 fixed_mode = drm_mode_duplicate(dev, scan);
3309 break;
3310 }
3311 }
3312
3313 /* fallback to VBT if available for eDP */
3314 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
3315 fixed_mode = drm_mode_duplicate(dev,
3316 dev_priv->vbt.lfp_lvds_vbt_mode);
3317 if (fixed_mode)
3318 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
3319 }
3320
3321 ironlake_edp_panel_vdd_off(intel_dp, false);
3322
3323 intel_panel_init(&intel_connector->panel, fixed_mode);
3324 intel_panel_setup_backlight(connector);
3325
3326 return true;
3327}
3328
16c25533 3329bool
f0fec3f2
PZ		 3330intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
3331 struct intel_connector *intel_connector)
a4fc5ed6 3332{
f0fec3f2
PZ		 3333 struct drm_connector *connector = &intel_connector->base;
3334 struct intel_dp *intel_dp = &intel_dig_port->dp;
3335 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3336 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 3337 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 3338 enum port port = intel_dig_port->port;
5eb08b69 3339 const char *name = NULL;
b2a14755 3340 int type, error;
a4fc5ed6 3341
0767935e
DV		 3342 /* Preserve the current hw state. */
3343 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 3344 intel_dp->attached_connector = intel_connector;
3d3dc149 3345
f7d24902 3346 type = DRM_MODE_CONNECTOR_DisplayPort;
19c03924
GB		 3347 /*
3348 * FIXME : We need to initialize built-in panels before external panels.
3349 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
3350 */
f7d24902
ID		 3351 switch (port) {
3352 case PORT_A:
b329530c 3353 type = DRM_MODE_CONNECTOR_eDP;
f7d24902
ID		 3354 break;
3355 case PORT_C:
3356 if (IS_VALLEYVIEW(dev))
3357 type = DRM_MODE_CONNECTOR_eDP;
3358 break;
3359 case PORT_D:
3360 if (HAS_PCH_SPLIT(dev) && intel_dpd_is_edp(dev))
3361 type = DRM_MODE_CONNECTOR_eDP;
3362 break;
3363 default: /* silence GCC warning */
3364 break;
b329530c
AJ		 3365 }
3366
f7d24902
ID		 3367 /*
3368 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
3369 * for DP the encoder type can be set by the caller to
3370 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
3371 */
3372 if (type == DRM_MODE_CONNECTOR_eDP)
3373 intel_encoder->type = INTEL_OUTPUT_EDP;
3374
e7281eab
ID		 3375 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
3376 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
3377 port_name(port));
3378
b329530c 3379 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 3380 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
3381
a4fc5ed6
KP		 3382 connector->interlace_allowed = true;
3383 connector->doublescan_allowed = 0;
3384
f0fec3f2
PZ		 3385 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3386 ironlake_panel_vdd_work);
a4fc5ed6 3387
df0e9248 3388 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 3389 drm_sysfs_connector_add(connector);
3390
affa9354 3391 if (HAS_DDI(dev))
bcbc889b
PZ		 3392 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3393 else
3394 intel_connector->get_hw_state = intel_connector_get_hw_state;
3395
9ed35ab1
PZ		 3396 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
3397 if (HAS_DDI(dev)) {
3398 switch (intel_dig_port->port) {
3399 case PORT_A:
3400 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
3401 break;
3402 case PORT_B:
3403 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
3404 break;
3405 case PORT_C:
3406 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
3407 break;
3408 case PORT_D:
3409 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
3410 break;
3411 default:
3412 BUG();
3413 }
3414 }
e8cb4558 3415
a4fc5ed6 3416 /* Set up the DDC bus. */
ab9d7c30
PZ		 3417 switch (port) {
3418 case PORT_A:
1d843f9d 3419 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 3420 name = "DPDDC-A";
3421 break;
3422 case PORT_B:
1d843f9d 3423 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 3424 name = "DPDDC-B";
3425 break;
3426 case PORT_C:
1d843f9d 3427 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 3428 name = "DPDDC-C";
3429 break;
3430 case PORT_D:
1d843f9d 3431 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 3432 name = "DPDDC-D";
3433 break;
3434 default:
ad1c0b19 3435 BUG();
5eb08b69
ZW		 3436 }
3437
b2a14755
PZ		 3438 error = intel_dp_i2c_init(intel_dp, intel_connector, name);
3439 WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
3440 error, port_name(port));
c1f05264 3441
2b28bb1b
RV		 3442 intel_dp->psr_setup_done = false;
3443
b2f246a8 3444 if (!intel_edp_init_connector(intel_dp, intel_connector)) {
15b1d171
PZ		 3445 i2c_del_adapter(&intel_dp->adapter);
3446 if (is_edp(intel_dp)) {
3447 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3448 mutex_lock(&dev->mode_config.mutex);
3449 ironlake_panel_vdd_off_sync(intel_dp);
3450 mutex_unlock(&dev->mode_config.mutex);
3451 }
b2f246a8
PZ		 3452 drm_sysfs_connector_remove(connector);
3453 drm_connector_cleanup(connector);
16c25533 3454 return false;
b2f246a8 3455 }
32f9d658 3456
f684960e
CW		 3457 intel_dp_add_properties(intel_dp, connector);
3458
a4fc5ed6
KP		 3459 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3460 * 0xd. Failure to do so will result in spurious interrupts being
3461 * generated on the port when a cable is not attached.
3462 */
3463 if (IS_G4X(dev) && !IS_GM45(dev)) {
3464 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
3465 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
3466 }
16c25533
PZ		 3467
3468 return true;
a4fc5ed6 3469}
f0fec3f2
PZ		 3470
3471void
3472intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
3473{
3474 struct intel_digital_port *intel_dig_port;
3475 struct intel_encoder *intel_encoder;
3476 struct drm_encoder *encoder;
3477 struct intel_connector *intel_connector;
3478
3479 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
3480 if (!intel_dig_port)
3481 return;
3482
3483 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
3484 if (!intel_connector) {
3485 kfree(intel_dig_port);
3486 return;
3487 }
3488
3489 intel_encoder = &intel_dig_port->base;
3490 encoder = &intel_encoder->base;
3491
3492 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
3493 DRM_MODE_ENCODER_TMDS);
00c09d70 3494 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 3495
5bfe2ac0 3496 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 3497 intel_encoder->enable = intel_enable_dp;
3498 intel_encoder->pre_enable = intel_pre_enable_dp;
3499 intel_encoder->disable = intel_disable_dp;
3500 intel_encoder->post_disable = intel_post_disable_dp;
3501 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 3502 intel_encoder->get_config = intel_dp_get_config;
89b667f8
JB		 3503 if (IS_VALLEYVIEW(dev))
3504 intel_encoder->pre_pll_enable = intel_dp_pre_pll_enable;
f0fec3f2 3505
174edf1f 3506 intel_dig_port->port = port;
f0fec3f2
PZ		 3507 intel_dig_port->dp.output_reg = output_reg;
3508
00c09d70 3509 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 3510 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3511 intel_encoder->cloneable = false;
3512 intel_encoder->hot_plug = intel_dp_hot_plug;
3513
15b1d171
PZ		 3514 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
3515 drm_encoder_cleanup(encoder);
3516 kfree(intel_dig_port);
b2f246a8 3517 kfree(intel_connector);
15b1d171 3518 }
f0fec3f2 3519}
Linux 6.x block layer and io_uring tree(s)