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drm/i915: Allow PPGTT enable to fail
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
760285e7
DH		 31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
a4fc5ed6 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
a4fc5ed6 37#include "i915_drv.h"
a4fc5ed6 38
a4fc5ed6
KP		 39#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
cfcb0fc9
JB		 41/**
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
44 *
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
47 */
48static bool is_edp(struct intel_dp *intel_dp)
49{
da63a9f2
PZ		 50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 53}
54
55/**
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
58 *
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
62 */
63static bool is_pch_edp(struct intel_dp *intel_dp)
64{
65 return intel_dp->is_pch_edp;
66}
67
1c95822a
AJ		 68/**
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
71 *
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 */
74static bool is_cpu_edp(struct intel_dp *intel_dp)
75{
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
77}
78
30add22d 79static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
ea5b213a 80{
da63a9f2
PZ		 81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82
83 return intel_dig_port->base.base.dev;
ea5b213a 84}
a4fc5ed6 85
df0e9248
CW		 86static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87{
fa90ecef 88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 89}
90
814948ad
JB		 91/**
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
94 *
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
96 * by intel_display.c.
97 */
98bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99{
100 struct intel_dp *intel_dp;
101
102 if (!encoder)
103 return false;
104
105 intel_dp = enc_to_intel_dp(encoder);
106
107 return is_pch_edp(intel_dp);
108}
109
ea5b213a 110static void intel_dp_link_down(struct intel_dp *intel_dp);
a4fc5ed6 111
a4fc5ed6 112static int
ea5b213a 113intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 114{
7183dc29 115 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
a4fc5ed6
KP		 116
117 switch (max_link_bw) {
118 case DP_LINK_BW_1_62:
119 case DP_LINK_BW_2_7:
120 break;
121 default:
122 max_link_bw = DP_LINK_BW_1_62;
123 break;
124 }
125 return max_link_bw;
126}
127
cd9dde44
AJ		 128/*
129 * The units on the numbers in the next two are... bizarre. Examples will
130 * make it clearer; this one parallels an example in the eDP spec.
131 *
132 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
133 *
134 * 270000 * 1 * 8 / 10 == 216000
135 *
136 * The actual data capacity of that configuration is 2.16Gbit/s, so the
137 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
138 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
139 * 119000. At 18bpp that's 2142000 kilobits per second.
140 *
141 * Thus the strange-looking division by 10 in intel_dp_link_required, to
142 * get the result in decakilobits instead of kilobits.
143 */
144
a4fc5ed6 145static int
c898261c 146intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 147{
cd9dde44 148 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 149}
150
fe27d53e
DA		 151static int
152intel_dp_max_data_rate(int max_link_clock, int max_lanes)
153{
154 return (max_link_clock * max_lanes * 8) / 10;
155}
156
a4fc5ed6
KP		 157static int
158intel_dp_mode_valid(struct drm_connector *connector,
159 struct drm_display_mode *mode)
160{
df0e9248 161 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 162 struct intel_connector *intel_connector = to_intel_connector(connector);
163 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 164 int target_clock = mode->clock;
165 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 166
dd06f90e
JN		 167 if (is_edp(intel_dp) && fixed_mode) {
168 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 169 return MODE_PANEL;
170
dd06f90e 171 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 172 return MODE_PANEL;
03afc4a2
DV		 173
174 target_clock = fixed_mode->clock;
7de56f43
ZY		 175 }
176
36008365
DV		 177 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
178 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
179
180 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
181 mode_rate = intel_dp_link_required(target_clock, 18);
182
183 if (mode_rate > max_rate)
c4867936 184 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 185
186 if (mode->clock < 10000)
187 return MODE_CLOCK_LOW;
188
0af78a2b
DV		 189 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
190 return MODE_H_ILLEGAL;
191
a4fc5ed6
KP		 192 return MODE_OK;
193}
194
195static uint32_t
196pack_aux(uint8_t *src, int src_bytes)
197{
198 int i;
199 uint32_t v = 0;
200
201 if (src_bytes > 4)
202 src_bytes = 4;
203 for (i = 0; i < src_bytes; i++)
204 v |= ((uint32_t) src[i]) << ((3-i) * 8);
205 return v;
206}
207
208static void
209unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
210{
211 int i;
212 if (dst_bytes > 4)
213 dst_bytes = 4;
214 for (i = 0; i < dst_bytes; i++)
215 dst[i] = src >> ((3-i) * 8);
216}
217
fb0f8fbf
KP		 218/* hrawclock is 1/4 the FSB frequency */
219static int
220intel_hrawclk(struct drm_device *dev)
221{
222 struct drm_i915_private *dev_priv = dev->dev_private;
223 uint32_t clkcfg;
224
9473c8f4
VP		 225 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
226 if (IS_VALLEYVIEW(dev))
227 return 200;
228
fb0f8fbf
KP		 229 clkcfg = I915_READ(CLKCFG);
230 switch (clkcfg & CLKCFG_FSB_MASK) {
231 case CLKCFG_FSB_400:
232 return 100;
233 case CLKCFG_FSB_533:
234 return 133;
235 case CLKCFG_FSB_667:
236 return 166;
237 case CLKCFG_FSB_800:
238 return 200;
239 case CLKCFG_FSB_1067:
240 return 266;
241 case CLKCFG_FSB_1333:
242 return 333;
243 /* these two are just a guess; one of them might be right */
244 case CLKCFG_FSB_1600:
245 case CLKCFG_FSB_1600_ALT:
246 return 400;
247 default:
248 return 133;
249 }
250}
251
ebf33b18
KP		 252static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
253{
30add22d 254 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 255 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 256 u32 pp_stat_reg;
ebf33b18 257
453c5420
JB		 258 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
259 return (I915_READ(pp_stat_reg) & PP_ON) != 0;
ebf33b18
KP		 260}
261
262static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
263{
30add22d 264 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 265 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 266 u32 pp_ctrl_reg;
ebf33b18 267
453c5420
JB		 268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
269 return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 270}
271
9b984dae
KP		 272static void
273intel_dp_check_edp(struct intel_dp *intel_dp)
274{
30add22d 275 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 276 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420 277 u32 pp_stat_reg, pp_ctrl_reg;
ebf33b18 278
9b984dae
KP		 279 if (!is_edp(intel_dp))
280 return;
453c5420
JB		 281
282 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
284
ebf33b18 285 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 286 WARN(1, "eDP powered off while attempting aux channel communication.\n");
287 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
453c5420
JB		 288 I915_READ(pp_stat_reg),
289 I915_READ(pp_ctrl_reg));
9b984dae
KP		 290 }
291}
292
9ee32fea
DV		 293static uint32_t
294intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_device *dev = intel_dig_port->base.base.dev;
298 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 299 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 300 uint32_t status;
301 bool done;
302
ef04f00d 303#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 304 if (has_aux_irq)
b90f5176
PZ		 305 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
306 msecs_to_jiffies(10));
9ee32fea
DV		 307 else
308 done = wait_for_atomic(C, 10) == 0;
309 if (!done)
310 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
311 has_aux_irq);
312#undef C
313
314 return status;
315}
316
a4fc5ed6 317static int
ea5b213a 318intel_dp_aux_ch(struct intel_dp *intel_dp,
a4fc5ed6
KP		 319 uint8_t *send, int send_bytes,
320 uint8_t *recv, int recv_size)
321{
174edf1f
PZ		 322 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
323 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 324 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 325 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
a4fc5ed6 326 uint32_t ch_data = ch_ctl + 4;
9ee32fea 327 int i, ret, recv_bytes;
a4fc5ed6 328 uint32_t status;
fb0f8fbf 329 uint32_t aux_clock_divider;
6b4e0a93 330 int try, precharge;
9ee32fea
DV		 331 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
332
333 /* dp aux is extremely sensitive to irq latency, hence request the
334 * lowest possible wakeup latency and so prevent the cpu from going into
335 * deep sleep states.
336 */
337 pm_qos_update_request(&dev_priv->pm_qos, 0);
a4fc5ed6 338
9b984dae 339 intel_dp_check_edp(intel_dp);
a4fc5ed6 340 /* The clock divider is based off the hrawclk,
fb0f8fbf
KP		 341 * and would like to run at 2MHz. So, take the
342 * hrawclk value and divide by 2 and use that
6176b8f9
JB		 343 *
344 * Note that PCH attached eDP panels should use a 125MHz input
345 * clock divider.
a4fc5ed6 346 */
1c95822a 347 if (is_cpu_edp(intel_dp)) {
affa9354 348 if (HAS_DDI(dev))
b8fc2f6a
PZ		 349 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
350 else if (IS_VALLEYVIEW(dev))
9473c8f4
VP		 351 aux_clock_divider = 100;
352 else if (IS_GEN6(dev) || IS_GEN7(dev))
1a2eb460 353 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18
ZW		 354 else
355 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
356 } else if (HAS_PCH_SPLIT(dev))
6b3ec1c9 357 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
5eb08b69
ZW		 358 else
359 aux_clock_divider = intel_hrawclk(dev) / 2;
360
6b4e0a93
DV		 361 if (IS_GEN6(dev))
362 precharge = 3;
363 else
364 precharge = 5;
365
11bee43e
JB		 366 /* Try to wait for any previous AUX channel activity */
367 for (try = 0; try < 3; try++) {
ef04f00d 368 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 369 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
370 break;
371 msleep(1);
372 }
373
374 if (try == 3) {
375 WARN(1, "dp_aux_ch not started status 0x%08x\n",
376 I915_READ(ch_ctl));
9ee32fea
DV		 377 ret = -EBUSY;
378 goto out;
4f7f7b7e
CW		 379 }
380
fb0f8fbf
KP		 381 /* Must try at least 3 times according to DP spec */
382 for (try = 0; try < 5; try++) {
383 /* Load the send data into the aux channel data registers */
4f7f7b7e
CW		 384 for (i = 0; i < send_bytes; i += 4)
385 I915_WRITE(ch_data + i,
386 pack_aux(send + i, send_bytes - i));
0206e353 387
fb0f8fbf 388 /* Send the command and wait for it to complete */
4f7f7b7e
CW		 389 I915_WRITE(ch_ctl,
390 DP_AUX_CH_CTL_SEND_BUSY |
9ee32fea 391 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
4f7f7b7e
CW		 392 DP_AUX_CH_CTL_TIME_OUT_400us |
393 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
394 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
395 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
396 DP_AUX_CH_CTL_DONE |
397 DP_AUX_CH_CTL_TIME_OUT_ERROR |
398 DP_AUX_CH_CTL_RECEIVE_ERROR);
9ee32fea
DV		 399
400 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
0206e353 401
fb0f8fbf 402 /* Clear done status and any errors */
4f7f7b7e
CW		 403 I915_WRITE(ch_ctl,
404 status |
405 DP_AUX_CH_CTL_DONE |
406 DP_AUX_CH_CTL_TIME_OUT_ERROR |
407 DP_AUX_CH_CTL_RECEIVE_ERROR);
d7e96fea
AJ		 408
409 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
410 DP_AUX_CH_CTL_RECEIVE_ERROR))
411 continue;
4f7f7b7e 412 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 413 break;
414 }
415
a4fc5ed6 416 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 417 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 418 ret = -EBUSY;
419 goto out;
a4fc5ed6
KP		 420 }
421
422 /* Check for timeout or receive error.
423 * Timeouts occur when the sink is not connected
424 */
a5b3da54 425 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 426 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 427 ret = -EIO;
428 goto out;
a5b3da54 429 }
1ae8c0a5
KP		 430
431 /* Timeouts occur when the device isn't connected, so they're
432 * "normal" -- don't fill the kernel log with these */
a5b3da54 433 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 434 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 435 ret = -ETIMEDOUT;
436 goto out;
a4fc5ed6
KP		 437 }
438
439 /* Unload any bytes sent back from the other side */
440 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
441 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 442 if (recv_bytes > recv_size)
443 recv_bytes = recv_size;
0206e353 444
4f7f7b7e
CW		 445 for (i = 0; i < recv_bytes; i += 4)
446 unpack_aux(I915_READ(ch_data + i),
447 recv + i, recv_bytes - i);
a4fc5ed6 448
9ee32fea
DV		 449 ret = recv_bytes;
450out:
451 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
452
453 return ret;
a4fc5ed6
KP		 454}
455
456/* Write data to the aux channel in native mode */
457static int
ea5b213a 458intel_dp_aux_native_write(struct intel_dp *intel_dp,
a4fc5ed6
KP		 459 uint16_t address, uint8_t *send, int send_bytes)
460{
461 int ret;
462 uint8_t msg[20];
463 int msg_bytes;
464 uint8_t ack;
465
9b984dae 466 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 467 if (send_bytes > 16)
468 return -1;
469 msg[0] = AUX_NATIVE_WRITE << 4;
470 msg[1] = address >> 8;
eebc863e 471 msg[2] = address & 0xff;
a4fc5ed6
KP		 472 msg[3] = send_bytes - 1;
473 memcpy(&msg[4], send, send_bytes);
474 msg_bytes = send_bytes + 4;
475 for (;;) {
ea5b213a 476 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
a4fc5ed6
KP		 477 if (ret < 0)
478 return ret;
479 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
480 break;
481 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
482 udelay(100);
483 else
a5b3da54 484 return -EIO;
a4fc5ed6
KP		 485 }
486 return send_bytes;
487}
488
489/* Write a single byte to the aux channel in native mode */
490static int
ea5b213a 491intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
a4fc5ed6
KP		 492 uint16_t address, uint8_t byte)
493{
ea5b213a 494 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
a4fc5ed6
KP		 495}
496
497/* read bytes from a native aux channel */
498static int
ea5b213a 499intel_dp_aux_native_read(struct intel_dp *intel_dp,
a4fc5ed6
KP		 500 uint16_t address, uint8_t *recv, int recv_bytes)
501{
502 uint8_t msg[4];
503 int msg_bytes;
504 uint8_t reply[20];
505 int reply_bytes;
506 uint8_t ack;
507 int ret;
508
9b984dae 509 intel_dp_check_edp(intel_dp);
a4fc5ed6
KP		 510 msg[0] = AUX_NATIVE_READ << 4;
511 msg[1] = address >> 8;
512 msg[2] = address & 0xff;
513 msg[3] = recv_bytes - 1;
514
515 msg_bytes = 4;
516 reply_bytes = recv_bytes + 1;
517
518 for (;;) {
ea5b213a 519 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
a4fc5ed6 520 reply, reply_bytes);
a5b3da54
KP		 521 if (ret == 0)
522 return -EPROTO;
523 if (ret < 0)
a4fc5ed6
KP		 524 return ret;
525 ack = reply[0];
526 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
527 memcpy(recv, reply + 1, ret - 1);
528 return ret - 1;
529 }
530 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
531 udelay(100);
532 else
a5b3da54 533 return -EIO;
a4fc5ed6
KP		 534 }
535}
536
537static int
ab2c0672
DA		 538intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
539 uint8_t write_byte, uint8_t *read_byte)
a4fc5ed6 540{
ab2c0672 541 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
ea5b213a
CW		 542 struct intel_dp *intel_dp = container_of(adapter,
543 struct intel_dp,
544 adapter);
ab2c0672
DA		 545 uint16_t address = algo_data->address;
546 uint8_t msg[5];
547 uint8_t reply[2];
8316f337 548 unsigned retry;
ab2c0672
DA		 549 int msg_bytes;
550 int reply_bytes;
551 int ret;
552
9b984dae 553 intel_dp_check_edp(intel_dp);
ab2c0672
DA		 554 /* Set up the command byte */
555 if (mode & MODE_I2C_READ)
556 msg[0] = AUX_I2C_READ << 4;
557 else
558 msg[0] = AUX_I2C_WRITE << 4;
559
560 if (!(mode & MODE_I2C_STOP))
561 msg[0] |= AUX_I2C_MOT << 4;
a4fc5ed6 562
ab2c0672
DA		 563 msg[1] = address >> 8;
564 msg[2] = address;
565
566 switch (mode) {
567 case MODE_I2C_WRITE:
568 msg[3] = 0;
569 msg[4] = write_byte;
570 msg_bytes = 5;
571 reply_bytes = 1;
572 break;
573 case MODE_I2C_READ:
574 msg[3] = 0;
575 msg_bytes = 4;
576 reply_bytes = 2;
577 break;
578 default:
579 msg_bytes = 3;
580 reply_bytes = 1;
581 break;
582 }
583
8316f337
DF		 584 for (retry = 0; retry < 5; retry++) {
585 ret = intel_dp_aux_ch(intel_dp,
586 msg, msg_bytes,
587 reply, reply_bytes);
ab2c0672 588 if (ret < 0) {
3ff99164 589 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
ab2c0672
DA		 590 return ret;
591 }
8316f337
DF		 592
593 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
594 case AUX_NATIVE_REPLY_ACK:
595 /* I2C-over-AUX Reply field is only valid
596 * when paired with AUX ACK.
597 */
598 break;
599 case AUX_NATIVE_REPLY_NACK:
600 DRM_DEBUG_KMS("aux_ch native nack\n");
601 return -EREMOTEIO;
602 case AUX_NATIVE_REPLY_DEFER:
603 udelay(100);
604 continue;
605 default:
606 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
607 reply[0]);
608 return -EREMOTEIO;
609 }
610
ab2c0672
DA		 611 switch (reply[0] & AUX_I2C_REPLY_MASK) {
612 case AUX_I2C_REPLY_ACK:
613 if (mode == MODE_I2C_READ) {
614 *read_byte = reply[1];
615 }
616 return reply_bytes - 1;
617 case AUX_I2C_REPLY_NACK:
8316f337 618 DRM_DEBUG_KMS("aux_i2c nack\n");
ab2c0672
DA		 619 return -EREMOTEIO;
620 case AUX_I2C_REPLY_DEFER:
8316f337 621 DRM_DEBUG_KMS("aux_i2c defer\n");
ab2c0672
DA		 622 udelay(100);
623 break;
624 default:
8316f337 625 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
ab2c0672
DA		 626 return -EREMOTEIO;
627 }
628 }
8316f337
DF		 629
630 DRM_ERROR("too many retries, giving up\n");
631 return -EREMOTEIO;
a4fc5ed6
KP		 632}
633
634static int
ea5b213a 635intel_dp_i2c_init(struct intel_dp *intel_dp,
55f78c43 636 struct intel_connector *intel_connector, const char *name)
a4fc5ed6 637{
0b5c541b
KP		 638 int ret;
639
d54e9d28 640 DRM_DEBUG_KMS("i2c_init %s\n", name);
ea5b213a
CW		 641 intel_dp->algo.running = false;
642 intel_dp->algo.address = 0;
643 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
644
0206e353 645 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
ea5b213a
CW		 646 intel_dp->adapter.owner = THIS_MODULE;
647 intel_dp->adapter.class = I2C_CLASS_DDC;
0206e353 648 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
ea5b213a
CW		 649 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
650 intel_dp->adapter.algo_data = &intel_dp->algo;
651 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
652
0b5c541b
KP		 653 ironlake_edp_panel_vdd_on(intel_dp);
654 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
bd943159 655 ironlake_edp_panel_vdd_off(intel_dp, false);
0b5c541b 656 return ret;
a4fc5ed6
KP		 657}
658
00c09d70 659bool
5bfe2ac0
DV		 660intel_dp_compute_config(struct intel_encoder *encoder,
661 struct intel_crtc_config *pipe_config)
a4fc5ed6 662{
5bfe2ac0 663 struct drm_device *dev = encoder->base.dev;
36008365 664 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0
DV		 665 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
666 struct drm_display_mode *mode = &pipe_config->requested_mode;
667 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
dd06f90e 668 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 669 int lane_count, clock;
397fe157 670 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
ea5b213a 671 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
083f9560 672 int bpp, mode_rate;
a4fc5ed6 673 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
36008365 674 int target_clock, link_avail, link_clock;
a4fc5ed6 675
5bfe2ac0
DV		 676 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
677 pipe_config->has_pch_encoder = true;
678
03afc4a2
DV		 679 pipe_config->has_dp_encoder = true;
680
dd06f90e
JN		 681 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
682 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
683 adjusted_mode);
53b41837
YN		 684 intel_pch_panel_fitting(dev,
685 intel_connector->panel.fitting_mode,
1d8e1c75 686 mode, adjusted_mode);
0d3a1bee 687 }
36008365
DV		 688 /* We need to take the panel's fixed mode into account. */
689 target_clock = adjusted_mode->clock;
0d3a1bee 690
cb1793ce 691 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 692 return false;
693
083f9560
DV		 694 DRM_DEBUG_KMS("DP link computation with max lane count %i "
695 "max bw %02x pixel clock %iKHz\n",
71244653 696 max_lane_count, bws[max_clock], adjusted_mode->clock);
083f9560 697
36008365
DV		 698 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
699 * bpc in between. */
03afc4a2 700 bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
36008365
DV		 701 for (; bpp >= 6*3; bpp -= 2*3) {
702 mode_rate = intel_dp_link_required(target_clock, bpp);
703
704 for (clock = 0; clock <= max_clock; clock++) {
705 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
706 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
707 link_avail = intel_dp_max_data_rate(link_clock,
708 lane_count);
709
710 if (mode_rate <= link_avail) {
711 goto found;
712 }
713 }
714 }
715 }
c4867936 716
36008365 717 return false;
3685a8f3 718
36008365 719found:
55bc60db
VS		 720 if (intel_dp->color_range_auto) {
721 /*
722 * See:
723 * CEA-861-E - 5.1 Default Encoding Parameters
724 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
725 */
18316c8c 726 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 727 intel_dp->color_range = DP_COLOR_RANGE_16_235;
728 else
729 intel_dp->color_range = 0;
730 }
731
3685a8f3 732 if (intel_dp->color_range)
50f3b016 733 pipe_config->limited_color_range = true;
3685a8f3 734
36008365
DV		 735 intel_dp->link_bw = bws[clock];
736 intel_dp->lane_count = lane_count;
737 adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
df92b1e6 738 pipe_config->pixel_target_clock = target_clock;
fe27d53e 739
36008365
DV		 740 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
741 intel_dp->link_bw, intel_dp->lane_count,
742 adjusted_mode->clock, bpp);
743 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
744 mode_rate, link_avail);
745
03afc4a2
DV		 746 intel_link_compute_m_n(bpp, lane_count,
747 target_clock, adjusted_mode->clock,
748 &pipe_config->dp_m_n);
a4fc5ed6 749
57c21963
DV		 750 /*
751 * XXX: We have a strange regression where using the vbt edp bpp value
752 * for the link bw computation results in black screens, the panel only
753 * works when we do the computation at the usual 24bpp (but still
754 * requires us to use 18bpp). Until that's fully debugged, stay
755 * bug-for-bug compatible with the old code.
756 */
757 if (is_edp(intel_dp) && dev_priv->edp.bpp) {
758 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
759 bpp, dev_priv->edp.bpp);
760 bpp = min_t(int, bpp, dev_priv->edp.bpp);
761 }
762 pipe_config->pipe_bpp = bpp;
763
03afc4a2 764 return true;
a4fc5ed6
KP		 765}
766
247d89f6
PZ		 767void intel_dp_init_link_config(struct intel_dp *intel_dp)
768{
769 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
770 intel_dp->link_configuration[0] = intel_dp->link_bw;
771 intel_dp->link_configuration[1] = intel_dp->lane_count;
772 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
773 /*
774 * Check for DPCD version > 1.1 and enhanced framing support
775 */
776 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
777 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
778 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
779 }
780}
781
ea9b6006
DV		 782static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
783{
784 struct drm_device *dev = crtc->dev;
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 u32 dpa_ctl;
787
788 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
789 dpa_ctl = I915_READ(DP_A);
790 dpa_ctl &= ~DP_PLL_FREQ_MASK;
791
792 if (clock < 200000) {
1ce17038
DV		 793 /* For a long time we've carried around a ILK-DevA w/a for the
794 * 160MHz clock. If we're really unlucky, it's still required.
795 */
796 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 797 dpa_ctl |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 798 } else {
799 dpa_ctl |= DP_PLL_FREQ_270MHZ;
800 }
1ce17038 801
ea9b6006
DV		 802 I915_WRITE(DP_A, dpa_ctl);
803
804 POSTING_READ(DP_A);
805 udelay(500);
806}
807
a4fc5ed6
KP		 808static void
809intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
810 struct drm_display_mode *adjusted_mode)
811{
e3421a18 812 struct drm_device *dev = encoder->dev;
417e822d 813 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 814 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
fa90ecef 815 struct drm_crtc *crtc = encoder->crtc;
a4fc5ed6
KP		 816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
817
417e822d 818 /*
1a2eb460 819 * There are four kinds of DP registers:
417e822d
KP		 820 *
821 * IBX PCH
1a2eb460
KP		 822 * SNB CPU
823 * IVB CPU
417e822d
KP		 824 * CPT PCH
825 *
826 * IBX PCH and CPU are the same for almost everything,
827 * except that the CPU DP PLL is configured in this
828 * register
829 *
830 * CPT PCH is quite different, having many bits moved
831 * to the TRANS_DP_CTL register instead. That
832 * configuration happens (oddly) in ironlake_pch_enable
833 */
9c9e7927 834
417e822d
KP		 835 /* Preserve the BIOS-computed detected bit. This is
836 * supposed to be read-only.
837 */
838 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 839
417e822d 840 /* Handle DP bits in common between all three register formats */
417e822d 841 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
a4fc5ed6 842
ea5b213a 843 switch (intel_dp->lane_count) {
a4fc5ed6 844 case 1:
ea5b213a 845 intel_dp->DP |= DP_PORT_WIDTH_1;
a4fc5ed6
KP		 846 break;
847 case 2:
ea5b213a 848 intel_dp->DP |= DP_PORT_WIDTH_2;
a4fc5ed6
KP		 849 break;
850 case 4:
ea5b213a 851 intel_dp->DP |= DP_PORT_WIDTH_4;
a4fc5ed6
KP		 852 break;
853 }
e0dac65e
WF		 854 if (intel_dp->has_audio) {
855 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
856 pipe_name(intel_crtc->pipe));
ea5b213a 857 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
e0dac65e
WF		 858 intel_write_eld(encoder, adjusted_mode);
859 }
247d89f6
PZ		 860
861 intel_dp_init_link_config(intel_dp);
a4fc5ed6 862
417e822d 863 /* Split out the IBX/CPU vs CPT settings */
32f9d658 864
19c03924 865 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 866 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
867 intel_dp->DP |= DP_SYNC_HS_HIGH;
868 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
869 intel_dp->DP |= DP_SYNC_VS_HIGH;
870 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
871
872 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
873 intel_dp->DP |= DP_ENHANCED_FRAMING;
874
875 intel_dp->DP |= intel_crtc->pipe << 29;
876
877 /* don't miss out required setting for eDP */
1a2eb460
KP		 878 if (adjusted_mode->clock < 200000)
879 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
880 else
881 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
882 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
b2634017 883 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 884 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 885
886 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
887 intel_dp->DP |= DP_SYNC_HS_HIGH;
888 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
889 intel_dp->DP |= DP_SYNC_VS_HIGH;
890 intel_dp->DP |= DP_LINK_TRAIN_OFF;
891
892 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
893 intel_dp->DP |= DP_ENHANCED_FRAMING;
894
895 if (intel_crtc->pipe == 1)
896 intel_dp->DP |= DP_PIPEB_SELECT;
897
b2634017 898 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
417e822d 899 /* don't miss out required setting for eDP */
417e822d
KP		 900 if (adjusted_mode->clock < 200000)
901 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
902 else
903 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
904 }
905 } else {
906 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 907 }
ea9b6006 908
5d66d5b6 909 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
ea9b6006 910 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
a4fc5ed6
KP		 911}
912
99ea7127
KP		 913#define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
914#define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
915
916#define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
917#define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
918
919#define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
920#define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
921
922static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
923 u32 mask,
924 u32 value)
bd943159 925{
30add22d 926 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 927 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 928 u32 pp_stat_reg, pp_ctrl_reg;
929
930 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
931 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
32ce697c 932
99ea7127 933 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 934 mask, value,
935 I915_READ(pp_stat_reg),
936 I915_READ(pp_ctrl_reg));
32ce697c 937
453c5420 938 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 939 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 940 I915_READ(pp_stat_reg),
941 I915_READ(pp_ctrl_reg));
32ce697c 942 }
99ea7127 943}
32ce697c 944
99ea7127
KP		 945static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
946{
947 DRM_DEBUG_KMS("Wait for panel power on\n");
948 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 949}
950
99ea7127
KP		 951static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
952{
953 DRM_DEBUG_KMS("Wait for panel power off time\n");
954 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
955}
956
957static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
958{
959 DRM_DEBUG_KMS("Wait for panel power cycle\n");
960 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
961}
962
963
832dd3c1
KP		 964/* Read the current pp_control value, unlocking the register if it
965 * is locked
966 */
967
453c5420 968static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 969{
453c5420
JB		 970 struct drm_device *dev = intel_dp_to_dev(intel_dp);
971 struct drm_i915_private *dev_priv = dev->dev_private;
972 u32 control;
973 u32 pp_ctrl_reg;
974
975 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
976 control = I915_READ(pp_ctrl_reg);
832dd3c1
KP		 977
978 control &= ~PANEL_UNLOCK_MASK;
979 control |= PANEL_UNLOCK_REGS;
980 return control;
bd943159
KP		 981}
982
82a4d9c0 983void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 984{
30add22d 985 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 986 struct drm_i915_private *dev_priv = dev->dev_private;
987 u32 pp;
453c5420 988 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 989
97af61f5
KP		 990 if (!is_edp(intel_dp))
991 return;
f01eca2e 992 DRM_DEBUG_KMS("Turn eDP VDD on\n");
5d613501 993
bd943159
KP		 994 WARN(intel_dp->want_panel_vdd,
995 "eDP VDD already requested on\n");
996
997 intel_dp->want_panel_vdd = true;
99ea7127 998
bd943159
KP		 999 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1000 DRM_DEBUG_KMS("eDP VDD already on\n");
1001 return;
1002 }
1003
99ea7127
KP		 1004 if (!ironlake_edp_have_panel_power(intel_dp))
1005 ironlake_wait_panel_power_cycle(intel_dp);
1006
453c5420 1007 pp = ironlake_get_pp_control(intel_dp);
5d613501 1008 pp |= EDP_FORCE_VDD;
ebf33b18 1009
453c5420
JB		 1010 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1011 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1012
1013 I915_WRITE(pp_ctrl_reg, pp);
1014 POSTING_READ(pp_ctrl_reg);
1015 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1016 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1017 /*
1018 * If the panel wasn't on, delay before accessing aux channel
1019 */
1020 if (!ironlake_edp_have_panel_power(intel_dp)) {
bd943159 1021 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1022 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1023 }
5d613501
JB		 1024}
1025
bd943159 1026static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1027{
30add22d 1028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1029 struct drm_i915_private *dev_priv = dev->dev_private;
1030 u32 pp;
453c5420 1031 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1032
a0e99e68
DV		 1033 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1034
bd943159 1035 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
453c5420 1036 pp = ironlake_get_pp_control(intel_dp);
bd943159 1037 pp &= ~EDP_FORCE_VDD;
bd943159 1038
453c5420
JB		 1039 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
1040 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1041
1042 I915_WRITE(pp_ctrl_reg, pp);
1043 POSTING_READ(pp_ctrl_reg);
99ea7127 1044
453c5420
JB		 1045 /* Make sure sequencer is idle before allowing subsequent activity */
1046 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1047 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
99ea7127 1048 msleep(intel_dp->panel_power_down_delay);
bd943159
KP		 1049 }
1050}
5d613501 1051
bd943159
KP		 1052static void ironlake_panel_vdd_work(struct work_struct *__work)
1053{
1054 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1055 struct intel_dp, panel_vdd_work);
30add22d 1056 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1057
627f7675 1058 mutex_lock(&dev->mode_config.mutex);
bd943159 1059 ironlake_panel_vdd_off_sync(intel_dp);
627f7675 1060 mutex_unlock(&dev->mode_config.mutex);
bd943159
KP		 1061}
1062
82a4d9c0 1063void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1064{
97af61f5
KP		 1065 if (!is_edp(intel_dp))
1066 return;
5d613501 1067
bd943159
KP		 1068 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1069 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1070
bd943159
KP		 1071 intel_dp->want_panel_vdd = false;
1072
1073 if (sync) {
1074 ironlake_panel_vdd_off_sync(intel_dp);
1075 } else {
1076 /*
1077 * Queue the timer to fire a long
1078 * time from now (relative to the power down delay)
1079 * to keep the panel power up across a sequence of operations
1080 */
1081 schedule_delayed_work(&intel_dp->panel_vdd_work,
1082 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1083 }
5d613501
JB		 1084}
1085
82a4d9c0 1086void ironlake_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1087{
30add22d 1088 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1089 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1090 u32 pp;
453c5420 1091 u32 pp_ctrl_reg;
9934c132 1092
97af61f5 1093 if (!is_edp(intel_dp))
bd943159 1094 return;
99ea7127
KP		 1095
1096 DRM_DEBUG_KMS("Turn eDP power on\n");
1097
1098 if (ironlake_edp_have_panel_power(intel_dp)) {
1099 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1100 return;
99ea7127 1101 }
9934c132 1102
99ea7127 1103 ironlake_wait_panel_power_cycle(intel_dp);
37c6c9b0 1104
453c5420 1105 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1106 if (IS_GEN5(dev)) {
1107 /* ILK workaround: disable reset around power sequence */
1108 pp &= ~PANEL_POWER_RESET;
1109 I915_WRITE(PCH_PP_CONTROL, pp);
1110 POSTING_READ(PCH_PP_CONTROL);
1111 }
37c6c9b0 1112
1c0ae80a 1113 pp |= POWER_TARGET_ON;
99ea7127
KP		 1114 if (!IS_GEN5(dev))
1115 pp |= PANEL_POWER_RESET;
1116
453c5420
JB		 1117 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1118
1119 I915_WRITE(pp_ctrl_reg, pp);
1120 POSTING_READ(pp_ctrl_reg);
9934c132 1121
99ea7127 1122 ironlake_wait_panel_on(intel_dp);
9934c132 1123
05ce1a49
KP		 1124 if (IS_GEN5(dev)) {
1125 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1126 I915_WRITE(PCH_PP_CONTROL, pp);
1127 POSTING_READ(PCH_PP_CONTROL);
1128 }
9934c132
JB		 1129}
1130
82a4d9c0 1131void ironlake_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1132{
30add22d 1133 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1134 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1135 u32 pp;
453c5420 1136 u32 pp_ctrl_reg;
9934c132 1137
97af61f5
KP		 1138 if (!is_edp(intel_dp))
1139 return;
37c6c9b0 1140
99ea7127 1141 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1142
6cb49835 1143 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
37c6c9b0 1144
453c5420 1145 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1146 /* We need to switch off panel power _and_ force vdd, for otherwise some
1147 * panels get very unhappy and cease to work. */
1148 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
453c5420
JB		 1149
1150 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1151
1152 I915_WRITE(pp_ctrl_reg, pp);
1153 POSTING_READ(pp_ctrl_reg);
9934c132 1154
35a38556
DV		 1155 intel_dp->want_panel_vdd = false;
1156
99ea7127 1157 ironlake_wait_panel_off(intel_dp);
9934c132
JB		 1158}
1159
d6c50ff8 1160void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1161{
da63a9f2
PZ		 1162 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1163 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658 1164 struct drm_i915_private *dev_priv = dev->dev_private;
da63a9f2 1165 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
32f9d658 1166 u32 pp;
453c5420 1167 u32 pp_ctrl_reg;
32f9d658 1168
f01eca2e
KP		 1169 if (!is_edp(intel_dp))
1170 return;
1171
28c97730 1172 DRM_DEBUG_KMS("\n");
01cb9ea6
JB		 1173 /*
1174 * If we enable the backlight right away following a panel power
1175 * on, we may see slight flicker as the panel syncs with the eDP
1176 * link. So delay a bit to make sure the image is solid before
1177 * allowing it to appear.
1178 */
f01eca2e 1179 msleep(intel_dp->backlight_on_delay);
453c5420 1180 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1181 pp |= EDP_BLC_ENABLE;
453c5420
JB		 1182
1183 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1184
1185 I915_WRITE(pp_ctrl_reg, pp);
1186 POSTING_READ(pp_ctrl_reg);
035aa3de
DV		 1187
1188 intel_panel_enable_backlight(dev, pipe);
32f9d658
ZW		 1189}
1190
d6c50ff8 1191void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1192{
30add22d 1193 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1194 struct drm_i915_private *dev_priv = dev->dev_private;
1195 u32 pp;
453c5420 1196 u32 pp_ctrl_reg;
32f9d658 1197
f01eca2e
KP		 1198 if (!is_edp(intel_dp))
1199 return;
1200
035aa3de
DV		 1201 intel_panel_disable_backlight(dev);
1202
28c97730 1203 DRM_DEBUG_KMS("\n");
453c5420 1204 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1205 pp &= ~EDP_BLC_ENABLE;
453c5420
JB		 1206
1207 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
1208
1209 I915_WRITE(pp_ctrl_reg, pp);
1210 POSTING_READ(pp_ctrl_reg);
f01eca2e 1211 msleep(intel_dp->backlight_off_delay);
32f9d658 1212}
a4fc5ed6 1213
2bd2ad64 1214static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1215{
da63a9f2
PZ		 1216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1217 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1218 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1219 struct drm_i915_private *dev_priv = dev->dev_private;
1220 u32 dpa_ctl;
1221
2bd2ad64
DV		 1222 assert_pipe_disabled(dev_priv,
1223 to_intel_crtc(crtc)->pipe);
1224
d240f20f
JB		 1225 DRM_DEBUG_KMS("\n");
1226 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1227 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1228 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1229
1230 /* We don't adjust intel_dp->DP while tearing down the link, to
1231 * facilitate link retraining (e.g. after hotplug). Hence clear all
1232 * enable bits here to ensure that we don't enable too much. */
1233 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1234 intel_dp->DP |= DP_PLL_ENABLE;
1235 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1236 POSTING_READ(DP_A);
1237 udelay(200);
d240f20f
JB		 1238}
1239
2bd2ad64 1240static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1241{
da63a9f2
PZ		 1242 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1243 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1244 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1245 struct drm_i915_private *dev_priv = dev->dev_private;
1246 u32 dpa_ctl;
1247
2bd2ad64
DV		 1248 assert_pipe_disabled(dev_priv,
1249 to_intel_crtc(crtc)->pipe);
1250
d240f20f 1251 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1252 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1253 "dp pll off, should be on\n");
1254 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1255
1256 /* We can't rely on the value tracked for the DP register in
1257 * intel_dp->DP because link_down must not change that (otherwise link
1258 * re-training will fail. */
298b0b39 1259 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1260 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1261 POSTING_READ(DP_A);
d240f20f
JB		 1262 udelay(200);
1263}
1264
c7ad3810 1265/* If the sink supports it, try to set the power state appropriately */
c19b0669 1266void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1267{
1268 int ret, i;
1269
1270 /* Should have a valid DPCD by this point */
1271 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1272 return;
1273
1274 if (mode != DRM_MODE_DPMS_ON) {
1275 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1276 DP_SET_POWER_D3);
1277 if (ret != 1)
1278 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1279 } else {
1280 /*
1281 * When turning on, we need to retry for 1ms to give the sink
1282 * time to wake up.
1283 */
1284 for (i = 0; i < 3; i++) {
1285 ret = intel_dp_aux_native_write_1(intel_dp,
1286 DP_SET_POWER,
1287 DP_SET_POWER_D0);
1288 if (ret == 1)
1289 break;
1290 msleep(1);
1291 }
1292 }
1293}
1294
19d8fe15
DV		 1295static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1296 enum pipe *pipe)
d240f20f 1297{
19d8fe15
DV		 1298 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1299 struct drm_device *dev = encoder->base.dev;
1300 struct drm_i915_private *dev_priv = dev->dev_private;
1301 u32 tmp = I915_READ(intel_dp->output_reg);
1302
1303 if (!(tmp & DP_PORT_EN))
1304 return false;
1305
5d66d5b6 1306 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15
DV		 1307 *pipe = PORT_TO_PIPE_CPT(tmp);
1308 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1309 *pipe = PORT_TO_PIPE(tmp);
1310 } else {
1311 u32 trans_sel;
1312 u32 trans_dp;
1313 int i;
1314
1315 switch (intel_dp->output_reg) {
1316 case PCH_DP_B:
1317 trans_sel = TRANS_DP_PORT_SEL_B;
1318 break;
1319 case PCH_DP_C:
1320 trans_sel = TRANS_DP_PORT_SEL_C;
1321 break;
1322 case PCH_DP_D:
1323 trans_sel = TRANS_DP_PORT_SEL_D;
1324 break;
1325 default:
1326 return true;
1327 }
1328
1329 for_each_pipe(i) {
1330 trans_dp = I915_READ(TRANS_DP_CTL(i));
1331 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1332 *pipe = i;
1333 return true;
1334 }
1335 }
19d8fe15 1336
4a0833ec
DV		 1337 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1338 intel_dp->output_reg);
1339 }
d240f20f 1340
2af8898b 1341 return true;
19d8fe15 1342}
d240f20f 1343
e8cb4558 1344static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 1345{
e8cb4558 1346 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
6cb49835
DV		 1347
1348 /* Make sure the panel is off before trying to change the mode. But also
1349 * ensure that we have vdd while we switch off the panel. */
1350 ironlake_edp_panel_vdd_on(intel_dp);
21264c63 1351 ironlake_edp_backlight_off(intel_dp);
c7ad3810 1352 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
35a38556 1353 ironlake_edp_panel_off(intel_dp);
3739850b
DV		 1354
1355 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1356 if (!is_cpu_edp(intel_dp))
1357 intel_dp_link_down(intel_dp);
d240f20f
JB		 1358}
1359
2bd2ad64 1360static void intel_post_disable_dp(struct intel_encoder *encoder)
d240f20f 1361{
2bd2ad64 1362 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1363 struct drm_device *dev = encoder->base.dev;
2bd2ad64 1364
3739850b
DV		 1365 if (is_cpu_edp(intel_dp)) {
1366 intel_dp_link_down(intel_dp);
b2634017
JB		 1367 if (!IS_VALLEYVIEW(dev))
1368 ironlake_edp_pll_off(intel_dp);
3739850b 1369 }
2bd2ad64
DV		 1370}
1371
e8cb4558 1372static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 1373{
e8cb4558
DV		 1374 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1375 struct drm_device *dev = encoder->base.dev;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 1378
0c33d8d7
DV		 1379 if (WARN_ON(dp_reg & DP_PORT_EN))
1380 return;
5d613501 1381
97af61f5 1382 ironlake_edp_panel_vdd_on(intel_dp);
f01eca2e 1383 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 1384 intel_dp_start_link_train(intel_dp);
97af61f5 1385 ironlake_edp_panel_on(intel_dp);
bd943159 1386 ironlake_edp_panel_vdd_off(intel_dp, true);
33a34e4e 1387 intel_dp_complete_link_train(intel_dp);
f01eca2e 1388 ironlake_edp_backlight_on(intel_dp);
d240f20f
JB		 1389}
1390
2bd2ad64 1391static void intel_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 1392{
2bd2ad64 1393 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
b2634017 1394 struct drm_device *dev = encoder->base.dev;
a4fc5ed6 1395
b2634017 1396 if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
2bd2ad64 1397 ironlake_edp_pll_on(intel_dp);
a4fc5ed6
KP		 1398}
1399
1400/*
df0c237d
JB		 1401 * Native read with retry for link status and receiver capability reads for
1402 * cases where the sink may still be asleep.
a4fc5ed6
KP		 1403 */
1404static bool
df0c237d
JB		 1405intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1406 uint8_t *recv, int recv_bytes)
a4fc5ed6 1407{
61da5fab
JB		 1408 int ret, i;
1409
df0c237d
JB		 1410 /*
1411 * Sinks are *supposed* to come up within 1ms from an off state,
1412 * but we're also supposed to retry 3 times per the spec.
1413 */
61da5fab 1414 for (i = 0; i < 3; i++) {
df0c237d
JB		 1415 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1416 recv_bytes);
1417 if (ret == recv_bytes)
61da5fab
JB		 1418 return true;
1419 msleep(1);
1420 }
a4fc5ed6 1421
61da5fab 1422 return false;
a4fc5ed6
KP		 1423}
1424
1425/*
1426 * Fetch AUX CH registers 0x202 - 0x207 which contain
1427 * link status information
1428 */
1429static bool
93f62dad 1430intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 1431{
df0c237d
JB		 1432 return intel_dp_aux_native_read_retry(intel_dp,
1433 DP_LANE0_1_STATUS,
93f62dad 1434 link_status,
df0c237d 1435 DP_LINK_STATUS_SIZE);
a4fc5ed6
KP		 1436}
1437
a4fc5ed6
KP		 1438#if 0
1439static char *voltage_names[] = {
1440 "0.4V", "0.6V", "0.8V", "1.2V"
1441};
1442static char *pre_emph_names[] = {
1443 "0dB", "3.5dB", "6dB", "9.5dB"
1444};
1445static char *link_train_names[] = {
1446 "pattern 1", "pattern 2", "idle", "off"
1447};
1448#endif
1449
1450/*
1451 * These are source-specific values; current Intel hardware supports
1452 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1453 */
a4fc5ed6
KP		 1454
1455static uint8_t
1a2eb460 1456intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 1457{
30add22d 1458 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460
KP		 1459
1460 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1461 return DP_TRAIN_VOLTAGE_SWING_800;
1462 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1463 return DP_TRAIN_VOLTAGE_SWING_1200;
1464 else
1465 return DP_TRAIN_VOLTAGE_SWING_800;
1466}
1467
1468static uint8_t
1469intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1470{
30add22d 1471 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1a2eb460 1472
22b8bf17 1473 if (HAS_DDI(dev)) {
d6c0d722
PZ		 1474 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1475 case DP_TRAIN_VOLTAGE_SWING_400:
1476 return DP_TRAIN_PRE_EMPHASIS_9_5;
1477 case DP_TRAIN_VOLTAGE_SWING_600:
1478 return DP_TRAIN_PRE_EMPHASIS_6;
1479 case DP_TRAIN_VOLTAGE_SWING_800:
1480 return DP_TRAIN_PRE_EMPHASIS_3_5;
1481 case DP_TRAIN_VOLTAGE_SWING_1200:
1482 default:
1483 return DP_TRAIN_PRE_EMPHASIS_0;
1484 }
1485 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1486 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1487 case DP_TRAIN_VOLTAGE_SWING_400:
1488 return DP_TRAIN_PRE_EMPHASIS_6;
1489 case DP_TRAIN_VOLTAGE_SWING_600:
1490 case DP_TRAIN_VOLTAGE_SWING_800:
1491 return DP_TRAIN_PRE_EMPHASIS_3_5;
1492 default:
1493 return DP_TRAIN_PRE_EMPHASIS_0;
1494 }
1495 } else {
1496 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1497 case DP_TRAIN_VOLTAGE_SWING_400:
1498 return DP_TRAIN_PRE_EMPHASIS_6;
1499 case DP_TRAIN_VOLTAGE_SWING_600:
1500 return DP_TRAIN_PRE_EMPHASIS_6;
1501 case DP_TRAIN_VOLTAGE_SWING_800:
1502 return DP_TRAIN_PRE_EMPHASIS_3_5;
1503 case DP_TRAIN_VOLTAGE_SWING_1200:
1504 default:
1505 return DP_TRAIN_PRE_EMPHASIS_0;
1506 }
a4fc5ed6
KP		 1507 }
1508}
1509
1510static void
93f62dad 1511intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 1512{
1513 uint8_t v = 0;
1514 uint8_t p = 0;
1515 int lane;
1a2eb460
KP		 1516 uint8_t voltage_max;
1517 uint8_t preemph_max;
a4fc5ed6 1518
33a34e4e 1519 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 1520 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1521 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 1522
1523 if (this_v > v)
1524 v = this_v;
1525 if (this_p > p)
1526 p = this_p;
1527 }
1528
1a2eb460 1529 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 1530 if (v >= voltage_max)
1531 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 1532
1a2eb460
KP		 1533 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1534 if (p >= preemph_max)
1535 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 1536
1537 for (lane = 0; lane < 4; lane++)
33a34e4e 1538 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 1539}
1540
1541static uint32_t
f0a3424e 1542intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 1543{
3cf2efb1 1544 uint32_t signal_levels = 0;
a4fc5ed6 1545
3cf2efb1 1546 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 1547 case DP_TRAIN_VOLTAGE_SWING_400:
1548 default:
1549 signal_levels |= DP_VOLTAGE_0_4;
1550 break;
1551 case DP_TRAIN_VOLTAGE_SWING_600:
1552 signal_levels |= DP_VOLTAGE_0_6;
1553 break;
1554 case DP_TRAIN_VOLTAGE_SWING_800:
1555 signal_levels |= DP_VOLTAGE_0_8;
1556 break;
1557 case DP_TRAIN_VOLTAGE_SWING_1200:
1558 signal_levels |= DP_VOLTAGE_1_2;
1559 break;
1560 }
3cf2efb1 1561 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 1562 case DP_TRAIN_PRE_EMPHASIS_0:
1563 default:
1564 signal_levels |= DP_PRE_EMPHASIS_0;
1565 break;
1566 case DP_TRAIN_PRE_EMPHASIS_3_5:
1567 signal_levels |= DP_PRE_EMPHASIS_3_5;
1568 break;
1569 case DP_TRAIN_PRE_EMPHASIS_6:
1570 signal_levels |= DP_PRE_EMPHASIS_6;
1571 break;
1572 case DP_TRAIN_PRE_EMPHASIS_9_5:
1573 signal_levels |= DP_PRE_EMPHASIS_9_5;
1574 break;
1575 }
1576 return signal_levels;
1577}
1578
e3421a18
ZW		 1579/* Gen6's DP voltage swing and pre-emphasis control */
1580static uint32_t
1581intel_gen6_edp_signal_levels(uint8_t train_set)
1582{
3c5a62b5
YL		 1583 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1584 DP_TRAIN_PRE_EMPHASIS_MASK);
1585 switch (signal_levels) {
e3421a18 1586 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1587 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1588 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1589 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1590 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 1591 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 1592 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1593 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 1594 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 1595 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1596 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 1597 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 1598 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1599 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 1600 default:
3c5a62b5
YL		 1601 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1602 "0x%x\n", signal_levels);
1603 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 1604 }
1605}
1606
1a2eb460
KP		 1607/* Gen7's DP voltage swing and pre-emphasis control */
1608static uint32_t
1609intel_gen7_edp_signal_levels(uint8_t train_set)
1610{
1611 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1612 DP_TRAIN_PRE_EMPHASIS_MASK);
1613 switch (signal_levels) {
1614 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1615 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1616 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1617 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1618 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1619 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1620
1621 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1622 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1623 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1624 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1625
1626 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1627 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1628 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1629 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1630
1631 default:
1632 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1633 "0x%x\n", signal_levels);
1634 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1635 }
1636}
1637
d6c0d722
PZ		 1638/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1639static uint32_t
f0a3424e 1640intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 1641{
d6c0d722
PZ		 1642 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1643 DP_TRAIN_PRE_EMPHASIS_MASK);
1644 switch (signal_levels) {
1645 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1646 return DDI_BUF_EMP_400MV_0DB_HSW;
1647 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1648 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1649 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1650 return DDI_BUF_EMP_400MV_6DB_HSW;
1651 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1652 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 1653
d6c0d722
PZ		 1654 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1655 return DDI_BUF_EMP_600MV_0DB_HSW;
1656 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1657 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1658 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1659 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 1660
d6c0d722
PZ		 1661 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1662 return DDI_BUF_EMP_800MV_0DB_HSW;
1663 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1664 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1665 default:
1666 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1667 "0x%x\n", signal_levels);
1668 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 1669 }
a4fc5ed6
KP		 1670}
1671
f0a3424e
PZ		 1672/* Properly updates "DP" with the correct signal levels. */
1673static void
1674intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1675{
1676 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1677 struct drm_device *dev = intel_dig_port->base.base.dev;
1678 uint32_t signal_levels, mask;
1679 uint8_t train_set = intel_dp->train_set[0];
1680
22b8bf17 1681 if (HAS_DDI(dev)) {
f0a3424e
PZ		 1682 signal_levels = intel_hsw_signal_levels(train_set);
1683 mask = DDI_BUF_EMP_MASK;
1684 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1685 signal_levels = intel_gen7_edp_signal_levels(train_set);
1686 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1687 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1688 signal_levels = intel_gen6_edp_signal_levels(train_set);
1689 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1690 } else {
1691 signal_levels = intel_gen4_signal_levels(train_set);
1692 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1693 }
1694
1695 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1696
1697 *DP = (*DP & ~mask) | signal_levels;
1698}
1699
a4fc5ed6 1700static bool
ea5b213a 1701intel_dp_set_link_train(struct intel_dp *intel_dp,
a4fc5ed6 1702 uint32_t dp_reg_value,
58e10eb9 1703 uint8_t dp_train_pat)
a4fc5ed6 1704{
174edf1f
PZ		 1705 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1706 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1707 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 1708 enum port port = intel_dig_port->port;
a4fc5ed6 1709 int ret;
d6c0d722 1710 uint32_t temp;
a4fc5ed6 1711
22b8bf17 1712 if (HAS_DDI(dev)) {
174edf1f 1713 temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 1714
1715 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1716 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1717 else
1718 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1719
1720 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1721 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1722 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722 1723
10aa17c8
PZ		 1724 if (port != PORT_A) {
1725 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1726 I915_WRITE(DP_TP_CTL(port), temp);
1727
1728 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1729 DP_TP_STATUS_IDLE_DONE), 1))
1730 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1731
1732 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1733 }
d6c0d722 1734
d6c0d722
PZ		 1735 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1736
1737 break;
1738 case DP_TRAINING_PATTERN_1:
1739 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1740 break;
1741 case DP_TRAINING_PATTERN_2:
1742 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1743 break;
1744 case DP_TRAINING_PATTERN_3:
1745 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1746 break;
1747 }
174edf1f 1748 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722
PZ		 1749
1750 } else if (HAS_PCH_CPT(dev) &&
1751 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
47ea7542
PZ		 1752 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1753
1754 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1755 case DP_TRAINING_PATTERN_DISABLE:
1756 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1757 break;
1758 case DP_TRAINING_PATTERN_1:
1759 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1760 break;
1761 case DP_TRAINING_PATTERN_2:
1762 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1763 break;
1764 case DP_TRAINING_PATTERN_3:
1765 DRM_ERROR("DP training pattern 3 not supported\n");
1766 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1767 break;
1768 }
1769
1770 } else {
1771 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1772
1773 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1774 case DP_TRAINING_PATTERN_DISABLE:
1775 dp_reg_value |= DP_LINK_TRAIN_OFF;
1776 break;
1777 case DP_TRAINING_PATTERN_1:
1778 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1779 break;
1780 case DP_TRAINING_PATTERN_2:
1781 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1782 break;
1783 case DP_TRAINING_PATTERN_3:
1784 DRM_ERROR("DP training pattern 3 not supported\n");
1785 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1786 break;
1787 }
1788 }
1789
ea5b213a
CW		 1790 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1791 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 1792
ea5b213a 1793 intel_dp_aux_native_write_1(intel_dp,
a4fc5ed6
KP		 1794 DP_TRAINING_PATTERN_SET,
1795 dp_train_pat);
1796
47ea7542
PZ		 1797 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1798 DP_TRAINING_PATTERN_DISABLE) {
1799 ret = intel_dp_aux_native_write(intel_dp,
1800 DP_TRAINING_LANE0_SET,
1801 intel_dp->train_set,
1802 intel_dp->lane_count);
1803 if (ret != intel_dp->lane_count)
1804 return false;
1805 }
a4fc5ed6
KP		 1806
1807 return true;
1808}
1809
33a34e4e 1810/* Enable corresponding port and start training pattern 1 */
c19b0669 1811void
33a34e4e 1812intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 1813{
da63a9f2 1814 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 1815 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 1816 int i;
1817 uint8_t voltage;
1818 bool clock_recovery = false;
cdb0e95b 1819 int voltage_tries, loop_tries;
ea5b213a 1820 uint32_t DP = intel_dp->DP;
a4fc5ed6 1821
affa9354 1822 if (HAS_DDI(dev))
c19b0669
PZ		 1823 intel_ddi_prepare_link_retrain(encoder);
1824
3cf2efb1
CW		 1825 /* Write the link configuration data */
1826 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1827 intel_dp->link_configuration,
1828 DP_LINK_CONFIGURATION_SIZE);
a4fc5ed6
KP		 1829
1830 DP |= DP_PORT_EN;
1a2eb460 1831
33a34e4e 1832 memset(intel_dp->train_set, 0, 4);
a4fc5ed6 1833 voltage = 0xff;
cdb0e95b
KP		 1834 voltage_tries = 0;
1835 loop_tries = 0;
a4fc5ed6
KP		 1836 clock_recovery = false;
1837 for (;;) {
33a34e4e 1838 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
93f62dad 1839 uint8_t link_status[DP_LINK_STATUS_SIZE];
f0a3424e
PZ		 1840
1841 intel_dp_set_signal_levels(intel_dp, &DP);
a4fc5ed6 1842
a7c9655f 1843 /* Set training pattern 1 */
47ea7542 1844 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1845 DP_TRAINING_PATTERN_1 |
1846 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6 1847 break;
a4fc5ed6 1848
a7c9655f 1849 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 1850 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1851 DRM_ERROR("failed to get link status\n");
a4fc5ed6 1852 break;
93f62dad 1853 }
a4fc5ed6 1854
01916270 1855 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 1856 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 1857 clock_recovery = true;
1858 break;
1859 }
1860
1861 /* Check to see if we've tried the max voltage */
1862 for (i = 0; i < intel_dp->lane_count; i++)
1863 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 1864 break;
3b4f819d 1865 if (i == intel_dp->lane_count) {
b06fbda3
DV		 1866 ++loop_tries;
1867 if (loop_tries == 5) {
cdb0e95b
KP		 1868 DRM_DEBUG_KMS("too many full retries, give up\n");
1869 break;
1870 }
1871 memset(intel_dp->train_set, 0, 4);
1872 voltage_tries = 0;
1873 continue;
1874 }
a4fc5ed6 1875
3cf2efb1 1876 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 1877 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 1878 ++voltage_tries;
b06fbda3
DV		 1879 if (voltage_tries == 5) {
1880 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1881 break;
1882 }
1883 } else
1884 voltage_tries = 0;
1885 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 1886
3cf2efb1 1887 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1888 intel_get_adjust_train(intel_dp, link_status);
a4fc5ed6
KP		 1889 }
1890
33a34e4e
JB		 1891 intel_dp->DP = DP;
1892}
1893
c19b0669 1894void
33a34e4e
JB		 1895intel_dp_complete_link_train(struct intel_dp *intel_dp)
1896{
33a34e4e 1897 bool channel_eq = false;
37f80975 1898 int tries, cr_tries;
33a34e4e
JB		 1899 uint32_t DP = intel_dp->DP;
1900
a4fc5ed6
KP		 1901 /* channel equalization */
1902 tries = 0;
37f80975 1903 cr_tries = 0;
a4fc5ed6
KP		 1904 channel_eq = false;
1905 for (;;) {
93f62dad 1906 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 1907
37f80975
JB		 1908 if (cr_tries > 5) {
1909 DRM_ERROR("failed to train DP, aborting\n");
1910 intel_dp_link_down(intel_dp);
1911 break;
1912 }
1913
f0a3424e 1914 intel_dp_set_signal_levels(intel_dp, &DP);
e3421a18 1915
a4fc5ed6 1916 /* channel eq pattern */
47ea7542 1917 if (!intel_dp_set_link_train(intel_dp, DP,
81055854
AJ		 1918 DP_TRAINING_PATTERN_2 |
1919 DP_LINK_SCRAMBLING_DISABLE))
a4fc5ed6
KP		 1920 break;
1921
a7c9655f 1922 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
93f62dad 1923 if (!intel_dp_get_link_status(intel_dp, link_status))
a4fc5ed6 1924 break;
a4fc5ed6 1925
37f80975 1926 /* Make sure clock is still ok */
01916270 1927 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975
JB		 1928 intel_dp_start_link_train(intel_dp);
1929 cr_tries++;
1930 continue;
1931 }
1932
1ffdff13 1933 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 1934 channel_eq = true;
1935 break;
1936 }
a4fc5ed6 1937
37f80975
JB		 1938 /* Try 5 times, then try clock recovery if that fails */
1939 if (tries > 5) {
1940 intel_dp_link_down(intel_dp);
1941 intel_dp_start_link_train(intel_dp);
1942 tries = 0;
1943 cr_tries++;
1944 continue;
1945 }
a4fc5ed6 1946
3cf2efb1 1947 /* Compute new intel_dp->train_set as requested by target */
93f62dad 1948 intel_get_adjust_train(intel_dp, link_status);
3cf2efb1 1949 ++tries;
869184a6 1950 }
3cf2efb1 1951
d6c0d722
PZ		 1952 if (channel_eq)
1953 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1954
47ea7542 1955 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 1956}
1957
1958static void
ea5b213a 1959intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 1960{
da63a9f2
PZ		 1961 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1962 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 1963 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 1964 struct intel_crtc *intel_crtc =
1965 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 1966 uint32_t DP = intel_dp->DP;
a4fc5ed6 1967
c19b0669
PZ		 1968 /*
1969 * DDI code has a strict mode set sequence and we should try to respect
1970 * it, otherwise we might hang the machine in many different ways. So we
1971 * really should be disabling the port only on a complete crtc_disable
1972 * sequence. This function is just called under two conditions on DDI
1973 * code:
1974 * - Link train failed while doing crtc_enable, and on this case we
1975 * really should respect the mode set sequence and wait for a
1976 * crtc_disable.
1977 * - Someone turned the monitor off and intel_dp_check_link_status
1978 * called us. We don't need to disable the whole port on this case, so
1979 * when someone turns the monitor on again,
1980 * intel_ddi_prepare_link_retrain will take care of redoing the link
1981 * train.
1982 */
affa9354 1983 if (HAS_DDI(dev))
c19b0669
PZ		 1984 return;
1985
0c33d8d7 1986 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 1987 return;
1988
28c97730 1989 DRM_DEBUG_KMS("\n");
32f9d658 1990
1a2eb460 1991 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
e3421a18 1992 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 1993 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18
ZW		 1994 } else {
1995 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 1996 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 1997 }
fe255d00 1998 POSTING_READ(intel_dp->output_reg);
5eb08b69 1999
ab527efc
DV		 2000 /* We don't really know why we're doing this */
2001 intel_wait_for_vblank(dev, intel_crtc->pipe);
5eb08b69 2002
493a7081 2003 if (HAS_PCH_IBX(dev) &&
1b39d6f3 2004 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 2005 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 2006
5bddd17f
EA		 2007 /* Hardware workaround: leaving our transcoder select
2008 * set to transcoder B while it's off will prevent the
2009 * corresponding HDMI output on transcoder A.
2010 *
2011 * Combine this with another hardware workaround:
2012 * transcoder select bit can only be cleared while the
2013 * port is enabled.
2014 */
2015 DP &= ~DP_PIPEB_SELECT;
2016 I915_WRITE(intel_dp->output_reg, DP);
2017
2018 /* Changes to enable or select take place the vblank
2019 * after being written.
2020 */
ff50afe9
DV		 2021 if (WARN_ON(crtc == NULL)) {
2022 /* We should never try to disable a port without a crtc
2023 * attached. For paranoia keep the code around for a
2024 * bit. */
31acbcc4
CW		 2025 POSTING_READ(intel_dp->output_reg);
2026 msleep(50);
2027 } else
ab527efc 2028 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 2029 }
2030
832afda6 2031 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 2032 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2033 POSTING_READ(intel_dp->output_reg);
f01eca2e 2034 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 2035}
2036
26d61aad
KP		 2037static bool
2038intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 2039{
577c7a50
DL		 2040 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2041
92fd8fd1 2042 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
edb39244
AJ		 2043 sizeof(intel_dp->dpcd)) == 0)
2044 return false; /* aux transfer failed */
92fd8fd1 2045
577c7a50
DL		 2046 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2047 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2048 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2049
edb39244
AJ		 2050 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2051 return false; /* DPCD not present */
2052
2053 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2054 DP_DWN_STRM_PORT_PRESENT))
2055 return true; /* native DP sink */
2056
2057 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2058 return true; /* no per-port downstream info */
2059
2060 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2061 intel_dp->downstream_ports,
2062 DP_MAX_DOWNSTREAM_PORTS) == 0)
2063 return false; /* downstream port status fetch failed */
2064
2065 return true;
92fd8fd1
KP		 2066}
2067
0d198328
AJ		 2068static void
2069intel_dp_probe_oui(struct intel_dp *intel_dp)
2070{
2071 u8 buf[3];
2072
2073 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2074 return;
2075
351cfc34
DV		 2076 ironlake_edp_panel_vdd_on(intel_dp);
2077
0d198328
AJ		 2078 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2079 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2080 buf[0], buf[1], buf[2]);
2081
2082 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2083 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2084 buf[0], buf[1], buf[2]);
351cfc34
DV		 2085
2086 ironlake_edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 2087}
2088
a60f0e38
JB		 2089static bool
2090intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2091{
2092 int ret;
2093
2094 ret = intel_dp_aux_native_read_retry(intel_dp,
2095 DP_DEVICE_SERVICE_IRQ_VECTOR,
2096 sink_irq_vector, 1);
2097 if (!ret)
2098 return false;
2099
2100 return true;
2101}
2102
2103static void
2104intel_dp_handle_test_request(struct intel_dp *intel_dp)
2105{
2106 /* NAK by default */
9324cf7f 2107 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 2108}
2109
a4fc5ed6
KP		 2110/*
2111 * According to DP spec
2112 * 5.1.2:
2113 * 1. Read DPCD
2114 * 2. Configure link according to Receiver Capabilities
2115 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2116 * 4. Check link status on receipt of hot-plug interrupt
2117 */
2118
00c09d70 2119void
ea5b213a 2120intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 2121{
da63a9f2 2122 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 2123 u8 sink_irq_vector;
93f62dad 2124 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 2125
da63a9f2 2126 if (!intel_encoder->connectors_active)
d2b996ac 2127 return;
59cd09e1 2128
da63a9f2 2129 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 2130 return;
2131
92fd8fd1 2132 /* Try to read receiver status if the link appears to be up */
93f62dad 2133 if (!intel_dp_get_link_status(intel_dp, link_status)) {
ea5b213a 2134 intel_dp_link_down(intel_dp);
a4fc5ed6
KP		 2135 return;
2136 }
2137
92fd8fd1 2138 /* Now read the DPCD to see if it's actually running */
26d61aad 2139 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 2140 intel_dp_link_down(intel_dp);
2141 return;
2142 }
2143
a60f0e38
JB		 2144 /* Try to read the source of the interrupt */
2145 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2146 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2147 /* Clear interrupt source */
2148 intel_dp_aux_native_write_1(intel_dp,
2149 DP_DEVICE_SERVICE_IRQ_VECTOR,
2150 sink_irq_vector);
2151
2152 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2153 intel_dp_handle_test_request(intel_dp);
2154 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2155 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2156 }
2157
1ffdff13 2158 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 2159 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
da63a9f2 2160 drm_get_encoder_name(&intel_encoder->base));
33a34e4e
JB		 2161 intel_dp_start_link_train(intel_dp);
2162 intel_dp_complete_link_train(intel_dp);
2163 }
a4fc5ed6 2164}
a4fc5ed6 2165
caf9ab24 2166/* XXX this is probably wrong for multiple downstream ports */
71ba9000 2167static enum drm_connector_status
26d61aad 2168intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 2169{
caf9ab24
AJ		 2170 uint8_t *dpcd = intel_dp->dpcd;
2171 bool hpd;
2172 uint8_t type;
2173
2174 if (!intel_dp_get_dpcd(intel_dp))
2175 return connector_status_disconnected;
2176
2177 /* if there's no downstream port, we're done */
2178 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 2179 return connector_status_connected;
caf9ab24
AJ		 2180
2181 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2182 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2183 if (hpd) {
23235177 2184 uint8_t reg;
caf9ab24 2185 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
23235177 2186 &reg, 1))
caf9ab24 2187 return connector_status_unknown;
23235177
AJ		 2188 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2189 : connector_status_disconnected;
caf9ab24
AJ		 2190 }
2191
2192 /* If no HPD, poke DDC gently */
2193 if (drm_probe_ddc(&intel_dp->adapter))
26d61aad 2194 return connector_status_connected;
caf9ab24
AJ		 2195
2196 /* Well we tried, say unknown for unreliable port types */
2197 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2198 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2199 return connector_status_unknown;
2200
2201 /* Anything else is out of spec, warn and ignore */
2202 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 2203 return connector_status_disconnected;
71ba9000
AJ		 2204}
2205
5eb08b69 2206static enum drm_connector_status
a9756bb5 2207ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 2208{
30add22d 2209 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 2210 struct drm_i915_private *dev_priv = dev->dev_private;
2211 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 2212 enum drm_connector_status status;
2213
fe16d949
CW		 2214 /* Can't disconnect eDP, but you can close the lid... */
2215 if (is_edp(intel_dp)) {
30add22d 2216 status = intel_panel_detect(dev);
fe16d949
CW		 2217 if (status == connector_status_unknown)
2218 status = connector_status_connected;
2219 return status;
2220 }
01cb9ea6 2221
1b469639
DL		 2222 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2223 return connector_status_disconnected;
2224
26d61aad 2225 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 2226}
2227
a4fc5ed6 2228static enum drm_connector_status
a9756bb5 2229g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 2230{
30add22d 2231 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 2232 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 2233 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 2234 uint32_t bit;
5eb08b69 2235
35aad75f
JB		 2236 /* Can't disconnect eDP, but you can close the lid... */
2237 if (is_edp(intel_dp)) {
2238 enum drm_connector_status status;
2239
2240 status = intel_panel_detect(dev);
2241 if (status == connector_status_unknown)
2242 status = connector_status_connected;
2243 return status;
2244 }
2245
34f2be46
VS		 2246 switch (intel_dig_port->port) {
2247 case PORT_B:
26739f12 2248 bit = PORTB_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2249 break;
34f2be46 2250 case PORT_C:
26739f12 2251 bit = PORTC_HOTPLUG_LIVE_STATUS;
a4fc5ed6 2252 break;
34f2be46 2253 case PORT_D:
26739f12 2254 bit = PORTD_HOTPLUG_LIVE_STATUS;
a4fc5ed6
KP		 2255 break;
2256 default:
2257 return connector_status_unknown;
2258 }
2259
10f76a38 2260 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 2261 return connector_status_disconnected;
2262
26d61aad 2263 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 2264}
2265
8c241fef
KP		 2266static struct edid *
2267intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2268{
9cd300e0 2269 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 2270
9cd300e0
JN		 2271 /* use cached edid if we have one */
2272 if (intel_connector->edid) {
2273 struct edid *edid;
2274 int size;
2275
2276 /* invalid edid */
2277 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 2278 return NULL;
2279
9cd300e0 2280 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
d6f24d0f
JB		 2281 edid = kmalloc(size, GFP_KERNEL);
2282 if (!edid)
2283 return NULL;
2284
9cd300e0 2285 memcpy(edid, intel_connector->edid, size);
d6f24d0f
JB		 2286 return edid;
2287 }
8c241fef 2288
9cd300e0 2289 return drm_get_edid(connector, adapter);
8c241fef
KP		 2290}
2291
2292static int
2293intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2294{
9cd300e0 2295 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 2296
9cd300e0
JN		 2297 /* use cached edid if we have one */
2298 if (intel_connector->edid) {
2299 /* invalid edid */
2300 if (IS_ERR(intel_connector->edid))
2301 return 0;
2302
2303 return intel_connector_update_modes(connector,
2304 intel_connector->edid);
d6f24d0f
JB		 2305 }
2306
9cd300e0 2307 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 2308}
2309
a9756bb5
ZW		 2310static enum drm_connector_status
2311intel_dp_detect(struct drm_connector *connector, bool force)
2312{
2313 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 2314 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2315 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 2316 struct drm_device *dev = connector->dev;
a9756bb5
ZW		 2317 enum drm_connector_status status;
2318 struct edid *edid = NULL;
2319
2320 intel_dp->has_audio = false;
2321
2322 if (HAS_PCH_SPLIT(dev))
2323 status = ironlake_dp_detect(intel_dp);
2324 else
2325 status = g4x_dp_detect(intel_dp);
1b9be9d0 2326
a9756bb5
ZW		 2327 if (status != connector_status_connected)
2328 return status;
2329
0d198328
AJ		 2330 intel_dp_probe_oui(intel_dp);
2331
c3e5f67b
DV		 2332 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2333 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 2334 } else {
8c241fef 2335 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
f684960e
CW		 2336 if (edid) {
2337 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 2338 kfree(edid);
2339 }
a9756bb5
ZW		 2340 }
2341
d63885da
PZ		 2342 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2343 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
a9756bb5 2344 return connector_status_connected;
a4fc5ed6
KP		 2345}
2346
2347static int intel_dp_get_modes(struct drm_connector *connector)
2348{
df0e9248 2349 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e 2350 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 2351 struct drm_device *dev = connector->dev;
32f9d658 2352 int ret;
a4fc5ed6
KP		 2353
2354 /* We should parse the EDID data and find out if it has an audio sink
2355 */
2356
8c241fef 2357 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
f8779fda 2358 if (ret)
32f9d658
ZW		 2359 return ret;
2360
f8779fda 2361 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 2362 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 2363 struct drm_display_mode *mode;
dd06f90e
JN		 2364 mode = drm_mode_duplicate(dev,
2365 intel_connector->panel.fixed_mode);
f8779fda 2366 if (mode) {
32f9d658
ZW		 2367 drm_mode_probed_add(connector, mode);
2368 return 1;
2369 }
2370 }
2371 return 0;
a4fc5ed6
KP		 2372}
2373
1aad7ac0
CW		 2374static bool
2375intel_dp_detect_audio(struct drm_connector *connector)
2376{
2377 struct intel_dp *intel_dp = intel_attached_dp(connector);
2378 struct edid *edid;
2379 bool has_audio = false;
2380
8c241fef 2381 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
1aad7ac0
CW		 2382 if (edid) {
2383 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 2384 kfree(edid);
2385 }
2386
2387 return has_audio;
2388}
2389
f684960e
CW		 2390static int
2391intel_dp_set_property(struct drm_connector *connector,
2392 struct drm_property *property,
2393 uint64_t val)
2394{
e953fd7b 2395 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 2396 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 2397 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2398 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 2399 int ret;
2400
662595df 2401 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 2402 if (ret)
2403 return ret;
2404
3f43c48d 2405 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2406 int i = val;
2407 bool has_audio;
2408
2409 if (i == intel_dp->force_audio)
f684960e
CW		 2410 return 0;
2411
1aad7ac0 2412 intel_dp->force_audio = i;
f684960e 2413
c3e5f67b 2414 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2415 has_audio = intel_dp_detect_audio(connector);
2416 else
c3e5f67b 2417 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 2418
2419 if (has_audio == intel_dp->has_audio)
f684960e
CW		 2420 return 0;
2421
1aad7ac0 2422 intel_dp->has_audio = has_audio;
f684960e
CW		 2423 goto done;
2424 }
2425
e953fd7b 2426 if (property == dev_priv->broadcast_rgb_property) {
55bc60db
VS		 2427 switch (val) {
2428 case INTEL_BROADCAST_RGB_AUTO:
2429 intel_dp->color_range_auto = true;
2430 break;
2431 case INTEL_BROADCAST_RGB_FULL:
2432 intel_dp->color_range_auto = false;
2433 intel_dp->color_range = 0;
2434 break;
2435 case INTEL_BROADCAST_RGB_LIMITED:
2436 intel_dp->color_range_auto = false;
2437 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2438 break;
2439 default:
2440 return -EINVAL;
2441 }
e953fd7b
CW		 2442 goto done;
2443 }
2444
53b41837
YN		 2445 if (is_edp(intel_dp) &&
2446 property == connector->dev->mode_config.scaling_mode_property) {
2447 if (val == DRM_MODE_SCALE_NONE) {
2448 DRM_DEBUG_KMS("no scaling not supported\n");
2449 return -EINVAL;
2450 }
2451
2452 if (intel_connector->panel.fitting_mode == val) {
2453 /* the eDP scaling property is not changed */
2454 return 0;
2455 }
2456 intel_connector->panel.fitting_mode = val;
2457
2458 goto done;
2459 }
2460
f684960e
CW		 2461 return -EINVAL;
2462
2463done:
c0c36b94
CW		 2464 if (intel_encoder->base.crtc)
2465 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 2466
2467 return 0;
2468}
2469
a4fc5ed6 2470static void
0206e353 2471intel_dp_destroy(struct drm_connector *connector)
a4fc5ed6 2472{
aaa6fd2a 2473 struct drm_device *dev = connector->dev;
be3cd5e3 2474 struct intel_dp *intel_dp = intel_attached_dp(connector);
1d508706 2475 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 2476
9cd300e0
JN		 2477 if (!IS_ERR_OR_NULL(intel_connector->edid))
2478 kfree(intel_connector->edid);
2479
1d508706 2480 if (is_edp(intel_dp)) {
aaa6fd2a 2481 intel_panel_destroy_backlight(dev);
1d508706
JN		 2482 intel_panel_fini(&intel_connector->panel);
2483 }
aaa6fd2a 2484
a4fc5ed6
KP		 2485 drm_sysfs_connector_remove(connector);
2486 drm_connector_cleanup(connector);
55f78c43 2487 kfree(connector);
a4fc5ed6
KP		 2488}
2489
00c09d70 2490void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 2491{
da63a9f2
PZ		 2492 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2493 struct intel_dp *intel_dp = &intel_dig_port->dp;
24d05927
DV		 2494
2495 i2c_del_adapter(&intel_dp->adapter);
2496 drm_encoder_cleanup(encoder);
bd943159
KP		 2497 if (is_edp(intel_dp)) {
2498 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2499 ironlake_panel_vdd_off_sync(intel_dp);
2500 }
da63a9f2 2501 kfree(intel_dig_port);
24d05927
DV		 2502}
2503
a4fc5ed6 2504static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
a4fc5ed6 2505 .mode_set = intel_dp_mode_set,
a4fc5ed6
KP		 2506};
2507
2508static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 2509 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 2510 .detect = intel_dp_detect,
2511 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 2512 .set_property = intel_dp_set_property,
a4fc5ed6
KP		 2513 .destroy = intel_dp_destroy,
2514};
2515
2516static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2517 .get_modes = intel_dp_get_modes,
2518 .mode_valid = intel_dp_mode_valid,
df0e9248 2519 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 2520};
2521
a4fc5ed6 2522static const struct drm_encoder_funcs intel_dp_enc_funcs = {
24d05927 2523 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 2524};
2525
995b6762 2526static void
21d40d37 2527intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 2528{
fa90ecef 2529 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
c8110e52 2530
885a5014 2531 intel_dp_check_link_status(intel_dp);
c8110e52 2532}
6207937d 2533
e3421a18
ZW		 2534/* Return which DP Port should be selected for Transcoder DP control */
2535int
0206e353 2536intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 2537{
2538 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 2539 struct intel_encoder *intel_encoder;
2540 struct intel_dp *intel_dp;
e3421a18 2541
fa90ecef
PZ		 2542 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2543 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 2544
fa90ecef
PZ		 2545 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2546 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 2547 return intel_dp->output_reg;
e3421a18 2548 }
ea5b213a 2549
e3421a18
ZW		 2550 return -1;
2551}
2552
36e83a18 2553/* check the VBT to see whether the eDP is on DP-D port */
cb0953d7 2554bool intel_dpd_is_edp(struct drm_device *dev)
36e83a18
ZY		 2555{
2556 struct drm_i915_private *dev_priv = dev->dev_private;
2557 struct child_device_config *p_child;
2558 int i;
2559
2560 if (!dev_priv->child_dev_num)
2561 return false;
2562
2563 for (i = 0; i < dev_priv->child_dev_num; i++) {
2564 p_child = dev_priv->child_dev + i;
2565
2566 if (p_child->dvo_port == PORT_IDPD &&
2567 p_child->device_type == DEVICE_TYPE_eDP)
2568 return true;
2569 }
2570 return false;
2571}
2572
f684960e
CW		 2573static void
2574intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2575{
53b41837
YN		 2576 struct intel_connector *intel_connector = to_intel_connector(connector);
2577
3f43c48d 2578 intel_attach_force_audio_property(connector);
e953fd7b 2579 intel_attach_broadcast_rgb_property(connector);
55bc60db 2580 intel_dp->color_range_auto = true;
53b41837
YN		 2581
2582 if (is_edp(intel_dp)) {
2583 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 2584 drm_object_attach_property(
2585 &connector->base,
53b41837 2586 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 2587 DRM_MODE_SCALE_ASPECT);
2588 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 2589 }
f684960e
CW		 2590}
2591
67a54566
DV		 2592static void
2593intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 2594 struct intel_dp *intel_dp,
2595 struct edp_power_seq *out)
67a54566
DV		 2596{
2597 struct drm_i915_private *dev_priv = dev->dev_private;
2598 struct edp_power_seq cur, vbt, spec, final;
2599 u32 pp_on, pp_off, pp_div, pp;
453c5420
JB		 2600 int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;
2601
2602 if (HAS_PCH_SPLIT(dev)) {
2603 pp_control_reg = PCH_PP_CONTROL;
2604 pp_on_reg = PCH_PP_ON_DELAYS;
2605 pp_off_reg = PCH_PP_OFF_DELAYS;
2606 pp_div_reg = PCH_PP_DIVISOR;
2607 } else {
2608 pp_control_reg = PIPEA_PP_CONTROL;
2609 pp_on_reg = PIPEA_PP_ON_DELAYS;
2610 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2611 pp_div_reg = PIPEA_PP_DIVISOR;
2612 }
67a54566
DV		 2613
2614 /* Workaround: Need to write PP_CONTROL with the unlock key as
2615 * the very first thing. */
453c5420
JB		 2616 pp = ironlake_get_pp_control(intel_dp);
2617 I915_WRITE(pp_control_reg, pp);
67a54566 2618
453c5420
JB		 2619 pp_on = I915_READ(pp_on_reg);
2620 pp_off = I915_READ(pp_off_reg);
2621 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 2622
2623 /* Pull timing values out of registers */
2624 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2625 PANEL_POWER_UP_DELAY_SHIFT;
2626
2627 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2628 PANEL_LIGHT_ON_DELAY_SHIFT;
2629
2630 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2631 PANEL_LIGHT_OFF_DELAY_SHIFT;
2632
2633 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2634 PANEL_POWER_DOWN_DELAY_SHIFT;
2635
2636 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2637 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2638
2639 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2640 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2641
2642 vbt = dev_priv->edp.pps;
2643
2644 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2645 * our hw here, which are all in 100usec. */
2646 spec.t1_t3 = 210 * 10;
2647 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2648 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2649 spec.t10 = 500 * 10;
2650 /* This one is special and actually in units of 100ms, but zero
2651 * based in the hw (so we need to add 100 ms). But the sw vbt
2652 * table multiplies it with 1000 to make it in units of 100usec,
2653 * too. */
2654 spec.t11_t12 = (510 + 100) * 10;
2655
2656 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2657 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2658
2659 /* Use the max of the register settings and vbt. If both are
2660 * unset, fall back to the spec limits. */
2661#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2662 spec.field : \
2663 max(cur.field, vbt.field))
2664 assign_final(t1_t3);
2665 assign_final(t8);
2666 assign_final(t9);
2667 assign_final(t10);
2668 assign_final(t11_t12);
2669#undef assign_final
2670
2671#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2672 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2673 intel_dp->backlight_on_delay = get_delay(t8);
2674 intel_dp->backlight_off_delay = get_delay(t9);
2675 intel_dp->panel_power_down_delay = get_delay(t10);
2676 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2677#undef get_delay
2678
f30d26e4
JN		 2679 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2680 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2681 intel_dp->panel_power_cycle_delay);
2682
2683 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2684 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2685
2686 if (out)
2687 *out = final;
2688}
2689
2690static void
2691intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2692 struct intel_dp *intel_dp,
2693 struct edp_power_seq *seq)
2694{
2695 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 2696 u32 pp_on, pp_off, pp_div, port_sel = 0;
2697 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
2698 int pp_on_reg, pp_off_reg, pp_div_reg;
2699
2700 if (HAS_PCH_SPLIT(dev)) {
2701 pp_on_reg = PCH_PP_ON_DELAYS;
2702 pp_off_reg = PCH_PP_OFF_DELAYS;
2703 pp_div_reg = PCH_PP_DIVISOR;
2704 } else {
2705 pp_on_reg = PIPEA_PP_ON_DELAYS;
2706 pp_off_reg = PIPEA_PP_OFF_DELAYS;
2707 pp_div_reg = PIPEA_PP_DIVISOR;
2708 }
2709
2710 if (IS_VALLEYVIEW(dev))
2711 port_sel = I915_READ(pp_on_reg) & 0xc0000000;
f30d26e4 2712
67a54566 2713 /* And finally store the new values in the power sequencer. */
f30d26e4
JN		 2714 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2715 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2716 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2717 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 2718 /* Compute the divisor for the pp clock, simply match the Bspec
2719 * formula. */
453c5420 2720 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 2721 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 2722 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2723
2724 /* Haswell doesn't have any port selection bits for the panel
2725 * power sequencer any more. */
2726 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2727 if (is_cpu_edp(intel_dp))
453c5420 2728 port_sel = PANEL_POWER_PORT_DP_A;
67a54566 2729 else
453c5420 2730 port_sel = PANEL_POWER_PORT_DP_D;
67a54566
DV		 2731 }
2732
453c5420
JB		 2733 pp_on |= port_sel;
2734
2735 I915_WRITE(pp_on_reg, pp_on);
2736 I915_WRITE(pp_off_reg, pp_off);
2737 I915_WRITE(pp_div_reg, pp_div);
67a54566 2738
67a54566 2739 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 2740 I915_READ(pp_on_reg),
2741 I915_READ(pp_off_reg),
2742 I915_READ(pp_div_reg));
f684960e
CW		 2743}
2744
a4fc5ed6 2745void
f0fec3f2
PZ		 2746intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2747 struct intel_connector *intel_connector)
a4fc5ed6 2748{
f0fec3f2
PZ		 2749 struct drm_connector *connector = &intel_connector->base;
2750 struct intel_dp *intel_dp = &intel_dig_port->dp;
2751 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2752 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 2753 struct drm_i915_private *dev_priv = dev->dev_private;
f8779fda 2754 struct drm_display_mode *fixed_mode = NULL;
f30d26e4 2755 struct edp_power_seq power_seq = { 0 };
174edf1f 2756 enum port port = intel_dig_port->port;
5eb08b69 2757 const char *name = NULL;
b329530c 2758 int type;
a4fc5ed6 2759
0767935e
DV		 2760 /* Preserve the current hw state. */
2761 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 2762 intel_dp->attached_connector = intel_connector;
3d3dc149 2763
f0fec3f2 2764 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
b329530c 2765 if (intel_dpd_is_edp(dev))
ea5b213a 2766 intel_dp->is_pch_edp = true;
b329530c 2767
19c03924
GB		 2768 /*
2769 * FIXME : We need to initialize built-in panels before external panels.
2770 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2771 */
f0fec3f2 2772 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
19c03924
GB		 2773 type = DRM_MODE_CONNECTOR_eDP;
2774 intel_encoder->type = INTEL_OUTPUT_EDP;
f0fec3f2 2775 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
b329530c
AJ		 2776 type = DRM_MODE_CONNECTOR_eDP;
2777 intel_encoder->type = INTEL_OUTPUT_EDP;
2778 } else {
00c09d70
PZ		 2779 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2780 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2781 * rewrite it.
2782 */
b329530c 2783 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c
AJ		 2784 }
2785
b329530c 2786 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 2787 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2788
eb1f8e4f 2789 connector->polled = DRM_CONNECTOR_POLL_HPD;
a4fc5ed6
KP		 2790 connector->interlace_allowed = true;
2791 connector->doublescan_allowed = 0;
2792
f0fec3f2
PZ		 2793 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2794 ironlake_panel_vdd_work);
a4fc5ed6 2795
df0e9248 2796 intel_connector_attach_encoder(intel_connector, intel_encoder);
a4fc5ed6
KP		 2797 drm_sysfs_connector_add(connector);
2798
affa9354 2799 if (HAS_DDI(dev))
bcbc889b
PZ		 2800 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2801 else
2802 intel_connector->get_hw_state = intel_connector_get_hw_state;
2803
9ed35ab1
PZ		 2804 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
2805 if (HAS_DDI(dev)) {
2806 switch (intel_dig_port->port) {
2807 case PORT_A:
2808 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
2809 break;
2810 case PORT_B:
2811 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
2812 break;
2813 case PORT_C:
2814 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
2815 break;
2816 case PORT_D:
2817 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
2818 break;
2819 default:
2820 BUG();
2821 }
2822 }
e8cb4558 2823
a4fc5ed6 2824 /* Set up the DDC bus. */
ab9d7c30
PZ		 2825 switch (port) {
2826 case PORT_A:
1d843f9d 2827 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 2828 name = "DPDDC-A";
2829 break;
2830 case PORT_B:
1d843f9d 2831 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 2832 name = "DPDDC-B";
2833 break;
2834 case PORT_C:
1d843f9d 2835 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 2836 name = "DPDDC-C";
2837 break;
2838 case PORT_D:
1d843f9d 2839 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 2840 name = "DPDDC-D";
2841 break;
2842 default:
ad1c0b19 2843 BUG();
5eb08b69
ZW		 2844 }
2845
67a54566 2846 if (is_edp(intel_dp))
f30d26e4 2847 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
c1f05264
DA		 2848
2849 intel_dp_i2c_init(intel_dp, intel_connector, name);
2850
67a54566 2851 /* Cache DPCD and EDID for edp. */
c1f05264
DA		 2852 if (is_edp(intel_dp)) {
2853 bool ret;
f8779fda 2854 struct drm_display_mode *scan;
c1f05264 2855 struct edid *edid;
5d613501
JB		 2856
2857 ironlake_edp_panel_vdd_on(intel_dp);
59f3e272 2858 ret = intel_dp_get_dpcd(intel_dp);
bd943159 2859 ironlake_edp_panel_vdd_off(intel_dp, false);
99ea7127 2860
59f3e272 2861 if (ret) {
7183dc29
JB		 2862 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2863 dev_priv->no_aux_handshake =
2864 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
89667383
JB		 2865 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2866 } else {
3d3dc149 2867 /* if this fails, presume the device is a ghost */
48898b03 2868 DRM_INFO("failed to retrieve link info, disabling eDP\n");
fa90ecef
PZ		 2869 intel_dp_encoder_destroy(&intel_encoder->base);
2870 intel_dp_destroy(connector);
3d3dc149 2871 return;
89667383 2872 }
89667383 2873
f30d26e4
JN		 2874 /* We now know it's not a ghost, init power sequence regs. */
2875 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2876 &power_seq);
2877
d6f24d0f
JB		 2878 ironlake_edp_panel_vdd_on(intel_dp);
2879 edid = drm_get_edid(connector, &intel_dp->adapter);
2880 if (edid) {
9cd300e0
JN		 2881 if (drm_add_edid_modes(connector, edid)) {
2882 drm_mode_connector_update_edid_property(connector, edid);
2883 drm_edid_to_eld(connector, edid);
2884 } else {
2885 kfree(edid);
2886 edid = ERR_PTR(-EINVAL);
2887 }
2888 } else {
2889 edid = ERR_PTR(-ENOENT);
d6f24d0f 2890 }
9cd300e0 2891 intel_connector->edid = edid;
f8779fda
JN		 2892
2893 /* prefer fixed mode from EDID if available */
2894 list_for_each_entry(scan, &connector->probed_modes, head) {
2895 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2896 fixed_mode = drm_mode_duplicate(dev, scan);
2897 break;
2898 }
d6f24d0f 2899 }
f8779fda
JN		 2900
2901 /* fallback to VBT if available for eDP */
2902 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2903 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2904 if (fixed_mode)
2905 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2906 }
f8779fda 2907
d6f24d0f
JB		 2908 ironlake_edp_panel_vdd_off(intel_dp, false);
2909 }
552fb0b7 2910
4d926461 2911 if (is_edp(intel_dp)) {
dd06f90e 2912 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 2913 intel_panel_setup_backlight(connector);
32f9d658
ZW		 2914 }
2915
f684960e
CW		 2916 intel_dp_add_properties(intel_dp, connector);
2917
a4fc5ed6
KP		 2918 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2919 * 0xd. Failure to do so will result in spurious interrupts being
2920 * generated on the port when a cable is not attached.
2921 */
2922 if (IS_G4X(dev) && !IS_GM45(dev)) {
2923 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2924 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2925 }
2926}
f0fec3f2
PZ		 2927
2928void
2929intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2930{
2931 struct intel_digital_port *intel_dig_port;
2932 struct intel_encoder *intel_encoder;
2933 struct drm_encoder *encoder;
2934 struct intel_connector *intel_connector;
2935
2936 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2937 if (!intel_dig_port)
2938 return;
2939
2940 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2941 if (!intel_connector) {
2942 kfree(intel_dig_port);
2943 return;
2944 }
2945
2946 intel_encoder = &intel_dig_port->base;
2947 encoder = &intel_encoder->base;
2948
2949 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2950 DRM_MODE_ENCODER_TMDS);
00c09d70 2951 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
f0fec3f2 2952
5bfe2ac0 2953 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70
PZ		 2954 intel_encoder->enable = intel_enable_dp;
2955 intel_encoder->pre_enable = intel_pre_enable_dp;
2956 intel_encoder->disable = intel_disable_dp;
2957 intel_encoder->post_disable = intel_post_disable_dp;
2958 intel_encoder->get_hw_state = intel_dp_get_hw_state;
f0fec3f2 2959
174edf1f 2960 intel_dig_port->port = port;
f0fec3f2
PZ		 2961 intel_dig_port->dp.output_reg = output_reg;
2962
00c09d70 2963 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
f0fec3f2
PZ		 2964 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2965 intel_encoder->cloneable = false;
2966 intel_encoder->hot_plug = intel_dp_hot_plug;
2967
2968 intel_dp_init_connector(intel_dig_port, intel_connector);
2969}
Linux 6.x block layer and io_uring tree(s)