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drm/i915: add some framework for backlight bl_power support
[linux-2.6-block.git] / drivers / gpu / drm / i915 / intel_dp.c
CommitLineData
a4fc5ed6
KP		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
2d1a8a48 30#include <linux/export.h>
01527b31
CT		 31#include <linux/notifier.h>
32#include <linux/reboot.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/drm_crtc.h>
35#include <drm/drm_crtc_helper.h>
36#include <drm/drm_edid.h>
a4fc5ed6 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
a4fc5ed6 39#include "i915_drv.h"
a4fc5ed6 40
a4fc5ed6
KP		 41#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42
9dd4ffdf
CML		 43struct dp_link_dpll {
44 int link_bw;
45 struct dpll dpll;
46};
47
48static const struct dp_link_dpll gen4_dpll[] = {
49 { DP_LINK_BW_1_62,
50 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
51 { DP_LINK_BW_2_7,
52 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
53};
54
55static const struct dp_link_dpll pch_dpll[] = {
56 { DP_LINK_BW_1_62,
57 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
58 { DP_LINK_BW_2_7,
59 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
60};
61
65ce4bf5
CML		 62static const struct dp_link_dpll vlv_dpll[] = {
63 { DP_LINK_BW_1_62,
58f6e632 64 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
65ce4bf5
CML		 65 { DP_LINK_BW_2_7,
66 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
67};
68
ef9348c8
CML		 69/*
70 * CHV supports eDP 1.4 that have more link rates.
71 * Below only provides the fixed rate but exclude variable rate.
72 */
73static const struct dp_link_dpll chv_dpll[] = {
74 /*
75 * CHV requires to program fractional division for m2.
76 * m2 is stored in fixed point format using formula below
77 * (m2_int << 22) | m2_fraction
78 */
79 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
80 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
81 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
83 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
84 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
85};
86
cfcb0fc9
JB		 87/**
88 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
89 * @intel_dp: DP struct
90 *
91 * If a CPU or PCH DP output is attached to an eDP panel, this function
92 * will return true, and false otherwise.
93 */
94static bool is_edp(struct intel_dp *intel_dp)
95{
da63a9f2
PZ		 96 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
97
98 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
cfcb0fc9
JB		 99}
100
68b4d824 101static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
cfcb0fc9 102{
68b4d824
ID		 103 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
104
105 return intel_dig_port->base.base.dev;
cfcb0fc9
JB		 106}
107
df0e9248
CW		 108static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
109{
fa90ecef 110 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
df0e9248
CW		 111}
112
ea5b213a 113static void intel_dp_link_down(struct intel_dp *intel_dp);
adddaaf4 114static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
4be73780 115static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
a4fc5ed6 116
0e32b39c 117int
ea5b213a 118intel_dp_max_link_bw(struct intel_dp *intel_dp)
a4fc5ed6 119{
7183dc29 120 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
06ea66b6 121 struct drm_device *dev = intel_dp->attached_connector->base.dev;
a4fc5ed6
KP		 122
123 switch (max_link_bw) {
124 case DP_LINK_BW_1_62:
125 case DP_LINK_BW_2_7:
126 break;
d4eead50 127 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
9bbfd20a
PZ		 128 if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
129 INTEL_INFO(dev)->gen >= 8) &&
06ea66b6
TP		 130 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
131 max_link_bw = DP_LINK_BW_5_4;
132 else
133 max_link_bw = DP_LINK_BW_2_7;
d4eead50 134 break;
a4fc5ed6 135 default:
d4eead50
ID		 136 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
137 max_link_bw);
a4fc5ed6
KP		 138 max_link_bw = DP_LINK_BW_1_62;
139 break;
140 }
141 return max_link_bw;
142}
143
eeb6324d
PZ		 144static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
145{
146 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
147 struct drm_device *dev = intel_dig_port->base.base.dev;
148 u8 source_max, sink_max;
149
150 source_max = 4;
151 if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
152 (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
153 source_max = 2;
154
155 sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
156
157 return min(source_max, sink_max);
158}
159
cd9dde44
AJ		 160/*
161 * The units on the numbers in the next two are... bizarre. Examples will
162 * make it clearer; this one parallels an example in the eDP spec.
163 *
164 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
165 *
166 * 270000 * 1 * 8 / 10 == 216000
167 *
168 * The actual data capacity of that configuration is 2.16Gbit/s, so the
169 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
170 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
171 * 119000. At 18bpp that's 2142000 kilobits per second.
172 *
173 * Thus the strange-looking division by 10 in intel_dp_link_required, to
174 * get the result in decakilobits instead of kilobits.
175 */
176
a4fc5ed6 177static int
c898261c 178intel_dp_link_required(int pixel_clock, int bpp)
a4fc5ed6 179{
cd9dde44 180 return (pixel_clock * bpp + 9) / 10;
a4fc5ed6
KP		 181}
182
fe27d53e
DA		 183static int
184intel_dp_max_data_rate(int max_link_clock, int max_lanes)
185{
186 return (max_link_clock * max_lanes * 8) / 10;
187}
188
c19de8eb 189static enum drm_mode_status
a4fc5ed6
KP		 190intel_dp_mode_valid(struct drm_connector *connector,
191 struct drm_display_mode *mode)
192{
df0e9248 193 struct intel_dp *intel_dp = intel_attached_dp(connector);
dd06f90e
JN		 194 struct intel_connector *intel_connector = to_intel_connector(connector);
195 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
36008365
DV		 196 int target_clock = mode->clock;
197 int max_rate, mode_rate, max_lanes, max_link_clock;
a4fc5ed6 198
dd06f90e
JN		 199 if (is_edp(intel_dp) && fixed_mode) {
200 if (mode->hdisplay > fixed_mode->hdisplay)
7de56f43
ZY		 201 return MODE_PANEL;
202
dd06f90e 203 if (mode->vdisplay > fixed_mode->vdisplay)
7de56f43 204 return MODE_PANEL;
03afc4a2
DV		 205
206 target_clock = fixed_mode->clock;
7de56f43
ZY		 207 }
208
36008365 209 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
eeb6324d 210 max_lanes = intel_dp_max_lane_count(intel_dp);
36008365
DV		 211
212 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
213 mode_rate = intel_dp_link_required(target_clock, 18);
214
215 if (mode_rate > max_rate)
c4867936 216 return MODE_CLOCK_HIGH;
a4fc5ed6
KP		 217
218 if (mode->clock < 10000)
219 return MODE_CLOCK_LOW;
220
0af78a2b
DV		 221 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
222 return MODE_H_ILLEGAL;
223
a4fc5ed6
KP		 224 return MODE_OK;
225}
226
227static uint32_t
228pack_aux(uint8_t *src, int src_bytes)
229{
230 int i;
231 uint32_t v = 0;
232
233 if (src_bytes > 4)
234 src_bytes = 4;
235 for (i = 0; i < src_bytes; i++)
236 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237 return v;
238}
239
240static void
241unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242{
243 int i;
244 if (dst_bytes > 4)
245 dst_bytes = 4;
246 for (i = 0; i < dst_bytes; i++)
247 dst[i] = src >> ((3-i) * 8);
248}
249
fb0f8fbf
KP		 250/* hrawclock is 1/4 the FSB frequency */
251static int
252intel_hrawclk(struct drm_device *dev)
253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255 uint32_t clkcfg;
256
9473c8f4
VP		 257 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
258 if (IS_VALLEYVIEW(dev))
259 return 200;
260
fb0f8fbf
KP		 261 clkcfg = I915_READ(CLKCFG);
262 switch (clkcfg & CLKCFG_FSB_MASK) {
263 case CLKCFG_FSB_400:
264 return 100;
265 case CLKCFG_FSB_533:
266 return 133;
267 case CLKCFG_FSB_667:
268 return 166;
269 case CLKCFG_FSB_800:
270 return 200;
271 case CLKCFG_FSB_1067:
272 return 266;
273 case CLKCFG_FSB_1333:
274 return 333;
275 /* these two are just a guess; one of them might be right */
276 case CLKCFG_FSB_1600:
277 case CLKCFG_FSB_1600_ALT:
278 return 400;
279 default:
280 return 133;
281 }
282}
283
bf13e81b
JN		 284static void
285intel_dp_init_panel_power_sequencer(struct drm_device *dev,
286 struct intel_dp *intel_dp,
287 struct edp_power_seq *out);
288static void
289intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
290 struct intel_dp *intel_dp,
291 struct edp_power_seq *out);
292
293static enum pipe
294vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
295{
296 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
297 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
298 struct drm_device *dev = intel_dig_port->base.base.dev;
299 struct drm_i915_private *dev_priv = dev->dev_private;
300 enum port port = intel_dig_port->port;
301 enum pipe pipe;
302
303 /* modeset should have pipe */
304 if (crtc)
305 return to_intel_crtc(crtc)->pipe;
306
307 /* init time, try to find a pipe with this port selected */
308 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
309 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
310 PANEL_PORT_SELECT_MASK;
311 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
312 return pipe;
313 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
314 return pipe;
315 }
316
317 /* shrug */
318 return PIPE_A;
319}
320
321static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
322{
323 struct drm_device *dev = intel_dp_to_dev(intel_dp);
324
325 if (HAS_PCH_SPLIT(dev))
326 return PCH_PP_CONTROL;
327 else
328 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
329}
330
331static u32 _pp_stat_reg(struct intel_dp *intel_dp)
332{
333 struct drm_device *dev = intel_dp_to_dev(intel_dp);
334
335 if (HAS_PCH_SPLIT(dev))
336 return PCH_PP_STATUS;
337 else
338 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
339}
340
01527b31
CT		 341/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
342 This function only applicable when panel PM state is not to be tracked */
343static int edp_notify_handler(struct notifier_block *this, unsigned long code,
344 void *unused)
345{
346 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
347 edp_notifier);
348 struct drm_device *dev = intel_dp_to_dev(intel_dp);
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 u32 pp_div;
351 u32 pp_ctrl_reg, pp_div_reg;
352 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
353
354 if (!is_edp(intel_dp) || code != SYS_RESTART)
355 return 0;
356
357 if (IS_VALLEYVIEW(dev)) {
358 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
359 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
360 pp_div = I915_READ(pp_div_reg);
361 pp_div &= PP_REFERENCE_DIVIDER_MASK;
362
363 /* 0x1F write to PP_DIV_REG sets max cycle delay */
364 I915_WRITE(pp_div_reg, pp_div | 0x1F);
365 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
366 msleep(intel_dp->panel_power_cycle_delay);
367 }
368
369 return 0;
370}
371
4be73780 372static bool edp_have_panel_power(struct intel_dp *intel_dp)
ebf33b18 373{
30add22d 374 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18
KP		 375 struct drm_i915_private *dev_priv = dev->dev_private;
376
bf13e81b 377 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
ebf33b18
KP		 378}
379
4be73780 380static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
ebf33b18 381{
30add22d 382 struct drm_device *dev = intel_dp_to_dev(intel_dp);
ebf33b18 383 struct drm_i915_private *dev_priv = dev->dev_private;
bb4932c4
ID		 384 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
385 struct intel_encoder *intel_encoder = &intel_dig_port->base;
386 enum intel_display_power_domain power_domain;
ebf33b18 387
bb4932c4
ID		 388 power_domain = intel_display_port_power_domain(intel_encoder);
389 return intel_display_power_enabled(dev_priv, power_domain) &&
efbc20ab 390 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
ebf33b18
KP		 391}
392
9b984dae
KP		 393static void
394intel_dp_check_edp(struct intel_dp *intel_dp)
395{
30add22d 396 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9b984dae 397 struct drm_i915_private *dev_priv = dev->dev_private;
ebf33b18 398
9b984dae
KP		 399 if (!is_edp(intel_dp))
400 return;
453c5420 401
4be73780 402 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
9b984dae
KP		 403 WARN(1, "eDP powered off while attempting aux channel communication.\n");
404 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
bf13e81b
JN		 405 I915_READ(_pp_stat_reg(intel_dp)),
406 I915_READ(_pp_ctrl_reg(intel_dp)));
9b984dae
KP		 407 }
408}
409
9ee32fea
DV		 410static uint32_t
411intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
412{
413 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
414 struct drm_device *dev = intel_dig_port->base.base.dev;
415 struct drm_i915_private *dev_priv = dev->dev_private;
9ed35ab1 416 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
9ee32fea
DV		 417 uint32_t status;
418 bool done;
419
ef04f00d 420#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
9ee32fea 421 if (has_aux_irq)
b18ac466 422 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
3598706b 423 msecs_to_jiffies_timeout(10));
9ee32fea
DV		 424 else
425 done = wait_for_atomic(C, 10) == 0;
426 if (!done)
427 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
428 has_aux_irq);
429#undef C
430
431 return status;
432}
433
ec5b01dd 434static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
a4fc5ed6 435{
174edf1f
PZ		 436 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
437 struct drm_device *dev = intel_dig_port->base.base.dev;
9ee32fea 438
ec5b01dd
DL		 439 /*
440 * The clock divider is based off the hrawclk, and would like to run at
441 * 2MHz. So, take the hrawclk value and divide by 2 and use that
a4fc5ed6 442 */
ec5b01dd
DL		 443 return index ? 0 : intel_hrawclk(dev) / 2;
444}
445
446static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
447{
448 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
449 struct drm_device *dev = intel_dig_port->base.base.dev;
450
451 if (index)
452 return 0;
453
454 if (intel_dig_port->port == PORT_A) {
455 if (IS_GEN6(dev) || IS_GEN7(dev))
b84a1cf8 456 return 200; /* SNB & IVB eDP input clock at 400Mhz */
e3421a18 457 else
b84a1cf8 458 return 225; /* eDP input clock at 450Mhz */
ec5b01dd
DL		 459 } else {
460 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
461 }
462}
463
464static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
465{
466 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
467 struct drm_device *dev = intel_dig_port->base.base.dev;
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 if (intel_dig_port->port == PORT_A) {
471 if (index)
472 return 0;
473 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
2c55c336
JN		 474 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
475 /* Workaround for non-ULT HSW */
bc86625a
CW		 476 switch (index) {
477 case 0: return 63;
478 case 1: return 72;
479 default: return 0;
480 }
ec5b01dd 481 } else {
bc86625a 482 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
2c55c336 483 }
b84a1cf8
RV		 484}
485
ec5b01dd
DL		 486static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
487{
488 return index ? 0 : 100;
489}
490
5ed12a19
DL		 491static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
492 bool has_aux_irq,
493 int send_bytes,
494 uint32_t aux_clock_divider)
495{
496 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
497 struct drm_device *dev = intel_dig_port->base.base.dev;
498 uint32_t precharge, timeout;
499
500 if (IS_GEN6(dev))
501 precharge = 3;
502 else
503 precharge = 5;
504
505 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
506 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
507 else
508 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
509
510 return DP_AUX_CH_CTL_SEND_BUSY |
788d4433 511 DP_AUX_CH_CTL_DONE |
5ed12a19 512 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
788d4433 513 DP_AUX_CH_CTL_TIME_OUT_ERROR |
5ed12a19 514 timeout |
788d4433 515 DP_AUX_CH_CTL_RECEIVE_ERROR |
5ed12a19
DL		 516 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
517 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
788d4433 518 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
5ed12a19
DL		 519}
520
b84a1cf8
RV		 521static int
522intel_dp_aux_ch(struct intel_dp *intel_dp,
523 uint8_t *send, int send_bytes,
524 uint8_t *recv, int recv_size)
525{
526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
527 struct drm_device *dev = intel_dig_port->base.base.dev;
528 struct drm_i915_private *dev_priv = dev->dev_private;
529 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
530 uint32_t ch_data = ch_ctl + 4;
bc86625a 531 uint32_t aux_clock_divider;
b84a1cf8
RV		 532 int i, ret, recv_bytes;
533 uint32_t status;
5ed12a19 534 int try, clock = 0;
4e6b788c 535 bool has_aux_irq = HAS_AUX_IRQ(dev);
884f19e9
JN		 536 bool vdd;
537
538 vdd = _edp_panel_vdd_on(intel_dp);
b84a1cf8
RV		 539
540 /* dp aux is extremely sensitive to irq latency, hence request the
541 * lowest possible wakeup latency and so prevent the cpu from going into
542 * deep sleep states.
543 */
544 pm_qos_update_request(&dev_priv->pm_qos, 0);
545
546 intel_dp_check_edp(intel_dp);
5eb08b69 547
c67a470b
PZ		 548 intel_aux_display_runtime_get(dev_priv);
549
11bee43e
JB		 550 /* Try to wait for any previous AUX channel activity */
551 for (try = 0; try < 3; try++) {
ef04f00d 552 status = I915_READ_NOTRACE(ch_ctl);
11bee43e
JB		 553 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
554 break;
555 msleep(1);
556 }
557
558 if (try == 3) {
559 WARN(1, "dp_aux_ch not started status 0x%08x\n",
560 I915_READ(ch_ctl));
9ee32fea
DV		 561 ret = -EBUSY;
562 goto out;
4f7f7b7e
CW		 563 }
564
46a5ae9f
PZ		 565 /* Only 5 data registers! */
566 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
567 ret = -E2BIG;
568 goto out;
569 }
570
ec5b01dd 571 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
153b1100
DL		 572 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
573 has_aux_irq,
574 send_bytes,
575 aux_clock_divider);
5ed12a19 576
bc86625a
CW		 577 /* Must try at least 3 times according to DP spec */
578 for (try = 0; try < 5; try++) {
579 /* Load the send data into the aux channel data registers */
580 for (i = 0; i < send_bytes; i += 4)
581 I915_WRITE(ch_data + i,
582 pack_aux(send + i, send_bytes - i));
583
584 /* Send the command and wait for it to complete */
5ed12a19 585 I915_WRITE(ch_ctl, send_ctl);
bc86625a
CW		 586
587 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
588
589 /* Clear done status and any errors */
590 I915_WRITE(ch_ctl,
591 status |
592 DP_AUX_CH_CTL_DONE |
593 DP_AUX_CH_CTL_TIME_OUT_ERROR |
594 DP_AUX_CH_CTL_RECEIVE_ERROR);
595
596 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
597 DP_AUX_CH_CTL_RECEIVE_ERROR))
598 continue;
599 if (status & DP_AUX_CH_CTL_DONE)
600 break;
601 }
4f7f7b7e 602 if (status & DP_AUX_CH_CTL_DONE)
a4fc5ed6
KP		 603 break;
604 }
605
a4fc5ed6 606 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1ae8c0a5 607 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
9ee32fea
DV		 608 ret = -EBUSY;
609 goto out;
a4fc5ed6
KP		 610 }
611
612 /* Check for timeout or receive error.
613 * Timeouts occur when the sink is not connected
614 */
a5b3da54 615 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1ae8c0a5 616 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
9ee32fea
DV		 617 ret = -EIO;
618 goto out;
a5b3da54 619 }
1ae8c0a5
KP		 620
621 /* Timeouts occur when the device isn't connected, so they're
622 * "normal" -- don't fill the kernel log with these */
a5b3da54 623 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
28c97730 624 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
9ee32fea
DV		 625 ret = -ETIMEDOUT;
626 goto out;
a4fc5ed6
KP		 627 }
628
629 /* Unload any bytes sent back from the other side */
630 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
631 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
a4fc5ed6
KP		 632 if (recv_bytes > recv_size)
633 recv_bytes = recv_size;
0206e353 634
4f7f7b7e
CW		 635 for (i = 0; i < recv_bytes; i += 4)
636 unpack_aux(I915_READ(ch_data + i),
637 recv + i, recv_bytes - i);
a4fc5ed6 638
9ee32fea
DV		 639 ret = recv_bytes;
640out:
641 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
c67a470b 642 intel_aux_display_runtime_put(dev_priv);
9ee32fea 643
884f19e9
JN		 644 if (vdd)
645 edp_panel_vdd_off(intel_dp, false);
646
9ee32fea 647 return ret;
a4fc5ed6
KP		 648}
649
a6c8aff0
JN		 650#define BARE_ADDRESS_SIZE 3
651#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
9d1a1031
JN		 652static ssize_t
653intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
a4fc5ed6 654{
9d1a1031
JN		 655 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
656 uint8_t txbuf[20], rxbuf[20];
657 size_t txsize, rxsize;
a4fc5ed6 658 int ret;
a4fc5ed6 659
9d1a1031
JN		 660 txbuf[0] = msg->request << 4;
661 txbuf[1] = msg->address >> 8;
662 txbuf[2] = msg->address & 0xff;
663 txbuf[3] = msg->size - 1;
46a5ae9f 664
9d1a1031
JN		 665 switch (msg->request & ~DP_AUX_I2C_MOT) {
666 case DP_AUX_NATIVE_WRITE:
667 case DP_AUX_I2C_WRITE:
a6c8aff0 668 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
9d1a1031 669 rxsize = 1;
f51a44b9 670
9d1a1031
JN		 671 if (WARN_ON(txsize > 20))
672 return -E2BIG;
a4fc5ed6 673
9d1a1031 674 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
a4fc5ed6 675
9d1a1031
JN		 676 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
677 if (ret > 0) {
678 msg->reply = rxbuf[0] >> 4;
a4fc5ed6 679
9d1a1031
JN		 680 /* Return payload size. */
681 ret = msg->size;
682 }
683 break;
46a5ae9f 684
9d1a1031
JN		 685 case DP_AUX_NATIVE_READ:
686 case DP_AUX_I2C_READ:
a6c8aff0 687 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
9d1a1031 688 rxsize = msg->size + 1;
a4fc5ed6 689
9d1a1031
JN		 690 if (WARN_ON(rxsize > 20))
691 return -E2BIG;
a4fc5ed6 692
9d1a1031
JN		 693 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
694 if (ret > 0) {
695 msg->reply = rxbuf[0] >> 4;
696 /*
697 * Assume happy day, and copy the data. The caller is
698 * expected to check msg->reply before touching it.
699 *
700 * Return payload size.
701 */
702 ret--;
703 memcpy(msg->buffer, rxbuf + 1, ret);
a4fc5ed6 704 }
9d1a1031
JN		 705 break;
706
707 default:
708 ret = -EINVAL;
709 break;
a4fc5ed6 710 }
f51a44b9 711
9d1a1031 712 return ret;
a4fc5ed6
KP		 713}
714
9d1a1031
JN		 715static void
716intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
717{
718 struct drm_device *dev = intel_dp_to_dev(intel_dp);
33ad6626
JN		 719 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
720 enum port port = intel_dig_port->port;
0b99836f 721 const char *name = NULL;
ab2c0672
DA		 722 int ret;
723
33ad6626
JN		 724 switch (port) {
725 case PORT_A:
726 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
0b99836f 727 name = "DPDDC-A";
ab2c0672 728 break;
33ad6626
JN		 729 case PORT_B:
730 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
0b99836f 731 name = "DPDDC-B";
ab2c0672 732 break;
33ad6626
JN		 733 case PORT_C:
734 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
0b99836f 735 name = "DPDDC-C";
ab2c0672 736 break;
33ad6626
JN		 737 case PORT_D:
738 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
0b99836f 739 name = "DPDDC-D";
33ad6626
JN		 740 break;
741 default:
742 BUG();
ab2c0672
DA		 743 }
744
33ad6626
JN		 745 if (!HAS_DDI(dev))
746 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
8316f337 747
0b99836f 748 intel_dp->aux.name = name;
9d1a1031
JN		 749 intel_dp->aux.dev = dev->dev;
750 intel_dp->aux.transfer = intel_dp_aux_transfer;
8316f337 751
0b99836f
JN		 752 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
753 connector->base.kdev->kobj.name);
8316f337 754
4f71d0cb 755 ret = drm_dp_aux_register(&intel_dp->aux);
0b99836f 756 if (ret < 0) {
4f71d0cb 757 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
0b99836f
JN		 758 name, ret);
759 return;
ab2c0672 760 }
8a5e6aeb 761
0b99836f
JN		 762 ret = sysfs_create_link(&connector->base.kdev->kobj,
763 &intel_dp->aux.ddc.dev.kobj,
764 intel_dp->aux.ddc.dev.kobj.name);
765 if (ret < 0) {
766 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
4f71d0cb 767 drm_dp_aux_unregister(&intel_dp->aux);
ab2c0672 768 }
a4fc5ed6
KP		 769}
770
80f65de3
ID		 771static void
772intel_dp_connector_unregister(struct intel_connector *intel_connector)
773{
774 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
775
0e32b39c
DA		 776 if (!intel_connector->mst_port)
777 sysfs_remove_link(&intel_connector->base.kdev->kobj,
778 intel_dp->aux.ddc.dev.kobj.name);
80f65de3
ID		 779 intel_connector_unregister(intel_connector);
780}
781
0e50338c
DV		 782static void
783hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
784{
785 switch (link_bw) {
786 case DP_LINK_BW_1_62:
787 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
788 break;
789 case DP_LINK_BW_2_7:
790 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
791 break;
792 case DP_LINK_BW_5_4:
793 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
794 break;
795 }
796}
797
c6bb3538
DV		 798static void
799intel_dp_set_clock(struct intel_encoder *encoder,
800 struct intel_crtc_config *pipe_config, int link_bw)
801{
802 struct drm_device *dev = encoder->base.dev;
9dd4ffdf
CML		 803 const struct dp_link_dpll *divisor = NULL;
804 int i, count = 0;
c6bb3538
DV		 805
806 if (IS_G4X(dev)) {
9dd4ffdf
CML		 807 divisor = gen4_dpll;
808 count = ARRAY_SIZE(gen4_dpll);
c6bb3538 809 } else if (HAS_PCH_SPLIT(dev)) {
9dd4ffdf
CML		 810 divisor = pch_dpll;
811 count = ARRAY_SIZE(pch_dpll);
ef9348c8
CML		 812 } else if (IS_CHERRYVIEW(dev)) {
813 divisor = chv_dpll;
814 count = ARRAY_SIZE(chv_dpll);
c6bb3538 815 } else if (IS_VALLEYVIEW(dev)) {
65ce4bf5
CML		 816 divisor = vlv_dpll;
817 count = ARRAY_SIZE(vlv_dpll);
c6bb3538 818 }
9dd4ffdf
CML		 819
820 if (divisor && count) {
821 for (i = 0; i < count; i++) {
822 if (link_bw == divisor[i].link_bw) {
823 pipe_config->dpll = divisor[i].dpll;
824 pipe_config->clock_set = true;
825 break;
826 }
827 }
c6bb3538
DV		 828 }
829}
830
00c09d70 831bool
5bfe2ac0
DV		 832intel_dp_compute_config(struct intel_encoder *encoder,
833 struct intel_crtc_config *pipe_config)
a4fc5ed6 834{
5bfe2ac0 835 struct drm_device *dev = encoder->base.dev;
36008365 836 struct drm_i915_private *dev_priv = dev->dev_private;
5bfe2ac0 837 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5bfe2ac0 838 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 839 enum port port = dp_to_dig_port(intel_dp)->port;
2dd24552 840 struct intel_crtc *intel_crtc = encoder->new_crtc;
dd06f90e 841 struct intel_connector *intel_connector = intel_dp->attached_connector;
a4fc5ed6 842 int lane_count, clock;
56071a20 843 int min_lane_count = 1;
eeb6324d 844 int max_lane_count = intel_dp_max_lane_count(intel_dp);
06ea66b6 845 /* Conveniently, the link BW constants become indices with a shift...*/
56071a20 846 int min_clock = 0;
06ea66b6 847 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
083f9560 848 int bpp, mode_rate;
06ea66b6 849 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
ff9a6750 850 int link_avail, link_clock;
a4fc5ed6 851
bc7d38a4 852 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
5bfe2ac0
DV		 853 pipe_config->has_pch_encoder = true;
854
03afc4a2 855 pipe_config->has_dp_encoder = true;
f769cd24 856 pipe_config->has_drrs = false;
9ed109a7 857 pipe_config->has_audio = intel_dp->has_audio;
a4fc5ed6 858
dd06f90e
JN		 859 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
860 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
861 adjusted_mode);
2dd24552
JB		 862 if (!HAS_PCH_SPLIT(dev))
863 intel_gmch_panel_fitting(intel_crtc, pipe_config,
864 intel_connector->panel.fitting_mode);
865 else
b074cec8
JB		 866 intel_pch_panel_fitting(intel_crtc, pipe_config,
867 intel_connector->panel.fitting_mode);
0d3a1bee
ZY		 868 }
869
cb1793ce 870 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
0af78a2b
DV		 871 return false;
872
083f9560
DV		 873 DRM_DEBUG_KMS("DP link computation with max lane count %i "
874 "max bw %02x pixel clock %iKHz\n",
241bfc38
DL		 875 max_lane_count, bws[max_clock],
876 adjusted_mode->crtc_clock);
083f9560 877
36008365
DV		 878 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
879 * bpc in between. */
3e7ca985 880 bpp = pipe_config->pipe_bpp;
56071a20
JN		 881 if (is_edp(intel_dp)) {
882 if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
883 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
884 dev_priv->vbt.edp_bpp);
885 bpp = dev_priv->vbt.edp_bpp;
886 }
887
f4cdbc21
JN		 888 if (IS_BROADWELL(dev)) {
889 /* Yes, it's an ugly hack. */
890 min_lane_count = max_lane_count;
891 DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
892 min_lane_count);
893 } else if (dev_priv->vbt.edp_lanes) {
56071a20
JN		 894 min_lane_count = min(dev_priv->vbt.edp_lanes,
895 max_lane_count);
896 DRM_DEBUG_KMS("using min %u lanes per VBT\n",
897 min_lane_count);
898 }
899
900 if (dev_priv->vbt.edp_rate) {
901 min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
902 DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
903 bws[min_clock]);
904 }
7984211e 905 }
657445fe 906
36008365 907 for (; bpp >= 6*3; bpp -= 2*3) {
241bfc38
DL		 908 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
909 bpp);
36008365 910
c6930992
DA		 911 for (clock = min_clock; clock <= max_clock; clock++) {
912 for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
36008365
DV		 913 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
914 link_avail = intel_dp_max_data_rate(link_clock,
915 lane_count);
916
917 if (mode_rate <= link_avail) {
918 goto found;
919 }
920 }
921 }
922 }
c4867936 923
36008365 924 return false;
3685a8f3 925
36008365 926found:
55bc60db
VS		 927 if (intel_dp->color_range_auto) {
928 /*
929 * See:
930 * CEA-861-E - 5.1 Default Encoding Parameters
931 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
932 */
18316c8c 933 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
55bc60db
VS		 934 intel_dp->color_range = DP_COLOR_RANGE_16_235;
935 else
936 intel_dp->color_range = 0;
937 }
938
3685a8f3 939 if (intel_dp->color_range)
50f3b016 940 pipe_config->limited_color_range = true;
a4fc5ed6 941
36008365
DV		 942 intel_dp->link_bw = bws[clock];
943 intel_dp->lane_count = lane_count;
657445fe 944 pipe_config->pipe_bpp = bpp;
ff9a6750 945 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
a4fc5ed6 946
36008365
DV		 947 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
948 intel_dp->link_bw, intel_dp->lane_count,
ff9a6750 949 pipe_config->port_clock, bpp);
36008365
DV		 950 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
951 mode_rate, link_avail);
a4fc5ed6 952
03afc4a2 953 intel_link_compute_m_n(bpp, lane_count,
241bfc38
DL		 954 adjusted_mode->crtc_clock,
955 pipe_config->port_clock,
03afc4a2 956 &pipe_config->dp_m_n);
9d1a455b 957
439d7ac0
PB		 958 if (intel_connector->panel.downclock_mode != NULL &&
959 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
f769cd24 960 pipe_config->has_drrs = true;
439d7ac0
PB		 961 intel_link_compute_m_n(bpp, lane_count,
962 intel_connector->panel.downclock_mode->clock,
963 pipe_config->port_clock,
964 &pipe_config->dp_m2_n2);
965 }
966
ea155f32 967 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
0e50338c
DV		 968 hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
969 else
970 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
c6bb3538 971
03afc4a2 972 return true;
a4fc5ed6
KP		 973}
974
7c62a164 975static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
ea9b6006 976{
7c62a164
DV		 977 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
978 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
979 struct drm_device *dev = crtc->base.dev;
ea9b6006
DV		 980 struct drm_i915_private *dev_priv = dev->dev_private;
981 u32 dpa_ctl;
982
ff9a6750 983 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
ea9b6006
DV		 984 dpa_ctl = I915_READ(DP_A);
985 dpa_ctl &= ~DP_PLL_FREQ_MASK;
986
ff9a6750 987 if (crtc->config.port_clock == 162000) {
1ce17038
DV		 988 /* For a long time we've carried around a ILK-DevA w/a for the
989 * 160MHz clock. If we're really unlucky, it's still required.
990 */
991 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
ea9b6006 992 dpa_ctl |= DP_PLL_FREQ_160MHZ;
7c62a164 993 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
ea9b6006
DV		 994 } else {
995 dpa_ctl |= DP_PLL_FREQ_270MHZ;
7c62a164 996 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
ea9b6006 997 }
1ce17038 998
ea9b6006
DV		 999 I915_WRITE(DP_A, dpa_ctl);
1000
1001 POSTING_READ(DP_A);
1002 udelay(500);
1003}
1004
8ac33ed3 1005static void intel_dp_prepare(struct intel_encoder *encoder)
a4fc5ed6 1006{
b934223d 1007 struct drm_device *dev = encoder->base.dev;
417e822d 1008 struct drm_i915_private *dev_priv = dev->dev_private;
b934223d 1009 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1010 enum port port = dp_to_dig_port(intel_dp)->port;
b934223d
DV		 1011 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1012 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
a4fc5ed6 1013
417e822d 1014 /*
1a2eb460 1015 * There are four kinds of DP registers:
417e822d
KP		 1016 *
1017 * IBX PCH
1a2eb460
KP		 1018 * SNB CPU
1019 * IVB CPU
417e822d
KP		 1020 * CPT PCH
1021 *
1022 * IBX PCH and CPU are the same for almost everything,
1023 * except that the CPU DP PLL is configured in this
1024 * register
1025 *
1026 * CPT PCH is quite different, having many bits moved
1027 * to the TRANS_DP_CTL register instead. That
1028 * configuration happens (oddly) in ironlake_pch_enable
1029 */
9c9e7927 1030
417e822d
KP		 1031 /* Preserve the BIOS-computed detected bit. This is
1032 * supposed to be read-only.
1033 */
1034 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
a4fc5ed6 1035
417e822d 1036 /* Handle DP bits in common between all three register formats */
417e822d 1037 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
17aa6be9 1038 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
a4fc5ed6 1039
9ed109a7 1040 if (crtc->config.has_audio) {
e0dac65e 1041 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
7c62a164 1042 pipe_name(crtc->pipe));
ea5b213a 1043 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
b934223d 1044 intel_write_eld(&encoder->base, adjusted_mode);
e0dac65e 1045 }
247d89f6 1046
417e822d 1047 /* Split out the IBX/CPU vs CPT settings */
32f9d658 1048
bc7d38a4 1049 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1a2eb460
KP		 1050 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1051 intel_dp->DP |= DP_SYNC_HS_HIGH;
1052 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1053 intel_dp->DP |= DP_SYNC_VS_HIGH;
1054 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1055
6aba5b6c 1056 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1a2eb460
KP		 1057 intel_dp->DP |= DP_ENHANCED_FRAMING;
1058
7c62a164 1059 intel_dp->DP |= crtc->pipe << 29;
bc7d38a4 1060 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
b2634017 1061 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
3685a8f3 1062 intel_dp->DP |= intel_dp->color_range;
417e822d
KP		 1063
1064 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1065 intel_dp->DP |= DP_SYNC_HS_HIGH;
1066 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1067 intel_dp->DP |= DP_SYNC_VS_HIGH;
1068 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1069
6aba5b6c 1070 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
417e822d
KP		 1071 intel_dp->DP |= DP_ENHANCED_FRAMING;
1072
44f37d1f
CML		 1073 if (!IS_CHERRYVIEW(dev)) {
1074 if (crtc->pipe == 1)
1075 intel_dp->DP |= DP_PIPEB_SELECT;
1076 } else {
1077 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1078 }
417e822d
KP		 1079 } else {
1080 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
32f9d658 1081 }
a4fc5ed6
KP		 1082}
1083
ffd6749d
PZ		 1084#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1085#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
99ea7127 1086
1a5ef5b7
PZ		 1087#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1088#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
99ea7127 1089
ffd6749d
PZ		 1090#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1091#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
99ea7127 1092
4be73780 1093static void wait_panel_status(struct intel_dp *intel_dp,
99ea7127
KP		 1094 u32 mask,
1095 u32 value)
bd943159 1096{
30add22d 1097 struct drm_device *dev = intel_dp_to_dev(intel_dp);
99ea7127 1098 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 1099 u32 pp_stat_reg, pp_ctrl_reg;
1100
bf13e81b
JN		 1101 pp_stat_reg = _pp_stat_reg(intel_dp);
1102 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
32ce697c 1103
99ea7127 1104 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
453c5420
JB		 1105 mask, value,
1106 I915_READ(pp_stat_reg),
1107 I915_READ(pp_ctrl_reg));
32ce697c 1108
453c5420 1109 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
99ea7127 1110 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
453c5420
JB		 1111 I915_READ(pp_stat_reg),
1112 I915_READ(pp_ctrl_reg));
32ce697c 1113 }
54c136d4
CW		 1114
1115 DRM_DEBUG_KMS("Wait complete\n");
99ea7127 1116}
32ce697c 1117
4be73780 1118static void wait_panel_on(struct intel_dp *intel_dp)
99ea7127
KP		 1119{
1120 DRM_DEBUG_KMS("Wait for panel power on\n");
4be73780 1121 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
bd943159
KP		 1122}
1123
4be73780 1124static void wait_panel_off(struct intel_dp *intel_dp)
99ea7127
KP		 1125{
1126 DRM_DEBUG_KMS("Wait for panel power off time\n");
4be73780 1127 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
99ea7127
KP		 1128}
1129
4be73780 1130static void wait_panel_power_cycle(struct intel_dp *intel_dp)
99ea7127
KP		 1131{
1132 DRM_DEBUG_KMS("Wait for panel power cycle\n");
dce56b3c
PZ		 1133
1134 /* When we disable the VDD override bit last we have to do the manual
1135 * wait. */
1136 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1137 intel_dp->panel_power_cycle_delay);
1138
4be73780 1139 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
99ea7127
KP		 1140}
1141
4be73780 1142static void wait_backlight_on(struct intel_dp *intel_dp)
dce56b3c
PZ		 1143{
1144 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1145 intel_dp->backlight_on_delay);
1146}
1147
4be73780 1148static void edp_wait_backlight_off(struct intel_dp *intel_dp)
dce56b3c
PZ		 1149{
1150 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1151 intel_dp->backlight_off_delay);
1152}
99ea7127 1153
832dd3c1
KP		 1154/* Read the current pp_control value, unlocking the register if it
1155 * is locked
1156 */
1157
453c5420 1158static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
832dd3c1 1159{
453c5420
JB		 1160 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1161 struct drm_i915_private *dev_priv = dev->dev_private;
1162 u32 control;
832dd3c1 1163
bf13e81b 1164 control = I915_READ(_pp_ctrl_reg(intel_dp));
832dd3c1
KP		 1165 control &= ~PANEL_UNLOCK_MASK;
1166 control |= PANEL_UNLOCK_REGS;
1167 return control;
bd943159
KP		 1168}
1169
adddaaf4 1170static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
5d613501 1171{
30add22d 1172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
4e6e1a54
ID		 1173 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1174 struct intel_encoder *intel_encoder = &intel_dig_port->base;
5d613501 1175 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1176 enum intel_display_power_domain power_domain;
5d613501 1177 u32 pp;
453c5420 1178 u32 pp_stat_reg, pp_ctrl_reg;
adddaaf4 1179 bool need_to_disable = !intel_dp->want_panel_vdd;
5d613501 1180
97af61f5 1181 if (!is_edp(intel_dp))
adddaaf4 1182 return false;
bd943159
KP		 1183
1184 intel_dp->want_panel_vdd = true;
99ea7127 1185
4be73780 1186 if (edp_have_panel_vdd(intel_dp))
adddaaf4 1187 return need_to_disable;
b0665d57 1188
4e6e1a54
ID		 1189 power_domain = intel_display_port_power_domain(intel_encoder);
1190 intel_display_power_get(dev_priv, power_domain);
e9cb81a2 1191
b0665d57 1192 DRM_DEBUG_KMS("Turning eDP VDD on\n");
bd943159 1193
4be73780
DV		 1194 if (!edp_have_panel_power(intel_dp))
1195 wait_panel_power_cycle(intel_dp);
99ea7127 1196
453c5420 1197 pp = ironlake_get_pp_control(intel_dp);
5d613501 1198 pp |= EDP_FORCE_VDD;
ebf33b18 1199
bf13e81b
JN		 1200 pp_stat_reg = _pp_stat_reg(intel_dp);
1201 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1202
1203 I915_WRITE(pp_ctrl_reg, pp);
1204 POSTING_READ(pp_ctrl_reg);
1205 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1206 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
ebf33b18
KP		 1207 /*
1208 * If the panel wasn't on, delay before accessing aux channel
1209 */
4be73780 1210 if (!edp_have_panel_power(intel_dp)) {
bd943159 1211 DRM_DEBUG_KMS("eDP was not running\n");
f01eca2e 1212 msleep(intel_dp->panel_power_up_delay);
f01eca2e 1213 }
adddaaf4
JN		 1214
1215 return need_to_disable;
1216}
1217
b80d6c78 1218void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
adddaaf4
JN		 1219{
1220 if (is_edp(intel_dp)) {
1221 bool vdd = _edp_panel_vdd_on(intel_dp);
1222
1223 WARN(!vdd, "eDP VDD already requested on\n");
1224 }
5d613501
JB		 1225}
1226
4be73780 1227static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
5d613501 1228{
30add22d 1229 struct drm_device *dev = intel_dp_to_dev(intel_dp);
5d613501
JB		 1230 struct drm_i915_private *dev_priv = dev->dev_private;
1231 u32 pp;
453c5420 1232 u32 pp_stat_reg, pp_ctrl_reg;
5d613501 1233
51fd371b 1234 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
a0e99e68 1235
4be73780 1236 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
4e6e1a54
ID		 1237 struct intel_digital_port *intel_dig_port =
1238 dp_to_dig_port(intel_dp);
1239 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1240 enum intel_display_power_domain power_domain;
1241
b0665d57
PZ		 1242 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1243
453c5420 1244 pp = ironlake_get_pp_control(intel_dp);
bd943159 1245 pp &= ~EDP_FORCE_VDD;
bd943159 1246
9f08ef59
PZ		 1247 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1248 pp_stat_reg = _pp_stat_reg(intel_dp);
453c5420
JB		 1249
1250 I915_WRITE(pp_ctrl_reg, pp);
1251 POSTING_READ(pp_ctrl_reg);
99ea7127 1252
453c5420
JB		 1253 /* Make sure sequencer is idle before allowing subsequent activity */
1254 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1255 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
90791a5c
PZ		 1256
1257 if ((pp & POWER_TARGET_ON) == 0)
dce56b3c 1258 intel_dp->last_power_cycle = jiffies;
e9cb81a2 1259
4e6e1a54
ID		 1260 power_domain = intel_display_port_power_domain(intel_encoder);
1261 intel_display_power_put(dev_priv, power_domain);
bd943159
KP		 1262 }
1263}
5d613501 1264
4be73780 1265static void edp_panel_vdd_work(struct work_struct *__work)
bd943159
KP		 1266{
1267 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1268 struct intel_dp, panel_vdd_work);
30add22d 1269 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bd943159 1270
51fd371b 1271 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 1272 edp_panel_vdd_off_sync(intel_dp);
51fd371b 1273 drm_modeset_unlock(&dev->mode_config.connection_mutex);
bd943159
KP		 1274}
1275
aba86890
ID		 1276static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1277{
1278 unsigned long delay;
1279
1280 /*
1281 * Queue the timer to fire a long time from now (relative to the power
1282 * down delay) to keep the panel power up across a sequence of
1283 * operations.
1284 */
1285 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1286 schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
1287}
1288
4be73780 1289static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
bd943159 1290{
97af61f5
KP		 1291 if (!is_edp(intel_dp))
1292 return;
5d613501 1293
bd943159 1294 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
f2e8b18a 1295
bd943159
KP		 1296 intel_dp->want_panel_vdd = false;
1297
aba86890 1298 if (sync)
4be73780 1299 edp_panel_vdd_off_sync(intel_dp);
aba86890
ID		 1300 else
1301 edp_panel_vdd_schedule_off(intel_dp);
5d613501
JB		 1302}
1303
4be73780 1304void intel_edp_panel_on(struct intel_dp *intel_dp)
9934c132 1305{
30add22d 1306 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1307 struct drm_i915_private *dev_priv = dev->dev_private;
99ea7127 1308 u32 pp;
453c5420 1309 u32 pp_ctrl_reg;
9934c132 1310
97af61f5 1311 if (!is_edp(intel_dp))
bd943159 1312 return;
99ea7127
KP		 1313
1314 DRM_DEBUG_KMS("Turn eDP power on\n");
1315
4be73780 1316 if (edp_have_panel_power(intel_dp)) {
99ea7127 1317 DRM_DEBUG_KMS("eDP power already on\n");
7d639f35 1318 return;
99ea7127 1319 }
9934c132 1320
4be73780 1321 wait_panel_power_cycle(intel_dp);
37c6c9b0 1322
bf13e81b 1323 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1324 pp = ironlake_get_pp_control(intel_dp);
05ce1a49
KP		 1325 if (IS_GEN5(dev)) {
1326 /* ILK workaround: disable reset around power sequence */
1327 pp &= ~PANEL_POWER_RESET;
bf13e81b
JN		 1328 I915_WRITE(pp_ctrl_reg, pp);
1329 POSTING_READ(pp_ctrl_reg);
05ce1a49 1330 }
37c6c9b0 1331
1c0ae80a 1332 pp |= POWER_TARGET_ON;
99ea7127
KP		 1333 if (!IS_GEN5(dev))
1334 pp |= PANEL_POWER_RESET;
1335
453c5420
JB		 1336 I915_WRITE(pp_ctrl_reg, pp);
1337 POSTING_READ(pp_ctrl_reg);
9934c132 1338
4be73780 1339 wait_panel_on(intel_dp);
dce56b3c 1340 intel_dp->last_power_on = jiffies;
9934c132 1341
05ce1a49
KP		 1342 if (IS_GEN5(dev)) {
1343 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
bf13e81b
JN		 1344 I915_WRITE(pp_ctrl_reg, pp);
1345 POSTING_READ(pp_ctrl_reg);
05ce1a49 1346 }
9934c132
JB		 1347}
1348
4be73780 1349void intel_edp_panel_off(struct intel_dp *intel_dp)
9934c132 1350{
4e6e1a54
ID		 1351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
30add22d 1353 struct drm_device *dev = intel_dp_to_dev(intel_dp);
9934c132 1354 struct drm_i915_private *dev_priv = dev->dev_private;
4e6e1a54 1355 enum intel_display_power_domain power_domain;
99ea7127 1356 u32 pp;
453c5420 1357 u32 pp_ctrl_reg;
9934c132 1358
97af61f5
KP		 1359 if (!is_edp(intel_dp))
1360 return;
37c6c9b0 1361
99ea7127 1362 DRM_DEBUG_KMS("Turn eDP power off\n");
37c6c9b0 1363
24f3e092
JN		 1364 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1365
453c5420 1366 pp = ironlake_get_pp_control(intel_dp);
35a38556
DV		 1367 /* We need to switch off panel power _and_ force vdd, for otherwise some
1368 * panels get very unhappy and cease to work. */
b3064154
PJ		 1369 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1370 EDP_BLC_ENABLE);
453c5420 1371
bf13e81b 1372 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420 1373
849e39f5
PZ		 1374 intel_dp->want_panel_vdd = false;
1375
453c5420
JB		 1376 I915_WRITE(pp_ctrl_reg, pp);
1377 POSTING_READ(pp_ctrl_reg);
9934c132 1378
dce56b3c 1379 intel_dp->last_power_cycle = jiffies;
4be73780 1380 wait_panel_off(intel_dp);
849e39f5
PZ		 1381
1382 /* We got a reference when we enabled the VDD. */
4e6e1a54
ID		 1383 power_domain = intel_display_port_power_domain(intel_encoder);
1384 intel_display_power_put(dev_priv, power_domain);
9934c132
JB		 1385}
1386
1250d107
JN		 1387/* Enable backlight in the panel power control. */
1388static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
32f9d658 1389{
da63a9f2
PZ		 1390 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1391 struct drm_device *dev = intel_dig_port->base.base.dev;
32f9d658
ZW		 1392 struct drm_i915_private *dev_priv = dev->dev_private;
1393 u32 pp;
453c5420 1394 u32 pp_ctrl_reg;
32f9d658 1395
01cb9ea6
JB		 1396 /*
1397 * If we enable the backlight right away following a panel power
1398 * on, we may see slight flicker as the panel syncs with the eDP
1399 * link. So delay a bit to make sure the image is solid before
1400 * allowing it to appear.
1401 */
4be73780 1402 wait_backlight_on(intel_dp);
453c5420 1403 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1404 pp |= EDP_BLC_ENABLE;
453c5420 1405
bf13e81b 1406 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1407
1408 I915_WRITE(pp_ctrl_reg, pp);
1409 POSTING_READ(pp_ctrl_reg);
32f9d658
ZW		 1410}
1411
1250d107
JN		 1412/* Enable backlight PWM and backlight PP control. */
1413void intel_edp_backlight_on(struct intel_dp *intel_dp)
1414{
1415 if (!is_edp(intel_dp))
1416 return;
1417
1418 DRM_DEBUG_KMS("\n");
1419
1420 intel_panel_enable_backlight(intel_dp->attached_connector);
1421 _intel_edp_backlight_on(intel_dp);
1422}
1423
1424/* Disable backlight in the panel power control. */
1425static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
32f9d658 1426{
30add22d 1427 struct drm_device *dev = intel_dp_to_dev(intel_dp);
32f9d658
ZW		 1428 struct drm_i915_private *dev_priv = dev->dev_private;
1429 u32 pp;
453c5420 1430 u32 pp_ctrl_reg;
32f9d658 1431
453c5420 1432 pp = ironlake_get_pp_control(intel_dp);
32f9d658 1433 pp &= ~EDP_BLC_ENABLE;
453c5420 1434
bf13e81b 1435 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
453c5420
JB		 1436
1437 I915_WRITE(pp_ctrl_reg, pp);
1438 POSTING_READ(pp_ctrl_reg);
dce56b3c 1439 intel_dp->last_backlight_off = jiffies;
f7d2323c
JB		 1440
1441 edp_wait_backlight_off(intel_dp);
1250d107
JN		 1442}
1443
1444/* Disable backlight PP control and backlight PWM. */
1445void intel_edp_backlight_off(struct intel_dp *intel_dp)
1446{
1447 if (!is_edp(intel_dp))
1448 return;
1449
1450 DRM_DEBUG_KMS("\n");
f7d2323c 1451
1250d107 1452 _intel_edp_backlight_off(intel_dp);
f7d2323c 1453 intel_panel_disable_backlight(intel_dp->attached_connector);
32f9d658 1454}
a4fc5ed6 1455
2bd2ad64 1456static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
d240f20f 1457{
da63a9f2
PZ		 1458 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1459 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1460 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1461 struct drm_i915_private *dev_priv = dev->dev_private;
1462 u32 dpa_ctl;
1463
2bd2ad64
DV		 1464 assert_pipe_disabled(dev_priv,
1465 to_intel_crtc(crtc)->pipe);
1466
d240f20f
JB		 1467 DRM_DEBUG_KMS("\n");
1468 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1469 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1470 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1471
1472 /* We don't adjust intel_dp->DP while tearing down the link, to
1473 * facilitate link retraining (e.g. after hotplug). Hence clear all
1474 * enable bits here to ensure that we don't enable too much. */
1475 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1476 intel_dp->DP |= DP_PLL_ENABLE;
1477 I915_WRITE(DP_A, intel_dp->DP);
298b0b39
JB		 1478 POSTING_READ(DP_A);
1479 udelay(200);
d240f20f
JB		 1480}
1481
2bd2ad64 1482static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
d240f20f 1483{
da63a9f2
PZ		 1484 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1485 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1486 struct drm_device *dev = crtc->dev;
d240f20f
JB		 1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 u32 dpa_ctl;
1489
2bd2ad64
DV		 1490 assert_pipe_disabled(dev_priv,
1491 to_intel_crtc(crtc)->pipe);
1492
d240f20f 1493 dpa_ctl = I915_READ(DP_A);
0767935e
DV		 1494 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1495 "dp pll off, should be on\n");
1496 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1497
1498 /* We can't rely on the value tracked for the DP register in
1499 * intel_dp->DP because link_down must not change that (otherwise link
1500 * re-training will fail. */
298b0b39 1501 dpa_ctl &= ~DP_PLL_ENABLE;
d240f20f 1502 I915_WRITE(DP_A, dpa_ctl);
1af5fa1b 1503 POSTING_READ(DP_A);
d240f20f
JB		 1504 udelay(200);
1505}
1506
c7ad3810 1507/* If the sink supports it, try to set the power state appropriately */
c19b0669 1508void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
c7ad3810
JB		 1509{
1510 int ret, i;
1511
1512 /* Should have a valid DPCD by this point */
1513 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1514 return;
1515
1516 if (mode != DRM_MODE_DPMS_ON) {
9d1a1031
JN		 1517 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1518 DP_SET_POWER_D3);
c7ad3810
JB		 1519 if (ret != 1)
1520 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1521 } else {
1522 /*
1523 * When turning on, we need to retry for 1ms to give the sink
1524 * time to wake up.
1525 */
1526 for (i = 0; i < 3; i++) {
9d1a1031
JN		 1527 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1528 DP_SET_POWER_D0);
c7ad3810
JB		 1529 if (ret == 1)
1530 break;
1531 msleep(1);
1532 }
1533 }
1534}
1535
19d8fe15
DV		 1536static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1537 enum pipe *pipe)
d240f20f 1538{
19d8fe15 1539 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 1540 enum port port = dp_to_dig_port(intel_dp)->port;
19d8fe15
DV		 1541 struct drm_device *dev = encoder->base.dev;
1542 struct drm_i915_private *dev_priv = dev->dev_private;
6d129bea
ID		 1543 enum intel_display_power_domain power_domain;
1544 u32 tmp;
1545
1546 power_domain = intel_display_port_power_domain(encoder);
1547 if (!intel_display_power_enabled(dev_priv, power_domain))
1548 return false;
1549
1550 tmp = I915_READ(intel_dp->output_reg);
19d8fe15
DV		 1551
1552 if (!(tmp & DP_PORT_EN))
1553 return false;
1554
bc7d38a4 1555 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
19d8fe15 1556 *pipe = PORT_TO_PIPE_CPT(tmp);
71485e0a
VS		 1557 } else if (IS_CHERRYVIEW(dev)) {
1558 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
bc7d38a4 1559 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
19d8fe15
DV		 1560 *pipe = PORT_TO_PIPE(tmp);
1561 } else {
1562 u32 trans_sel;
1563 u32 trans_dp;
1564 int i;
1565
1566 switch (intel_dp->output_reg) {
1567 case PCH_DP_B:
1568 trans_sel = TRANS_DP_PORT_SEL_B;
1569 break;
1570 case PCH_DP_C:
1571 trans_sel = TRANS_DP_PORT_SEL_C;
1572 break;
1573 case PCH_DP_D:
1574 trans_sel = TRANS_DP_PORT_SEL_D;
1575 break;
1576 default:
1577 return true;
1578 }
1579
1580 for_each_pipe(i) {
1581 trans_dp = I915_READ(TRANS_DP_CTL(i));
1582 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1583 *pipe = i;
1584 return true;
1585 }
1586 }
19d8fe15 1587
4a0833ec
DV		 1588 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1589 intel_dp->output_reg);
1590 }
d240f20f 1591
19d8fe15
DV		 1592 return true;
1593}
d240f20f 1594
045ac3b5
JB		 1595static void intel_dp_get_config(struct intel_encoder *encoder,
1596 struct intel_crtc_config *pipe_config)
1597{
1598 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
045ac3b5 1599 u32 tmp, flags = 0;
63000ef6
XZ		 1600 struct drm_device *dev = encoder->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 enum port port = dp_to_dig_port(intel_dp)->port;
1603 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
18442d08 1604 int dotclock;
045ac3b5 1605
9ed109a7
DV		 1606 tmp = I915_READ(intel_dp->output_reg);
1607 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1608 pipe_config->has_audio = true;
1609
63000ef6 1610 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
63000ef6
XZ		 1611 if (tmp & DP_SYNC_HS_HIGH)
1612 flags |= DRM_MODE_FLAG_PHSYNC;
1613 else
1614 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1615
63000ef6
XZ		 1616 if (tmp & DP_SYNC_VS_HIGH)
1617 flags |= DRM_MODE_FLAG_PVSYNC;
1618 else
1619 flags |= DRM_MODE_FLAG_NVSYNC;
1620 } else {
1621 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1622 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1623 flags |= DRM_MODE_FLAG_PHSYNC;
1624 else
1625 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1626
63000ef6
XZ		 1627 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1628 flags |= DRM_MODE_FLAG_PVSYNC;
1629 else
1630 flags |= DRM_MODE_FLAG_NVSYNC;
1631 }
045ac3b5
JB		 1632
1633 pipe_config->adjusted_mode.flags |= flags;
f1f644dc 1634
eb14cb74
VS		 1635 pipe_config->has_dp_encoder = true;
1636
1637 intel_dp_get_m_n(crtc, pipe_config);
1638
18442d08 1639 if (port == PORT_A) {
f1f644dc
JB		 1640 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1641 pipe_config->port_clock = 162000;
1642 else
1643 pipe_config->port_clock = 270000;
1644 }
18442d08
VS		 1645
1646 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1647 &pipe_config->dp_m_n);
1648
1649 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1650 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1651
241bfc38 1652 pipe_config->adjusted_mode.crtc_clock = dotclock;
7f16e5c1 1653
c6cd2ee2
JN		 1654 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1655 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1656 /*
1657 * This is a big fat ugly hack.
1658 *
1659 * Some machines in UEFI boot mode provide us a VBT that has 18
1660 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1661 * unknown we fail to light up. Yet the same BIOS boots up with
1662 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1663 * max, not what it tells us to use.
1664 *
1665 * Note: This will still be broken if the eDP panel is not lit
1666 * up by the BIOS, and thus we can't get the mode at module
1667 * load.
1668 */
1669 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1670 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1671 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1672 }
045ac3b5
JB		 1673}
1674
34eb7579 1675static bool is_edp_psr(struct intel_dp *intel_dp)
2293bb5c 1676{
34eb7579 1677 return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2293bb5c
SK		 1678}
1679
2b28bb1b
RV		 1680static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1681{
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683
18b5992c 1684 if (!HAS_PSR(dev))
2b28bb1b
RV		 1685 return false;
1686
18b5992c 1687 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2b28bb1b
RV		 1688}
1689
1690static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1691 struct edp_vsc_psr *vsc_psr)
1692{
1693 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1694 struct drm_device *dev = dig_port->base.base.dev;
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1697 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1698 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1699 uint32_t *data = (uint32_t *) vsc_psr;
1700 unsigned int i;
1701
1702 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1703 the video DIP being updated before program video DIP data buffer
1704 registers for DIP being updated. */
1705 I915_WRITE(ctl_reg, 0);
1706 POSTING_READ(ctl_reg);
1707
1708 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1709 if (i < sizeof(struct edp_vsc_psr))
1710 I915_WRITE(data_reg + i, *data++);
1711 else
1712 I915_WRITE(data_reg + i, 0);
1713 }
1714
1715 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1716 POSTING_READ(ctl_reg);
1717}
1718
1719static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1720{
1721 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1722 struct drm_i915_private *dev_priv = dev->dev_private;
1723 struct edp_vsc_psr psr_vsc;
1724
2b28bb1b
RV		 1725 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1726 memset(&psr_vsc, 0, sizeof(psr_vsc));
1727 psr_vsc.sdp_header.HB0 = 0;
1728 psr_vsc.sdp_header.HB1 = 0x7;
1729 psr_vsc.sdp_header.HB2 = 0x2;
1730 psr_vsc.sdp_header.HB3 = 0x8;
1731 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1732
1733 /* Avoid continuous PSR exit by masking memup and hpd */
18b5992c 1734 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
0cc4b699 1735 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2b28bb1b
RV		 1736}
1737
1738static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1739{
0e0ae652
RV		 1740 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1741 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b 1742 struct drm_i915_private *dev_priv = dev->dev_private;
ec5b01dd 1743 uint32_t aux_clock_divider;
2b28bb1b
RV		 1744 int precharge = 0x3;
1745 int msg_size = 5; /* Header(4) + Message(1) */
0e0ae652 1746 bool only_standby = false;
2b28bb1b 1747
ec5b01dd
DL		 1748 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1749
0e0ae652
RV		 1750 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1751 only_standby = true;
1752
2b28bb1b 1753 /* Enable PSR in sink */
0e0ae652 1754 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
9d1a1031
JN		 1755 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1756 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b 1757 else
9d1a1031
JN		 1758 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1759 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
2b28bb1b
RV		 1760
1761 /* Setup AUX registers */
18b5992c
BW		 1762 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1763 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1764 I915_WRITE(EDP_PSR_AUX_CTL(dev),
2b28bb1b
RV		 1765 DP_AUX_CH_CTL_TIME_OUT_400us |
1766 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1767 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1768 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1769}
1770
1771static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1772{
0e0ae652
RV		 1773 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1774 struct drm_device *dev = dig_port->base.base.dev;
2b28bb1b
RV		 1775 struct drm_i915_private *dev_priv = dev->dev_private;
1776 uint32_t max_sleep_time = 0x1f;
1777 uint32_t idle_frames = 1;
1778 uint32_t val = 0x0;
ed8546ac 1779 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
0e0ae652
RV		 1780 bool only_standby = false;
1781
1782 if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
1783 only_standby = true;
2b28bb1b 1784
0e0ae652 1785 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
2b28bb1b
RV		 1786 val |= EDP_PSR_LINK_STANDBY;
1787 val |= EDP_PSR_TP2_TP3_TIME_0us;
1788 val |= EDP_PSR_TP1_TIME_0us;
1789 val |= EDP_PSR_SKIP_AUX_EXIT;
82c56254 1790 val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
2b28bb1b
RV		 1791 } else
1792 val |= EDP_PSR_LINK_DISABLE;
1793
18b5992c 1794 I915_WRITE(EDP_PSR_CTL(dev), val |
24bd9bf5 1795 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
2b28bb1b
RV		 1796 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1797 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1798 EDP_PSR_ENABLE);
1799}
1800
3f51e471
RV		 1801static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1802{
1803 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1804 struct drm_device *dev = dig_port->base.base.dev;
1805 struct drm_i915_private *dev_priv = dev->dev_private;
1806 struct drm_crtc *crtc = dig_port->base.base.crtc;
1807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3f51e471 1808
f0355c4a 1809 lockdep_assert_held(&dev_priv->psr.lock);
f0355c4a
DV		 1810 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1811 WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
1812
a031d709
RV		 1813 dev_priv->psr.source_ok = false;
1814
9ca15301 1815 if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
3f51e471 1816 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
3f51e471
RV		 1817 return false;
1818 }
1819
d330a953 1820 if (!i915.enable_psr) {
105b7c11 1821 DRM_DEBUG_KMS("PSR disable by flag\n");
105b7c11
RV		 1822 return false;
1823 }
1824
4c8c7000
RV		 1825 /* Below limitations aren't valid for Broadwell */
1826 if (IS_BROADWELL(dev))
1827 goto out;
1828
3f51e471
RV		 1829 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1830 S3D_ENABLE) {
1831 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
3f51e471
RV		 1832 return false;
1833 }
1834
ca73b4f0 1835 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
3f51e471 1836 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
3f51e471
RV		 1837 return false;
1838 }
1839
4c8c7000 1840 out:
a031d709 1841 dev_priv->psr.source_ok = true;
3f51e471
RV		 1842 return true;
1843}
1844
3d739d92 1845static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
2b28bb1b 1846{
7c8f8a70
RV		 1847 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1848 struct drm_device *dev = intel_dig_port->base.base.dev;
1849 struct drm_i915_private *dev_priv = dev->dev_private;
2b28bb1b 1850
3638379c
DV		 1851 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1852 WARN_ON(dev_priv->psr.active);
f0355c4a 1853 lockdep_assert_held(&dev_priv->psr.lock);
2b28bb1b 1854
2b28bb1b
RV		 1855 /* Enable PSR on the panel */
1856 intel_edp_psr_enable_sink(intel_dp);
1857
1858 /* Enable PSR on the host */
1859 intel_edp_psr_enable_source(intel_dp);
7c8f8a70 1860
7c8f8a70 1861 dev_priv->psr.active = true;
2b28bb1b
RV		 1862}
1863
3d739d92
RV		 1864void intel_edp_psr_enable(struct intel_dp *intel_dp)
1865{
1866 struct drm_device *dev = intel_dp_to_dev(intel_dp);
109fc2ad 1867 struct drm_i915_private *dev_priv = dev->dev_private;
3d739d92 1868
4704c573
RV		 1869 if (!HAS_PSR(dev)) {
1870 DRM_DEBUG_KMS("PSR not supported on this platform\n");
1871 return;
1872 }
1873
34eb7579
RV		 1874 if (!is_edp_psr(intel_dp)) {
1875 DRM_DEBUG_KMS("PSR not supported by this panel\n");
1876 return;
1877 }
1878
f0355c4a 1879 mutex_lock(&dev_priv->psr.lock);
109fc2ad
DV		 1880 if (dev_priv->psr.enabled) {
1881 DRM_DEBUG_KMS("PSR already in use\n");
f0355c4a 1882 mutex_unlock(&dev_priv->psr.lock);
109fc2ad
DV		 1883 return;
1884 }
1885
9ca15301
DV		 1886 dev_priv->psr.busy_frontbuffer_bits = 0;
1887
16487254
RV		 1888 /* Setup PSR once */
1889 intel_edp_psr_setup(intel_dp);
1890
7c8f8a70 1891 if (intel_edp_psr_match_conditions(intel_dp))
9ca15301 1892 dev_priv->psr.enabled = intel_dp;
f0355c4a 1893 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1894}
1895
2b28bb1b
RV		 1896void intel_edp_psr_disable(struct intel_dp *intel_dp)
1897{
1898 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900
f0355c4a
DV		 1901 mutex_lock(&dev_priv->psr.lock);
1902 if (!dev_priv->psr.enabled) {
1903 mutex_unlock(&dev_priv->psr.lock);
1904 return;
1905 }
1906
3638379c
DV		 1907 if (dev_priv->psr.active) {
1908 I915_WRITE(EDP_PSR_CTL(dev),
1909 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
1910
1911 /* Wait till PSR is idle */
1912 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
1913 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1914 DRM_ERROR("Timed out waiting for PSR Idle State\n");
2b28bb1b 1915
3638379c
DV		 1916 dev_priv->psr.active = false;
1917 } else {
1918 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
1919 }
7c8f8a70 1920
2807cf69 1921 dev_priv->psr.enabled = NULL;
f0355c4a 1922 mutex_unlock(&dev_priv->psr.lock);
9ca15301
DV		 1923
1924 cancel_delayed_work_sync(&dev_priv->psr.work);
2b28bb1b
RV		 1925}
1926
f02a326e 1927static void intel_edp_psr_work(struct work_struct *work)
7c8f8a70
RV		 1928{
1929 struct drm_i915_private *dev_priv =
1930 container_of(work, typeof(*dev_priv), psr.work.work);
2807cf69
DV		 1931 struct intel_dp *intel_dp = dev_priv->psr.enabled;
1932
f0355c4a
DV		 1933 mutex_lock(&dev_priv->psr.lock);
1934 intel_dp = dev_priv->psr.enabled;
1935
2807cf69 1936 if (!intel_dp)
f0355c4a 1937 goto unlock;
2807cf69 1938
9ca15301
DV		 1939 /*
1940 * The delayed work can race with an invalidate hence we need to
1941 * recheck. Since psr_flush first clears this and then reschedules we
1942 * won't ever miss a flush when bailing out here.
1943 */
1944 if (dev_priv->psr.busy_frontbuffer_bits)
1945 goto unlock;
1946
1947 intel_edp_psr_do_enable(intel_dp);
f0355c4a
DV		 1948unlock:
1949 mutex_unlock(&dev_priv->psr.lock);
3d739d92
RV		 1950}
1951
9ca15301 1952static void intel_edp_psr_do_exit(struct drm_device *dev)
7c8f8a70
RV		 1953{
1954 struct drm_i915_private *dev_priv = dev->dev_private;
1955
3638379c
DV		 1956 if (dev_priv->psr.active) {
1957 u32 val = I915_READ(EDP_PSR_CTL(dev));
1958
1959 WARN_ON(!(val & EDP_PSR_ENABLE));
1960
1961 I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
1962
1963 dev_priv->psr.active = false;
1964 }
7c8f8a70 1965
9ca15301
DV		 1966}
1967
1968void intel_edp_psr_invalidate(struct drm_device *dev,
1969 unsigned frontbuffer_bits)
1970{
1971 struct drm_i915_private *dev_priv = dev->dev_private;
1972 struct drm_crtc *crtc;
1973 enum pipe pipe;
1974
9ca15301
DV		 1975 mutex_lock(&dev_priv->psr.lock);
1976 if (!dev_priv->psr.enabled) {
1977 mutex_unlock(&dev_priv->psr.lock);
1978 return;
1979 }
1980
1981 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
1982 pipe = to_intel_crtc(crtc)->pipe;
1983
1984 intel_edp_psr_do_exit(dev);
1985
1986 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
1987
1988 dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
1989 mutex_unlock(&dev_priv->psr.lock);
1990}
1991
1992void intel_edp_psr_flush(struct drm_device *dev,
1993 unsigned frontbuffer_bits)
1994{
1995 struct drm_i915_private *dev_priv = dev->dev_private;
1996 struct drm_crtc *crtc;
1997 enum pipe pipe;
1998
9ca15301
DV		 1999 mutex_lock(&dev_priv->psr.lock);
2000 if (!dev_priv->psr.enabled) {
2001 mutex_unlock(&dev_priv->psr.lock);
2002 return;
2003 }
2004
2005 crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
2006 pipe = to_intel_crtc(crtc)->pipe;
2007 dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
2008
2009 /*
2010 * On Haswell sprite plane updates don't result in a psr invalidating
2011 * signal in the hardware. Which means we need to manually fake this in
2012 * software for all flushes, not just when we've seen a preceding
2013 * invalidation through frontbuffer rendering.
2014 */
2015 if (IS_HASWELL(dev) &&
2016 (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
2017 intel_edp_psr_do_exit(dev);
2018
2019 if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
2020 schedule_delayed_work(&dev_priv->psr.work,
2021 msecs_to_jiffies(100));
f0355c4a 2022 mutex_unlock(&dev_priv->psr.lock);
7c8f8a70
RV		 2023}
2024
2025void intel_edp_psr_init(struct drm_device *dev)
2026{
2027 struct drm_i915_private *dev_priv = dev->dev_private;
2028
7c8f8a70 2029 INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
f0355c4a 2030 mutex_init(&dev_priv->psr.lock);
7c8f8a70
RV		 2031}
2032
e8cb4558 2033static void intel_disable_dp(struct intel_encoder *encoder)
d240f20f 2034{
e8cb4558 2035 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866
ID		 2036 enum port port = dp_to_dig_port(intel_dp)->port;
2037 struct drm_device *dev = encoder->base.dev;
6cb49835
DV		 2038
2039 /* Make sure the panel is off before trying to change the mode. But also
2040 * ensure that we have vdd while we switch off the panel. */
24f3e092 2041 intel_edp_panel_vdd_on(intel_dp);
4be73780 2042 intel_edp_backlight_off(intel_dp);
fdbc3b1f 2043 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
4be73780 2044 intel_edp_panel_off(intel_dp);
3739850b
DV		 2045
2046 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
982a3866 2047 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
3739850b 2048 intel_dp_link_down(intel_dp);
d240f20f
JB		 2049}
2050
49277c31 2051static void g4x_post_disable_dp(struct intel_encoder *encoder)
d240f20f 2052{
2bd2ad64 2053 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
982a3866 2054 enum port port = dp_to_dig_port(intel_dp)->port;
2bd2ad64 2055
49277c31
VS		 2056 if (port != PORT_A)
2057 return;
2058
2059 intel_dp_link_down(intel_dp);
2060 ironlake_edp_pll_off(intel_dp);
2061}
2062
2063static void vlv_post_disable_dp(struct intel_encoder *encoder)
2064{
2065 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2066
2067 intel_dp_link_down(intel_dp);
2bd2ad64
DV		 2068}
2069
580d3811
VS		 2070static void chv_post_disable_dp(struct intel_encoder *encoder)
2071{
2072 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2073 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2074 struct drm_device *dev = encoder->base.dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct intel_crtc *intel_crtc =
2077 to_intel_crtc(encoder->base.crtc);
2078 enum dpio_channel ch = vlv_dport_to_channel(dport);
2079 enum pipe pipe = intel_crtc->pipe;
2080 u32 val;
2081
2082 intel_dp_link_down(intel_dp);
2083
2084 mutex_lock(&dev_priv->dpio_lock);
2085
2086 /* Propagate soft reset to data lane reset */
97fd4d5c 2087 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2088 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c 2089 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
d2152b25 2090
97fd4d5c
VS		 2091 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2092 val |= CHV_PCS_REQ_SOFTRESET_EN;
2093 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2094
2095 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2096 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2097 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2098
2099 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
580d3811 2100 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2101 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
580d3811
VS		 2102
2103 mutex_unlock(&dev_priv->dpio_lock);
2104}
2105
e8cb4558 2106static void intel_enable_dp(struct intel_encoder *encoder)
d240f20f 2107{
e8cb4558
DV		 2108 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2109 struct drm_device *dev = encoder->base.dev;
2110 struct drm_i915_private *dev_priv = dev->dev_private;
2111 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
5d613501 2112
0c33d8d7
DV		 2113 if (WARN_ON(dp_reg & DP_PORT_EN))
2114 return;
5d613501 2115
24f3e092 2116 intel_edp_panel_vdd_on(intel_dp);
f01eca2e 2117 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
33a34e4e 2118 intel_dp_start_link_train(intel_dp);
4be73780
DV		 2119 intel_edp_panel_on(intel_dp);
2120 edp_panel_vdd_off(intel_dp, true);
33a34e4e 2121 intel_dp_complete_link_train(intel_dp);
3ab9c637 2122 intel_dp_stop_link_train(intel_dp);
ab1f90f9 2123}
89b667f8 2124
ecff4f3b
JN		 2125static void g4x_enable_dp(struct intel_encoder *encoder)
2126{
828f5c6e
JN		 2127 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2128
ecff4f3b 2129 intel_enable_dp(encoder);
4be73780 2130 intel_edp_backlight_on(intel_dp);
ab1f90f9 2131}
89b667f8 2132
ab1f90f9
JN		 2133static void vlv_enable_dp(struct intel_encoder *encoder)
2134{
828f5c6e
JN		 2135 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2136
4be73780 2137 intel_edp_backlight_on(intel_dp);
d240f20f
JB		 2138}
2139
ecff4f3b 2140static void g4x_pre_enable_dp(struct intel_encoder *encoder)
ab1f90f9
JN		 2141{
2142 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2143 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2144
8ac33ed3
DV		 2145 intel_dp_prepare(encoder);
2146
d41f1efb
DV		 2147 /* Only ilk+ has port A */
2148 if (dport->port == PORT_A) {
2149 ironlake_set_pll_cpu_edp(intel_dp);
ab1f90f9 2150 ironlake_edp_pll_on(intel_dp);
d41f1efb 2151 }
ab1f90f9
JN		 2152}
2153
2154static void vlv_pre_enable_dp(struct intel_encoder *encoder)
a4fc5ed6 2155{
2bd2ad64 2156 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
bc7d38a4 2157 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
b2634017 2158 struct drm_device *dev = encoder->base.dev;
89b667f8 2159 struct drm_i915_private *dev_priv = dev->dev_private;
ab1f90f9 2160 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
e4607fcf 2161 enum dpio_channel port = vlv_dport_to_channel(dport);
ab1f90f9 2162 int pipe = intel_crtc->pipe;
bf13e81b 2163 struct edp_power_seq power_seq;
ab1f90f9 2164 u32 val;
a4fc5ed6 2165
ab1f90f9 2166 mutex_lock(&dev_priv->dpio_lock);
89b667f8 2167
ab3c759a 2168 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
ab1f90f9
JN		 2169 val = 0;
2170 if (pipe)
2171 val |= (1<<21);
2172 else
2173 val &= ~(1<<21);
2174 val |= 0x001000c4;
ab3c759a
CML		 2175 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2176 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2177 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
89b667f8 2178
ab1f90f9
JN		 2179 mutex_unlock(&dev_priv->dpio_lock);
2180
2cac613b
ID		 2181 if (is_edp(intel_dp)) {
2182 /* init power sequencer on this pipe and port */
2183 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2184 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2185 &power_seq);
2186 }
bf13e81b 2187
ab1f90f9
JN		 2188 intel_enable_dp(encoder);
2189
e4607fcf 2190 vlv_wait_port_ready(dev_priv, dport);
89b667f8
JB		 2191}
2192
ecff4f3b 2193static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
89b667f8
JB		 2194{
2195 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2196 struct drm_device *dev = encoder->base.dev;
2197 struct drm_i915_private *dev_priv = dev->dev_private;
5e69f97f
CML		 2198 struct intel_crtc *intel_crtc =
2199 to_intel_crtc(encoder->base.crtc);
e4607fcf 2200 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2201 int pipe = intel_crtc->pipe;
89b667f8 2202
8ac33ed3
DV		 2203 intel_dp_prepare(encoder);
2204
89b667f8 2205 /* Program Tx lane resets to default */
0980a60f 2206 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 2207 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
89b667f8
JB		 2208 DPIO_PCS_TX_LANE2_RESET |
2209 DPIO_PCS_TX_LANE1_RESET);
ab3c759a 2210 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
89b667f8
JB		 2211 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2212 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2213 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2214 DPIO_PCS_CLK_SOFT_RESET);
2215
2216 /* Fix up inter-pair skew failure */
ab3c759a
CML		 2217 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2218 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2219 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
0980a60f 2220 mutex_unlock(&dev_priv->dpio_lock);
a4fc5ed6
KP		 2221}
2222
e4a1d846
CML		 2223static void chv_pre_enable_dp(struct intel_encoder *encoder)
2224{
2225 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2226 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2227 struct drm_device *dev = encoder->base.dev;
2228 struct drm_i915_private *dev_priv = dev->dev_private;
2229 struct edp_power_seq power_seq;
2230 struct intel_crtc *intel_crtc =
2231 to_intel_crtc(encoder->base.crtc);
2232 enum dpio_channel ch = vlv_dport_to_channel(dport);
2233 int pipe = intel_crtc->pipe;
2234 int data, i;
949c1d43 2235 u32 val;
e4a1d846 2236
e4a1d846 2237 mutex_lock(&dev_priv->dpio_lock);
949c1d43
VS		 2238
2239 /* Deassert soft data lane reset*/
97fd4d5c 2240 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
d2152b25 2241 val |= CHV_PCS_REQ_SOFTRESET_EN;
97fd4d5c
VS		 2242 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2243
2244 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2245 val |= CHV_PCS_REQ_SOFTRESET_EN;
2246 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2247
2248 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2249 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2250 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
d2152b25 2251
97fd4d5c 2252 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
949c1d43 2253 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
97fd4d5c 2254 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
949c1d43
VS		 2255
2256 /* Program Tx lane latency optimal setting*/
e4a1d846
CML		 2257 for (i = 0; i < 4; i++) {
2258 /* Set the latency optimal bit */
2259 data = (i == 1) ? 0x0 : 0x6;
2260 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2261 data << DPIO_FRC_LATENCY_SHFIT);
2262
2263 /* Set the upar bit */
2264 data = (i == 1) ? 0x0 : 0x1;
2265 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2266 data << DPIO_UPAR_SHIFT);
2267 }
2268
2269 /* Data lane stagger programming */
2270 /* FIXME: Fix up value only after power analysis */
2271
2272 mutex_unlock(&dev_priv->dpio_lock);
2273
2274 if (is_edp(intel_dp)) {
2275 /* init power sequencer on this pipe and port */
2276 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2277 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2278 &power_seq);
2279 }
2280
2281 intel_enable_dp(encoder);
2282
2283 vlv_wait_port_ready(dev_priv, dport);
2284}
2285
9197c88b
VS		 2286static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
2287{
2288 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2289 struct drm_device *dev = encoder->base.dev;
2290 struct drm_i915_private *dev_priv = dev->dev_private;
2291 struct intel_crtc *intel_crtc =
2292 to_intel_crtc(encoder->base.crtc);
2293 enum dpio_channel ch = vlv_dport_to_channel(dport);
2294 enum pipe pipe = intel_crtc->pipe;
2295 u32 val;
2296
625695f8
VS		 2297 intel_dp_prepare(encoder);
2298
9197c88b
VS		 2299 mutex_lock(&dev_priv->dpio_lock);
2300
b9e5ac3c
VS		 2301 /* program left/right clock distribution */
2302 if (pipe != PIPE_B) {
2303 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
2304 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
2305 if (ch == DPIO_CH0)
2306 val |= CHV_BUFLEFTENA1_FORCE;
2307 if (ch == DPIO_CH1)
2308 val |= CHV_BUFRIGHTENA1_FORCE;
2309 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
2310 } else {
2311 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
2312 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
2313 if (ch == DPIO_CH0)
2314 val |= CHV_BUFLEFTENA2_FORCE;
2315 if (ch == DPIO_CH1)
2316 val |= CHV_BUFRIGHTENA2_FORCE;
2317 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
2318 }
2319
9197c88b
VS		 2320 /* program clock channel usage */
2321 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
2322 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2323 if (pipe != PIPE_B)
2324 val &= ~CHV_PCS_USEDCLKCHANNEL;
2325 else
2326 val |= CHV_PCS_USEDCLKCHANNEL;
2327 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
2328
2329 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
2330 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
2331 if (pipe != PIPE_B)
2332 val &= ~CHV_PCS_USEDCLKCHANNEL;
2333 else
2334 val |= CHV_PCS_USEDCLKCHANNEL;
2335 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
2336
2337 /*
2338 * This a a bit weird since generally CL
2339 * matches the pipe, but here we need to
2340 * pick the CL based on the port.
2341 */
2342 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
2343 if (pipe != PIPE_B)
2344 val &= ~CHV_CMN_USEDCLKCHANNEL;
2345 else
2346 val |= CHV_CMN_USEDCLKCHANNEL;
2347 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
2348
2349 mutex_unlock(&dev_priv->dpio_lock);
2350}
2351
a4fc5ed6 2352/*
df0c237d
JB		 2353 * Native read with retry for link status and receiver capability reads for
2354 * cases where the sink may still be asleep.
9d1a1031
JN		 2355 *
2356 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2357 * supposed to retry 3 times per the spec.
a4fc5ed6 2358 */
9d1a1031
JN		 2359static ssize_t
2360intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2361 void *buffer, size_t size)
a4fc5ed6 2362{
9d1a1031
JN		 2363 ssize_t ret;
2364 int i;
61da5fab 2365
61da5fab 2366 for (i = 0; i < 3; i++) {
9d1a1031
JN		 2367 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2368 if (ret == size)
2369 return ret;
61da5fab
JB		 2370 msleep(1);
2371 }
a4fc5ed6 2372
9d1a1031 2373 return ret;
a4fc5ed6
KP		 2374}
2375
2376/*
2377 * Fetch AUX CH registers 0x202 - 0x207 which contain
2378 * link status information
2379 */
2380static bool
93f62dad 2381intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6 2382{
9d1a1031
JN		 2383 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2384 DP_LANE0_1_STATUS,
2385 link_status,
2386 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
a4fc5ed6
KP		 2387}
2388
1100244e 2389/* These are source-specific values. */
a4fc5ed6 2390static uint8_t
1a2eb460 2391intel_dp_voltage_max(struct intel_dp *intel_dp)
a4fc5ed6 2392{
30add22d 2393 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2394 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2395
9576c27f 2396 if (IS_VALLEYVIEW(dev))
e2fa6fba 2397 return DP_TRAIN_VOLTAGE_SWING_1200;
bc7d38a4 2398 else if (IS_GEN7(dev) && port == PORT_A)
1a2eb460 2399 return DP_TRAIN_VOLTAGE_SWING_800;
bc7d38a4 2400 else if (HAS_PCH_CPT(dev) && port != PORT_A)
1a2eb460
KP		 2401 return DP_TRAIN_VOLTAGE_SWING_1200;
2402 else
2403 return DP_TRAIN_VOLTAGE_SWING_800;
2404}
2405
2406static uint8_t
2407intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2408{
30add22d 2409 struct drm_device *dev = intel_dp_to_dev(intel_dp);
bc7d38a4 2410 enum port port = dp_to_dig_port(intel_dp)->port;
1a2eb460 2411
9576c27f 2412 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
d6c0d722
PZ		 2413 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2414 case DP_TRAIN_VOLTAGE_SWING_400:
2415 return DP_TRAIN_PRE_EMPHASIS_9_5;
2416 case DP_TRAIN_VOLTAGE_SWING_600:
2417 return DP_TRAIN_PRE_EMPHASIS_6;
2418 case DP_TRAIN_VOLTAGE_SWING_800:
2419 return DP_TRAIN_PRE_EMPHASIS_3_5;
2420 case DP_TRAIN_VOLTAGE_SWING_1200:
2421 default:
2422 return DP_TRAIN_PRE_EMPHASIS_0;
2423 }
e2fa6fba
P		 2424 } else if (IS_VALLEYVIEW(dev)) {
2425 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2426 case DP_TRAIN_VOLTAGE_SWING_400:
2427 return DP_TRAIN_PRE_EMPHASIS_9_5;
2428 case DP_TRAIN_VOLTAGE_SWING_600:
2429 return DP_TRAIN_PRE_EMPHASIS_6;
2430 case DP_TRAIN_VOLTAGE_SWING_800:
2431 return DP_TRAIN_PRE_EMPHASIS_3_5;
2432 case DP_TRAIN_VOLTAGE_SWING_1200:
2433 default:
2434 return DP_TRAIN_PRE_EMPHASIS_0;
2435 }
bc7d38a4 2436 } else if (IS_GEN7(dev) && port == PORT_A) {
1a2eb460
KP		 2437 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2438 case DP_TRAIN_VOLTAGE_SWING_400:
2439 return DP_TRAIN_PRE_EMPHASIS_6;
2440 case DP_TRAIN_VOLTAGE_SWING_600:
2441 case DP_TRAIN_VOLTAGE_SWING_800:
2442 return DP_TRAIN_PRE_EMPHASIS_3_5;
2443 default:
2444 return DP_TRAIN_PRE_EMPHASIS_0;
2445 }
2446 } else {
2447 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2448 case DP_TRAIN_VOLTAGE_SWING_400:
2449 return DP_TRAIN_PRE_EMPHASIS_6;
2450 case DP_TRAIN_VOLTAGE_SWING_600:
2451 return DP_TRAIN_PRE_EMPHASIS_6;
2452 case DP_TRAIN_VOLTAGE_SWING_800:
2453 return DP_TRAIN_PRE_EMPHASIS_3_5;
2454 case DP_TRAIN_VOLTAGE_SWING_1200:
2455 default:
2456 return DP_TRAIN_PRE_EMPHASIS_0;
2457 }
a4fc5ed6
KP		 2458 }
2459}
2460
e2fa6fba
P		 2461static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2462{
2463 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
5e69f97f
CML		 2466 struct intel_crtc *intel_crtc =
2467 to_intel_crtc(dport->base.base.crtc);
e2fa6fba
P		 2468 unsigned long demph_reg_value, preemph_reg_value,
2469 uniqtranscale_reg_value;
2470 uint8_t train_set = intel_dp->train_set[0];
e4607fcf 2471 enum dpio_channel port = vlv_dport_to_channel(dport);
5e69f97f 2472 int pipe = intel_crtc->pipe;
e2fa6fba
P		 2473
2474 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2475 case DP_TRAIN_PRE_EMPHASIS_0:
2476 preemph_reg_value = 0x0004000;
2477 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2478 case DP_TRAIN_VOLTAGE_SWING_400:
2479 demph_reg_value = 0x2B405555;
2480 uniqtranscale_reg_value = 0x552AB83A;
2481 break;
2482 case DP_TRAIN_VOLTAGE_SWING_600:
2483 demph_reg_value = 0x2B404040;
2484 uniqtranscale_reg_value = 0x5548B83A;
2485 break;
2486 case DP_TRAIN_VOLTAGE_SWING_800:
2487 demph_reg_value = 0x2B245555;
2488 uniqtranscale_reg_value = 0x5560B83A;
2489 break;
2490 case DP_TRAIN_VOLTAGE_SWING_1200:
2491 demph_reg_value = 0x2B405555;
2492 uniqtranscale_reg_value = 0x5598DA3A;
2493 break;
2494 default:
2495 return 0;
2496 }
2497 break;
2498 case DP_TRAIN_PRE_EMPHASIS_3_5:
2499 preemph_reg_value = 0x0002000;
2500 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2501 case DP_TRAIN_VOLTAGE_SWING_400:
2502 demph_reg_value = 0x2B404040;
2503 uniqtranscale_reg_value = 0x5552B83A;
2504 break;
2505 case DP_TRAIN_VOLTAGE_SWING_600:
2506 demph_reg_value = 0x2B404848;
2507 uniqtranscale_reg_value = 0x5580B83A;
2508 break;
2509 case DP_TRAIN_VOLTAGE_SWING_800:
2510 demph_reg_value = 0x2B404040;
2511 uniqtranscale_reg_value = 0x55ADDA3A;
2512 break;
2513 default:
2514 return 0;
2515 }
2516 break;
2517 case DP_TRAIN_PRE_EMPHASIS_6:
2518 preemph_reg_value = 0x0000000;
2519 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2520 case DP_TRAIN_VOLTAGE_SWING_400:
2521 demph_reg_value = 0x2B305555;
2522 uniqtranscale_reg_value = 0x5570B83A;
2523 break;
2524 case DP_TRAIN_VOLTAGE_SWING_600:
2525 demph_reg_value = 0x2B2B4040;
2526 uniqtranscale_reg_value = 0x55ADDA3A;
2527 break;
2528 default:
2529 return 0;
2530 }
2531 break;
2532 case DP_TRAIN_PRE_EMPHASIS_9_5:
2533 preemph_reg_value = 0x0006000;
2534 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2535 case DP_TRAIN_VOLTAGE_SWING_400:
2536 demph_reg_value = 0x1B405555;
2537 uniqtranscale_reg_value = 0x55ADDA3A;
2538 break;
2539 default:
2540 return 0;
2541 }
2542 break;
2543 default:
2544 return 0;
2545 }
2546
0980a60f 2547 mutex_lock(&dev_priv->dpio_lock);
ab3c759a
CML		 2548 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2549 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2550 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
e2fa6fba 2551 uniqtranscale_reg_value);
ab3c759a
CML		 2552 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2553 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2554 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2555 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
0980a60f 2556 mutex_unlock(&dev_priv->dpio_lock);
e2fa6fba
P		 2557
2558 return 0;
2559}
2560
e4a1d846
CML		 2561static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2562{
2563 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2564 struct drm_i915_private *dev_priv = dev->dev_private;
2565 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2566 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
f72df8db 2567 u32 deemph_reg_value, margin_reg_value, val;
e4a1d846
CML		 2568 uint8_t train_set = intel_dp->train_set[0];
2569 enum dpio_channel ch = vlv_dport_to_channel(dport);
f72df8db
VS		 2570 enum pipe pipe = intel_crtc->pipe;
2571 int i;
e4a1d846
CML		 2572
2573 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2574 case DP_TRAIN_PRE_EMPHASIS_0:
2575 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2576 case DP_TRAIN_VOLTAGE_SWING_400:
2577 deemph_reg_value = 128;
2578 margin_reg_value = 52;
2579 break;
2580 case DP_TRAIN_VOLTAGE_SWING_600:
2581 deemph_reg_value = 128;
2582 margin_reg_value = 77;
2583 break;
2584 case DP_TRAIN_VOLTAGE_SWING_800:
2585 deemph_reg_value = 128;
2586 margin_reg_value = 102;
2587 break;
2588 case DP_TRAIN_VOLTAGE_SWING_1200:
2589 deemph_reg_value = 128;
2590 margin_reg_value = 154;
2591 /* FIXME extra to set for 1200 */
2592 break;
2593 default:
2594 return 0;
2595 }
2596 break;
2597 case DP_TRAIN_PRE_EMPHASIS_3_5:
2598 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2599 case DP_TRAIN_VOLTAGE_SWING_400:
2600 deemph_reg_value = 85;
2601 margin_reg_value = 78;
2602 break;
2603 case DP_TRAIN_VOLTAGE_SWING_600:
2604 deemph_reg_value = 85;
2605 margin_reg_value = 116;
2606 break;
2607 case DP_TRAIN_VOLTAGE_SWING_800:
2608 deemph_reg_value = 85;
2609 margin_reg_value = 154;
2610 break;
2611 default:
2612 return 0;
2613 }
2614 break;
2615 case DP_TRAIN_PRE_EMPHASIS_6:
2616 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2617 case DP_TRAIN_VOLTAGE_SWING_400:
2618 deemph_reg_value = 64;
2619 margin_reg_value = 104;
2620 break;
2621 case DP_TRAIN_VOLTAGE_SWING_600:
2622 deemph_reg_value = 64;
2623 margin_reg_value = 154;
2624 break;
2625 default:
2626 return 0;
2627 }
2628 break;
2629 case DP_TRAIN_PRE_EMPHASIS_9_5:
2630 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2631 case DP_TRAIN_VOLTAGE_SWING_400:
2632 deemph_reg_value = 43;
2633 margin_reg_value = 154;
2634 break;
2635 default:
2636 return 0;
2637 }
2638 break;
2639 default:
2640 return 0;
2641 }
2642
2643 mutex_lock(&dev_priv->dpio_lock);
2644
2645 /* Clear calc init */
1966e59e
VS		 2646 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2647 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2648 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2649
2650 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2651 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
2652 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2653
2654 /* Program swing deemph */
f72df8db
VS		 2655 for (i = 0; i < 4; i++) {
2656 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
2657 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2658 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2659 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
2660 }
e4a1d846
CML		 2661
2662 /* Program swing margin */
f72df8db
VS		 2663 for (i = 0; i < 4; i++) {
2664 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1fb44505
VS		 2665 val &= ~DPIO_SWING_MARGIN000_MASK;
2666 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
f72df8db
VS		 2667 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2668 }
e4a1d846
CML		 2669
2670 /* Disable unique transition scale */
f72df8db
VS		 2671 for (i = 0; i < 4; i++) {
2672 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2673 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2674 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2675 }
e4a1d846
CML		 2676
2677 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2678 == DP_TRAIN_PRE_EMPHASIS_0) &&
2679 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2680 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2681
2682 /*
2683 * The document said it needs to set bit 27 for ch0 and bit 26
2684 * for ch1. Might be a typo in the doc.
2685 * For now, for this unique transition scale selection, set bit
2686 * 27 for ch0 and ch1.
2687 */
f72df8db
VS		 2688 for (i = 0; i < 4; i++) {
2689 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
2690 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2691 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
2692 }
e4a1d846 2693
f72df8db
VS		 2694 for (i = 0; i < 4; i++) {
2695 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2696 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2697 val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2698 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
2699 }
e4a1d846
CML		 2700 }
2701
2702 /* Start swing calculation */
1966e59e
VS		 2703 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
2704 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2705 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
2706
2707 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
2708 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
2709 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
e4a1d846
CML		 2710
2711 /* LRC Bypass */
2712 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2713 val |= DPIO_LRC_BYPASS;
2714 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2715
2716 mutex_unlock(&dev_priv->dpio_lock);
2717
2718 return 0;
2719}
2720
a4fc5ed6 2721static void
0301b3ac
JN		 2722intel_get_adjust_train(struct intel_dp *intel_dp,
2723 const uint8_t link_status[DP_LINK_STATUS_SIZE])
a4fc5ed6
KP		 2724{
2725 uint8_t v = 0;
2726 uint8_t p = 0;
2727 int lane;
1a2eb460
KP		 2728 uint8_t voltage_max;
2729 uint8_t preemph_max;
a4fc5ed6 2730
33a34e4e 2731 for (lane = 0; lane < intel_dp->lane_count; lane++) {
0f037bde
DV		 2732 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2733 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
a4fc5ed6
KP		 2734
2735 if (this_v > v)
2736 v = this_v;
2737 if (this_p > p)
2738 p = this_p;
2739 }
2740
1a2eb460 2741 voltage_max = intel_dp_voltage_max(intel_dp);
417e822d
KP		 2742 if (v >= voltage_max)
2743 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
a4fc5ed6 2744
1a2eb460
KP		 2745 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2746 if (p >= preemph_max)
2747 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
a4fc5ed6
KP		 2748
2749 for (lane = 0; lane < 4; lane++)
33a34e4e 2750 intel_dp->train_set[lane] = v | p;
a4fc5ed6
KP		 2751}
2752
2753static uint32_t
f0a3424e 2754intel_gen4_signal_levels(uint8_t train_set)
a4fc5ed6 2755{
3cf2efb1 2756 uint32_t signal_levels = 0;
a4fc5ed6 2757
3cf2efb1 2758 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
a4fc5ed6
KP		 2759 case DP_TRAIN_VOLTAGE_SWING_400:
2760 default:
2761 signal_levels |= DP_VOLTAGE_0_4;
2762 break;
2763 case DP_TRAIN_VOLTAGE_SWING_600:
2764 signal_levels |= DP_VOLTAGE_0_6;
2765 break;
2766 case DP_TRAIN_VOLTAGE_SWING_800:
2767 signal_levels |= DP_VOLTAGE_0_8;
2768 break;
2769 case DP_TRAIN_VOLTAGE_SWING_1200:
2770 signal_levels |= DP_VOLTAGE_1_2;
2771 break;
2772 }
3cf2efb1 2773 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
a4fc5ed6
KP		 2774 case DP_TRAIN_PRE_EMPHASIS_0:
2775 default:
2776 signal_levels |= DP_PRE_EMPHASIS_0;
2777 break;
2778 case DP_TRAIN_PRE_EMPHASIS_3_5:
2779 signal_levels |= DP_PRE_EMPHASIS_3_5;
2780 break;
2781 case DP_TRAIN_PRE_EMPHASIS_6:
2782 signal_levels |= DP_PRE_EMPHASIS_6;
2783 break;
2784 case DP_TRAIN_PRE_EMPHASIS_9_5:
2785 signal_levels |= DP_PRE_EMPHASIS_9_5;
2786 break;
2787 }
2788 return signal_levels;
2789}
2790
e3421a18
ZW		 2791/* Gen6's DP voltage swing and pre-emphasis control */
2792static uint32_t
2793intel_gen6_edp_signal_levels(uint8_t train_set)
2794{
3c5a62b5
YL		 2795 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2796 DP_TRAIN_PRE_EMPHASIS_MASK);
2797 switch (signal_levels) {
e3421a18 2798 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2799 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2800 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2801 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2802 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
e3421a18 2803 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
3c5a62b5
YL		 2804 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2805 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
e3421a18 2806 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
3c5a62b5
YL		 2807 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2808 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
e3421a18 2809 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
3c5a62b5
YL		 2810 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2811 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
e3421a18 2812 default:
3c5a62b5
YL		 2813 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2814 "0x%x\n", signal_levels);
2815 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
e3421a18
ZW		 2816 }
2817}
2818
1a2eb460
KP		 2819/* Gen7's DP voltage swing and pre-emphasis control */
2820static uint32_t
2821intel_gen7_edp_signal_levels(uint8_t train_set)
2822{
2823 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2824 DP_TRAIN_PRE_EMPHASIS_MASK);
2825 switch (signal_levels) {
2826 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2827 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2828 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2829 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2830 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2831 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2832
2833 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2834 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2835 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2836 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2837
2838 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2839 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2840 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2841 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2842
2843 default:
2844 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2845 "0x%x\n", signal_levels);
2846 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2847 }
2848}
2849
d6c0d722
PZ		 2850/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2851static uint32_t
f0a3424e 2852intel_hsw_signal_levels(uint8_t train_set)
a4fc5ed6 2853{
d6c0d722
PZ		 2854 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2855 DP_TRAIN_PRE_EMPHASIS_MASK);
2856 switch (signal_levels) {
2857 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2858 return DDI_BUF_EMP_400MV_0DB_HSW;
2859 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2860 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2861 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2862 return DDI_BUF_EMP_400MV_6DB_HSW;
2863 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2864 return DDI_BUF_EMP_400MV_9_5DB_HSW;
a4fc5ed6 2865
d6c0d722
PZ		 2866 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2867 return DDI_BUF_EMP_600MV_0DB_HSW;
2868 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2869 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2870 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2871 return DDI_BUF_EMP_600MV_6DB_HSW;
a4fc5ed6 2872
d6c0d722
PZ		 2873 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2874 return DDI_BUF_EMP_800MV_0DB_HSW;
2875 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2876 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2877 default:
2878 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2879 "0x%x\n", signal_levels);
2880 return DDI_BUF_EMP_400MV_0DB_HSW;
a4fc5ed6 2881 }
a4fc5ed6
KP		 2882}
2883
f0a3424e
PZ		 2884/* Properly updates "DP" with the correct signal levels. */
2885static void
2886intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2887{
2888 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 2889 enum port port = intel_dig_port->port;
f0a3424e
PZ		 2890 struct drm_device *dev = intel_dig_port->base.base.dev;
2891 uint32_t signal_levels, mask;
2892 uint8_t train_set = intel_dp->train_set[0];
2893
9576c27f 2894 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
f0a3424e
PZ		 2895 signal_levels = intel_hsw_signal_levels(train_set);
2896 mask = DDI_BUF_EMP_MASK;
e4a1d846
CML		 2897 } else if (IS_CHERRYVIEW(dev)) {
2898 signal_levels = intel_chv_signal_levels(intel_dp);
2899 mask = 0;
e2fa6fba
P		 2900 } else if (IS_VALLEYVIEW(dev)) {
2901 signal_levels = intel_vlv_signal_levels(intel_dp);
2902 mask = 0;
bc7d38a4 2903 } else if (IS_GEN7(dev) && port == PORT_A) {
f0a3424e
PZ		 2904 signal_levels = intel_gen7_edp_signal_levels(train_set);
2905 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
bc7d38a4 2906 } else if (IS_GEN6(dev) && port == PORT_A) {
f0a3424e
PZ		 2907 signal_levels = intel_gen6_edp_signal_levels(train_set);
2908 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2909 } else {
2910 signal_levels = intel_gen4_signal_levels(train_set);
2911 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2912 }
2913
2914 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2915
2916 *DP = (*DP & ~mask) | signal_levels;
2917}
2918
a4fc5ed6 2919static bool
ea5b213a 2920intel_dp_set_link_train(struct intel_dp *intel_dp,
70aff66c 2921 uint32_t *DP,
58e10eb9 2922 uint8_t dp_train_pat)
a4fc5ed6 2923{
174edf1f
PZ		 2924 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2925 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 2926 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 2927 enum port port = intel_dig_port->port;
2cdfe6c8
JN		 2928 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2929 int ret, len;
a4fc5ed6 2930
22b8bf17 2931 if (HAS_DDI(dev)) {
3ab9c637 2932 uint32_t temp = I915_READ(DP_TP_CTL(port));
d6c0d722
PZ		 2933
2934 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2935 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2936 else
2937 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2938
2939 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2940 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2941 case DP_TRAINING_PATTERN_DISABLE:
d6c0d722
PZ		 2942 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2943
2944 break;
2945 case DP_TRAINING_PATTERN_1:
2946 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2947 break;
2948 case DP_TRAINING_PATTERN_2:
2949 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2950 break;
2951 case DP_TRAINING_PATTERN_3:
2952 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2953 break;
2954 }
174edf1f 2955 I915_WRITE(DP_TP_CTL(port), temp);
d6c0d722 2956
bc7d38a4 2957 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
70aff66c 2958 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
47ea7542
PZ		 2959
2960 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2961 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2962 *DP |= DP_LINK_TRAIN_OFF_CPT;
47ea7542
PZ		 2963 break;
2964 case DP_TRAINING_PATTERN_1:
70aff66c 2965 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
47ea7542
PZ		 2966 break;
2967 case DP_TRAINING_PATTERN_2:
70aff66c 2968 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2969 break;
2970 case DP_TRAINING_PATTERN_3:
2971 DRM_ERROR("DP training pattern 3 not supported\n");
70aff66c 2972 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
47ea7542
PZ		 2973 break;
2974 }
2975
2976 } else {
aad3d14d
VS		 2977 if (IS_CHERRYVIEW(dev))
2978 *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2979 else
2980 *DP &= ~DP_LINK_TRAIN_MASK;
47ea7542
PZ		 2981
2982 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2983 case DP_TRAINING_PATTERN_DISABLE:
70aff66c 2984 *DP |= DP_LINK_TRAIN_OFF;
47ea7542
PZ		 2985 break;
2986 case DP_TRAINING_PATTERN_1:
70aff66c 2987 *DP |= DP_LINK_TRAIN_PAT_1;
47ea7542
PZ		 2988 break;
2989 case DP_TRAINING_PATTERN_2:
70aff66c 2990 *DP |= DP_LINK_TRAIN_PAT_2;
47ea7542
PZ		 2991 break;
2992 case DP_TRAINING_PATTERN_3:
aad3d14d
VS		 2993 if (IS_CHERRYVIEW(dev)) {
2994 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2995 } else {
2996 DRM_ERROR("DP training pattern 3 not supported\n");
2997 *DP |= DP_LINK_TRAIN_PAT_2;
2998 }
47ea7542
PZ		 2999 break;
3000 }
3001 }
3002
70aff66c 3003 I915_WRITE(intel_dp->output_reg, *DP);
ea5b213a 3004 POSTING_READ(intel_dp->output_reg);
a4fc5ed6 3005
2cdfe6c8
JN		 3006 buf[0] = dp_train_pat;
3007 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
47ea7542 3008 DP_TRAINING_PATTERN_DISABLE) {
2cdfe6c8
JN		 3009 /* don't write DP_TRAINING_LANEx_SET on disable */
3010 len = 1;
3011 } else {
3012 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
3013 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
3014 len = intel_dp->lane_count + 1;
47ea7542 3015 }
a4fc5ed6 3016
9d1a1031
JN		 3017 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
3018 buf, len);
2cdfe6c8
JN		 3019
3020 return ret == len;
a4fc5ed6
KP		 3021}
3022
70aff66c
JN		 3023static bool
3024intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
3025 uint8_t dp_train_pat)
3026{
953d22e8 3027 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
70aff66c
JN		 3028 intel_dp_set_signal_levels(intel_dp, DP);
3029 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3030}
3031
3032static bool
3033intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
0301b3ac 3034 const uint8_t link_status[DP_LINK_STATUS_SIZE])
70aff66c
JN		 3035{
3036 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3037 struct drm_device *dev = intel_dig_port->base.base.dev;
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 int ret;
3040
3041 intel_get_adjust_train(intel_dp, link_status);
3042 intel_dp_set_signal_levels(intel_dp, DP);
3043
3044 I915_WRITE(intel_dp->output_reg, *DP);
3045 POSTING_READ(intel_dp->output_reg);
3046
9d1a1031
JN		 3047 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
3048 intel_dp->train_set, intel_dp->lane_count);
70aff66c
JN		 3049
3050 return ret == intel_dp->lane_count;
3051}
3052
3ab9c637
ID		 3053static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3054{
3055 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3056 struct drm_device *dev = intel_dig_port->base.base.dev;
3057 struct drm_i915_private *dev_priv = dev->dev_private;
3058 enum port port = intel_dig_port->port;
3059 uint32_t val;
3060
3061 if (!HAS_DDI(dev))
3062 return;
3063
3064 val = I915_READ(DP_TP_CTL(port));
3065 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3066 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3067 I915_WRITE(DP_TP_CTL(port), val);
3068
3069 /*
3070 * On PORT_A we can have only eDP in SST mode. There the only reason
3071 * we need to set idle transmission mode is to work around a HW issue
3072 * where we enable the pipe while not in idle link-training mode.
3073 * In this case there is requirement to wait for a minimum number of
3074 * idle patterns to be sent.
3075 */
3076 if (port == PORT_A)
3077 return;
3078
3079 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3080 1))
3081 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3082}
3083
33a34e4e 3084/* Enable corresponding port and start training pattern 1 */
c19b0669 3085void
33a34e4e 3086intel_dp_start_link_train(struct intel_dp *intel_dp)
a4fc5ed6 3087{
da63a9f2 3088 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
c19b0669 3089 struct drm_device *dev = encoder->dev;
a4fc5ed6
KP		 3090 int i;
3091 uint8_t voltage;
cdb0e95b 3092 int voltage_tries, loop_tries;
ea5b213a 3093 uint32_t DP = intel_dp->DP;
6aba5b6c 3094 uint8_t link_config[2];
a4fc5ed6 3095
affa9354 3096 if (HAS_DDI(dev))
c19b0669
PZ		 3097 intel_ddi_prepare_link_retrain(encoder);
3098
3cf2efb1 3099 /* Write the link configuration data */
6aba5b6c
JN		 3100 link_config[0] = intel_dp->link_bw;
3101 link_config[1] = intel_dp->lane_count;
3102 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3103 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
9d1a1031 3104 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
6aba5b6c
JN		 3105
3106 link_config[0] = 0;
3107 link_config[1] = DP_SET_ANSI_8B10B;
9d1a1031 3108 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
a4fc5ed6
KP		 3109
3110 DP |= DP_PORT_EN;
1a2eb460 3111
70aff66c
JN		 3112 /* clock recovery */
3113 if (!intel_dp_reset_link_train(intel_dp, &DP,
3114 DP_TRAINING_PATTERN_1 |
3115 DP_LINK_SCRAMBLING_DISABLE)) {
3116 DRM_ERROR("failed to enable link training\n");
3117 return;
3118 }
3119
a4fc5ed6 3120 voltage = 0xff;
cdb0e95b
KP		 3121 voltage_tries = 0;
3122 loop_tries = 0;
a4fc5ed6 3123 for (;;) {
70aff66c 3124 uint8_t link_status[DP_LINK_STATUS_SIZE];
a4fc5ed6 3125
a7c9655f 3126 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
93f62dad
KP		 3127 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3128 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3129 break;
93f62dad 3130 }
a4fc5ed6 3131
01916270 3132 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
93f62dad 3133 DRM_DEBUG_KMS("clock recovery OK\n");
3cf2efb1
CW		 3134 break;
3135 }
3136
3137 /* Check to see if we've tried the max voltage */
3138 for (i = 0; i < intel_dp->lane_count; i++)
3139 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
a4fc5ed6 3140 break;
3b4f819d 3141 if (i == intel_dp->lane_count) {
b06fbda3
DV		 3142 ++loop_tries;
3143 if (loop_tries == 5) {
3def84b3 3144 DRM_ERROR("too many full retries, give up\n");
cdb0e95b
KP		 3145 break;
3146 }
70aff66c
JN		 3147 intel_dp_reset_link_train(intel_dp, &DP,
3148 DP_TRAINING_PATTERN_1 |
3149 DP_LINK_SCRAMBLING_DISABLE);
cdb0e95b
KP		 3150 voltage_tries = 0;
3151 continue;
3152 }
a4fc5ed6 3153
3cf2efb1 3154 /* Check to see if we've tried the same voltage 5 times */
b06fbda3 3155 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
24773670 3156 ++voltage_tries;
b06fbda3 3157 if (voltage_tries == 5) {
3def84b3 3158 DRM_ERROR("too many voltage retries, give up\n");
b06fbda3
DV		 3159 break;
3160 }
3161 } else
3162 voltage_tries = 0;
3163 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
a4fc5ed6 3164
70aff66c
JN		 3165 /* Update training set as requested by target */
3166 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3167 DRM_ERROR("failed to update link training\n");
3168 break;
3169 }
a4fc5ed6
KP		 3170 }
3171
33a34e4e
JB		 3172 intel_dp->DP = DP;
3173}
3174
c19b0669 3175void
33a34e4e
JB		 3176intel_dp_complete_link_train(struct intel_dp *intel_dp)
3177{
33a34e4e 3178 bool channel_eq = false;
37f80975 3179 int tries, cr_tries;
33a34e4e 3180 uint32_t DP = intel_dp->DP;
06ea66b6
TP		 3181 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
3182
3183 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
3184 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
3185 training_pattern = DP_TRAINING_PATTERN_3;
33a34e4e 3186
a4fc5ed6 3187 /* channel equalization */
70aff66c 3188 if (!intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3189 training_pattern |
70aff66c
JN		 3190 DP_LINK_SCRAMBLING_DISABLE)) {
3191 DRM_ERROR("failed to start channel equalization\n");
3192 return;
3193 }
3194
a4fc5ed6 3195 tries = 0;
37f80975 3196 cr_tries = 0;
a4fc5ed6
KP		 3197 channel_eq = false;
3198 for (;;) {
70aff66c 3199 uint8_t link_status[DP_LINK_STATUS_SIZE];
e3421a18 3200
37f80975
JB		 3201 if (cr_tries > 5) {
3202 DRM_ERROR("failed to train DP, aborting\n");
37f80975
JB		 3203 break;
3204 }
3205
a7c9655f 3206 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
70aff66c
JN		 3207 if (!intel_dp_get_link_status(intel_dp, link_status)) {
3208 DRM_ERROR("failed to get link status\n");
a4fc5ed6 3209 break;
70aff66c 3210 }
a4fc5ed6 3211
37f80975 3212 /* Make sure clock is still ok */
01916270 3213 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
37f80975 3214 intel_dp_start_link_train(intel_dp);
70aff66c 3215 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3216 training_pattern |
70aff66c 3217 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3218 cr_tries++;
3219 continue;
3220 }
3221
1ffdff13 3222 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3cf2efb1
CW		 3223 channel_eq = true;
3224 break;
3225 }
a4fc5ed6 3226
37f80975
JB		 3227 /* Try 5 times, then try clock recovery if that fails */
3228 if (tries > 5) {
3229 intel_dp_link_down(intel_dp);
3230 intel_dp_start_link_train(intel_dp);
70aff66c 3231 intel_dp_set_link_train(intel_dp, &DP,
06ea66b6 3232 training_pattern |
70aff66c 3233 DP_LINK_SCRAMBLING_DISABLE);
37f80975
JB		 3234 tries = 0;
3235 cr_tries++;
3236 continue;
3237 }
a4fc5ed6 3238
70aff66c
JN		 3239 /* Update training set as requested by target */
3240 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
3241 DRM_ERROR("failed to update link training\n");
3242 break;
3243 }
3cf2efb1 3244 ++tries;
869184a6 3245 }
3cf2efb1 3246
3ab9c637
ID		 3247 intel_dp_set_idle_link_train(intel_dp);
3248
3249 intel_dp->DP = DP;
3250
d6c0d722 3251 if (channel_eq)
07f42258 3252 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
d6c0d722 3253
3ab9c637
ID		 3254}
3255
3256void intel_dp_stop_link_train(struct intel_dp *intel_dp)
3257{
70aff66c 3258 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3ab9c637 3259 DP_TRAINING_PATTERN_DISABLE);
a4fc5ed6
KP		 3260}
3261
3262static void
ea5b213a 3263intel_dp_link_down(struct intel_dp *intel_dp)
a4fc5ed6 3264{
da63a9f2 3265 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
bc7d38a4 3266 enum port port = intel_dig_port->port;
da63a9f2 3267 struct drm_device *dev = intel_dig_port->base.base.dev;
a4fc5ed6 3268 struct drm_i915_private *dev_priv = dev->dev_private;
ab527efc
DV		 3269 struct intel_crtc *intel_crtc =
3270 to_intel_crtc(intel_dig_port->base.base.crtc);
ea5b213a 3271 uint32_t DP = intel_dp->DP;
a4fc5ed6 3272
bc76e320 3273 if (WARN_ON(HAS_DDI(dev)))
c19b0669
PZ		 3274 return;
3275
0c33d8d7 3276 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1b39d6f3
CW		 3277 return;
3278
28c97730 3279 DRM_DEBUG_KMS("\n");
32f9d658 3280
bc7d38a4 3281 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
e3421a18 3282 DP &= ~DP_LINK_TRAIN_MASK_CPT;
ea5b213a 3283 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
e3421a18 3284 } else {
aad3d14d
VS		 3285 if (IS_CHERRYVIEW(dev))
3286 DP &= ~DP_LINK_TRAIN_MASK_CHV;
3287 else
3288 DP &= ~DP_LINK_TRAIN_MASK;
ea5b213a 3289 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
e3421a18 3290 }
fe255d00 3291 POSTING_READ(intel_dp->output_reg);
5eb08b69 3292
493a7081 3293 if (HAS_PCH_IBX(dev) &&
1b39d6f3 3294 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
da63a9f2 3295 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
31acbcc4 3296
5bddd17f
EA		 3297 /* Hardware workaround: leaving our transcoder select
3298 * set to transcoder B while it's off will prevent the
3299 * corresponding HDMI output on transcoder A.
3300 *
3301 * Combine this with another hardware workaround:
3302 * transcoder select bit can only be cleared while the
3303 * port is enabled.
3304 */
3305 DP &= ~DP_PIPEB_SELECT;
3306 I915_WRITE(intel_dp->output_reg, DP);
3307
3308 /* Changes to enable or select take place the vblank
3309 * after being written.
3310 */
ff50afe9
DV		 3311 if (WARN_ON(crtc == NULL)) {
3312 /* We should never try to disable a port without a crtc
3313 * attached. For paranoia keep the code around for a
3314 * bit. */
31acbcc4
CW		 3315 POSTING_READ(intel_dp->output_reg);
3316 msleep(50);
3317 } else
ab527efc 3318 intel_wait_for_vblank(dev, intel_crtc->pipe);
5bddd17f
EA		 3319 }
3320
832afda6 3321 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
ea5b213a
CW		 3322 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3323 POSTING_READ(intel_dp->output_reg);
f01eca2e 3324 msleep(intel_dp->panel_power_down_delay);
a4fc5ed6
KP		 3325}
3326
26d61aad
KP		 3327static bool
3328intel_dp_get_dpcd(struct intel_dp *intel_dp)
92fd8fd1 3329{
a031d709
RV		 3330 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3331 struct drm_device *dev = dig_port->base.base.dev;
3332 struct drm_i915_private *dev_priv = dev->dev_private;
3333
577c7a50
DL		 3334 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3335
9d1a1031
JN		 3336 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3337 sizeof(intel_dp->dpcd)) < 0)
edb39244 3338 return false; /* aux transfer failed */
92fd8fd1 3339
577c7a50
DL		 3340 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3341 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3342 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3343
edb39244
AJ		 3344 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3345 return false; /* DPCD not present */
3346
2293bb5c
SK		 3347 /* Check if the panel supports PSR */
3348 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
50003939 3349 if (is_edp(intel_dp)) {
9d1a1031
JN		 3350 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3351 intel_dp->psr_dpcd,
3352 sizeof(intel_dp->psr_dpcd));
a031d709
RV		 3353 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3354 dev_priv->psr.sink_support = true;
50003939 3355 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
a031d709 3356 }
50003939
JN		 3357 }
3358
06ea66b6
TP		 3359 /* Training Pattern 3 support */
3360 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3361 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3362 intel_dp->use_tps3 = true;
3363 DRM_DEBUG_KMS("Displayport TPS3 supported");
3364 } else
3365 intel_dp->use_tps3 = false;
3366
edb39244
AJ		 3367 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3368 DP_DWN_STRM_PORT_PRESENT))
3369 return true; /* native DP sink */
3370
3371 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3372 return true; /* no per-port downstream info */
3373
9d1a1031
JN		 3374 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3375 intel_dp->downstream_ports,
3376 DP_MAX_DOWNSTREAM_PORTS) < 0)
edb39244
AJ		 3377 return false; /* downstream port status fetch failed */
3378
3379 return true;
92fd8fd1
KP		 3380}
3381
0d198328
AJ		 3382static void
3383intel_dp_probe_oui(struct intel_dp *intel_dp)
3384{
3385 u8 buf[3];
3386
3387 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3388 return;
3389
24f3e092 3390 intel_edp_panel_vdd_on(intel_dp);
351cfc34 3391
9d1a1031 3392 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
0d198328
AJ		 3393 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3394 buf[0], buf[1], buf[2]);
3395
9d1a1031 3396 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
0d198328
AJ		 3397 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3398 buf[0], buf[1], buf[2]);
351cfc34 3399
4be73780 3400 edp_panel_vdd_off(intel_dp, false);
0d198328
AJ		 3401}
3402
0e32b39c
DA		 3403static bool
3404intel_dp_probe_mst(struct intel_dp *intel_dp)
3405{
3406 u8 buf[1];
3407
3408 if (!intel_dp->can_mst)
3409 return false;
3410
3411 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3412 return false;
3413
3414 _edp_panel_vdd_on(intel_dp);
3415 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3416 if (buf[0] & DP_MST_CAP) {
3417 DRM_DEBUG_KMS("Sink is MST capable\n");
3418 intel_dp->is_mst = true;
3419 } else {
3420 DRM_DEBUG_KMS("Sink is not MST capable\n");
3421 intel_dp->is_mst = false;
3422 }
3423 }
3424 edp_panel_vdd_off(intel_dp, false);
3425
3426 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3427 return intel_dp->is_mst;
3428}
3429
d2e216d0
RV		 3430int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3431{
3432 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3433 struct drm_device *dev = intel_dig_port->base.base.dev;
3434 struct intel_crtc *intel_crtc =
3435 to_intel_crtc(intel_dig_port->base.base.crtc);
3436 u8 buf[1];
3437
9d1a1031 3438 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
d2e216d0
RV		 3439 return -EAGAIN;
3440
3441 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3442 return -ENOTTY;
3443
9d1a1031
JN		 3444 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3445 DP_TEST_SINK_START) < 0)
d2e216d0
RV		 3446 return -EAGAIN;
3447
3448 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3449 intel_wait_for_vblank(dev, intel_crtc->pipe);
3450 intel_wait_for_vblank(dev, intel_crtc->pipe);
3451
9d1a1031 3452 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
d2e216d0
RV		 3453 return -EAGAIN;
3454
9d1a1031 3455 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
d2e216d0
RV		 3456 return 0;
3457}
3458
a60f0e38
JB		 3459static bool
3460intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3461{
9d1a1031
JN		 3462 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3463 DP_DEVICE_SERVICE_IRQ_VECTOR,
3464 sink_irq_vector, 1) == 1;
a60f0e38
JB		 3465}
3466
0e32b39c
DA		 3467static bool
3468intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3469{
3470 int ret;
3471
3472 ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
3473 DP_SINK_COUNT_ESI,
3474 sink_irq_vector, 14);
3475 if (ret != 14)
3476 return false;
3477
3478 return true;
3479}
3480
a60f0e38
JB		 3481static void
3482intel_dp_handle_test_request(struct intel_dp *intel_dp)
3483{
3484 /* NAK by default */
9d1a1031 3485 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
a60f0e38
JB		 3486}
3487
0e32b39c
DA		 3488static int
3489intel_dp_check_mst_status(struct intel_dp *intel_dp)
3490{
3491 bool bret;
3492
3493 if (intel_dp->is_mst) {
3494 u8 esi[16] = { 0 };
3495 int ret = 0;
3496 int retry;
3497 bool handled;
3498 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3499go_again:
3500 if (bret == true) {
3501
3502 /* check link status - esi[10] = 0x200c */
3503 if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
3504 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
3505 intel_dp_start_link_train(intel_dp);
3506 intel_dp_complete_link_train(intel_dp);
3507 intel_dp_stop_link_train(intel_dp);
3508 }
3509
3510 DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3511 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
3512
3513 if (handled) {
3514 for (retry = 0; retry < 3; retry++) {
3515 int wret;
3516 wret = drm_dp_dpcd_write(&intel_dp->aux,
3517 DP_SINK_COUNT_ESI+1,
3518 &esi[1], 3);
3519 if (wret == 3) {
3520 break;
3521 }
3522 }
3523
3524 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
3525 if (bret == true) {
3526 DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
3527 goto go_again;
3528 }
3529 } else
3530 ret = 0;
3531
3532 return ret;
3533 } else {
3534 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3535 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
3536 intel_dp->is_mst = false;
3537 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3538 /* send a hotplug event */
3539 drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
3540 }
3541 }
3542 return -EINVAL;
3543}
3544
a4fc5ed6
KP		 3545/*
3546 * According to DP spec
3547 * 5.1.2:
3548 * 1. Read DPCD
3549 * 2. Configure link according to Receiver Capabilities
3550 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3551 * 4. Check link status on receipt of hot-plug interrupt
3552 */
00c09d70 3553void
ea5b213a 3554intel_dp_check_link_status(struct intel_dp *intel_dp)
a4fc5ed6 3555{
5b215bcf 3556 struct drm_device *dev = intel_dp_to_dev(intel_dp);
da63a9f2 3557 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
a60f0e38 3558 u8 sink_irq_vector;
93f62dad 3559 u8 link_status[DP_LINK_STATUS_SIZE];
a60f0e38 3560
5b215bcf
DA		 3561 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
3562
da63a9f2 3563 if (!intel_encoder->connectors_active)
d2b996ac 3564 return;
59cd09e1 3565
da63a9f2 3566 if (WARN_ON(!intel_encoder->base.crtc))
a4fc5ed6
KP		 3567 return;
3568
1a125d8a
ID		 3569 if (!to_intel_crtc(intel_encoder->base.crtc)->active)
3570 return;
3571
92fd8fd1 3572 /* Try to read receiver status if the link appears to be up */
93f62dad 3573 if (!intel_dp_get_link_status(intel_dp, link_status)) {
a4fc5ed6
KP		 3574 return;
3575 }
3576
92fd8fd1 3577 /* Now read the DPCD to see if it's actually running */
26d61aad 3578 if (!intel_dp_get_dpcd(intel_dp)) {
59cd09e1
JB		 3579 return;
3580 }
3581
a60f0e38
JB		 3582 /* Try to read the source of the interrupt */
3583 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3584 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3585 /* Clear interrupt source */
9d1a1031
JN		 3586 drm_dp_dpcd_writeb(&intel_dp->aux,
3587 DP_DEVICE_SERVICE_IRQ_VECTOR,
3588 sink_irq_vector);
a60f0e38
JB		 3589
3590 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3591 intel_dp_handle_test_request(intel_dp);
3592 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3593 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3594 }
3595
1ffdff13 3596 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
92fd8fd1 3597 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
8e329a03 3598 intel_encoder->base.name);
33a34e4e
JB		 3599 intel_dp_start_link_train(intel_dp);
3600 intel_dp_complete_link_train(intel_dp);
3ab9c637 3601 intel_dp_stop_link_train(intel_dp);
33a34e4e 3602 }
a4fc5ed6 3603}
a4fc5ed6 3604
caf9ab24 3605/* XXX this is probably wrong for multiple downstream ports */
71ba9000 3606static enum drm_connector_status
26d61aad 3607intel_dp_detect_dpcd(struct intel_dp *intel_dp)
71ba9000 3608{
caf9ab24 3609 uint8_t *dpcd = intel_dp->dpcd;
caf9ab24
AJ		 3610 uint8_t type;
3611
3612 if (!intel_dp_get_dpcd(intel_dp))
3613 return connector_status_disconnected;
3614
3615 /* if there's no downstream port, we're done */
3616 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
26d61aad 3617 return connector_status_connected;
caf9ab24
AJ		 3618
3619 /* If we're HPD-aware, SINK_COUNT changes dynamically */
c9ff160b
JN		 3620 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3621 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
23235177 3622 uint8_t reg;
9d1a1031
JN		 3623
3624 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3625 &reg, 1) < 0)
caf9ab24 3626 return connector_status_unknown;
9d1a1031 3627
23235177
AJ		 3628 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3629 : connector_status_disconnected;
caf9ab24
AJ		 3630 }
3631
3632 /* If no HPD, poke DDC gently */
0b99836f 3633 if (drm_probe_ddc(&intel_dp->aux.ddc))
26d61aad 3634 return connector_status_connected;
caf9ab24
AJ		 3635
3636 /* Well we tried, say unknown for unreliable port types */
c9ff160b
JN		 3637 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3638 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3639 if (type == DP_DS_PORT_TYPE_VGA ||
3640 type == DP_DS_PORT_TYPE_NON_EDID)
3641 return connector_status_unknown;
3642 } else {
3643 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3644 DP_DWN_STRM_PORT_TYPE_MASK;
3645 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3646 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3647 return connector_status_unknown;
3648 }
caf9ab24
AJ		 3649
3650 /* Anything else is out of spec, warn and ignore */
3651 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
26d61aad 3652 return connector_status_disconnected;
71ba9000
AJ		 3653}
3654
5eb08b69 3655static enum drm_connector_status
a9756bb5 3656ironlake_dp_detect(struct intel_dp *intel_dp)
5eb08b69 3657{
30add22d 3658 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1b469639
DL		 3659 struct drm_i915_private *dev_priv = dev->dev_private;
3660 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5eb08b69
ZW		 3661 enum drm_connector_status status;
3662
fe16d949
CW		 3663 /* Can't disconnect eDP, but you can close the lid... */
3664 if (is_edp(intel_dp)) {
30add22d 3665 status = intel_panel_detect(dev);
fe16d949
CW		 3666 if (status == connector_status_unknown)
3667 status = connector_status_connected;
3668 return status;
3669 }
01cb9ea6 3670
1b469639
DL		 3671 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3672 return connector_status_disconnected;
3673
26d61aad 3674 return intel_dp_detect_dpcd(intel_dp);
5eb08b69
ZW		 3675}
3676
a4fc5ed6 3677static enum drm_connector_status
a9756bb5 3678g4x_dp_detect(struct intel_dp *intel_dp)
a4fc5ed6 3679{
30add22d 3680 struct drm_device *dev = intel_dp_to_dev(intel_dp);
a4fc5ed6 3681 struct drm_i915_private *dev_priv = dev->dev_private;
34f2be46 3682 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
10f76a38 3683 uint32_t bit;
5eb08b69 3684
35aad75f
JB		 3685 /* Can't disconnect eDP, but you can close the lid... */
3686 if (is_edp(intel_dp)) {
3687 enum drm_connector_status status;
3688
3689 status = intel_panel_detect(dev);
3690 if (status == connector_status_unknown)
3691 status = connector_status_connected;
3692 return status;
3693 }
3694
232a6ee9
TP		 3695 if (IS_VALLEYVIEW(dev)) {
3696 switch (intel_dig_port->port) {
3697 case PORT_B:
3698 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3699 break;
3700 case PORT_C:
3701 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3702 break;
3703 case PORT_D:
3704 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3705 break;
3706 default:
3707 return connector_status_unknown;
3708 }
3709 } else {
3710 switch (intel_dig_port->port) {
3711 case PORT_B:
3712 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3713 break;
3714 case PORT_C:
3715 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3716 break;
3717 case PORT_D:
3718 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3719 break;
3720 default:
3721 return connector_status_unknown;
3722 }
a4fc5ed6
KP		 3723 }
3724
10f76a38 3725 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
a4fc5ed6
KP		 3726 return connector_status_disconnected;
3727
26d61aad 3728 return intel_dp_detect_dpcd(intel_dp);
a9756bb5
ZW		 3729}
3730
8c241fef
KP		 3731static struct edid *
3732intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3733{
9cd300e0 3734 struct intel_connector *intel_connector = to_intel_connector(connector);
d6f24d0f 3735
9cd300e0
JN		 3736 /* use cached edid if we have one */
3737 if (intel_connector->edid) {
9cd300e0
JN		 3738 /* invalid edid */
3739 if (IS_ERR(intel_connector->edid))
d6f24d0f
JB		 3740 return NULL;
3741
55e9edeb 3742 return drm_edid_duplicate(intel_connector->edid);
d6f24d0f 3743 }
8c241fef 3744
9cd300e0 3745 return drm_get_edid(connector, adapter);
8c241fef
KP		 3746}
3747
3748static int
3749intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3750{
9cd300e0 3751 struct intel_connector *intel_connector = to_intel_connector(connector);
8c241fef 3752
9cd300e0
JN		 3753 /* use cached edid if we have one */
3754 if (intel_connector->edid) {
3755 /* invalid edid */
3756 if (IS_ERR(intel_connector->edid))
3757 return 0;
3758
3759 return intel_connector_update_modes(connector,
3760 intel_connector->edid);
d6f24d0f
JB		 3761 }
3762
9cd300e0 3763 return intel_ddc_get_modes(connector, adapter);
8c241fef
KP		 3764}
3765
a9756bb5
ZW		 3766static enum drm_connector_status
3767intel_dp_detect(struct drm_connector *connector, bool force)
3768{
3769 struct intel_dp *intel_dp = intel_attached_dp(connector);
d63885da
PZ		 3770 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3771 struct intel_encoder *intel_encoder = &intel_dig_port->base;
fa90ecef 3772 struct drm_device *dev = connector->dev;
c8c8fb33 3773 struct drm_i915_private *dev_priv = dev->dev_private;
a9756bb5 3774 enum drm_connector_status status;
671dedd2 3775 enum intel_display_power_domain power_domain;
a9756bb5 3776 struct edid *edid = NULL;
0e32b39c 3777 bool ret;
a9756bb5 3778
671dedd2
ID		 3779 power_domain = intel_display_port_power_domain(intel_encoder);
3780 intel_display_power_get(dev_priv, power_domain);
3781
164c8598 3782 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 3783 connector->base.id, connector->name);
164c8598 3784
0e32b39c
DA		 3785 if (intel_dp->is_mst) {
3786 /* MST devices are disconnected from a monitor POV */
3787 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3788 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3789 status = connector_status_disconnected;
3790 goto out;
3791 }
3792
a9756bb5
ZW		 3793 intel_dp->has_audio = false;
3794
3795 if (HAS_PCH_SPLIT(dev))
3796 status = ironlake_dp_detect(intel_dp);
3797 else
3798 status = g4x_dp_detect(intel_dp);
1b9be9d0 3799
a9756bb5 3800 if (status != connector_status_connected)
c8c8fb33 3801 goto out;
a9756bb5 3802
0d198328
AJ		 3803 intel_dp_probe_oui(intel_dp);
3804
0e32b39c
DA		 3805 ret = intel_dp_probe_mst(intel_dp);
3806 if (ret) {
3807 /* if we are in MST mode then this connector
3808 won't appear connected or have anything with EDID on it */
3809 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3810 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3811 status = connector_status_disconnected;
3812 goto out;
3813 }
3814
c3e5f67b
DV		 3815 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3816 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
f684960e 3817 } else {
0b99836f 3818 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
f684960e
CW		 3819 if (edid) {
3820 intel_dp->has_audio = drm_detect_monitor_audio(edid);
f684960e
CW		 3821 kfree(edid);
3822 }
a9756bb5
ZW		 3823 }
3824
d63885da
PZ		 3825 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3826 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
c8c8fb33
PZ		 3827 status = connector_status_connected;
3828
3829out:
671dedd2 3830 intel_display_power_put(dev_priv, power_domain);
c8c8fb33 3831 return status;
a4fc5ed6
KP		 3832}
3833
3834static int intel_dp_get_modes(struct drm_connector *connector)
3835{
df0e9248 3836 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3837 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3838 struct intel_encoder *intel_encoder = &intel_dig_port->base;
dd06f90e 3839 struct intel_connector *intel_connector = to_intel_connector(connector);
fa90ecef 3840 struct drm_device *dev = connector->dev;
671dedd2
ID		 3841 struct drm_i915_private *dev_priv = dev->dev_private;
3842 enum intel_display_power_domain power_domain;
32f9d658 3843 int ret;
a4fc5ed6
KP		 3844
3845 /* We should parse the EDID data and find out if it has an audio sink
3846 */
3847
671dedd2
ID		 3848 power_domain = intel_display_port_power_domain(intel_encoder);
3849 intel_display_power_get(dev_priv, power_domain);
3850
0b99836f 3851 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
671dedd2 3852 intel_display_power_put(dev_priv, power_domain);
f8779fda 3853 if (ret)
32f9d658
ZW		 3854 return ret;
3855
f8779fda 3856 /* if eDP has no EDID, fall back to fixed mode */
dd06f90e 3857 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
f8779fda 3858 struct drm_display_mode *mode;
dd06f90e
JN		 3859 mode = drm_mode_duplicate(dev,
3860 intel_connector->panel.fixed_mode);
f8779fda 3861 if (mode) {
32f9d658
ZW		 3862 drm_mode_probed_add(connector, mode);
3863 return 1;
3864 }
3865 }
3866 return 0;
a4fc5ed6
KP		 3867}
3868
1aad7ac0
CW		 3869static bool
3870intel_dp_detect_audio(struct drm_connector *connector)
3871{
3872 struct intel_dp *intel_dp = intel_attached_dp(connector);
671dedd2
ID		 3873 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3874 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3875 struct drm_device *dev = connector->dev;
3876 struct drm_i915_private *dev_priv = dev->dev_private;
3877 enum intel_display_power_domain power_domain;
1aad7ac0
CW		 3878 struct edid *edid;
3879 bool has_audio = false;
3880
671dedd2
ID		 3881 power_domain = intel_display_port_power_domain(intel_encoder);
3882 intel_display_power_get(dev_priv, power_domain);
3883
0b99836f 3884 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
1aad7ac0
CW		 3885 if (edid) {
3886 has_audio = drm_detect_monitor_audio(edid);
1aad7ac0
CW		 3887 kfree(edid);
3888 }
3889
671dedd2
ID		 3890 intel_display_power_put(dev_priv, power_domain);
3891
1aad7ac0
CW		 3892 return has_audio;
3893}
3894
f684960e
CW		 3895static int
3896intel_dp_set_property(struct drm_connector *connector,
3897 struct drm_property *property,
3898 uint64_t val)
3899{
e953fd7b 3900 struct drm_i915_private *dev_priv = connector->dev->dev_private;
53b41837 3901 struct intel_connector *intel_connector = to_intel_connector(connector);
da63a9f2
PZ		 3902 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3903 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
f684960e
CW		 3904 int ret;
3905
662595df 3906 ret = drm_object_property_set_value(&connector->base, property, val);
f684960e
CW		 3907 if (ret)
3908 return ret;
3909
3f43c48d 3910 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 3911 int i = val;
3912 bool has_audio;
3913
3914 if (i == intel_dp->force_audio)
f684960e
CW		 3915 return 0;
3916
1aad7ac0 3917 intel_dp->force_audio = i;
f684960e 3918
c3e5f67b 3919 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 3920 has_audio = intel_dp_detect_audio(connector);
3921 else
c3e5f67b 3922 has_audio = (i == HDMI_AUDIO_ON);
1aad7ac0
CW		 3923
3924 if (has_audio == intel_dp->has_audio)
f684960e
CW		 3925 return 0;
3926
1aad7ac0 3927 intel_dp->has_audio = has_audio;
f684960e
CW		 3928 goto done;
3929 }
3930
e953fd7b 3931 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 3932 bool old_auto = intel_dp->color_range_auto;
3933 uint32_t old_range = intel_dp->color_range;
3934
55bc60db
VS		 3935 switch (val) {
3936 case INTEL_BROADCAST_RGB_AUTO:
3937 intel_dp->color_range_auto = true;
3938 break;
3939 case INTEL_BROADCAST_RGB_FULL:
3940 intel_dp->color_range_auto = false;
3941 intel_dp->color_range = 0;
3942 break;
3943 case INTEL_BROADCAST_RGB_LIMITED:
3944 intel_dp->color_range_auto = false;
3945 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3946 break;
3947 default:
3948 return -EINVAL;
3949 }
ae4edb80
DV		 3950
3951 if (old_auto == intel_dp->color_range_auto &&
3952 old_range == intel_dp->color_range)
3953 return 0;
3954
e953fd7b
CW		 3955 goto done;
3956 }
3957
53b41837
YN		 3958 if (is_edp(intel_dp) &&
3959 property == connector->dev->mode_config.scaling_mode_property) {
3960 if (val == DRM_MODE_SCALE_NONE) {
3961 DRM_DEBUG_KMS("no scaling not supported\n");
3962 return -EINVAL;
3963 }
3964
3965 if (intel_connector->panel.fitting_mode == val) {
3966 /* the eDP scaling property is not changed */
3967 return 0;
3968 }
3969 intel_connector->panel.fitting_mode = val;
3970
3971 goto done;
3972 }
3973
f684960e
CW		 3974 return -EINVAL;
3975
3976done:
c0c36b94
CW		 3977 if (intel_encoder->base.crtc)
3978 intel_crtc_restore_mode(intel_encoder->base.crtc);
f684960e
CW		 3979
3980 return 0;
3981}
3982
a4fc5ed6 3983static void
73845adf 3984intel_dp_connector_destroy(struct drm_connector *connector)
a4fc5ed6 3985{
1d508706 3986 struct intel_connector *intel_connector = to_intel_connector(connector);
aaa6fd2a 3987
9cd300e0
JN		 3988 if (!IS_ERR_OR_NULL(intel_connector->edid))
3989 kfree(intel_connector->edid);
3990
acd8db10
PZ		 3991 /* Can't call is_edp() since the encoder may have been destroyed
3992 * already. */
3993 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
1d508706 3994 intel_panel_fini(&intel_connector->panel);
aaa6fd2a 3995
a4fc5ed6 3996 drm_connector_cleanup(connector);
55f78c43 3997 kfree(connector);
a4fc5ed6
KP		 3998}
3999
00c09d70 4000void intel_dp_encoder_destroy(struct drm_encoder *encoder)
24d05927 4001{
da63a9f2
PZ		 4002 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4003 struct intel_dp *intel_dp = &intel_dig_port->dp;
bd173813 4004 struct drm_device *dev = intel_dp_to_dev(intel_dp);
24d05927 4005
4f71d0cb 4006 drm_dp_aux_unregister(&intel_dp->aux);
0e32b39c 4007 intel_dp_mst_encoder_cleanup(intel_dig_port);
24d05927 4008 drm_encoder_cleanup(encoder);
bd943159
KP		 4009 if (is_edp(intel_dp)) {
4010 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4011 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4012 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4013 drm_modeset_unlock(&dev->mode_config.connection_mutex);
01527b31
CT		 4014 if (intel_dp->edp_notifier.notifier_call) {
4015 unregister_reboot_notifier(&intel_dp->edp_notifier);
4016 intel_dp->edp_notifier.notifier_call = NULL;
4017 }
bd943159 4018 }
da63a9f2 4019 kfree(intel_dig_port);
24d05927
DV		 4020}
4021
07f9cd0b
ID		 4022static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4023{
4024 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4025
4026 if (!is_edp(intel_dp))
4027 return;
4028
4029 edp_panel_vdd_off_sync(intel_dp);
4030}
4031
6d93c0c4
ID		 4032static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4033{
4034 intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
4035}
4036
a4fc5ed6 4037static const struct drm_connector_funcs intel_dp_connector_funcs = {
2bd2ad64 4038 .dpms = intel_connector_dpms,
a4fc5ed6
KP		 4039 .detect = intel_dp_detect,
4040 .fill_modes = drm_helper_probe_single_connector_modes,
f684960e 4041 .set_property = intel_dp_set_property,
73845adf 4042 .destroy = intel_dp_connector_destroy,
a4fc5ed6
KP		 4043};
4044
4045static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4046 .get_modes = intel_dp_get_modes,
4047 .mode_valid = intel_dp_mode_valid,
df0e9248 4048 .best_encoder = intel_best_encoder,
a4fc5ed6
KP		 4049};
4050
a4fc5ed6 4051static const struct drm_encoder_funcs intel_dp_enc_funcs = {
6d93c0c4 4052 .reset = intel_dp_encoder_reset,
24d05927 4053 .destroy = intel_dp_encoder_destroy,
a4fc5ed6
KP		 4054};
4055
0e32b39c 4056void
21d40d37 4057intel_dp_hot_plug(struct intel_encoder *intel_encoder)
c8110e52 4058{
0e32b39c 4059 return;
c8110e52 4060}
6207937d 4061
13cf5504
DA		 4062bool
4063intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4064{
4065 struct intel_dp *intel_dp = &intel_dig_port->dp;
1c767b33 4066 struct intel_encoder *intel_encoder = &intel_dig_port->base;
0e32b39c
DA		 4067 struct drm_device *dev = intel_dig_port->base.base.dev;
4068 struct drm_i915_private *dev_priv = dev->dev_private;
1c767b33
ID		 4069 enum intel_display_power_domain power_domain;
4070 bool ret = true;
4071
0e32b39c
DA		 4072 if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
4073 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
13cf5504 4074
26fbb774
VS		 4075 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
4076 port_name(intel_dig_port->port),
0e32b39c 4077 long_hpd ? "long" : "short");
13cf5504 4078
1c767b33
ID		 4079 power_domain = intel_display_port_power_domain(intel_encoder);
4080 intel_display_power_get(dev_priv, power_domain);
4081
0e32b39c
DA		 4082 if (long_hpd) {
4083 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
4084 goto mst_fail;
4085
4086 if (!intel_dp_get_dpcd(intel_dp)) {
4087 goto mst_fail;
4088 }
4089
4090 intel_dp_probe_oui(intel_dp);
4091
4092 if (!intel_dp_probe_mst(intel_dp))
4093 goto mst_fail;
4094
4095 } else {
4096 if (intel_dp->is_mst) {
1c767b33 4097 if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
0e32b39c
DA		 4098 goto mst_fail;
4099 }
4100
4101 if (!intel_dp->is_mst) {
4102 /*
4103 * we'll check the link status via the normal hot plug path later -
4104 * but for short hpds we should check it now
4105 */
5b215bcf 4106 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
0e32b39c 4107 intel_dp_check_link_status(intel_dp);
5b215bcf 4108 drm_modeset_unlock(&dev->mode_config.connection_mutex);
0e32b39c
DA		 4109 }
4110 }
1c767b33
ID		 4111 ret = false;
4112 goto put_power;
0e32b39c
DA		 4113mst_fail:
4114 /* if we were in MST mode, and device is not there get out of MST mode */
4115 if (intel_dp->is_mst) {
4116 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
4117 intel_dp->is_mst = false;
4118 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4119 }
1c767b33
ID		 4120put_power:
4121 intel_display_power_put(dev_priv, power_domain);
4122
4123 return ret;
13cf5504
DA		 4124}
4125
e3421a18
ZW		 4126/* Return which DP Port should be selected for Transcoder DP control */
4127int
0206e353 4128intel_trans_dp_port_sel(struct drm_crtc *crtc)
e3421a18
ZW		 4129{
4130 struct drm_device *dev = crtc->dev;
fa90ecef
PZ		 4131 struct intel_encoder *intel_encoder;
4132 struct intel_dp *intel_dp;
e3421a18 4133
fa90ecef
PZ		 4134 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4135 intel_dp = enc_to_intel_dp(&intel_encoder->base);
e3421a18 4136
fa90ecef
PZ		 4137 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4138 intel_encoder->type == INTEL_OUTPUT_EDP)
ea5b213a 4139 return intel_dp->output_reg;
e3421a18 4140 }
ea5b213a 4141
e3421a18
ZW		 4142 return -1;
4143}
4144
36e83a18 4145/* check the VBT to see whether the eDP is on DP-D port */
5d8a7752 4146bool intel_dp_is_edp(struct drm_device *dev, enum port port)
36e83a18
ZY		 4147{
4148 struct drm_i915_private *dev_priv = dev->dev_private;
768f69c9 4149 union child_device_config *p_child;
36e83a18 4150 int i;
5d8a7752
VS		 4151 static const short port_mapping[] = {
4152 [PORT_B] = PORT_IDPB,
4153 [PORT_C] = PORT_IDPC,
4154 [PORT_D] = PORT_IDPD,
4155 };
36e83a18 4156
3b32a35b
VS		 4157 if (port == PORT_A)
4158 return true;
4159
41aa3448 4160 if (!dev_priv->vbt.child_dev_num)
36e83a18
ZY		 4161 return false;
4162
41aa3448
RV		 4163 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
4164 p_child = dev_priv->vbt.child_dev + i;
36e83a18 4165
5d8a7752 4166 if (p_child->common.dvo_port == port_mapping[port] &&
f02586df
VS		 4167 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
4168 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
36e83a18
ZY		 4169 return true;
4170 }
4171 return false;
4172}
4173
0e32b39c 4174void
f684960e
CW		 4175intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
4176{
53b41837
YN		 4177 struct intel_connector *intel_connector = to_intel_connector(connector);
4178
3f43c48d 4179 intel_attach_force_audio_property(connector);
e953fd7b 4180 intel_attach_broadcast_rgb_property(connector);
55bc60db 4181 intel_dp->color_range_auto = true;
53b41837
YN		 4182
4183 if (is_edp(intel_dp)) {
4184 drm_mode_create_scaling_mode_property(connector->dev);
6de6d846
RC		 4185 drm_object_attach_property(
4186 &connector->base,
53b41837 4187 connector->dev->mode_config.scaling_mode_property,
8e740cd1
YN		 4188 DRM_MODE_SCALE_ASPECT);
4189 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
53b41837 4190 }
f684960e
CW		 4191}
4192
dada1a9f
ID		 4193static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
4194{
4195 intel_dp->last_power_cycle = jiffies;
4196 intel_dp->last_power_on = jiffies;
4197 intel_dp->last_backlight_off = jiffies;
4198}
4199
67a54566
DV		 4200static void
4201intel_dp_init_panel_power_sequencer(struct drm_device *dev,
f30d26e4
JN		 4202 struct intel_dp *intel_dp,
4203 struct edp_power_seq *out)
67a54566
DV		 4204{
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206 struct edp_power_seq cur, vbt, spec, final;
4207 u32 pp_on, pp_off, pp_div, pp;
bf13e81b 4208 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
453c5420
JB		 4209
4210 if (HAS_PCH_SPLIT(dev)) {
bf13e81b 4211 pp_ctrl_reg = PCH_PP_CONTROL;
453c5420
JB		 4212 pp_on_reg = PCH_PP_ON_DELAYS;
4213 pp_off_reg = PCH_PP_OFF_DELAYS;
4214 pp_div_reg = PCH_PP_DIVISOR;
4215 } else {
bf13e81b
JN		 4216 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4217
4218 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
4219 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4220 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4221 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420 4222 }
67a54566
DV		 4223
4224 /* Workaround: Need to write PP_CONTROL with the unlock key as
4225 * the very first thing. */
453c5420 4226 pp = ironlake_get_pp_control(intel_dp);
bf13e81b 4227 I915_WRITE(pp_ctrl_reg, pp);
67a54566 4228
453c5420
JB		 4229 pp_on = I915_READ(pp_on_reg);
4230 pp_off = I915_READ(pp_off_reg);
4231 pp_div = I915_READ(pp_div_reg);
67a54566
DV		 4232
4233 /* Pull timing values out of registers */
4234 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
4235 PANEL_POWER_UP_DELAY_SHIFT;
4236
4237 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
4238 PANEL_LIGHT_ON_DELAY_SHIFT;
4239
4240 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
4241 PANEL_LIGHT_OFF_DELAY_SHIFT;
4242
4243 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
4244 PANEL_POWER_DOWN_DELAY_SHIFT;
4245
4246 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
4247 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
4248
4249 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4250 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
4251
41aa3448 4252 vbt = dev_priv->vbt.edp_pps;
67a54566
DV		 4253
4254 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
4255 * our hw here, which are all in 100usec. */
4256 spec.t1_t3 = 210 * 10;
4257 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
4258 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
4259 spec.t10 = 500 * 10;
4260 /* This one is special and actually in units of 100ms, but zero
4261 * based in the hw (so we need to add 100 ms). But the sw vbt
4262 * table multiplies it with 1000 to make it in units of 100usec,
4263 * too. */
4264 spec.t11_t12 = (510 + 100) * 10;
4265
4266 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
4267 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
4268
4269 /* Use the max of the register settings and vbt. If both are
4270 * unset, fall back to the spec limits. */
4271#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
4272 spec.field : \
4273 max(cur.field, vbt.field))
4274 assign_final(t1_t3);
4275 assign_final(t8);
4276 assign_final(t9);
4277 assign_final(t10);
4278 assign_final(t11_t12);
4279#undef assign_final
4280
4281#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
4282 intel_dp->panel_power_up_delay = get_delay(t1_t3);
4283 intel_dp->backlight_on_delay = get_delay(t8);
4284 intel_dp->backlight_off_delay = get_delay(t9);
4285 intel_dp->panel_power_down_delay = get_delay(t10);
4286 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
4287#undef get_delay
4288
f30d26e4
JN		 4289 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
4290 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
4291 intel_dp->panel_power_cycle_delay);
4292
4293 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
4294 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
4295
4296 if (out)
4297 *out = final;
4298}
4299
4300static void
4301intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4302 struct intel_dp *intel_dp,
4303 struct edp_power_seq *seq)
4304{
4305 struct drm_i915_private *dev_priv = dev->dev_private;
453c5420
JB		 4306 u32 pp_on, pp_off, pp_div, port_sel = 0;
4307 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
4308 int pp_on_reg, pp_off_reg, pp_div_reg;
4309
4310 if (HAS_PCH_SPLIT(dev)) {
4311 pp_on_reg = PCH_PP_ON_DELAYS;
4312 pp_off_reg = PCH_PP_OFF_DELAYS;
4313 pp_div_reg = PCH_PP_DIVISOR;
4314 } else {
bf13e81b
JN		 4315 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
4316
4317 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
4318 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
4319 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
453c5420
JB		 4320 }
4321
b2f19d1a
PZ		 4322 /*
4323 * And finally store the new values in the power sequencer. The
4324 * backlight delays are set to 1 because we do manual waits on them. For
4325 * T8, even BSpec recommends doing it. For T9, if we don't do this,
4326 * we'll end up waiting for the backlight off delay twice: once when we
4327 * do the manual sleep, and once when we disable the panel and wait for
4328 * the PP_STATUS bit to become zero.
4329 */
f30d26e4 4330 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
b2f19d1a
PZ		 4331 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
4332 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
f30d26e4 4333 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
67a54566
DV		 4334 /* Compute the divisor for the pp clock, simply match the Bspec
4335 * formula. */
453c5420 4336 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
f30d26e4 4337 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
67a54566
DV		 4338 << PANEL_POWER_CYCLE_DELAY_SHIFT);
4339
4340 /* Haswell doesn't have any port selection bits for the panel
4341 * power sequencer any more. */
bc7d38a4 4342 if (IS_VALLEYVIEW(dev)) {
bf13e81b
JN		 4343 if (dp_to_dig_port(intel_dp)->port == PORT_B)
4344 port_sel = PANEL_PORT_SELECT_DPB_VLV;
4345 else
4346 port_sel = PANEL_PORT_SELECT_DPC_VLV;
bc7d38a4
ID		 4347 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4348 if (dp_to_dig_port(intel_dp)->port == PORT_A)
a24c144c 4349 port_sel = PANEL_PORT_SELECT_DPA;
67a54566 4350 else
a24c144c 4351 port_sel = PANEL_PORT_SELECT_DPD;
67a54566
DV		 4352 }
4353
453c5420
JB		 4354 pp_on |= port_sel;
4355
4356 I915_WRITE(pp_on_reg, pp_on);
4357 I915_WRITE(pp_off_reg, pp_off);
4358 I915_WRITE(pp_div_reg, pp_div);
67a54566 4359
67a54566 4360 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
453c5420
JB		 4361 I915_READ(pp_on_reg),
4362 I915_READ(pp_off_reg),
4363 I915_READ(pp_div_reg));
f684960e
CW		 4364}
4365
439d7ac0
PB		 4366void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
4367{
4368 struct drm_i915_private *dev_priv = dev->dev_private;
4369 struct intel_encoder *encoder;
4370 struct intel_dp *intel_dp = NULL;
4371 struct intel_crtc_config *config = NULL;
4372 struct intel_crtc *intel_crtc = NULL;
4373 struct intel_connector *intel_connector = dev_priv->drrs.connector;
4374 u32 reg, val;
4375 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
4376
4377 if (refresh_rate <= 0) {
4378 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
4379 return;
4380 }
4381
4382 if (intel_connector == NULL) {
4383 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
4384 return;
4385 }
4386
1fcc9d1c
DV		 4387 /*
4388 * FIXME: This needs proper synchronization with psr state. But really
4389 * hard to tell without seeing the user of this function of this code.
4390 * Check locking and ordering once that lands.
4391 */
439d7ac0
PB		 4392 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
4393 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
4394 return;
4395 }
4396
4397 encoder = intel_attached_encoder(&intel_connector->base);
4398 intel_dp = enc_to_intel_dp(&encoder->base);
4399 intel_crtc = encoder->new_crtc;
4400
4401 if (!intel_crtc) {
4402 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
4403 return;
4404 }
4405
4406 config = &intel_crtc->config;
4407
4408 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
4409 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
4410 return;
4411 }
4412
4413 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
4414 index = DRRS_LOW_RR;
4415
4416 if (index == intel_dp->drrs_state.refresh_rate_type) {
4417 DRM_DEBUG_KMS(
4418 "DRRS requested for previously set RR...ignoring\n");
4419 return;
4420 }
4421
4422 if (!intel_crtc->active) {
4423 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
4424 return;
4425 }
4426
4427 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
4428 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
4429 val = I915_READ(reg);
4430 if (index > DRRS_HIGH_RR) {
4431 val |= PIPECONF_EDP_RR_MODE_SWITCH;
f769cd24 4432 intel_dp_set_m_n(intel_crtc);
439d7ac0
PB		 4433 } else {
4434 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
4435 }
4436 I915_WRITE(reg, val);
4437 }
4438
4439 /*
4440 * mutex taken to ensure that there is no race between differnt
4441 * drrs calls trying to update refresh rate. This scenario may occur
4442 * in future when idleness detection based DRRS in kernel and
4443 * possible calls from user space to set differnt RR are made.
4444 */
4445
4446 mutex_lock(&intel_dp->drrs_state.mutex);
4447
4448 intel_dp->drrs_state.refresh_rate_type = index;
4449
4450 mutex_unlock(&intel_dp->drrs_state.mutex);
4451
4452 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
4453}
4454
4f9db5b5
PB		 4455static struct drm_display_mode *
4456intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
4457 struct intel_connector *intel_connector,
4458 struct drm_display_mode *fixed_mode)
4459{
4460 struct drm_connector *connector = &intel_connector->base;
4461 struct intel_dp *intel_dp = &intel_dig_port->dp;
4462 struct drm_device *dev = intel_dig_port->base.base.dev;
4463 struct drm_i915_private *dev_priv = dev->dev_private;
4464 struct drm_display_mode *downclock_mode = NULL;
4465
4466 if (INTEL_INFO(dev)->gen <= 6) {
4467 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4468 return NULL;
4469 }
4470
4471 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4079b8d1 4472 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4f9db5b5
PB		 4473 return NULL;
4474 }
4475
4476 downclock_mode = intel_find_panel_downclock
4477 (dev, fixed_mode, connector);
4478
4479 if (!downclock_mode) {
4079b8d1 4480 DRM_DEBUG_KMS("DRRS not supported\n");
4f9db5b5
PB		 4481 return NULL;
4482 }
4483
439d7ac0
PB		 4484 dev_priv->drrs.connector = intel_connector;
4485
4486 mutex_init(&intel_dp->drrs_state.mutex);
4487
4f9db5b5
PB		 4488 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4489
4490 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4079b8d1 4491 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4f9db5b5
PB		 4492 return downclock_mode;
4493}
4494
aba86890
ID		 4495void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
4496{
4497 struct drm_device *dev = intel_encoder->base.dev;
4498 struct drm_i915_private *dev_priv = dev->dev_private;
4499 struct intel_dp *intel_dp;
4500 enum intel_display_power_domain power_domain;
4501
4502 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4503 return;
4504
4505 intel_dp = enc_to_intel_dp(&intel_encoder->base);
4506 if (!edp_have_panel_vdd(intel_dp))
4507 return;
4508 /*
4509 * The VDD bit needs a power domain reference, so if the bit is
4510 * already enabled when we boot or resume, grab this reference and
4511 * schedule a vdd off, so we don't hold on to the reference
4512 * indefinitely.
4513 */
4514 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4515 power_domain = intel_display_port_power_domain(intel_encoder);
4516 intel_display_power_get(dev_priv, power_domain);
4517
4518 edp_panel_vdd_schedule_off(intel_dp);
4519}
4520
ed92f0b2 4521static bool intel_edp_init_connector(struct intel_dp *intel_dp,
0095e6dc
PZ		 4522 struct intel_connector *intel_connector,
4523 struct edp_power_seq *power_seq)
ed92f0b2
PZ		 4524{
4525 struct drm_connector *connector = &intel_connector->base;
4526 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
63635217
PZ		 4527 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4528 struct drm_device *dev = intel_encoder->base.dev;
ed92f0b2
PZ		 4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 struct drm_display_mode *fixed_mode = NULL;
4f9db5b5 4531 struct drm_display_mode *downclock_mode = NULL;
ed92f0b2
PZ		 4532 bool has_dpcd;
4533 struct drm_display_mode *scan;
4534 struct edid *edid;
4535
4f9db5b5
PB		 4536 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4537
ed92f0b2
PZ		 4538 if (!is_edp(intel_dp))
4539 return true;
4540
aba86890 4541 intel_edp_panel_vdd_sanitize(intel_encoder);
63635217 4542
ed92f0b2 4543 /* Cache DPCD and EDID for edp. */
24f3e092 4544 intel_edp_panel_vdd_on(intel_dp);
ed92f0b2 4545 has_dpcd = intel_dp_get_dpcd(intel_dp);
4be73780 4546 edp_panel_vdd_off(intel_dp, false);
ed92f0b2
PZ		 4547
4548 if (has_dpcd) {
4549 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4550 dev_priv->no_aux_handshake =
4551 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4552 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4553 } else {
4554 /* if this fails, presume the device is a ghost */
4555 DRM_INFO("failed to retrieve link info, disabling eDP\n");
ed92f0b2
PZ		 4556 return false;
4557 }
4558
4559 /* We now know it's not a ghost, init power sequence regs. */
0095e6dc 4560 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
ed92f0b2 4561
060c8778 4562 mutex_lock(&dev->mode_config.mutex);
0b99836f 4563 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
ed92f0b2
PZ		 4564 if (edid) {
4565 if (drm_add_edid_modes(connector, edid)) {
4566 drm_mode_connector_update_edid_property(connector,
4567 edid);
4568 drm_edid_to_eld(connector, edid);
4569 } else {
4570 kfree(edid);
4571 edid = ERR_PTR(-EINVAL);
4572 }
4573 } else {
4574 edid = ERR_PTR(-ENOENT);
4575 }
4576 intel_connector->edid = edid;
4577
4578 /* prefer fixed mode from EDID if available */
4579 list_for_each_entry(scan, &connector->probed_modes, head) {
4580 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4581 fixed_mode = drm_mode_duplicate(dev, scan);
4f9db5b5
PB		 4582 downclock_mode = intel_dp_drrs_init(
4583 intel_dig_port,
4584 intel_connector, fixed_mode);
ed92f0b2
PZ		 4585 break;
4586 }
4587 }
4588
4589 /* fallback to VBT if available for eDP */
4590 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4591 fixed_mode = drm_mode_duplicate(dev,
4592 dev_priv->vbt.lfp_lvds_vbt_mode);
4593 if (fixed_mode)
4594 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4595 }
060c8778 4596 mutex_unlock(&dev->mode_config.mutex);
ed92f0b2 4597
01527b31
CT		 4598 if (IS_VALLEYVIEW(dev)) {
4599 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
4600 register_reboot_notifier(&intel_dp->edp_notifier);
4601 }
4602
4f9db5b5 4603 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
ed92f0b2
PZ		 4604 intel_panel_setup_backlight(connector);
4605
4606 return true;
4607}
4608
16c25533 4609bool
f0fec3f2
PZ		 4610intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4611 struct intel_connector *intel_connector)
a4fc5ed6 4612{
f0fec3f2
PZ		 4613 struct drm_connector *connector = &intel_connector->base;
4614 struct intel_dp *intel_dp = &intel_dig_port->dp;
4615 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4616 struct drm_device *dev = intel_encoder->base.dev;
a4fc5ed6 4617 struct drm_i915_private *dev_priv = dev->dev_private;
174edf1f 4618 enum port port = intel_dig_port->port;
0095e6dc 4619 struct edp_power_seq power_seq = { 0 };
0b99836f 4620 int type;
a4fc5ed6 4621
ec5b01dd
DL		 4622 /* intel_dp vfuncs */
4623 if (IS_VALLEYVIEW(dev))
4624 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4625 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4626 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4627 else if (HAS_PCH_SPLIT(dev))
4628 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4629 else
4630 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4631
153b1100
DL		 4632 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4633
0767935e
DV		 4634 /* Preserve the current hw state. */
4635 intel_dp->DP = I915_READ(intel_dp->output_reg);
dd06f90e 4636 intel_dp->attached_connector = intel_connector;
3d3dc149 4637
3b32a35b 4638 if (intel_dp_is_edp(dev, port))
b329530c 4639 type = DRM_MODE_CONNECTOR_eDP;
3b32a35b
VS		 4640 else
4641 type = DRM_MODE_CONNECTOR_DisplayPort;
b329530c 4642
f7d24902
ID		 4643 /*
4644 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4645 * for DP the encoder type can be set by the caller to
4646 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4647 */
4648 if (type == DRM_MODE_CONNECTOR_eDP)
4649 intel_encoder->type = INTEL_OUTPUT_EDP;
4650
e7281eab
ID		 4651 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4652 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4653 port_name(port));
4654
b329530c 4655 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
a4fc5ed6
KP		 4656 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4657
a4fc5ed6
KP		 4658 connector->interlace_allowed = true;
4659 connector->doublescan_allowed = 0;
4660
f0fec3f2 4661 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4be73780 4662 edp_panel_vdd_work);
a4fc5ed6 4663
df0e9248 4664 intel_connector_attach_encoder(intel_connector, intel_encoder);
34ea3d38 4665 drm_connector_register(connector);
a4fc5ed6 4666
affa9354 4667 if (HAS_DDI(dev))
bcbc889b
PZ		 4668 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4669 else
4670 intel_connector->get_hw_state = intel_connector_get_hw_state;
80f65de3 4671 intel_connector->unregister = intel_dp_connector_unregister;
bcbc889b 4672
0b99836f 4673 /* Set up the hotplug pin. */
ab9d7c30
PZ		 4674 switch (port) {
4675 case PORT_A:
1d843f9d 4676 intel_encoder->hpd_pin = HPD_PORT_A;
ab9d7c30
PZ		 4677 break;
4678 case PORT_B:
1d843f9d 4679 intel_encoder->hpd_pin = HPD_PORT_B;
ab9d7c30
PZ		 4680 break;
4681 case PORT_C:
1d843f9d 4682 intel_encoder->hpd_pin = HPD_PORT_C;
ab9d7c30
PZ		 4683 break;
4684 case PORT_D:
1d843f9d 4685 intel_encoder->hpd_pin = HPD_PORT_D;
ab9d7c30
PZ		 4686 break;
4687 default:
ad1c0b19 4688 BUG();
5eb08b69
ZW		 4689 }
4690
dada1a9f
ID		 4691 if (is_edp(intel_dp)) {
4692 intel_dp_init_panel_power_timestamps(intel_dp);
0095e6dc 4693 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
dada1a9f 4694 }
0095e6dc 4695
9d1a1031 4696 intel_dp_aux_init(intel_dp, intel_connector);
c1f05264 4697
0e32b39c
DA		 4698 /* init MST on ports that can support it */
4699 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4700 if (port == PORT_B || port == PORT_C || port == PORT_D) {
4701 intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
4702 }
4703 }
4704
0095e6dc 4705 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4f71d0cb 4706 drm_dp_aux_unregister(&intel_dp->aux);
15b1d171
PZ		 4707 if (is_edp(intel_dp)) {
4708 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
51fd371b 4709 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4be73780 4710 edp_panel_vdd_off_sync(intel_dp);
51fd371b 4711 drm_modeset_unlock(&dev->mode_config.connection_mutex);
15b1d171 4712 }
34ea3d38 4713 drm_connector_unregister(connector);
b2f246a8 4714 drm_connector_cleanup(connector);
16c25533 4715 return false;
b2f246a8 4716 }
32f9d658 4717
f684960e
CW		 4718 intel_dp_add_properties(intel_dp, connector);
4719
a4fc5ed6
KP		 4720 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4721 * 0xd. Failure to do so will result in spurious interrupts being
4722 * generated on the port when a cable is not attached.
4723 */
4724 if (IS_G4X(dev) && !IS_GM45(dev)) {
4725 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4726 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4727 }
16c25533
PZ		 4728
4729 return true;
a4fc5ed6 4730}
f0fec3f2
PZ		 4731
4732void
4733intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4734{
13cf5504 4735 struct drm_i915_private *dev_priv = dev->dev_private;
f0fec3f2
PZ		 4736 struct intel_digital_port *intel_dig_port;
4737 struct intel_encoder *intel_encoder;
4738 struct drm_encoder *encoder;
4739 struct intel_connector *intel_connector;
4740
b14c5679 4741 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
f0fec3f2
PZ		 4742 if (!intel_dig_port)
4743 return;
4744
b14c5679 4745 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
f0fec3f2
PZ		 4746 if (!intel_connector) {
4747 kfree(intel_dig_port);
4748 return;
4749 }
4750
4751 intel_encoder = &intel_dig_port->base;
4752 encoder = &intel_encoder->base;
4753
4754 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4755 DRM_MODE_ENCODER_TMDS);
4756
5bfe2ac0 4757 intel_encoder->compute_config = intel_dp_compute_config;
00c09d70 4758 intel_encoder->disable = intel_disable_dp;
00c09d70 4759 intel_encoder->get_hw_state = intel_dp_get_hw_state;
045ac3b5 4760 intel_encoder->get_config = intel_dp_get_config;
07f9cd0b 4761 intel_encoder->suspend = intel_dp_encoder_suspend;
e4a1d846 4762 if (IS_CHERRYVIEW(dev)) {
9197c88b 4763 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
e4a1d846
CML		 4764 intel_encoder->pre_enable = chv_pre_enable_dp;
4765 intel_encoder->enable = vlv_enable_dp;
580d3811 4766 intel_encoder->post_disable = chv_post_disable_dp;
e4a1d846 4767 } else if (IS_VALLEYVIEW(dev)) {
ecff4f3b 4768 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
ab1f90f9
JN		 4769 intel_encoder->pre_enable = vlv_pre_enable_dp;
4770 intel_encoder->enable = vlv_enable_dp;
49277c31 4771 intel_encoder->post_disable = vlv_post_disable_dp;
ab1f90f9 4772 } else {
ecff4f3b
JN		 4773 intel_encoder->pre_enable = g4x_pre_enable_dp;
4774 intel_encoder->enable = g4x_enable_dp;
49277c31 4775 intel_encoder->post_disable = g4x_post_disable_dp;
ab1f90f9 4776 }
f0fec3f2 4777
174edf1f 4778 intel_dig_port->port = port;
f0fec3f2
PZ		 4779 intel_dig_port->dp.output_reg = output_reg;
4780
00c09d70 4781 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
882ec384
VS		 4782 if (IS_CHERRYVIEW(dev)) {
4783 if (port == PORT_D)
4784 intel_encoder->crtc_mask = 1 << 2;
4785 else
4786 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4787 } else {
4788 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4789 }
bc079e8b 4790 intel_encoder->cloneable = 0;
f0fec3f2
PZ		 4791 intel_encoder->hot_plug = intel_dp_hot_plug;
4792
13cf5504
DA		 4793 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
4794 dev_priv->hpd_irq_port[port] = intel_dig_port;
4795
15b1d171
PZ		 4796 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4797 drm_encoder_cleanup(encoder);
4798 kfree(intel_dig_port);
b2f246a8 4799 kfree(intel_connector);
15b1d171 4800 }
f0fec3f2 4801}
0e32b39c
DA		 4802
4803void intel_dp_mst_suspend(struct drm_device *dev)
4804{
4805 struct drm_i915_private *dev_priv = dev->dev_private;
4806 int i;
4807
4808 /* disable MST */
4809 for (i = 0; i < I915_MAX_PORTS; i++) {
4810 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4811 if (!intel_dig_port)
4812 continue;
4813
4814 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4815 if (!intel_dig_port->dp.can_mst)
4816 continue;
4817 if (intel_dig_port->dp.is_mst)
4818 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
4819 }
4820 }
4821}
4822
4823void intel_dp_mst_resume(struct drm_device *dev)
4824{
4825 struct drm_i915_private *dev_priv = dev->dev_private;
4826 int i;
4827
4828 for (i = 0; i < I915_MAX_PORTS; i++) {
4829 struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
4830 if (!intel_dig_port)
4831 continue;
4832 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
4833 int ret;
4834
4835 if (!intel_dig_port->dp.can_mst)
4836 continue;
4837
4838 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
4839 if (ret != 0) {
4840 intel_dp_check_mst_status(&intel_dig_port->dp);
4841 }
4842 }
4843 }
4844}
Linux 6.x block layer and io_uring tree(s)